Product Folder Sample & Buy Support & Community Tools & Software Technical Documents LP8731-Q1 SNVSA28 – DECEMBER 2014 LP8731-Q1 Dual High-Current Step-Down DC-DC And Dual Linear Regulators with I2C Interface 1 Features 3 Description • The LP8731-Q1 is a multi-function, programmable Power Management Unit (PMU), optimized for low power FPGAs, microprocessors, and DSPs. This device integrates two highly efficient 1.2-A step-down DC-DC converters with dynamic voltage management (DVM), two 300-mA linear regulators, and a 400-kHz I2C-compatible interface to allow a host controller access to the internal control registers of the LP8731Q1. The LP8731-Q1 device additionally features programmable power-on sequencing. 1 • • • • • • • • • • Two LDOs for Powering Internal Processor Functions and I/Os High-Speed Serial Interface for Independent Control of Device Functions and Settings Precision Internal Reference Thermal Overload Protection Current Overload Protection Software Programmable Regulators External Power-On-Reset Function for Buck1 and Buck2 (Power Good with Delay Function) Undervoltage Lockout (UVLO) LP8731-Q1 is an Automotive-Grade Product: AECQ-100 Grade-1 Qualified Step-Down DC/DC Converter (2xBuck) – Programmable VOUT from: – Buck1 : 0.8875 V – 1.675 V at 1.2 A – Buck2 : 0.8875 V – 1.675 V at 1.2 A – Up to 96% Efficiency – PWM Switching Frequency of 2.1 MHz – ±2% Output Voltage Accuracy – Automatic Soft Start Linear Regulators (2xLDO) – Programmable VOUT of 0.8 V to 3.3 V – ±3% Output Voltage Accuracy – 300-mA Output Current – 30-mV (Typical) Dropout Device Information(1) PART NUMBER LP8731-Q1 PACKAGE DSBGA (25) space space space Simplified Schematic LDO1 EN_T VINLDO12 • • Configurable Output PMU for ADAS (Advanced Driver Assistance Systems) FPGA, DSP Core Power Applications Processors VDD 1 PF I/O Voltage Domain ENLDO1 100k ENLDO2 nPOR ENSW1 VIN1 SDA 10 PF SCL ENSW2 2.2 PH LDO1 10 PF FB1 VINLDO1 GND_SW1 Buck1 LP8731 1 PF VINLDO2 Advanced Power Controller SW1 0.47 PF LDO1 VIN2 Core ADAS Domain Block 1 PF 10 PF 2.2 PH 0.47 PF SW2 SDA • 2.52 mm x 2.52 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. LDO2 2 Applications BODY SIZE (MAX) Buck2 10 PF FB2 LDO2 SCL Peripheral ADAS Blocks GND_SW2 GND_L GND_C AVDD 1 PF Application System or SoC 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LP8731-Q1 SNVSA28 – DECEMBER 2014 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Device Comparison Tables................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 3 5 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 5 5 5 5 6 6 7 7 7 8 9 Absolute Maximum Ratings ...................................... ESD Ratings ............................................................ Recommended Operating Conditions (Bucks).......... Thermal Information .................................................. General Electrical Characteristics............................. Low Dropout Regulators, LDO1 And LDO2.............. Buck Converters SW1, SW2..................................... I/O Electrical Characteristics..................................... Power-On Reset Threshold/Function (POR) ............ I2C-Compatible Interface Timing............................. Typical Characteristics ............................................ 8.2 8.3 8.4 8.5 8.6 9 Functional Block Diagram ....................................... Features Description ............................................... Device Functional Modes........................................ Programming........................................................... LP8731-Q1 Register Maps ..................................... 11 12 19 20 22 Application and Implementation ........................ 37 9.1 Application Information............................................ 37 9.2 Typical Application .................................................. 37 10 Power Supply Recommendations ..................... 43 10.1 Analog Power Signal Routing ............................... 43 11 Layout................................................................... 44 11.1 Layout Guidelines ................................................. 44 11.2 Layout Example .................................................... 44 12 Device and Documentation Support ................. 45 12.1 12.2 12.3 12.4 12.5 Detailed Description ............................................ 11 Device Support...................................................... Documentation Support ........................................ Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 45 45 45 45 45 13 Mechanical, Packaging, and Orderable Information ........................................................... 45 8.1 Overview ................................................................. 11 4 Revision History 2 DATE REVISION NOTES December 2014 * Initial release. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LP8731-Q1 LP8731-Q1 www.ti.com SNVSA28 – DECEMBER 2014 5 Device Comparison Tables Table 1. Factory Default Programming (1) (1) ORDER NUMBER BUCK1 BUCK2 LP8731QYZRRQ1 1.0625 V 1.0625 V nPOR UVLO 50 µs Disabled LDO1 LDO2 DEFAULT I2C ADDRESS 2.8 V 3.3 V 59 Start/shutdown sequence Buck1 (1.5 ms) → Buck2 (2 ms) → LDO1 (3 ms) → LDO2 (6 ms) All numbers are typical. Table 2. Power Block Operation POWER BLOCK OPERATION POWER BLOCK INPUT ENABLED DISABLED VIN+ (1) VIN+ AVDD VIN+ VIN+ VIN1 VIN+ VIN+ or 0 V VINLDO12 VIN2 VIN+ VIN+ or 0 V VINLDO 1 ≤ VIN+ ≤ VIN+ VINLDO 2 ≤ VIN+ ≤ VIN+ (1) NOTE Always powered If enabled, min VIN is 2.45 V VIN+ is the largest potential voltage on the device. 6 Pin Configuration and Functions DSBGA (YZR) Package 25 Pins Top View 5 VIN LDO2 VIN LDO12 GND_S W1 SW1 VIN1 4 LDO2 VIN LDO12 EN_T EN_S W1 FB1 3 EN_ LDO2 EN_ LDO1 nPOR GND_C AVDD 2 LDO1 SCL SDA EN_ SW2 FB2 1 VIN LDO1 GND_ L GND_ SW2 SW2 VIN2 A B C D E Pin Functions PIN I/O TYPE VINLDO1 I PWR VINLDO1 power in from either DC source or battery to input pin to LDO1. A2 LDO1 O PWR LDO1 Output A3 ENLDO2 I D A4 LDO2 O PWR LDO2 Output A5 VINLDO2 I PWR VINLDO2 power in from either DC source or battery to input pin to LDO2. NUMBER NAME A1 DESCRIPTION LDO2 enable pin, a logic HIGH enables the LDO2 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LP8731-Q1 3 LP8731-Q1 SNVSA28 – DECEMBER 2014 www.ti.com Pin Functions (continued) PIN I/O TYPE GND_L G G LDO ground SCL I D I2C Clock B3 ENLDO1 I D LDO1 enable pin, a logic HIGH enables the LDO1 B4, B5 VINLDO12 I PWR C1 GND_SW2 G G Buck2 NMOS Power ground C2 SDA I/O D I2C Data (bidirectional) C3 nPOR O D nPOR power-on reset pin for both Buck1 and Buck2. Open drain logic output 100K pull-up resistor. nPOR is pulled to ground when the voltages on these supplies are not good. See Flexible Power-On Reset (for example, Power Good with Delay) section for more info. C4 EN_T I D Enable for preset power-on sequence. (See Flexible Power-On Reset (for example, Power Good with Delay).) C5 GND_SW1 G G Buck1 NMOS power ground D1 SW2 O PWR D2 ENSW2 I D Enable pin for Buck2 switcher, a logic HIGH enables Buck2 D3 GND_C G G Non-switching core ground pin D4 ENSW1 I D Enable pin for Buck1 switcher, a logic HIGH enables Buck1 D5 SW1 O PWR Buck1 switcher output pin E1 VIN2 I PWR VIN2 power in from either DC source or Battery to Buck2 E2 FB2 I A E3 AVDD I PWR E4 FB1 I A E5 VIN1 I PWR NUMBER NAME B1 B2 DESCRIPTION Analog power for internal functions (VREF, BIAS, I2C, Logic) Buck2 switcher output pin Buck2 input feedback pin Analog Power for Buck converters Buck1 input feedback pin VIN1 power in from either DC source or Battery to Buck1 A: Analog Pin; D: Digital Pin; G: Ground Pin; PWR: Power Pin; I: Input Pin; O: Output Pin; I/O: Input/Output Pin 4 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LP8731-Q1 LP8731-Q1 www.ti.com SNVSA28 – DECEMBER 2014 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) VIN, SDA, SCL MIN MAX −0.3 6 GND to GND SLUG V ±0.3 Power dissipation (PD_MAX) Internally limited Junction temperature (TJ-MAX) 150 Maximum lead temperature (soldering) 260 Storage temperature (Tstg ) (1) UNIT –65 °C 150 Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability. 7.2 ESD Ratings VALUE V(ESD) (1) Electrostatic discharge Human-body model (HBM), per AEC Q100-002 (1) ±2000 Charged-device model (CDM), per AEC Q100-011 ±750 UNIT V AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification. 7.3 Recommended Operating Conditions (Bucks) over operating free-air temperature range (unless otherwise noted) MIN MAX VIN 2.8 5.5 VEN 0 (VIN + 0.3) Junction temperature (TJ) –40 125 Ambient temperature (TA) –40 125 UNIT V °C 7.4 Thermal Information LP8731-Q1 THERMAL METRIC (1) DSBGA (YZR) UNIT 25 PINS RθJA Junction-to-ambient thermal resistance 58.7 RθJC(top) Junction-to-case (top) thermal resistance 0.3 RθJB Junction-to-board thermal resistance ψJT Junction-to-top characterization parameter ψJB Junction-to-board characterization parameter 8 RθJC(bot) Junction-to-case (bottom) thermal resistance n/a (1) 8 0.6 °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LP8731-Q1 5 LP8731-Q1 SNVSA28 – DECEMBER 2014 www.ti.com 7.5 General Electrical Characteristics Unless otherwise noted, VIN = 3.6 V. Typical values and limits apply for TJ = 25°C. (1) PARAMETER TEST CONDITIONS MIN TYP IQ VINLDO12 shutdown current VIN = 3.6 V VPOR Power-on reset threshold VDD Falling Edge (2) TSD Thermal shutdown threshold 160 TSDH Thermal shutdown hysteresis 20 UVLO Undervoltage lockout (1) (2) MAX UNIT 3 µA 1.9 V Rising 2.9 Falling 2.7 °C V All voltages are with respect to the potential at the GND pin. VPOR is voltage at which the EPROM resets. This is different from the UVLO on VINLDO12, which is the voltage at which the regulators shut off; and is also different from the nPOR function, which signals if the regulators are in a specified range. 7.6 Low Dropout Regulators, LDO1 And LDO2 Unless otherwise noted, VIN = 3.6 V, CIN = 1 µF, COUT = 0.47 µF. Typical values and limits apply for TJ = 25°C. (1) (2) (3) PARAMETER TEST CONDITIONS VIN Operational voltage range VOUT Accuracy Output voltage accuracy (default VOUT) Load current = 1 mA Line regulation VIN = (VOUT + 0.3 V) to 5 V (6) Load current = 1 mA Load regulation VIN = 3.6 V, Load current = 1 mA to IMAX Short circuit current limit LDO1 to LDO2, VOUT = 0 V ΔVOUT ISC VINLDO1 and VINLDO2 PMOS pins 5.5 (5) 3% (5) 0.2 (5) 0.011 (5) 500 150 200 (5) ƒ = 10 kHz, Load current = IMAX θn Supply output noise 10 Hz < F < 100 KHz Quiescent current “on” IOUT = 0 mA Quiescent current “on” IOUT = IMAX (10) Quiescent current “off” EN is de-asserted Turn-on time Start-up from shutdown %/V %/mA mV dB 280 µVrms 40 µA 60 µA 0.03 µA 300 µs µF 0.33 0.47 −40°C ≤ TJ ≤ 125°C 0.68 1 5 V 45 Capacitance for stability 0°C ≤ TJ ≤ 125°C ESR UNIT mA Load current = 250 mA at VOUT = 2.8 V Power supply ripple rejection Output capacitance MAX 50 (5) PSRR COUT −3% (5) TYP 30 Dropout voltage TON 2.45 (5) Load current = 50 mA at VOUT = 2.8 V (7) VIN – VOUT IQ (8) (9) MIN (4) µF 500 mΩ (1) (2) All voltages are with respect to the potential at the GND pin. Minimum and Maximum limits are ensured by design, test, or statistical analysis. Typical numbers are not ensured, but do represent the most likely norm. (3) CIN, COUT: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics. (4) Pins A1 and/or A5 can operate from VIN min of 1.74 to a VIN max of 5.5 V. This rating is only for the series pass PMOS power FET. It allows the system design to use a lower voltage rating if the input voltage comes from a buck output. However, if VIN is required to operate at a higher voltage than other device supply pins, it is necessary to wire the VINLDO12 pins (B4 an B5) and VINLDO1 and VINLDO2 pins (A1 and/or A5) together to that higher voltage so that the LDO core supply has sufficient head-room to operate the gate of the PMOS. (5) Limits apply over the entire operating junction temperature range for operation, –40°C to 125°C. (6) VIN minimum for line regulation values is 1.8 V. (7) Dropout voltage is the voltage difference between the input and the output at which the output voltage drops to 100 mV below its nominal value. (8) Quiescent current is defined here as the difference in current between the input voltage source and the load at VOUT. (9) The IQ can be defined as the standing current of the LP8731-Q1 when the I2C bus is activated and all other power blocks have been disabled via the I2C bus, or it can be defined as the I2C bus active, and the other power blocks are active under no load condition. These two values can be used by the system designer when the LP8731-Q1 is powered using a battery. (10) The IQ exhibits a higher current draw when the EN pin is de-asserted because the I2C buffer pins draw an additional 2 µA. 6 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LP8731-Q1 LP8731-Q1 www.ti.com SNVSA28 – DECEMBER 2014 7.7 Buck Converters SW1, SW2 Unless otherwise noted, VIN = 3.6 V, CIN = 10 µF, COUT = 10 µF, LOUT = 2.2 µH ceramic. Typical values and limits apply for TJ = 25°C. (1) (2) (3) PARAMETER VFB TEST CONDITIONS MIN TYP −3% (4) Feedback voltage MAX UNIT 3% (4) Line regulation 2.8 V < VIN < 5.5 V IOUT = 10 mA 0.089% /V Load regulation 100 mA < IO < IMAX 0.0013% /mA Output accuracy (5) VIN = 3.3 V, VOUT from 0.8875 V to 1.1625 V Load from 0 mA to 600 mA Eff Efficiency Load current = 250 mA ISHDN Shutdown supply current EN is de-asserted fOSC Internal oscillator frequency VOUT IPEAK –2% (4) 2% (4) 90% 1.7 (4) 0.01 µA 2.1 MHz Buck1 peak switching current limit 1.7 Buck2 peak switching current limit 1.7 A IQ (6) Quiescent current “on” 2 mA RDSON (P) Pin-pin resistance PFET 200 mΩ RDSON (N) Pin-pin resistance NFET 180 mΩ TON Turn-on time Start-up from shutdown CIN Input capacitance Capacitance for stability 10 µF CO Output capacitance Capacitance for stability 10 µF (1) (2) (3) (4) (5) (6) No load PWM Mode 500 µs All voltages are with respect to the potential at the GND pin. Minimum and Maximum limits are ensured by design, test, or statistical analysis. Typical numbers are not ensured, but do represent the most likely norm. CIN, COUT: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics. Limits apply over the entire operating junction temperature range for operation, –40°C to 125°C Based on closed loop, bench test data with LP8731YZREVM. The IQ can be defined as the standing current of the LP8731-Q1 when the I2C bus is active and all other power blocks have been disabled via the I2C bus, or it can be defined as the I2C bus active, and the other power blocks are active under no load condition. These two values can be used by the system designer when the LP8731-Q1 is powered using a battery. 7.8 I/O Electrical Characteristics PARAMETER VIL Input low level VIH Input high level (1) TEST CONDITIONS MIN TYP MAX 0.4 (1) 1.2 (1) UNIT V This specification is ensured by design. 7.9 Power-On Reset Threshold/Function (POR) PARAMETER TEST CONDITIONS MIN TYP nPOR nPOR = Power-on reset for Buck1 and Buck2 Default nPOR threshold Percentage of target voltage Buck1 or Buck2 VBUCK1 AND VBUCK2 rising 94% VBUCK1 OR VBUCK2 falling 85% VOL Output level low Load = IOL = 0.2 mA 0.23 (1) MAX 50 UNIT µs 0.5 (1) V This specification is ensured by design. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LP8731-Q1 7 LP8731-Q1 SNVSA28 – DECEMBER 2014 www.ti.com 7.10 I2C-Compatible Interface Timing Unless otherwise noted, VIN = 3.6 V. Nominal values and limits apply for TJ = 25°C. (1) MIN NOM MAX UNIT 400 kHz ƒCLK Clock frequency tBF Bus-free time between start and stop See (1) 1.3 µs tHOLD Hold time repeated start condition See (1) 0.6 µs tCLKLP CLK low period See (1) 1.3 µs (1) tCLKHP CLK high period See 0.6 µs tSU Setup time repeated start condition See (1) 0.6 µs tDATAHLD Data hold time See (1) 0 µs (1) 100 ns 0.6 µs tDATASU Data setup time See TSU Setup time for start condition See (1) TTRANS Maximum pulse width of spikes that must be suppressed by the input filter of both DATA & CLK signals See (1) (1) 8 50 ns This specification is ensured by design. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LP8731-Q1 LP8731-Q1 www.ti.com SNVSA28 – DECEMBER 2014 7.11 Typical Characteristics 2.00 2.00 1.50 1.50 1.00 1.00 VOUT CHANGE (%) VOUT CHANGE (%) TA = 25°C unless otherwise noted 0.50 0.00 -0.50 0.50 0.00 -0.50 -1.00 -1.00 -1.50 -1.50 -2.00 -50 -35 -20 -5 10 25 40 55 70 85 100 -2.00 -50 -35 -20 -5 10 25 40 55 70 85 100 TEMPERATURE (°C) TEMPERATURE (°C) VIN = 3.6 V VOUT = 2.6 V 100-mA load Figure 1. Output Voltage Change vs. Temperature (LDO1) VIN = 3.6 V VOUT = 3.3 V 100-mA load Figure 2. Output Voltage Change vs. Temperature (LDO2) LDO-1 (50 mV/DIV) LDO-1 (50 mV/DIV) Iout (100 mA/DIV) Iout (100 mA/DIV) Time (500 µs/DIV) VOUT = 3.6 V VOUT = 1.8 V Time (500 µs/DIV) ILOAD = 0 to 300 mA Tr = Tf = 1 µs VOUT = 3.6 V VOUT = 1.8 V Figure 3. Load Transient 1-µs Edge Rate Figure 4. Load Transient 4-µs Edge Rate Vin Step (500 mV/DIV) Vin Step (500 mV/DIV) Vout LDO (10 mV/DIV) Vout LDO (10 mV/DIV) Time (100 µs/DIV) VIN = 3.6 V to 4.2 V VOUT = 1.8 V ILOAD = 0 to 300 mA Tr = Tf = 4 µs Time (1 ms/DIV) ILOAD = 300 mA Tr = Tf = 20 µs Figure 5. Line Transient 300-mA, 4-µs Edge Rate VIN = 3.6 V to 4.2 V VOUT = 1.8 V IOUT = 1 mA Tr = Tf = 30 µs Figure 6. Line Transient 1-mA, 30-µs Edge Rate Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LP8731-Q1 9 LP8731-Q1 SNVSA28 – DECEMBER 2014 www.ti.com Typical Characteristics (continued) TA = 25°C unless otherwise noted Vin Step (500 mV/DIV) Buck-2 (100 mV/DIV) Vout LDO (20 mV/DIV) Iout (400 mA/DIV) Time (50 µs/DIV) Time (50 µs/DIV) IOUT = 200 mA to 1.2 A PWM VIN Step Figure 7. Buck Load Transient PWM Mode Vin Step (500 mV/DIV) Vout LDO (20 mV/DIV) Vout LDO (20 mV/DIV) Time (50 µs/DIV) IOUT = 1.2 A Time (50 µs/DIV) Tr = Tf = 10 µs VIN Step Figure 9. Buck Line Transient PWM 10 Tr = Tf = 30 µs Figure 8. Buck Line Transient PWM Vin Step (500 mV/DIV) VIN Step IOUT = 300 mA Submit Documentation Feedback IOUT = 1.2 A Tr = Tf = 30 µs Figure 10. Buck Line Transient PWM Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LP8731-Q1 LP8731-Q1 www.ti.com SNVSA28 – DECEMBER 2014 8 Detailed Description 8.1 Overview The LP8731-Q1 supplies the various power needs of the application by means of two Linear Low Drop Regulators (LDO1 and LDO2) and two Buck converters (SW1 and SW2). Table 3 lists the output characteristics of the various regulators. Table 3. Supply Specification OUTPUT SUPPLY LOAD LDO1 LDO2 VOUT RANGE (V) RESOLUTION (mV) IMAX MAXIMUM OUTPUT CURRENT (mA) analog 0.8 to 3.3 100 300 analog 0.8 to 3.3 100 300 SW1 digital 0.8875 to 1.675 12.5 1200 SW2 digital 0.8875 to 1.675 12.5 1200 8.2 Functional Block Diagram 1P F 10 PF VIN1 10 PF VIN2 1P F VINLDO1 1P F AVDD 1P F VINLDO2 CVDD 4.7 PF VINLDO12 VBATT + ULVO OSC VIN OK BUCK1 AVDD LSW1 2.2PH 1.25V VBUCK1 SW1 CBUCK1 10PF VFB1 ENLDO1 LSW1 2.2PH ENLDO2 Power ON-OFF Logic ENSW 1 AVDD BUCK2 SW2 VFB2 1.25V VBUCK2 CBUCK2 10PF ENSW 2 EN_T VINLDO1 Thermal Shutdown 2.8V LDO1 LDO1 CLDO1 0.47PF RESET VINLDO12 VINLDO2 2 I C_SCL BIAS I 2C LDO2 2 I C_SDA LDO2 RDY1 Logic Control and Registers GND_SW1 GND_SW2 RDY2 VDD nPOR Power On Reset GND_C 1.8V CLDO2 0.47PF RPULLUP 100k GND_L Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LP8731-Q1 11 LP8731-Q1 SNVSA28 – DECEMBER 2014 www.ti.com 8.3 Features Description 8.3.1 Linear Low Dropout Regulators (LDOs) LDO1 and LDO2 are identical linear regulators targeting analog loads characterized by low noise requirements. LDO1 and LDO2 are enabled through the ENLDO pin or through the corresponding LDO1 or LDO2 control register. The output voltages of both LDOs are register programmable. The default output voltages are factory programmed during Final Test, which can be tailored to the specific needs of the system designer. VLDO VIN LDO Register controlled + - ENLDO Vref GND Figure 11. LDO Functional Block Diagram 8.3.2 No-Load Stability The LDOs remain stable and in regulation with no external load. This is an important consideration in some circuits, for example, CMOS RAM keep-alive applications. 8.3.3 LDO1 and LDO2 Control Registers LDO1 and LDO2 can be configured by means of the LDO1 and LDO2 control registers. The output voltage is programmable in steps of 100 mV from 1 V to 3.5 V by programming bits D4 to D0 in the LDO Control registers. Both LDO1 and LDO2 are enabled by applying a logic 1 to the ENLDO1 and ENLDO2 pin. Enable/disable control is also provided through enable bit of the LDO1 and LDO2 control registers. The value of the enable LDO bit in the register is logic 1 by default. The output voltage can be altered while the LDO is enabled. 8.3.4 SW1, SW2: Synchronous Step-Down Magnetic DC-DC Converters 8.3.4.1 Functional Description The LP8731-Q1 incorporates two high-efficiency synchronous switching buck regulators, SW1 and SW2, that deliver a constant voltage from a single Li-Ion battery to the portable system processors. Using a voltage mode architecture with synchronous rectification, both bucks have the ability to deliver up to 1200 mA, depending on the input voltage and output voltage (voltage head room), and the inductor chosen (maximum current capability). Both SW1 and SW2 can operate up to a 100% duty cycle (PMOS switch always on) for low dropout control of the output voltage. In this way the output voltage is controlled down to the lowest possible input voltage. Additional features include soft-start, undervoltage lockout, current overload protection, and thermal overload protection. 8.3.4.2 Circuit Operation A buck converter contains a control block, a switching PFET connected between input and output, a synchronous rectifying NFET connected between the output and ground (BUCKGND pin) and a feedback path. During the first portion of each switching cycle, the control block turns on the internal PFET switch. This allows current to flow from the input through the inductor to the output filter capacitor and load. The inductor limits the current to a ramp with a slope of VIN - VOUT (1) L 12 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LP8731-Q1 LP8731-Q1 www.ti.com SNVSA28 – DECEMBER 2014 Features Description (continued) by storing energy in a magnetic field. During the second portion of each cycle, the control block turns the PFET switch off, blocking current flow from the input, and then turns the NFET synchronous rectifier on. The inductor draws current from ground through the NFET to the output filter capacitor and load, which ramps the inductor current down with a slope of -VOUT (2) L The output filter stores charge when the inductor current is high, and releases it when low, smoothing the voltage across the load. 8.3.4.3 PWM Operation During PWM operation the converter operates as a voltage-mode controller with input voltage feed forward. This allows the converter to achieve excellent load and line regulation. The DC gain of the power stage is proportional to the input voltage. To eliminate this dependence, a feedforward voltage inversely proportional to the input voltage is introduced. 8.3.4.4 Internal Synchronous Rectification While in PWM mode, the buck uses an internal NFET as a synchronous rectifier to reduce rectifier forward voltage drop and associated power loss. Synchronous rectification provides a significant improvement in efficiency whenever the output voltage is relatively low compared to the voltage drop across an ordinary rectifier diode. 8.3.4.5 Current Limiting A current limit feature allows the converter to protect itself and external components during overload conditions. PWM mode implements current limiting using an internal comparator that trips at 1.7 A for Buck1 and Buck2 (typical). If the output is shorted to ground the device enters a timed current limit mode where the NFET is turned on for a longer duration until the inductor current falls below a low threshold, ensuring inductor current has more time to decay, thereby preventing runaway. 8.3.4.6 SW1, SW2 Operation SW1 and SW2 have selectable output voltages ranging from 0.8875 V to 1.675 V (typ.). Both SW1 and SW2 in the LP8731-Q1 are I2C register controlled and are enabled by default through the internal state machine of the LP8731-Q1 following a power-on event that moves the operating mode to the Active state. (See Flexible Power Sequencing of Multiple Power Supplies.) The SW1 and SW2 output voltages revert to default values when the power-on sequence has been completed. The default output voltage for each buck converter is factory programmable. (See Application and Implementation.) 8.3.4.7 SW1, SW2 Control Registers SW1, SW2 can be enabled/disabled through the corresponding control register. 8.3.4.8 Shutdown Mode During shutdown the PFET switch, reference, control and bias circuitry of the converters are turned off. The NFET switch is on in shutdown to discharge the output. When the converter is enabled, soft start is activated. It is recommended to disable the converter during the system power up and undervoltage conditions when the supply is less than 2.8 V. 8.3.4.9 Soft Start The soft-start feature allows the power converter to gradually reach the initial steady state operating point, thus reducing startup stresses and surges. The two LP8731-Q1 buck converters have a soft-start circuit that limits inrush current during start-up. During start-up the switch current limit is increased in steps. Soft start is activated only if EN goes from logic low to logic high after VIN reaches 2.8 V. Soft start is implemented by increasing switch current limit in steps of 180 mA, 300 mA, and 720 mA for Buck1; 180 mA, 300 mA and 720 mA for Buck2 (typical switch current limit). The start-up time thereby depends on the output capacitor and load current demanded at start-up. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LP8731-Q1 13 LP8731-Q1 SNVSA28 – DECEMBER 2014 www.ti.com Features Description (continued) 8.3.4.10 Low Dropout Operation The LP8731-Q1 can operate at 100% duty cycle (no switching; PMOS switch completely on) for low dropout support of the output voltage. In this way the output voltage is controlled down to the lowest possible input voltage. When the device operates near 100% duty cycle, output voltage ripple is approximately 25 mV. The minimum input voltage needed to support the output voltage is VIN, MIN = ILOAD × (RDSON, PFET + RINDUCTOR) + VOUT where • • • ILOAD: Load current RDSON, PFET: Drain to source resistance of PFET switch in the triode region RINDUCTOR: Inductor resistance (3) 8.3.4.11 Flexible Power Sequencing of Multiple Power Supplies The LP8731-Q1 provides several options for power on sequencing. The two bucks can be individually controlled with ENSW1 and ENSW2. The two LDOs can also be individually controlled with ENLDO1 and ENLDO2. If the user desires a set power-on sequence, the device can be programmed through I2C by raising EN_T from LOW to HIGH. 8.3.4.12 Power-Up Sequencing Using the EN_T Function EN_T assertion causes the LP8731-Q1 to emerge from Standby mode to Full Operation mode at a preset timing sequence. By default, the enables for the LDOs and Bucks (ENLDO1, ENLDO2, EN_T, ENSW1, ENSW2) are internally pulled down by a 500-kΩ resistor, which causes the part to stay OFF until enabled. If the user wishes to use the preset timing sequence to power on the regulators, transition the EN_T pin from LOW to HIGH. Otherwise, simply tie the enables of each specific regulator HIGH to turn on automatically. EN_T is edge triggered with rising edge signaling the device to power on. The EN_T input is deglitched, and the default is set at 1 ms. As shown in Figure 12 and Figure 13, a rising EN_T edge starts a power-on sequence, while a falling EN_T edge starts a shutdown sequence. If EN_T is high, toggling the external enables of the regulators has no effect on the device. The regulators can also be programmed through I2C to turn on and off. By default, I2C enables for the regulators on ON. The regulators are on following the pattern: Regulators on = (I2C enable) AND (External pin enable OR EN_T high). NOTE The EN_T power-up sequencing may also be employed immediately after VIN is applied to the device. However, VIN must be stable for approximately 8 ms minimum before EN_T be asserted high to ensure internal bias, reference, and the Flexible POR timing are stabilized. This initial EN_T delay is necessary only upon first time device power on for power-sequencing function to operate properly. 2 I C Regulator ON Ext_Enable Pins 0 1 Start Programmed Timing Sequence EN_T Figure 12. Enable Logic Diagram 14 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LP8731-Q1 LP8731-Q1 www.ti.com SNVSA28 – DECEMBER 2014 Features Description (continued) EN_T t1 Vout Buck1 t2 Vout Buck2 t3 Vout LDO1 t4 Vout LDO2 Figure 13. LP8731-Q1 Default Power-Up Sequence Table 4. Power-On Timing Specification MIN NOM MAX UNIT t1 Programmable delay from EN_T assertion to VCC_Buck1 on 1.5 ms t2 Programmable delay from EN_T assertion to VCC_Buck2 on 2 ms t3 Programmable delay from EN_T assertion to VCC_LDO1 on 3 ms t4 Programmable delay from EN_T assertion to VCC_LDO2 on 6 ms EN_T Vout Buck1 t1 Vout Buck2 t2 Vout LDO1 t3 Vout LDO2 t4 Figure 14. LP8731-Q1 Default Power-Off Sequence MIN NOM MAX UNIT t1 Programmable delay from EN_T deassertion to VCC_Buck1 off 1.5 ms t2 Programmable delay from EN_T deassertion to VCC_Buck2 off 2 ms t3 Programmable delay from EN_T deassertion to VCC_LDO1 off 3 ms t4 Programmable delay from EN_T deassertion to VCC_LDO2 off 6 ms Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LP8731-Q1 15 LP8731-Q1 SNVSA28 – DECEMBER 2014 www.ti.com NOTE The LP8731-Q1 default power-off delay setting is the same as the on sequence. 8.3.5 Flexible Power-On Reset (for example, Power Good with Delay) The LP8731-Q1 is equipped with an internal Power-On-Reset (“POR”) circuit which monitors the output voltage levels on bucks 1 and 2. The nPOR is an open-drain logic output which is logic LOW when either of the buck outputs are below 91% of the rising value, or when one or both outputs fall below 82% of the desired value. The time delay between output voltage level and when nPOR is enabled is (50 µs, 50 ms, 100 ms, 200 ms), 50 µs by default. The system designer can choose the external pull-up resistor (for example, 100 kΩ) for the nPOR pin. t2 t1 Case1 EN1 EN2 RDY1 RDY2 0V Counter delay nPOR t2 t1 Case2 EN1 EN2 RDY1 0V RDY2 Counter delay nPOR t2 t1 Case3 EN1 EN2 RDY1 RDY2 Counter delay nPOR Figure 15. nPOR With Counter Delay Figure 15 shows the simplest application of the Power-On Reset, where both switcher enables are tied together. In Case 1, EN1 causes nPOR to transition LOW and triggers the nPOR delay counter. If the power supply for Buck2 does not come on within that period, nPOR stays LOW, indicating a power fail mode. Case 2 indicates the vice-versa scenario if Buck1 supply did not come on. In both cases the nPOR remains LOW. 16 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LP8731-Q1 LP8731-Q1 www.ti.com SNVSA28 – DECEMBER 2014 Case 3 shows a typical application of the Power On Reset, where both switcher enables are tied together. Even if RDY1 ramps up slightly faster than RDY2 (or vice versa), then nPOR signal triggers a programmable delay before going HIGH, as explained in Figure 16. t0 t1 t2 t3 t4 EN1 RDY1 Counter delay Counter delay nPOR EN2 RDY2 Figure 16. Faults Occurring in Counter Delay after Start-Up The Figure 16 timing diagram details the power-good with delay with respect to the enable signals EN1, and EN2. The RDY1, RDY2 are internal signals derived from the output of two comparators. Each comparator has been trimmed as follows: COMPARATOR LEVEL BUCK SUPPLY LEVEL HIGH Greater than 94% LOW Less than 85% The circuits for EN1 and RDY1 are symmetrical to EN2 and RDY2, so each reference to EN1 and RDY1 also works for EN2 and RDY2 and vice versa. If EN1 and RDY1 signals are HIGH at time t1, then the RDY1 signal rising edge triggers the programmable delay counter (50 μs, 50 ms, 100 ms, 200 ms). This delay forces nPOR LOW between time interval t1 and t2. nPOR is then pulled HIGH after the programmable delay is completed. If EN2 and RDY2 are initiated during this interval, the nPOR signal ignores this event. If either RDY1or RDY2 were to go LOW at t3 then the programmable delay is triggered again. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LP8731-Q1 17 LP8731-Q1 SNVSA28 – DECEMBER 2014 www.ti.com t0 t1 t2 t3 t4 EN1 RDY1 Counter delay nPOR Case 1: EN2 RDY2 Mask Time Mask Window Counter delay nPOR Case 2: EN2 RDY2 0V Mask Time nPOR Mask Window Counter delay Figure 17. nPOR Mask Window If the EN1 and RDY1 are initiated in normal operation, then nPOR is asserted and deasserted . Case 1 in Figure 17 shows a case where EN2 and RDY2 are initiated after triggered programmable delay. To prevent the nPOR being asserted again, a masked window (5 ms) counter delay is triggered off the EN2 rising edge. nPOR is still held HIGH for the duration of the mask, whereupon the nPOR status afterwards depends on the status of both RDY1 and RDY2 lines. Case 2 shows the case where EN2 is initiated after the RDY1 triggered programmable delay, but RDY2 never goes HIGH (Buck2 never turns on). Normal operation of nPOR occurs with respect to EN1 and RDY1, and the nPOR signal is held HIGH for the duration of the mask window. nPOR goes LOW after the masking window has timed out because it is now dependent on RDY1 and RDY2, where RDY2 is LOW. 18 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LP8731-Q1 LP8731-Q1 www.ti.com SNVSA28 – DECEMBER 2014 Delay Mask Counter EN1 RDY1 EN2 RDY2 S Q R Q Delay nPOR POR Delay Mask Counter Figure 18. Design Implementation Of The Flexible Power-On Reset An internal power-on reset of the device is used with EN1 and EN2 to produce a reset signal (LOW) to the delay timer nPOR. EN1 and RDY1 or EN2 and RDY2 are used to generate the set signal (HIGH) to the delay timer. S = R = 1 never occurs. The mask timers are triggered by EN1 and EN2 which are gated with RDY1 and RDY2 to generate outputs to the final AND gate to generate the nPOR. 8.3.6 Undervoltage Lockout The LP8731-Q1 features an undervoltage lockout circuit. The function of this circuit is to continuously monitor the raw input supply voltage (VINLDO12) and automatically disables the four voltage regulators whenever this supply voltage is less than 2.8 VDC. The circuit incorporates a bandgap-based circuit that establishes the reference used to determine the 2.8-VDC trip point for a VIN OK – Not OK detector. This VIN OK signal is then used to gate the enable signals to the four regulators of the LP8731-Q1. When VINLDO12 is greater than 2.8 VDC, the four enables control the four regulators, when VINLDO12 is less than 2.8 VDC, the four regulators are disabled by the VIN detector being in the “Not OK” state. The circuit has built-in hysteresis to prevent chattering from occurring. 8.4 Device Functional Modes 8.4.1 Shutdown Mode During shutdown the PFET switch, reference, control, and bias circuitry of the converters are turned off. The NFET switch is turned on during shutdown to discharge the output. When the converter is enabled, soft start is activated. It is recommended that the converter be disabled during the system power up and undervoltage conditions when the supply is less than 2.8 V. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LP8731-Q1 19 LP8731-Q1 SNVSA28 – DECEMBER 2014 www.ti.com 8.5 Programming 8.5.1 I2C-Compatible Serial Interface 8.5.1.1 I2C Signals The LP8731-Q1 features an I2C-compatible serial interface, using two dedicated pins: SCL and SDA for I2C clock and data, respectively. Both signals need a pullup resistor according to the I2C specification. The LP8731-Q1 interface is an I2C slave that is clocked by the incoming SCL clock. Signal timing specifications are according to the I2C bus specification. The maximum bit rate is 400 kbit/s. See I2C specification from NXP Semiconductors for further details. 8.5.1.2 I2C Data Validity The data on the SDA line must be stable during the HIGH period of the clock signal (SCL), that is, the state of the data line can only be changed when CLK is LOW. 2 I C_SCL 2 I C_SDA data change allowed data valid data change allowed data change allowed data valid Figure 19. I2C Signals: Data Validity 8.5.1.3 I2C Start and Stop Conditions START and STOP bits classify the beginning and the end of the I2C session. START condition is defined as the SDA signal transitioning from HIGH to LOW while the SCL line is HIGH. STOP condition is defined as the SDA transitioning from LOW to HIGH while the SCL is HIGH. The I2C master always generates START and STOP bits. The I2C bus is considered to be busy after START condition and free after STOP condition. During data transmission, I2C master can generate repeated START conditions. First START and repeated START conditions are equivalent, function-wise. 2 I C_SDA 2 I C_SCL S START condition P STOP condition Figure 20. Start And Stop Conditions 8.5.1.4 Transferring Data Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first. Each byte of data has to be followed by an acknowledge bit. The acknowledged related clock pulse is generated by the master. The transmitter releases the SDA line (HIGH) during the acknowledge clock pulse. The receiver must pull down the SDA line during the 9th clock pulse, signifying acknowledgment. A receiver which has been addressed must generate an acknowledgment (“ACK”) after each byte has been received. After the START condition, the I2C master sends a chip address. This address is seven bits long followed by an eighth bit which is a data direction bit (R/W). 20 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LP8731-Q1 LP8731-Q1 www.ti.com SNVSA28 – DECEMBER 2014 Programming (continued) NOTE According to industry I2C standards for 7-bit addresses, the MSB of an 8-bit address is removed, and communication actually starts with the 7th most significant bit. For the eighth bit (LSB), a “0” indicates a WRITE and a “1” indicates a READ. The second byte selects the register to which the data is written. The third byte contains data to write to the selected register. The LP8731-Q1 has factory-programmed I2C addresses. The device has a chip address of 59'h. LSB MSB ADR6 bit7 ADR5 bit6 ADR4 bit5 ADR3 bit4 ADR2 bit3 ADR1 bit2 ADR0 bit1 1 1 0 0 0 0 0 R/W bit0 2 I C SLAVE address (chip address) Figure 21. I2C Chip Address (see NOTE above) ack from slave ack from slave start MSB Chip id LSB w ack MSB Register Addr LSB ack id = 101 1001b w ack Register address ack ack from slave MSB Data LSB ack stop ack stop SCL SDA start data w = write (SDA = “0”) r = read (SDA = “1”) ack = acknowledge (SDA pulled down by either master or slave) rs = repeated start id = LP8731-Q1 chip address: 0x59 Figure 22. I2C Write Cycle When a READ function is to be accomplished, a WRITE function must precede the READ function, as shown in the Read Cycle waveform. ack from slave start ack from slave Repeated start MSB Chip id LSB w ack MSB Register Addr LSB ack rs MSB Chip id LSB id = 101 1001b w ack Register address ack rs id = 101 1001b ack from slave r ack data from slave MSB Data LSB ack from master ack stop SCL SDA start ack data ack stop Figure 23. I2C Read Cycle Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LP8731-Q1 21 LP8731-Q1 SNVSA28 – DECEMBER 2014 www.ti.com 8.6 LP8731-Q1 Register Maps REGISTER ADDRESS REGISTER NAME READ/WRITE 0x02 ICRA R Interrupt Status Register A REGISTER DESCRIPTION 0x07 SCR1 R/W System Control 1 Register 0x10 BKLDOEN R/W Buck and LDO Output Voltage Enable Register 0x11 BKLDOSR R Buck and LDO Output Voltage Status Register 0x20 VCCR R/W Voltage Change Control Register 1 0x23 B1TV1 R/W Buck1 Target Voltage 1 Register 0x24 B1TV2 R/W Buck1 Target Voltage 2 Register 0x25 B1RC R/W Buck1 Ramp Control 0x29 B2TV1 R/W Buck2 Target Voltage 1 Register 0x2A B2TV2 R/W Buck2 Target Voltage 2 Register 0x2B B2RC R/W Buck2 Ramp Control 0x38 BFCR R/W Buck Function Register 0x39 LDO1VCR R/W LDO1 Voltage control Registers 0x3A LDO2VCR R/W LDO2 Voltage control Registers 8.6.1 Interrupt Status Register (ISRA) 0x02 This register informs the system engineer of the temperature status of the chip. D7-D2 D1 D0 Name — Temp 125°C — Access — R — Data Reserved Status bit for thermal warning PMIC T > 125°C 0 – PMIC Temp. < 125°C 1 – PMIC Temp. > 125°C Reserved Reset 0 0 0 8.6.2 System Control 1 Register (SCR1) 0x07 This register allows the user to select the preset delay sequence for power-on timing and to select between an internal and external clock for the bucks. D7 D6-D4 D3 D2 (1) D1 D0 Name — EN_DLY — FPWM2 Access — R/W — R/W R/W R/W Data Reserved Selects the preset delay sequence from EN_T assertion (shown below) Reserved Buck2 PWM /PFM Mode select 0 – Auto Switch PFM PWM operation 1 – PWM Mode Only Buck 1 PWM /PFM Mode select 0 – Auto Switch PFM PWM operation 1 – PWM Mode Only Reserved Reset 0 Factory-Programmed Default 1 Factory-Programmed Default Factory-Programmed Default 0 (1) 22 FPWM1 (1) ECEN Default PWM mode only — please contact TI sales office if Auto switch/PFM mode operation is needed. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LP8731-Q1 LP8731-Q1 www.ti.com SNVSA28 – DECEMBER 2014 8.6.3 EN_DLY Preset Delay Sequence after EN_T Assertion DELAY (ms) EN_DLY<2:0> Buck1 Buck2 LDO1 LDO2 000 1 1 1 1 001 1 1.5 2 2 010 1.5 2 3 6 011 1.5 2 1 1 100 1.5 2 3 6 101 1.5 1.5 2 2 110 3 2 1 1.5 111 2 3 6 11 8.6.4 Buck and LDO Output Voltage Enable Register (BKLDOEN) – 0x10 This register controls the enables for the Bucks and LDOs. D7 D6 D5 D4 D3 D2 D1 D0 Name — LDO2EN — LDO1EN — BK2EN — BK1EN Access — R/W — R/W — R/W — R/W Data Reserved 0 – Disable 1 – Enable Reserved 0 – Disable 1 – Enable Reserved 0 – Disable 1 – Enable Reserved 0 – Disable 1 – Enable Reset 0 1 1 1 0 1 0 1 8.6.5 Buck and LDO Status Register (BKLDOSR) – 0x11 This register monitors whether the Bucks and LDOs meet the voltage output specifications. D7 D6 D5 D4 D3 D2 D1 D0 Name BKS_OK LDOS_OK LDO2_OK LDO1_OK — BK2_OK — BK1_OK Access R R R R — R — R Data 0 – Buck 1-2 Not Valid 1 – Bucks Valid 0 – LDO 1-2 Not Valid 1 – LDOs Valid 0 – LDO2 Not Valid 1 – LDO2 Valid 0 – LDO1 Not Valid 1 – LDO1 Valid Reserve d 0 – Buck2 Not Valid 1 – Buck2 Valid Reserve d 0 – Buck1 Not Valid 1 – Buck1 Valid Reset 0 0 0 0 0 0 0 0 8.6.6 BUCK Voltage Change Control Register 1 (VCCR) – 0x20 This register selects and controls the output target voltages for the buck regulators. D7-D6 D5 D4 D3-2 D1 D0 Name — B2VS B2GO — B1VS B1GO Access — R/W R/W — R/W R/W Data Reserved Buck2 Target Voltage Select 0 – B2VT1 1 – B2VT2 Buck2 Voltage Ramp CTRL 0 – Hold 1 – Ramp to B2VS selection Reserved Buck1 Target Voltage Select 0 – B1VT1 1 – B1VT2 Buck1 Voltage Ramp CTRL 0 – Hold 1 – Ramp to B1VS selection Reset 00 0 0 00 0 0 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LP8731-Q1 23 LP8731-Q1 SNVSA28 – DECEMBER 2014 www.ti.com 8.6.7 BUCK1 Target Voltage 1 Register (B1TV1) – 0x23 This register allows the user to program the output target voltage of Buck1 (target voltage 1). D7-D6 D5 D4-0 BUCK1 OUTPUT VOLTAGE (V) Name — Buck1 12p5 mV step B1TV1 — Access — R/W R/W — 1’h0 5’h00 0.8875 1'h1 5’h00 0.9000 1’h0 5’h01 0.9125 1'h1 5’h01 0.9250 1’h0 5’h02 0.9375 1'h1 5’h02 0.9500 1’h0 5’h03 0.9625 Data 24 Reserved 1'h1 5’h03 0.9750 1’h0 5’h04 0.9875 1'h1 5’h04 1.0000 1’h0 5’h05 1.0125 1'h1 5’h05 1.0250 1’h0 5’h06 1.0375 1'h1 5’h06 1.0500 1’h0 5’h07 1.0625 1'h1 5’h07 1.0750 1’h0 5’h08 1.0875 1'h1 5’h08 1.1000 1’h0 5’h09 1.1125 1'h1 5’h09 1.1250 1’h0 5’h0A 1.1375 1'h1 5’h0A 1.1500 1’h0 5’h0B 1.1625 1'h1 5’h0B 1.1750 1’h0 5’h0C 1.1875 1'h1 5’h0C 1.2000 1’h0 5’h0D 1.2125 1'h1 5’h0D 1.2250 1’h0 5’h0E 1.2375 1'h1 5’h0E 1.2500 1’h0 5’h0F 1.2625 1'h1 5’h0F 1.2750 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LP8731-Q1 LP8731-Q1 www.ti.com Data SNVSA28 – DECEMBER 2014 D7-D6 D5 D4-0 BUCK1 OUTPUT VOLTAGE (V) Register 1’h0 5'h10 1.2875 1'h1 5'h10 1.3000 1’h0 5'h11 1.3125 1’h0 5'h11 1.3250 1'h1 5'h12 1.3375 1’h0 5'h12 1.3500 1'h1 5'h13 1.3625 1’h0 5'h13 1.3750 1'h1 5'h14 1.3875 1’h0 5'h14 1.4000 1'h1 5'h15 1.4125 1’h0 5'h15 1.4250 1'h1 5'h16 1.4375 1’h0 5'h16 1.4500 1'h1 5'h17 1.4625 1’h0 5'h17 1.4750 1’h0 5'h18 1.4875 1'h1 5'h18 1.5000 1’h0 5'h19 1.5125 1'h1 5'h19 1.5250 1’h0 5'h1A 1.5375 1'h1 5'h1A 1.5500 1’h0 5'h1B 1.5625 1'h1 5'h1B 1.5750 1’h0 5'h1C 1.5875 1'h1 5'h1C 1.6000 1'h0 5'h1D 1.6125 1'h1 5'h1D 1.6250 1'h0 5'h1E 1.6375 1'h1 5'h1E 1.6500 1'h0 5'h1F 1.6625 1'h1 5'h1F 1.6750 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LP8731-Q1 25 LP8731-Q1 SNVSA28 – DECEMBER 2014 www.ti.com 8.6.8 BUCK1 Target Voltage 2 Register (B1TV2) - 0x24 This register allows the user to program the output target voltage of Buck1 (target voltage 2). D7-D6 D5 D4-D0 BUCK1 OUTPUT VOLTAGE (V) Name — Buck1 12p5 mV step B1TV2 — Access — R/W R/W — 1’h0 5’h00 0.8875 1'h1 5’h00 0.9000 1’h0 5’h01 0.9125 1'h1 5’h01 0.9250 1’h0 5’h02 0.9375 1'h1 5’h02 0.9500 1’h0 5’h03 0.9625 Data 26 Reserved 1'h1 5’h03 0.9750 1’h0 5’h04 0.9875 1'h1 5’h04 1.0000 1’h0 5’h05 1.0125 1'h1 5’h05 1.0250 1’h0 5’h06 1.0375 1'h1 5’h06 1.0500 1’h0 5’h07 1.0625 1'h1 5’h07 1.0750 1’h0 5’h08 1.0875 1'h1 5’h08 1.1000 1’h0 5’h09 1.1125 1'h1 5’h09 1.1250 1’h0 5’h0A 1.1375 1'h1 5’h0A 1.1500 1’h0 5’h0B 1.1625 1'h1 5’h0B 1.1750 1’h0 5’h0C 1.1875 1'h1 5’h0C 1.2000 1’h0 5’h0D 1.2125 1'h1 5’h0D 1.2250 1’h0 5’h0E 1.2375 1'h1 5’h0E 1.2500 1’h0 5’h0F 1.2625 1'h1 5’h0F 1.2750 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LP8731-Q1 LP8731-Q1 www.ti.com SNVSA28 – DECEMBER 2014 D7-D6 Data Reserved D5 D4-D0 BUCK1 OUTPUT VOLTAGE (V) 1’h0 5'h10 1.2875 1'h1 5'h10 1.3000 1’h0 5'h11 1.3125 1’h0 5'h11 1.3250 1'h1 5'h12 1.3375 1’h0 5'h12 1.3500 1'h1 5'h13 1.3625 1’h0 5'h13 1.3750 1'h1 5'h14 1.3875 1’h0 5'h14 1.4000 1'h1 5'h15 1.4125 1’h0 5'h15 1.4250 1'h1 5'h16 1.4375 1’h0 5'h16 1.4500 1'h1 5'h17 1.4625 1’h0 5'h17 1.4750 1’h0 5'h18 1.4875 1'h1 5'h18 1.5000 1’h0 5'h19 1.5125 1'h1 5'h19 1.5250 1’h0 5'h1A 1.5375 1'h1 5'h1A 1.5500 1’h0 5'h1B 1.5625 1'h1 5'h1B 1.5750 1’h0 5'h1C 1.5875 1'h1 5'h1C 1.6000 1'h0 5'h1D 1.6125 1'h1 5'h1D 1.6250 1'h0 5'h1E 1.6375 1'h1 5'h1E 1.6500 1'h0 5'h1F 1.6625 1'h1 5'h1F 1.6750 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LP8731-Q1 27 LP8731-Q1 SNVSA28 – DECEMBER 2014 www.ti.com 8.6.9 BUCK1 Ramp Control Register (B1RC) - 0x25 This register allows the user to program the rate of change between the target voltages of Buck1. D7 D6-D4 D3-D0 Name ---- ---- B1RS Access ---- ---- R/W Reserved Reserved Data 28 Data Code Ramp Rate mV/us 4'h0 Instant 4'h1 1 4'h2 2 4'h3 3 4'h4 4 4'h'5 5 4'h6 6 4'h7 7 4'h8 8 4'h9 9 4'hA 10 4'hB - 4'hF 10 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LP8731-Q1 LP8731-Q1 www.ti.com SNVSA28 – DECEMBER 2014 8.6.10 BUCK2 Target 1 Register (B2TV1) - 0x29 This register allows the user to program the output target voltage of Buck2 (target voltage 1). D7-D6 D5 D4-D0 BUCK2 OUTPUT VOLTAGE (V) Name — Buck1 12.5 mV step B2TV1 — Access — R/W R/W — 1’h0 5’h00 0.8875 1'h1 5’h00 0.9000 1’h0 5’h01 0.9125 1'h1 5’h01 0.9250 1’h0 5’h02 0.9375 1'h1 5’h02 0.9500 1’h0 5’h03 0.9625 Data Reserved 1'h1 5’h03 0.9750 1’h0 5’h04 0.9875 1'h1 5’h04 1.0000 1’h0 5’h05 1.0125 1'h1 5’h05 1.0250 1’h0 5’h06 1.0375 1'h1 5’h06 1.0500 1’h0 5’h07 1.0625 1'h1 5’h07 1.0750 1’h0 5’h08 1.0875 1'h1 5’h08 1.1000 1’h0 5’h09 1.1125 1'h1 5’h09 1.1250 1’h0 5’h0A 1.1375 1'h1 5’h0A 1.1500 1’h0 5’h0B 1.1625 1'h1 5’h0B 1.1750 1’h0 5’h0C 1.1875 1'h1 5’h0C 1.2000 1’h0 5’h0D 1.2125 1'h1 5’h0D 1.2250 1’h0 5’h0E 1.2375 1'h1 5’h0E 1.2500 1’h0 5’h0F 1.2625 1'h1 5’h0F 1.2750 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LP8731-Q1 29 LP8731-Q1 SNVSA28 – DECEMBER 2014 D7-D6 Data 30 Reserved www.ti.com D5 D4-D0 BUCK2 OUTPUT VOLTAGE (V) 1’h0 5'h10 1.2875 1'h1 5'h10 1.3000 1’h0 5'h11 1.3125 1’h0 5'h11 1.3250 1'h1 5'h12 1.3375 1’h0 5'h12 1.3500 1'h1 5'h13 1.3625 1’h0 5'h13 1.3750 1'h1 5'h14 1.3875 1’h0 5'h14 1.4000 1'h1 5'h15 1.4125 1’h0 5'h15 1.4250 1'h1 5'h16 1.4375 1’h0 5'h16 1.4500 1'h1 5'h17 1.4625 1’h0 5'h17 1.4750 1’h0 5'h18 1.4875 1'h1 5'h18 1.5000 1’h0 5'h19 1.5125 1'h1 5'h19 1.5250 1’h0 5'h1A 1.5375 1'h1 5'h1A 1.5500 1’h0 5'h1B 1.5625 1'h1 5'h1B 1.5750 1’h0 5'h1C 1.5875 1'h1 5'h1C 1.6000 1'h0 5'h1D 1.6125 1'h1 5'h1D 1.6250 1'h0 5'h1E 1.6375 1'h1 5'h1E 1.6500 1'h0 5'h1F 1.6625 1'h1 5'h1F 1.6750 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LP8731-Q1 LP8731-Q1 www.ti.com SNVSA28 – DECEMBER 2014 8.6.11 BUCK2 Target 2 Register (B2TV2) - 0x2A This register allows the user to program the output target voltage of Buck2 (target voltage 2). D7-D6 D5 D4-D0 BUCK2 OUTPUT VOLTAGE (V) Name — Buck1 12.5 mV step B2TV2 — Access — R/W R/W — 1’h0 5’h00 0.8875 1'h1 5’h00 0.9000 1’h0 5’h01 0.9125 1'h1 5’h01 0.9250 1’h0 5’h02 0.9375 1'h1 5’h02 0.9500 1’h0 5’h03 0.9625 Data Reserved 1'h1 5’h03 0.9750 1’h0 5’h04 0.9875 1'h1 5’h04 1.0000 1’h0 5’h05 1.0125 1'h1 5’h05 1.0250 1’h0 5’h06 1.0375 1'h1 5’h06 1.0500 1’h0 5’h07 1.0625 1'h1 5’h07 1.0750 1’h0 5’h08 1.0875 1'h1 5’h08 1.1000 1’h0 5’h09 1.1125 1'h1 5’h09 1.1250 1’h0 5’h0A 1.1375 1'h1 5’h0A 1.1500 1’h0 5’h0B 1.1625 1'h1 5’h0B 1.1750 1’h0 5’h0C 1.1875 1'h1 5’h0C 1.2000 1’h0 5’h0D 1.2125 1'h1 5’h0D 1.2250 1’h0 5’h0E 1.2375 1'h1 5’h0E 1.2500 1’h0 5’h0F 1.2625 1'h1 5’h0F 1.2750 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LP8731-Q1 31 LP8731-Q1 SNVSA28 – DECEMBER 2014 D7-D6 Data 32 Reserved www.ti.com D5 D4-D0 BUCK2 OUTPUT VOLTAGE (V) 1’h0 5'h10 1.2875 1'h1 5'h10 1.3000 1’h0 5'h11 1.3125 1’h0 5'h11 1.3250 1'h1 5'h12 1.3375 1’h0 5'h12 1.3500 1'h1 5'h13 1.3625 1’h0 5'h13 1.3750 1'h1 5'h14 1.3875 1’h0 5'h14 1.4000 1'h1 5'h15 1.4125 1’h0 5'h15 1.4250 1'h1 5'h16 1.4375 1’h0 5'h16 1.4500 1'h1 5'h17 1.4625 1’h0 5'h17 1.4750 1’h0 5'h18 1.4875 1'h1 5'h18 1.5000 1’h0 5'h19 1.5125 1'h1 5'h19 1.5250 1’h0 5'h1A 1.5375 1'h1 5'h1A 1.5500 1’h0 5'h1B 1.5625 1'h1 5'h1B 1.5750 1’h0 5'h1C 1.5875 1'h1 5'h1C 1.6000 1'h0 5'h1D 1.6125 1'h1 5'h1D 1.6250 1'h0 5'h1E 1.6375 1'h1 5'h1E 1.6500 1'h0 5'h1F 1.6625 1'h1 5'h1F 1.6750 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LP8731-Q1 LP8731-Q1 www.ti.com SNVSA28 – DECEMBER 2014 8.6.12 BUCK2 Ramp Control Register (B2RC) - 0x2B This register allows the user to program the rate of change between the target voltages of Buck2. D7 D6-D4 D3-D0 Name ---- ---- B2RS Access ---- ---- R/W Reserved Reserved Data Data Code Ramp Rate mV/us 4'h0 Instant 4'h1 1 4'h2 2 4'h3 3 4'h4 4 4'h5 5 4'h6 6 4'h7 7 4'h8 8 4'h9 9 4'hA 10 4'hB - 4'hF Reset 0 10 010 1000 8.6.13 BUCK Function Register (BFCR) – 0x38 Clock Frequency This register allows the Buck switcher clock frequency to be spread across a wider range, allowing for less Electro-magnetic Interference (EMI). The spread spectrum modulation frequency refers to the rate at which the frequency ramps up and down, centered at 2 MHz. Spread Spectrum frequency Peak frequency deviation 2 kHz triangle wave 10 kHz triangle wave 2 MHz Time Figure 24. Spread Spectrum Frequency Modulation 8.6.14 Spread Spectrum Function Periodic switching in the buck regulator is inherently a noisier function block compared to an LDO. It can be challenging in some critical applications to comply with stringent regulatory standards or simply to minimize interference to sensitive circuits in space limited portable systems. The regulator’s switching frequency and harmonics can cause "noise" in the signal spectrum. The magnitude of this noise is measured by its power spectral density. The power spectral density of the switching frequency, FC, is one parameter that system designers want to be as low as practical to reduce interference to the environment and subsystems within their products. The LP8731-Q1 has a user-selectable function on the device, allowing a noise-reduction technique known as spread spectrum to be employed to ease customer’s design and production issues. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LP8731-Q1 33 LP8731-Q1 SNVSA28 – DECEMBER 2014 www.ti.com The principle behind spread spectrum is to modulate the switching frequency slightly and slowly, and spread the signal frequency over a broader bandwidth. Thus, its power spectral density becomes attenuated, used as a spread spectrum clock via two I2C control register bits bk_ssen, and slomod. With this feature enabled, the intense energy of the clock frequency can be spread across a small band of frequencies in the neighborhood of the center frequency. The results in a reduction of the peak energy! The LP8731-Q1 spread spectrum clock uses a triangular modulation profile with equal rise and fall slopes. The modulation has the following characteristics: • The center frequency: FC = 2 MHz, and • The modulating frequency, ƒM = 6.8 kHz or 12 kHz. • Peak frequency deviation: Δ_ƒ = ±100 kHz (or ±5%) • Modulation index β = Δ_ƒ/ƒM = 14.7 or 8.3 This register also allows dynamic scaling of the nPOR Delay Timing. The LP8731-Q1 is equipped with an internal Power-On Reset (POR) circuit which monitors the output voltage levels on the buck regulators, allowing the user to more actively monitor the power status of the device. The undervoltage lockout feature continuously monitor the raw input supply voltage (VINLDO12) and automatically disables the four voltage regulators whenever this supply voltage is less than 2.8 VDC. This prevents the user from damaging the power source (for example, the battery), but can be disabled if the user wishes. The UVLO feature continuously monitor the raw input supply voltage (VINLDO12) and automatically disables the four voltage regulators whenever this supply voltage is less than 2.8 VDC. This prevents the user from damaging the power source (for example, the battery), but can be disabled if the user wishes. NOTE If the supply to VINs is close to 2.8 V with a heavy load current on the regulators, the device could power down due to UVLO. If the user wishes to keep the device active under those conditions, the bypass UVLO feature should be enabled. D7-D5 Name Access D3-D2 D1 D0 BP_UVLO TPOR BK_SLOMOD BK_SSEN — R/W R/W R/W R/W Bypass UVLO monitoring 0 - Allow UVLO 1 - Disable UVLO nPOR Delay Timing 00 - 50 µs 01 - 50 ms 10 - 100 ms 11 - 200 ms Buck Spread Spectrum Modulation 0 – 10-kHz triangular wave 1 – 2-kHz triangular wave Spread Spectrum Function Output 0 – Disabled 1 – Enabled Data Reserved Reset 000 34 D4 — Factory-Programmed Default Submit Documentation Feedback 1 0 Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LP8731-Q1 LP8731-Q1 www.ti.com SNVSA28 – DECEMBER 2014 8.6.15 LDO1 Control Register (LDO1VCR) – 0x39 This register allows the user to program the output target voltage of LDO1. D7-D5 D4-D0 Name — LDO1_OUT Access — R/W Data Reserved LDO1 Output voltage (V) 5’h00 0.8 5’h01 0.9 5’h02 1.0 5’h03 1.1 5’h04 1.2 5’h05 1.3 5’h06 1.4 5’h07 1.5 5’h08 1.6 5’h09 1.7 5’h0A 1.8 5’h0B 1.9 5’h0C 2.0 5’h0D 2.1 5’h0E 2.2 5’h0F 2.3 5’h10 2.4 5’h11 2.5 5’h12 2.6 5’h13 2.7 5’h14 2.8 5’h15 2.9 5’h16 3.0 5’h17 3.1 5’h18 3.2 5’h19 3.3 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LP8731-Q1 35 LP8731-Q1 SNVSA28 – DECEMBER 2014 www.ti.com 8.6.16 LDO2 Control Register (LDO2VCR) – 0x3A This register allows the user to program the output target voltage of LDO2. D7-D5 D4-D0 Name — LDO2_OUT Access — R/W Data 36 Reserved LDO2 Output voltage (V) 5’h00 0.8 5’h01 0.9 5’h02 1.0 5’h03 1.1 5’h04 1.2 5’h05 1.3 5’h06 1.4 5’h07 1.5 5’h08 1.6 5’h09 1.7 5’h0A 1.8 5’h0B 1.9 5’h0C 2.0 5’h0D 2.1 5’h0E 2.2 5’h0F 2.3 5’h10 2.4 5’h11 2.5 5’h12 2.6 5’h13 2.7 5’h14 2.8 5’h15 2.9 5’h16 3.0 5’h17 3.1 5’h18 3.2 5’h19 3.3 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LP8731-Q1 LP8731-Q1 www.ti.com SNVSA28 – DECEMBER 2014 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information One of the key features of this integrated PMU is that it requires effectively no design procedures because the output voltage is digitally programmable and bounded, compensation components are internally fixed or selected, and the external support capacitors and inductors and optimized for typical applications and performance. Given the I/O range and maximum loading are fixed and target transient and output ripple are prescribed, as reflected in Design Requirements, the external components values are optimized as follows: • LDO CIN = 1 µF, COUT = 0.47 µF • Buck CIN = COUT = 10 µF • Buck Inductor = 2.2 µH The Component Selection section also details the background and sample calculations for capacitor and inductor selections, should users choose to operate with different component values than those recommended in order to achieve other performance characteristics that typically suggested. 9.2 Typical Application LDO1 EN_T VINLDO12 VDD I/O Voltage Domain 1 PF ENLDO1 100k ENLDO2 nPOR ENSW1 VIN1 SDA Advanced Power Controller 10 PF SCL ENSW2 2.2 PH LDO1 SW1 0.47 PF 10 PF FB1 VINLDO1 GND_SW1 Buck1 LP8731 1 PF VINLDO2 Core ADAS Domain Block LDO1 VIN2 1 PF 10 PF LDO2 2.2 PH 0.47 PF SW2 SDA Buck2 Peripheral ADAS Blocks 10 PF FB2 LDO2 SCL GND_SW2 GND_L GND_C Application System or SoC AVDD 1 PF Figure 25. LP8731-Q1 Simplified Schematic Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LP8731-Q1 37 LP8731-Q1 SNVSA28 – DECEMBER 2014 www.ti.com Typical Application (continued) 9.2.1 Design Requirements Table 5. Design Parameters DESIGN PARAMETER EXAMPLE VALUE Input voltage range 2.8 V to 5.5 V Switching frequency 2 MHz ±10% Output voltage range: bucks 0.8875 V to 1.675 V Output current rating: bucks 1.2 A Output voltage range: LDOs 0.8 V to 3.3 V Output current rating: LDOs 300 mA Transient response at max load with Tr = Tf = 10 µs ΔVOUT approximately equals ±1% Bucks output typical ripple voltage < 10 mV PWM, < 20 mV PFM 9.2.2 Detailed Design Procedure 9.2.2.1 Component Selection 9.2.2.1.1 Inductors for SW1 and SW2 There are two main considerations when choosing an inductor: the inductor should not saturate, and the inductor current ripple is small enough to achieve the desired output voltage ripple. Care should be taken when reviewing the different saturation current ratings that are specified by different manufacturers. Saturation current ratings are typically specified at 25°C, so ratings at maximum ambient temperature of the application should be requested from the manufacturer. There are two methods to choose the inductor saturation current rating: 9.2.2.1.1.1 Method 1: The saturation current is greater than the sum of the maximum load current and the worst case average to peak inductor current. This can be written as follows: Isat > Ioutmax + Iripple where Iripple = §1· ©f¹ x §VIN - VOUT· x § VOUT· © 2L ¹ © VIN ¹ where • • • • • • IRIPPLE: Average to peak inductor current IOUTMAX: Maximum load current VIN: Maximum input voltage to the buck L: Min inductor value including worse case tolerances (30% drop can be considered for method 1) ƒ: Minimum switching frequency (1.6 MHz) VOUT: Buck Output voltage (4) 9.2.2.1.1.2 Method 2: A more conservative and recommended approach is to choose an inductor that has saturation current rating greater than the maximum current limit of 1800 mA for Buck1 and Buck2. Given a peak-to-peak current ripple (IPP) the inductor needs to be at least: Lt 38 §VIN - VOUT· x § VOUT· x § 1 · © IPP ¹ © VIN ¹ © f ¹ (5) Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LP8731-Q1 LP8731-Q1 www.ti.com SNVSA28 – DECEMBER 2014 Table 6. Suggested Inductors INDUCTOR VALUE UNIT L × W × H (mm) DCR IRMS RATING TYP VENDORS PART ID LSW1,2 2.2 µH 3.2 × 2.5 × 1.2 70 mΩ 2.1 A Toko DFE322512C LSW1,2 2.2 µH 3.2 × 2.5 × 1.55 64 mΩ 1.85 A Murata LQH32PN2R2NNCL LSW1,2 2.2 µH 3.2 × 2.5 × 1.2 70 mΩ 2.1 A Chilisin MHCD322512-2R2M-A8DY LSW1,2 2.2 µH 5.0 × 5.0 × 1.5 70 mΩ 2A Taiyo Yuden NP04SZB 2R2N 9.2.2.1.2 External Capacitors The regulators on the LP8731-Q1 require external capacitors for regulator stability. These are specifically designed for portable applications requiring minimum board space and smallest components. These capacitors must be correctly selected for good performance. 9.2.2.2 LDO Capacitor Selection 9.2.2.2.1 Input Capacitor An input capacitor is required for stability. It is recommended that a 1-μF capacitor be connected between the LDO input pin and ground (this capacitance value may be increased without limit). This capacitor must be located a distance of not more than 1 cm from the input pin and returned to a clean analog ground. Any good quality ceramic, tantalum, or film capacitor may be used at the input. NOTE Tantalum capacitors can suffer catastrophic failures due to surge currents when connected to a low impedance source of power (like a battery or a very large capacitor). If a tantalum capacitor is used at the input, it must be ensured by the manufacturer to have a surge current rating sufficient for the application. There are no requirements for the ESR (Equivalent Series Resistance) on the input capacitor, but tolerance and temperature coefficient must be considered when selecting the capacitor to ensure the capacitance remains approximately 1 μF over the entire operating temperature range. 9.2.2.2.2 Output Capacitor The LDOs on the LP8731-Q1 are designed specifically to work with very small ceramic output capacitors. A 0.47µF ceramic capacitor (temperature types Z5U, Y5V or X7R) with ESR between 5 mΩ to 500 mΩ, is suitable in the application circuit. It is also possible to use tantalum or film capacitors at the device output, COUT (or VOUT), but these are not as attractive for reasons of size and cost. The output capacitor must meet the requirement for the minimum value of capacitance and also have an ESR value that is within the range 5 mΩ to 500 mΩ for stability. 9.2.2.2.3 Capacitor Characteristics The LDOs are designed to work with ceramic capacitors on the output to take advantage of the benefits they offer. For capacitance values in the range of 0.47 µF to 4.7 µF, ceramic capacitors are the smallest, least expensive, and have the lowest ESR values, thus making them best for eliminating high-frequency noise. The ESR of a typical 1-µF ceramic capacitor is in the range of 20 mΩ to 40 mΩ, which easily meets the ESR requirement for stability for the LDOs. For both input and output capacitors, careful interpretation of the capacitor specification is required to ensure correct device operation. The capacitor value can change greatly, depending on the operating conditions and capacitor type. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LP8731-Q1 39 LP8731-Q1 SNVSA28 – DECEMBER 2014 www.ti.com CAP VALUE (% of NOMINAL 1 PF) In particular, the output capacitor selection should take account of all the capacitor parameters, to ensure that the specification is met within the application. The capacitance can vary with DC bias conditions as well as temperature and frequency of operation. Capacitor values also show some decrease over time due to aging. The capacitor parameters are also dependent on the particular case size, with smaller sizes giving poorer performance figures in general. As an example, Figure 26 is typical graph comparing different capacitor case sizes in a capacitance vs DC bias plot. 0603, 10V, X5R 100% 80% 60% 0402, 6.3V, X5R 40% 20% 0 1.0 2.0 3.0 4.0 5.0 DC BIAS (V) Figure 26. Typical Variation In Capacitance vs DC Bias As shown in Figure 26, increasing the DC bias condition can result in the capacitance value that falls below the minimum value given in the recommended capacitor specifications table. Note that the graph shows the capacitance out of spec for the 0402 case size capacitor at higher bias voltages. It is therefore recommended that the capacitor manufacturers' specifications for the nominal value capacitor are consulted for all conditions, as some capacitor sizes (e.g. 0402) may not be suitable in the actual application. The ceramic capacitor’s capacitance can vary with temperature. The capacitor type X7R, which operates over a temperature range of −55°C to 125°C, only varies the capacitance to within ±15%. The capacitor type X5R has a similar tolerance over a reduced temperature range of −55°C to 85°C. Many large value ceramic capacitors, larger than 1 µF are manufactured with Z5U or Y5V temperature characteristics. Their capacitance can drop by more than 50% as the temperature varies from 25°C to 85°C. Therefore X7R is recommended over Z5U and Y5V in applications where the ambient temperature changes significantly above or below 25°C. Tantalum capacitors are less desirable than ceramic for use as output capacitors because they are more expensive when comparing equivalent capacitance and voltage ratings in the 0.47-µF to 4.7-µF range. Another important consideration is that tantalum capacitors have higher ESR values than equivalent size ceramics. This means that while it may be possible to find a tantalum capacitor with an ESR value within the stable range, it would have to be larger in capacitance (which means bigger and more costly) than a ceramic capacitor with the same ESR value. It should also be noted that the ESR of a typical tantalum increases about 2:1 as the temperature goes from 25°C down to −40°C, so some guard band must be allowed. 9.2.2.2.4 Input Capacitor Selection for SW1 And SW2 A ceramic input capacitor of 10 µF, 6.3 V is sufficient for the magnetic DC-DC converters. Place the input capacitor as close as possible to the input of the device. A large value may be used for improved input voltage filtering. The recommended capacitor types are X7R or X5R. Y5V type capacitors should not be used. DC bias characteristics of ceramic capacitors must be considered when selecting case sizes like 0805 and 0603. The input filter capacitor supplies current to the PFET switch of the DC-DC converter in the first half of each cycle and reduces voltage ripple imposed on the input power source. A ceramic capacitor’s low Equivalent Series Resistance (ESR) provides the best noise filtering of the input voltage spikes due to fast current transients. A capacitor with sufficient ripple current rating should be selected. The Input current ripple can be calculated as: Irms = Ioutmax VOUT VIN § 1 + r2 · © 12 ¹ where r= (Vin ± Vout) x Vout L x f x Ioutmax x Vin (6) The worse case is when VIN = 2 × VOUT. 40 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LP8731-Q1 LP8731-Q1 www.ti.com SNVSA28 – DECEMBER 2014 9.2.2.2.5 Output Capacitor Selection for SW1, SW2 A 10-μF, 6.3-V ceramic capacitor should be used on the output of the SW1 and SW2 magnetic DC-DC converters. The output capacitor needs to be mounted as close as possible to the output of the device. A large value may be used for improved input voltage filtering. The recommended capacitor types are X7R or X5R. Y5V type capacitors should not be used. DC bias characteristics of ceramic capacitors must be considered when selecting case sizes like 0805 and 0603. DC bias characteristics vary from manufacturer to manufacturer and DC bias curves should be requested from them and analyzed as part of the capacitor selection process. The output filter capacitor of the magnetic DC-DC converter smooths out current flow from the inductor to the load, helps maintain a steady output voltage during transient load changes and reduces output voltage ripple. These capacitors must be selected with sufficient capacitance and sufficiently low ESD to perform these functions. The output voltage ripple is caused by the charging and discharging of the output capacitor and also due to its ESR and can be calculated as follows: Vpp-c = Iripple 4xfxC (7) Voltage peak-to-peak ripple due to ESR can be expressed as follows: VPP–ESR = 2 × IRIPPLE × RESR (8) Because the VPP-C and VPP-ESR are out of phase, the rms value can be used to get an approximate value of the peak-to-peak ripple: Vpp-rms = Vpp-c2 + Vpp-esr2 (9) NOTE The output voltage ripple is dependent on the inductor current ripple and the equivalent series resistance of the output capacitor (RESR). The RESR is frequency dependent as well as temperature dependent. The RESR should be calculated with the applicable switching frequency and ambient temperature. Table 7. Suggested Capacitors CAPACITOR VALUE L × W × H (mm) TYPE TOLERANCE VENDORS PART ID CLDO1, CLDO2 0.47 µF 1.0 × 0.5 × 0.5 (0402) X7S, 10 V 10% Murata GCM155C71A474KE36 CSW1, CSW2 10 µF 3.2 × 1.6 × 1.6 (1206) X7R, 16 V 20% TDK C3216XR71C106M CSW1, CSW2 10 µF 2 × 1.25 × 1.45 (0805) X5R, 16 V 20% TDK CGA4J1X5R1C106M125AC CIN 1 µF 0.6 × 0.3 × 0.1 (0603) X7R, 6.3 V 20% TDK C2012XR71C105K CIN 1 µF 1.0 × 0.5× 0.5 (0402) X7S, 10 V 10% Murata GCM155C71A105KE38 9.2.2.2.6 I2C Pull-up Resistor Both SDA and SCL pins need to have pull-up resistors connected to VINLDO12 or to the power supply of the I2C master. The values of the pull-up resistors (typical approximately1.8 kΩ) are determined by the capacitance of the bus. Too large of a resistor combined with a given bus capacitance results in a rise time that would violate the maximum rise time specification. A too small resistor results in a contention with the pull-down transistor on either slave(s) or master. 9.2.2.2.7 Operation Without I2C Interface Operation of the LP8731-Q1 without the I2C interface is possible if the system can operate with default values for the LDO and buck regulators. The I2C-less system must rely on the correct default output values of the LDO and Buck converters. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LP8731-Q1 41 LP8731-Q1 SNVSA28 – DECEMBER 2014 www.ti.com 9.2.2.3 Junction Temperature The maximum junction temperature TJ-MAX-OP is 125°C of the IC package. The following equations demonstrate junction temperature determination, ambient temperature TA-MAX, and total device power must be controlled to keep TJ below this maximum: TJ-MAX-OP = TA-MAX + (RθJA) [°C/ Watt] * (PD-MAX) [Watts] Total IC power dissipation PD-MAX is the sum of the individual power dissipation of the four regulators plus a minor amount for device overhead. Device overhead is Bias, TSD and LDO analog. PD-MAX = PLDO1 + PLD02 + PBUCK1 + PBUCK2 + (0.0001 A × VIN) [Watts]. Power dissipation of LDO1 PLDO1 = (VINLDO1 – VOUTLDO1) × IOUTLDO1 [V × A] Power dissipation of LDO2 PLDO2 = (VINLDO2 – VOUTLDO2) × IOUTLDO2 [V × A] Power dissipation of Buck1 PBuck1 = PIN – POUT = VOUTBuck1 × IOUTBuck1 × (1 -η1) / η1 [V × A] η1 = efficiency of buck 1 Power dissipation of Buck2 PBuck2 = PIN – POUT = VOUTBuck2 × IOUTBuck2 × (1 - η2) / η2 [V × A] η2 = efficiency of Buck2 Where η is the efficiency for the specific condition taken from efficiency graphs. 9.2.3 Application Curves (LDO) Vin Step (500 mV/DIV) EN LDO (2 V/DIV) Vout LDO (1 V/DIV) Vout LDO (10 mV/DIV) Iin_rush (200 mA/DIV) Time (100 µs/DIV) VIN = 3.6 V to 4.2 V VOUT = 1.8 V Time (100 µs/DIV) IOUT = 300 mA Tr = Tf = 30 µs Figure 27. Line Transient 300-mA, 30-µs Edge Rate 42 VIN = 3.6 V VOUT = 1.8 V IOUT = 200 mA EN Tr = 18 ns Figure 28. LDO Enable Start-Up Time and Inrush Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LP8731-Q1 LP8731-Q1 www.ti.com SNVSA28 – DECEMBER 2014 9.2.4 Application Curves (BUCK) Vin Step (500 mV/DIV) Buck-2 (20 mV/DIV) Iout (200 mA/DIV) Vout LDO (20 mV/DIV) Time (50 µs/DIV) Time (50 µs/DIV) IOUT = 300 mA to 500 mA PWM VIN Step Figure 29. Buck Load Transient PWM Mode IOUT = 300 mA Tr = Tf = 30 µs Figure 30. Buck Line Transient PWM 10 Power Supply Recommendations The device is designed to operate from an input voltage supply range between 2.8 V and 5.5 V. This input supply may be a battery or regulated source with sufficient low internal resistance such that it is able to deliver the maximum input current and maintain stable voltage without significant voltage drop during start-up and at load transient conditions. Additional bulk capacitance may be necessary should the supply source is located more than five centimeters away from the LP8731-Q1. 10.1 Analog Power Signal Routing All power inputs should be tied to the main VDD source (for example, battery), unless the user wishes to power it from another source. (that is, external LDO output). The analog VDD input pins power the internal bias and error amplifiers, so they should be tied to the main VDD. The analog VDD inputs must have an input voltage between 2.8 and 5.5 V, as specified in the General Electrical Characteristics table. The other input pins (VINLDO1, VINLDO2, VIN1, and VIN2) can actually have inputs lower than 2.8 V, as long as it is higher than the programmed output (0.3 V, to be safe). The analog and digital grounds should be tied together outside of the device to reduce noise coupling. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LP8731-Q1 43 LP8731-Q1 SNVSA28 – DECEMBER 2014 www.ti.com 11 Layout 11.1 Layout Guidelines The LP8731-Q1 is a monolithic device with integrated power FETs. For that reason, it is important to pay special attention to the use of appropriate to input, output, power, and ground track dimensions in the PCB layout in order to achieve low impedance small current loop paths and tracks with adequate current density to carry the target currents. The device pin solder bumps are arranged with power and ground bumps at the edges of the package to facilitate PCB layout considerations. This enables using the top metal layer to route the power and ground tracks. Thus, the current loops for the bucks can be very short and this also makes placing the bypass caps on the device side of the PCB possible. (See Figure 31.) Avoid using vias to tap power and ground planes for the switcher supply pins, because they can be very inductive and could incur large i*dv/dt transient voltage drops. If vias are unavoidable, use them liberally to minimize the impedance they may present. For more information on board layout techniques, refer to Texas Instruments AN-1112 DSBGA Wafer Level Chip Scale Package (SNVA009). This application note also discusses recommended PCB pad geometry, package handling, solder stencil and the assembly process. See also Texas Instruments AN-1229 SIMPLE SWITCHER® PCB Layout Guidelines (SNVA054) and Texas Instruments AN-2078 PCB Layout for Texas Instrument' SIMPLE SWITCHER® Power Modules (SNVA452). 11.2 Layout Example All CIN and COUT caps should be placed as close to VIN, VOUT and GND pads as practical. CINLDO12 CINLDO2 COUTLDO2 COUTLDO1 CINLDO1 VIN, SW, VOUT, GND, CIN and COUT tracks be Suitably sized for low Impedance path and carry the target current. GND2 GND1 CINBK2 CINBK1 COUTBK1 COUTBK2 BUCK2 BUCK1 L2 L1 VIN2 VIN1 Figure 31. LP8731-Q1 Layout Example 44 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LP8731-Q1 LP8731-Q1 www.ti.com SNVSA28 – DECEMBER 2014 12 Device and Documentation Support 12.1 Device Support 12.1.1 Third-Party Products Disclaimer TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE. 12.2 Documentation Support 12.2.1 Related Documentation For related documentation, see the following: Texas Instruments AN-1112 DSBGA Wafer Level Chip Scale Package (SNVA009). Texas Instrument AN-1229 SIMPLE SWITCHER® PCB Layout Guidelines (SNVA054). Texas Instruments AN-2078 PCB Layout for Texas Instrument'sSIMPLE SWITCHER® Power Modules (SNVA452). 12.3 Trademarks SIMPLE SWITCHER is a registered trademark of Texas Instruments Incorporated. All other trademarks are the property of their respective owners. 12.4 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 12.5 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LP8731-Q1 45 PACKAGE OPTION ADDENDUM www.ti.com 18-Dec-2014 PACKAGING INFORMATION Orderable Device Status (1) LP8731QYZRRQ1 ACTIVE Package Type Package Pins Package Drawing Qty DSBGA YZR 25 3000 Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM Op Temp (°C) Device Marking (4/5) -40 to 125 RAEQ (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 18-Dec-2014 Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 19-Dec-2014 TAPE AND REEL INFORMATION *All dimensions are nominal Device LP8731QYZRRQ1 Package Package Pins Type Drawing SPQ DSBGA 3000 YZR 25 Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 178.0 8.4 Pack Materials-Page 1 2.69 B0 (mm) K0 (mm) P1 (mm) 2.69 0.76 4.0 W Pin1 (mm) Quadrant 8.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 19-Dec-2014 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LP8731QYZRRQ1 DSBGA YZR 25 3000 210.0 185.0 35.0 Pack Materials-Page 2 MECHANICAL DATA YZR0025xxx 0.600±0.075 D E TLA25XXX (Rev D) D: Max = 2.521 mm, Min = 2.46 mm E: Max = 2.521 mm, Min = 2.46 mm 4215055/A NOTES: A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994. B. 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