Sample & Buy Product Folder Technical Documents Support & Community Tools & Software LP3990 SNVS251J – MAY 2004 – REVISED SEPTEMBER 2014 LP3990 150-mA Linear Voltage Regulator for Digital Applications 1 Features 3 Description • • • • • • • • • • • • • • The LP3990 regulator is designed to meet the requirements of portable, battery-powered systems providing an accurate output voltage, low-noise, and low-quiescent current. The LP3990 will provide a 0.8V output from the low input voltage of 2 V at up to a 150-mA load current. When switched into shutdown mode via a logic signal at the enable pin (EN), the power consumption is reduced to virtually zero. 1 1% Voltage Accuracy at Room Temperature Stable with Ceramic Capacitor Logic Controlled Enable No Noise Bypass Capacitor Required Thermal-Overload and Short-Circuit Protection Input Voltage Range, 2 V to 6 V Output Voltage Range, 0.8 V to 3.3 V Output Current, 150 mA Output Stable - Capacitors, 1 µF Virtually Zero IQ (Disabled), < 10 nA Very Low IQ (Enabled), 43 µA Low Output Noise, 150 µVRMS PSRR, 55 dB at 1 kHz Fast Start-Up, 105 µs The LP3990 is designed to be stable with spacesaving ceramic capacitors with values as low as 1 µF. Performance is specified for a –40°C to 125°C junction temperature range. For output voltages other than 0.8 V, 1.2 V, 1.35 V, 1.5 V, 1.8 V, 2.5 V, 2.8 V, or 3.3 V, please contact the Texas Instruments sales office. Device Information(1) PART NUMBER 2 Applications • • Cellular Handsets Hand-Held Information Appliances LP3990 PACKAGE BODY SIZE (NOM) DSBGA (4) 1.324 mm x 1.045 mm (MAX) WSON (6) 2.90 mm x 1.60 mm SOT-23 (5) 3.00 mm x 3.00 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. Simplified Schematic VIN IN CIN 1 µF LP3990 VEN ON OFF GND VOUT OUT COUT 1 µF EN GND GND 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LP3990 SNVS251J – MAY 2004 – REVISED SEPTEMBER 2014 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 4 4 4 4 5 6 6 7 Absolute Maximum Ratings ...................................... Handling Ratings ...................................................... Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Output Capacitor, Recommended Specifications ..... Timing Requirements ................................................ Typical Performance Characteristics ........................ 7.3 Feature Description................................................... 9 7.4 Device Functional Modes........................................ 10 8 Application and Implementation ........................ 11 8.1 Application Information............................................ 11 8.2 Typical Application ................................................. 11 9 Power Supply Recommendations...................... 14 10 Layout................................................................... 14 10.1 10.2 10.3 10.4 Layout Guidelines ................................................. Layout Examples................................................... DSBGA Mounting.................................................. DSBGA Light Sensitivity ....................................... 14 15 16 16 11 Device and Documentation Support ................. 17 Detailed Description .............................................. 9 11.1 Trademarks ........................................................... 17 11.2 Electrostatic Discharge Caution ............................ 17 11.3 Glossary ................................................................ 17 7.1 Overview ................................................................... 9 7.2 Functional Block Diagram ......................................... 9 12 Mechanical, Packaging, and Orderable Information ........................................................... 17 4 Revision History Changes from Revision I (May 2013) to Revision J • 2 Page Added Device Information and Handling Rating tables, Feature Description, Device Functional Modes, Application and Implementation, Power Supply Recommendations, Layout, Device and Documentation Support, and Mechanical, Packaging, and Orderable Information sections; moved some curves to Application Curves section .............. 1 Submit Documentation Feedback Copyright © 2004–2014, Texas Instruments Incorporated Product Folder Links: LP3990 LP3990 www.ti.com SNVS251J – MAY 2004 – REVISED SEPTEMBER 2014 5 Pin Configuration and Functions 4 Pins DSBGA (YZR) 5 Pins SOT-23 (DBV) EN A2 IN B2 IN B2 EN A2 A1 GND B1 OUT B1 OUT A1 GND TOP VIEW EN 3 4 N/C BOTTOM VIEW IN 6 EN 5 N/C 4 WSON (NGG) 6 Pins N/C 4 2 GND EN 5 IN 1 5 OUT IN 6 Thermal DAP (Thermal DAP) 1 OUT GND 2 3 N/C 3 N/C TOP VIEW 2 GND 1 OUT BOTTOM VIEW Pin Functions PIN DSBGA SOT-23 WSON NAME YZR DBV NGG GND A1 2 2 EN A2 3 5 I/O — DESCRIPTION Common Ground. I Enable Input; Enables the Regulator when ≥ 0.95 V. Disables the Regulator when ≤ 0.4 V. Enable Input has 1-MΩ (typical) pull-down resistor to GND. O Voltage output. A 1-µF Low ESR Capacitor should be connected to this Pin. Connect this output to the load circuit. OUT B1 5 1 IN B2 1 6 I Voltage supply Input. A 1-µF capacitor should be connected at this input. 4 3 I No internal connection. 4 I No internal connection. Pad — N/C N/C N/A N/A Thermal pad. Connect to Pin 2. Submit Documentation Feedback Copyright © 2004–2014, Texas Instruments Incorporated Product Folder Links: LP3990 3 LP3990 SNVS251J – MAY 2004 – REVISED SEPTEMBER 2014 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings (1) (2) (3) over operating free-air temperature range (unless otherwise noted) MIN MAX Input voltage –0.3 6.5 Output voltage –0.3 Note (4) ENABLE input voltage –0.3 6.5 (2) (3) (4) (5) V Note (5) Continuous power dissipation internally limited (1) UNIT Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications. All voltages are with respect to the potential at the GND pin. The lower of VIN + 0.3 V or 6.5 V. Internal thermal shutdown circuitry protects the device from permanent damage. 6.2 Handling Ratings Tstg MIN MAX UNIT –65 150 °C –2000 2000 Charged device model (CDM), per JEDEC specification JESD22C101, all pins 250 1500 Machine model –200 200 Storage temperature range Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) V(ESD) (1) Electrostatic discharge V JEDEC document JEP155 states that 2000-V HBM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN Input voltage, VIN Enable input voltage, VEN Junction temperature, TJ (1) (1) NOM MAX 2 6 0.0 VIN –40 125 UNIT V °C TJ(max) = (TA(max) + (RθJA × PD(max)) ) 6.4 Thermal Information LP3990 THERMAL METRIC (1) YZR (DSBGA) DBV (SOT-23) NGG (WSON) 4 PINS 5 PINS 6 PINS 188.9 165.2 53.9 1.0 69.9 51.2 105.3 27.3 28.2 0.7 1.8 0.6 RθJA Junction-to-ambient thermal resistance RθJC(top) Junction-to-case (top) thermal resistance RθJB Junction-to-board thermal resistance ψJT Junction-to-top characterization parameter ψJB Junction-to-board characterization parameter 105.2 26.8 28.3 RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A 8.1 (1) 4 UNIT °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2004–2014, Texas Instruments Incorporated Product Folder Links: LP3990 LP3990 www.ti.com SNVS251J – MAY 2004 – REVISED SEPTEMBER 2014 6.5 Electrical Characteristics (1) (2) Unless otherwise noted, VEN = 950 mV, VIN = VOUT + 1 V or VIN = 2 V, whichever is higher. CIN = 1 µF, IOUT = 1 mA, COUT = 0.47 µF. PARAMETER VIN Input voltage TEST CONDITIONS Note (3) , TJ = 25°C Output voltage tolerance Over full line and load regulation Line regulation error VDO Dropout voltage ILOAD Load current –1 1% –1.5% 1.5% SOT-23 –1.5% 1.5% DSBGA –2.5% 2.5% WQFN –3% 3% SOT-23 –4% 0.02 0.1 VOUT = 0.8 V to 1.95 V DSBGA –0.005 0.002 0.005 VOUT = 0.8 V to 1.95 V WQFN, SOT-23 –0.008 0.003 0.008 VOUT = 2 V to 3.3 V DSBGA –0.002 0.0005 0.002 VOUT = 2 V to 3.3 V WQFN, SOT-23 –0.005 0.002 0.005 120 200 VEN = 950 mV, IOUT = 0 mA 43 80 VEN = 950 mV, IOUT = 150 mA 65 120 IOUT = 150 mA (4) Note (5) (5) (6) , TJ = 25°C Short circuit current limit IOUT Maximum output current PSRR Power Supply Rejection Ratio ƒ = 1 kHz, IOUT = 1 mA to 150 mA 55 ƒ = 10 kHz, IOUT = 150 mA 35 eη Output noise voltage (5) BW = 10 Hz to 100 kHz VEN = 0.4 V (output disabled), TJ = 25°C (1) (2) (3) (4) (5) (6) (7) %/mA mV µA ISC Thermal shutdown junction temperature %/V 0 Quiescent current Note V 4% 0.1 IOUT = 1 mA to 150 mA UNIT 6 IQ TSHUTDOWN MAX WQFN VIN = (VOUT(NOM) + 1 V) to 6 V ΔVOUT Load regulation error TYP 2 DSBGA ILOAD = 1 mA TJ = 25°C MIN (7) 0.002 0.2 550 1000 µA mA 150 VOUT = 0.8 V 60 VOUT = 1.5 V 125 VOUT = 3.3 V 180 Junction temperature (TJ) rising until the output is disabled Hysteresis dB µVRMS 155 °C 15 All voltages are with respect to the device GND terminal, unless otherwise stated. Minimum and Maximum limits are ensured through test, design, or statistical correlation over the operating junction temperature range (TJ) of –40°C to 125°C, unless otherwise stated. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. VIN(MIN) = VOUT(NOM) + 0.5 V, or 2 V, whichever is higher. Dropout voltage is voltage difference between input and output at which the output voltage drops to 100 mV below its nominal value. This parameter applies only for output voltages above 2 V. This electrical specification is verified by design. The device maintains the regulated output voltage without the load. Short-circuit current is measured with VOUT pulled to 0 V and VIN worst case = 6 V. Submit Documentation Feedback Copyright © 2004–2014, Texas Instruments Incorporated Product Folder Links: LP3990 5 LP3990 SNVS251J – MAY 2004 – REVISED SEPTEMBER 2014 www.ti.com Electrical Characteristics(1)(2) (continued) Unless otherwise noted, VEN = 950 mV, VIN = VOUT + 1 V or VIN = 2 V, whichever is higher. CIN = 1 µF, IOUT = 1 mA, COUT = 0.47 µF. PARAMETER TEST CONDITIONS MIN TYP MAX 0.001 0.1 6 10 UNIT ENABLE CONTROL CHARACTERISTICS Maximum input current at EN pin IEN (8) VIL VIH (8) VEN = 0 V (Output is disabled) TJ = 25°C VEN = 6 V 2.5 Low input threshold VIN = 2 V to 6 V VEN falling from ≥ VIH until the output is disabled High input threshold VIN = 2 V to 6 V VEN rising from ≤ VIL until the output is enabled µA 0.4 V 0.95 ENABLE Pin has 1-MΩ (typical) resistor connected to GND. 6.6 Output Capacitor, Recommended Specifications (1) PARAMETER COUT (1) (2) (3) Output capacitance TEST CONDITIONS Capacitance (2) MIN TYP MAX UNIT 0.7 (3) 1 500 µF ESR 5 mΩ Unless otherwise specified, values and limits apply for TJ = 25°C. The full operating conditions for the application should be considered when selecting a suitable capacitor to ensure that the minimum value of capacitance is always met. Recommended capacitor type is X7R. However, dependent on application, X5R, Y5V, and Z5U can also be used. (See Detailed Design Procedure.) Limit applies over the full operating junction temperature range (TJ) of −40°C to 125°C. 6.7 Timing Requirements NOM (1) MAX (2) VOUT = 0.8 V 80 150 VOUT = 1.5 V 105 200 VOUT = 3.3 V 175 250 8 16 mV (pkpk) 55 100 mV MIN TON Turnon time Transient response (1) (2) (3) 6 (3) From VEN ↑ VIH to VOUT 95% level (VIN(MIN) to 6 V) Line transient response (ΔVOUT) Trise = Tfall = 30 µs (3), ΔVIN = 600 mV Load transient response (ΔVOUT) Trise = Tfall = 1 µs (3), IOUT = 1 mA to 150 mA COUT = 1 µF UNIT µs Nom values apply for TJ = 25°C. Maximum limits apply over the full operating junction temperature (TJ) range of −40°C to 125°C. This electrical specification is verified by design. Submit Documentation Feedback Copyright © 2004–2014, Texas Instruments Incorporated Product Folder Links: LP3990 LP3990 www.ti.com SNVS251J – MAY 2004 – REVISED SEPTEMBER 2014 6.8 Typical Performance Characteristics 2.00 80 1.50 70 GROUND CURRENT (PA) VOUT CHANGE (%) Unless otherwise specified, CIN = 1 µF ceramic, COUT = 0.47 µF ceramic, VIN = VOUT(NOM) + 1 V, TA = 25°C, VOUT(NOM) = 1.5 V; VEN = VIN. 1.00 0.50 0.00 -0.50 -1.00 -1.50 TJ = 125°C 60 50 40 TJ = -40°C 30 TJ = 25°C 20 10 -2.00 -40 -25 0 25 50 75 100 0 125 0 25 TEMPERATURE (°C) 75 100 90 90 80 80 70 70 60 TJ = 125°C 125 150 60 TJ = 125°C 50 TJ = 25°C TJ = 25°C 40 40 TJ = -40°C 30 TJ = -40°C 30 20 20 2 2.5 3 3.5 4 4.5 5 5.5 6 2 2.5 3 VIN 3.5 4 4.5 5 5.5 6 VIN ILOAD = 0 mA ILOAD = 1 mA Figure 3. Ground Current vs VIN Figure 4. Ground Current vs VIN 100 VIN = 2.5V 800 90 80 TJ = 125°C CURRENT (mA) GND I (µA) 100 Figure 2. Ground Current vs Load Current 100 GND I (PA) GND I (PA) Figure 1. Output Voltage Change vs Temperature 50 50 LOAD CURRENT (mA) 70 TJ = 25°C 60 TJ = -40°C 50 600 400 200 0 VOUT 30 20 2 2.5 3 3.5 4 4.5 5 5.5 (1V/Div) 40 6 TIME (100 Ps/DIV) VIN ILOAD = 150 mA Figure 6. Short Circuit Current Figure 5. Ground Current vs VIN Submit Documentation Feedback Copyright © 2004–2014, Texas Instruments Incorporated Product Folder Links: LP3990 7 LP3990 SNVS251J – MAY 2004 – REVISED SEPTEMBER 2014 www.ti.com Typical Performance Characteristics (continued) Unless otherwise specified, CIN = 1 µF ceramic, COUT = 0.47 µF ceramic, VIN = VOUT(NOM) + 1 V, TA = 25°C, VOUT(NOM) = 1.5 V; VEN = VIN. CIN = 1 PF VIN = 6V COUT = 0.47 PF IL = 1 to 150 mA VIN (V) 600 400 2.5 200 (1V/Div) 'VOUT 0 VOUT 3.1 (10 mV/Div) CURRENT (mA) 800 TIME (100 Ps/DIV) TIME (100 Ps/DIV) Figure 7. Short Circuit Current Figure 8. Line Transient 0 0 -10 COUT = 0.47 PF -20 RIPPLE REJECTION (dB) RIPPLE REJECTION (dB) -10 -30 IL = 1 mA -40 -50 COUT = 1 PF -60 -70 -80 100 1k 10k 100k -50 COUT = 0.47 PF -60 -70 -80 100 1k 10k 100k 1M FREQUENCY (Hz) FREQUENCY (Hz) Figure 9. Power Supply Rejection Ratio Figure 10. Power Supply Rejection Ratio 10 (500 mV/Div) NOISE (PV/ Hz) VOUT = 3.3V (1V/Div) VOUT ILOAD = 150 mA -40 1M IL = 1 mA VEN -30 -90 -90 1 VOUT = 1.5V 0.1 0.01 0.1 TIME (50 Ps/DIV) 1 10 100 FREQUENCY (kHz) Figure 11. Enable Start-Up Time 8 COUT = 1 PF -20 Figure 12. Noise Density Submit Documentation Feedback Copyright © 2004–2014, Texas Instruments Incorporated Product Folder Links: LP3990 LP3990 www.ti.com SNVS251J – MAY 2004 – REVISED SEPTEMBER 2014 7 Detailed Description 7.1 Overview Designed meet the requirements of portable, battery-powered digital systems providing an accurate output voltage with fast start-up. When disabled via a low logic signal at the enable pin (EN), the power consumption is reduced to virtually zero The LP3990 is designed to perform with a single 1-μF input capacitor and a single 1-μF ceramic output capacitor. 7.2 Functional Block Diagram LP3990 IN OUT Current Limit Thermal Shutdown + ON VREF 800 mV OFF EN 1M GND 7.3 Feature Description 7.3.1 Enable (EN) The LP3990 Enable (EN) pin is internally held low by a 1-MΩ resistor to GND. The EN pin voltage must be higher than the VIH threshold to ensure that the device is fully enabled under all operating conditions. The EN pin voltage must be lower than the VIL threshold to ensure that the device is fully disabled. If the EN pin is left open the LP3990 output will be disabled. 7.3.2 Thermal Overload Protection (TSD) Thermal Shutdown disables the output when the junction temperature rises to approximately 155°C which allows the device to cool. When the junction temperature cools to approximately 140°C, the output circuitry enables. Based on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may cycle on and off. This thermal cycling limits the dissipation of the regulator and protects it from damage as a result of overheating. The Thermal Shutdown circuitry of the LP3990 has been designed to protect against temporary thermal overload conditions. The Thermal Shutdown circuitry was not intended to replace proper heat-sinking. Continuously running the LP3990 device into thermal shutdown may degrade device reliability. Submit Documentation Feedback Copyright © 2004–2014, Texas Instruments Incorporated Product Folder Links: LP3990 9 LP3990 SNVS251J – MAY 2004 – REVISED SEPTEMBER 2014 www.ti.com 7.4 Device Functional Modes 7.4.1 Enable (EN) The LP3990 EN pin is internally held low by a 1-MΩ resistor to GND. The EN pin voltage must be higher than the VIH threshold to ensure that the device is fully enabled under all operating conditions. 7.4.2 Minimum Operating Input Voltage (VIN) The LP3990 does not include any dedicated UVLO circuitry. The LP3990 internal circuitry is not fully functional until VIN is at least 2 V. The output voltage is not regulated until VIN ≥ (VOUT + VDO), or 2 V, whichever is higher. 10 Submit Documentation Feedback Copyright © 2004–2014, Texas Instruments Incorporated Product Folder Links: LP3990 LP3990 www.ti.com SNVS251J – MAY 2004 – REVISED SEPTEMBER 2014 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The LP3990 is a linear voltage regulator for digital applications designed to be stable with space-saving ceramic capacitors as small as 1 µF. 8.2 Typical Application Figure 13 shows the typical application circuit for the LP3990. The input and output capacitances may need to be increased above the 1 μF shown for some applications. VIN IN CIN 1 µF LP3990 VEN ON VOUT OUT COUT 1 µF EN OFF GND GND GND Figure 13. LP3990 Typical Application 8.2.1 Design Requirements DESIGN PARAMETER EXAMPLE VALUE Input voltage range 2 V to 6 V Output voltage 1.8 V Output current 100 mA Output capacitor range 1 µF Input/output capacitor ESR range 5 mΩ to 500 mΩ 8.2.2 Detailed Design Procedure To • • • • begin the design process, determine the following: Available input voltage range Output voltage needed Output current needed Input and output capacitors 8.2.2.1 Power Dissipation and Device Operation The permissible power dissipation for any package is a measure of the capability of the device to pass heat from the power source, the junctions of the IC, to the ultimate heat sink, the ambient environment. Thus, the power dissipation is dependent on the ambient temperature and the thermal resistance across the various interfaces between the die junction and ambient air. The maximum allowable power dissipation for the device in a given package can be calculated using Equation 1: PD-MAX = ((TJ-MAX - TA) / RθJA) (1) Submit Documentation Feedback Copyright © 2004–2014, Texas Instruments Incorporated Product Folder Links: LP3990 11 LP3990 SNVS251J – MAY 2004 – REVISED SEPTEMBER 2014 www.ti.com The actual power being dissipated in the device can be represented by Equation 2: PD = (VIN - VOUT) x IOUT (2) These two equations establish the relationship between the maximum power dissipation allowed due to thermal consideration, the voltage drop across the device, and the continuous current capability of the device. These two equations should be used to determine the optimum operating conditions for the device in the application. In applications where lower power dissipation (PD) and/or excellent package thermal resistance (RθJA) is present, the maximum ambient temperature (TA-MAX) may be increased. In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature (TA-MAX) may have to be derated. TA-MAX is dependent on the maximum operating junction temperature (TJ-MAX-OP = 125°C), the maximum allowable power dissipation in the device package in the application (PD-MAX), and the junction-to ambient thermal resistance of the part/package in the application (RθJA), as given by Equation 3: TA-MAX = (TJ-MAX-OP – (RθJA × PD-MAX)) (3) Alternately, if TA-MAX can not be derated, the PD value must be reduced. This can be accomplished by reducing VIN in the 'VIN–VOUT' term as long as the minimum VIN is met, or by reducing the IOUT term, or by some combination of the two. 8.2.2.2 External Capacitors In common with most regulators, the LP3990 requires external capacitors for regulator stability. The LP3990 is specifically designed for portable applications requiring minimum board space and smallest components. These capacitors must be correctly selected for good performance. 8.2.2.3 Input Capacitor An input capacitor is required for stability. It is recommended that a 1-µF capacitor be connected between the LP3990 IN pin and GND pin (this capacitance value may be increased without limit). This capacitor must be located a distance of not more than 1 cm from the IN pin and returned to a clean analogue ground. Any good quality ceramic, tantalum, or film capacitor may be used at the input. Important: To ensure stable operation it is essential that good PCB design practices are employed to minimize ground impedance and keep input inductance low. If these conditions cannot be met, or if long leads are used to connect the battery or other power source to the LP3990, then it is recommended that the input capacitor is increased. Also, tantalum capacitors can suffer catastrophic failures due to surge current when connected to a low-impedance source of power (like a battery or a very large capacitor). If a tantalum capacitor is used at the input, it must be ensured by the manufacturer to have a surge current rating sufficient for the application. There are no requirements for the ESR (Equivalent Series Resistance) on the input capacitor, but tolerance and temperature coefficient must be considered when selecting the capacitor to ensure the capacitance will remain approximately 1 µF over the entire operating temperature range. 8.2.2.4 Output Capacitor The LP3990 is designed specifically to work with very small ceramic output capacitors. A 1-µF ceramic capacitor (temperature types Z5U, Y5V or X7R/X5R) with ESR between 5 mΩ to 500 mΩ, is suitable in the LP3990 application circuit. For this device the output capacitor should be connected between the OUT pin and GND pin. It is also possible to use tantalum or film capacitors at the device output, but these are not as attractive for reasons of size and cost (see Capacitor Characteristics). The output capacitor must meet the requirement for the minimum value of capacitance and also have an ESR value that is within the range 5 mΩ to 500 mΩ for stability. 8.2.2.5 No-Load Stability The LP3990 will remain stable and in regulation with no external load. This is an important consideration in some circuits, for example CMOS RAM keep-alive applications. 12 Submit Documentation Feedback Copyright © 2004–2014, Texas Instruments Incorporated Product Folder Links: LP3990 LP3990 www.ti.com SNVS251J – MAY 2004 – REVISED SEPTEMBER 2014 8.2.2.6 Capacitor Characteristics The LP3990 is designed to work with ceramic capacitors on the output to take advantage of the benefits they offer. For capacitance values in the range of 0.47 µF to 4.7 µF, ceramic capacitors are the smallest, least expensive and have the lowest ESR values, thus making them best for eliminating high frequency noise. The ESR of a typical 1-µF ceramic capacitor is in the range of 20 mΩ to 40 mΩ, which easily meets the ESR requirement for stability for the LP3990. For both input and output capacitors, careful interpretation of the capacitor specification is required to ensure correct device operation. The capacitor value can change greatly, depending on the operating conditions and capacitor type. CAP VALUE (% of NOMINAL 1 PF) In particular, the output capacitor selection should take account of all the capacitor parameters, to ensure that the specification is met within the application. The capacitance can vary with DC bias conditions as well as temperature and frequency of operation. Capacitor values will also show some decrease over time due to aging. The capacitor parameters are also dependant on the particular case size, with smaller sizes giving poorer performance figures in general. As an example, Figure 14 shows a typical graph comparing different capacitor case sizes in a Capacitance vs. DC Bias plot. As shown in the graph, increasing the DC Bias condition can result in the capacitance value falling below the minimum value given in the recommended capacitor specifications table (0.7 µF in this case). Note that the graph shows the capacitance out of spec for the 0402 case size capacitor at higher bias voltages. It is therefore recommended that the capacitor manufacturers’ specifications for the nominal value capacitor are consulted for all conditions, as some capacitor sizes (for example, 0402) may not be suitable in the actual application. 0603, 10V, X5R 100% 80% 60% 0402, 6.3V, X5R 40% 20% 0 1.0 2.0 3.0 4.0 5.0 DC BIAS (V) Figure 14. Graph Showing A Typical Variation In Capacitance vs DC Bias The ceramic capacitor’s capacitance can vary with temperature. The capacitor type X7R, which operates over a temperature range of –55°C to 125°C, will only vary the capacitance to within ±15%. The capacitor type X5R has a similar tolerance over a reduced temperature range of –55°C to 85°C. Many large value ceramic capacitors, larger than 1 µF are manufactured with Z5U or Y5V temperature characteristics. Their capacitance can drop by more than 50% as the temperature varies from 25°C to 85°C. Therefore, X7R and X5R types are recommended over Z5U and Y5V in applications where the ambient temperature will change significantly above or below 25°C. Tantalum capacitors are less desirable than ceramic for use as output capacitors because they are more expensive when comparing equivalent capacitance and voltage ratings in the 0.47-µF to 4.7-µF range. Another important consideration is that tantalum capacitors have higher ESR values than equivalent size ceramics. This means that while it may be possible to find a tantalum capacitor with an ESR value within the stable range, it would have to be larger in capacitance (which means bigger and more costly) than a ceramic capacitor with the same ESR value. It should also be noted that the ESR of a typical tantalum will increase about 2:1 as the temperature goes from 25°C down to -40°C, so some guard band must be allowed. 8.2.2.7 Enable Control The LP3990 features an active high Enable pin, EN, which turns the device on when pulled high. When not enabled the regulator output is off and the device typically consumes 2 nA. If the application does not require the Enable switching feature, the EN pin should be tied to VIN to keep the regulator output permanently on. Submit Documentation Feedback Copyright © 2004–2014, Texas Instruments Incorporated Product Folder Links: LP3990 13 LP3990 SNVS251J – MAY 2004 – REVISED SEPTEMBER 2014 www.ti.com To ensure proper operation, the signal source used to drive the EN input must be able to swing above and below the specified turn-on/off voltage thresholds listed in the Electrical Characteristics section under VIL and VIH. An internal 1-MΩ pull-down resistor ties the EN input to ground, ensuring that the device remains off if the EN pin is left open circuit. 8.2.3 Application Curves (500 mV/Div) 'VOUT (50 mV/Div) LOAD CURRENT (mA) VEN CIN = 1 PF COUT = 0.47 PF (1V/Div) VOUT IL = 150 mA TIME (50 Ps/DIV) 150 1 TIME (20 Ps/DIV) Figure 16. Load Transient Figure 15. Enable Start-Up Time 9 Power Supply Recommendations This device is designed to operate from an input supply voltage range of 2 V to 6 V. The input supply should be well regulated and free of spurious noise. To ensure that the LP3990 output voltage is well regulated, the input supply should be at least VOUT + 0.5 V, or 2 V, whichever is higher. A minimum capacitor value of 1-μF is required to be within 1 cm of the IN pin. 10 Layout 10.1 Layout Guidelines The dynamic performance of the LP3990 is dependant on the layout of the PCB. PCB layout practices that are adequate for typical LDO's may degrade the load regulation, PSRR, noise, or transient performance of the LP3990. Best performance is achieved by placing CIN and COUT on the same side of the PCB as the LP3990, and as close as is practical to the package. The ground connections for CIN and COUT should be back to the LP3990 ground pin using as wide, and as short, of a copper trace as is practical. Connections using long trace lengths, narrow trace widths, and/or connections through vias should be avoided. These will add parasitic inductances and resistance that results in inferior performance especially during transient conditions. A Ground Plane, either on the opposite side of a two-layer PCB, or embedded in a multi-layer PCB, is strongly recommended. This Ground Plane serves two purposes : 1) Provide a circuit reference plane to assure accuracy, and 2) provides a thermal plane to remove heat from the LP3990 WSON package through thermal vias under the package DAP. 14 Submit Documentation Feedback Copyright © 2004–2014, Texas Instruments Incorporated Product Folder Links: LP3990 LP3990 www.ti.com SNVS251J – MAY 2004 – REVISED SEPTEMBER 2014 10.2 Layout Examples VIN VOUT LP3990TL B2 B1 COUT CIN A2 A1 Power Ground VEN Figure 17. LP3990 DSBGA Layout LP3990MF VOUT VIN IN 1 OUT 5 COUT CIN 2 GND Power Ground 3 VEN EN 4 N/C Figure 18. LP3990 SOT-23 Layout LP3990SD CIN VOUT COUT Power Ground 1 2 3 VIN 6 Thermal Pad 5 VEN 4 Figure 19. LP3990 WSON Layout Submit Documentation Feedback Copyright © 2004–2014, Texas Instruments Incorporated Product Folder Links: LP3990 15 LP3990 SNVS251J – MAY 2004 – REVISED SEPTEMBER 2014 www.ti.com 10.3 DSBGA Mounting The DSBGA package requires specific mounting techniques, which are detailed in TI Application Note DSBGA Wafer Level Chip Scale PackageSNVA009. For best results during assembly, alignment ordinals on the PC board may be used to facilitate placement of the DSBGA device. 10.4 DSBGA Light Sensitivity Exposing the DSBGA device to direct light may affect the operation of the device. Light sources, such as halogen lamps, can affect electrical performance, if placed in close proximity to the device. Light with wavelengths in the infra-red portion of the spectrum is the most detrimental, and so, fluorescent lighting used inside most buildings, has little or no effect on performance. 16 Submit Documentation Feedback Copyright © 2004–2014, Texas Instruments Incorporated Product Folder Links: LP3990 LP3990 www.ti.com SNVS251J – MAY 2004 – REVISED SEPTEMBER 2014 11 Device and Documentation Support 11.1 Trademarks All trademarks are the property of their respective owners. 11.2 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.3 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright © 2004–2014, Texas Instruments Incorporated Product Folder Links: LP3990 17 PACKAGE OPTION ADDENDUM www.ti.com 11-Dec-2014 PACKAGING INFORMATION Orderable Device Status (1) LP3990MF-1.2/NOPB Package Type Package Pins Package Drawing Qty ACTIVE SOT-23 DBV 5 1000 Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 SCDB (4/5) LP3990MF-1.8 NRND SOT-23 DBV 5 1000 TBD Call TI Call TI -40 to 125 SCFB LP3990MF-1.8/NOPB ACTIVE SOT-23 DBV 5 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 SCFB LP3990MF-2.5 NRND SOT-23 DBV 5 1000 TBD Call TI Call TI -40 to 125 SCJB LP3990MF-2.5/NOPB ACTIVE SOT-23 DBV 5 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 SCJB LP3990MF-2.8/NOPB ACTIVE SOT-23 DBV 5 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 SCKB LP3990MF-3.3/NOPB ACTIVE SOT-23 DBV 5 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 SCLB LP3990MFX-1.2/NOPB ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 SCDB LP3990MFX-1.8/NOPB ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 SCFB LP3990MFX-3.3/NOPB ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 SCLB LP3990SD-1.2/NOPB ACTIVE WSON NGG 6 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L086B LP3990SD-1.5/NOPB ACTIVE WSON NGG 6 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L087B LP3990SD-1.8/NOPB ACTIVE WSON NGG 6 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L088B LP3990TL-0.8/NOPB ACTIVE DSBGA YZR 4 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 LP3990TL-1.2/NOPB ACTIVE DSBGA YZR 4 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 LP3990TL-1.35/NOPB ACTIVE DSBGA YZR 4 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 LP3990TL-1.5/NOPB ACTIVE DSBGA YZR 4 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 LP3990TL-1.8/NOPB ACTIVE DSBGA YZR 4 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 11-Dec-2014 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) LP3990TL-2.5/NOPB ACTIVE DSBGA YZR 4 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 LP3990TL-2.8/NOPB ACTIVE DSBGA YZR 4 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 LP3990TLX-0.8/NOPB ACTIVE DSBGA YZR 4 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 LP3990TLX-1.2/NOPB ACTIVE DSBGA YZR 4 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 LP3990TLX-1.35/NOPB ACTIVE DSBGA YZR 4 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 LP3990TLX-1.5/NOPB ACTIVE DSBGA YZR 4 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 LP3990TLX-1.8/NOPB ACTIVE DSBGA YZR 4 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 LP3990TLX-2.5/NOPB ACTIVE DSBGA YZR 4 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 LP3990TLX-2.8/NOPB ACTIVE DSBGA YZR 4 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 2 Samples PACKAGE OPTION ADDENDUM www.ti.com (4) 11-Dec-2014 There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF LP3990 : • Automotive: LP3990-Q1 NOTE: Qualified Version Definitions: • Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 3 PACKAGE MATERIALS INFORMATION www.ti.com 5-Dec-2014 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) LP3990MF-1.2/NOPB SOT-23 DBV 5 1000 178.0 8.4 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 3.2 3.2 1.4 4.0 8.0 Q3 LP3990MF-1.8 SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LP3990MF-1.8/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LP3990MF-2.5 SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LP3990MF-2.5/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LP3990MF-2.8/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LP3990MF-3.3/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LP3990MFX-1.2/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LP3990MFX-1.8/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LP3990MFX-3.3/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LP3990SD-1.2/NOPB WSON NGG 6 1000 178.0 12.4 3.3 3.3 1.0 8.0 12.0 Q1 LP3990SD-1.5/NOPB WSON NGG 6 1000 178.0 12.4 3.3 3.3 1.0 8.0 12.0 Q1 LP3990SD-1.8/NOPB WSON NGG 6 1000 178.0 12.4 3.3 3.3 1.0 8.0 12.0 Q1 LP3990TL-0.8/NOPB DSBGA YZR 4 250 178.0 8.4 1.09 1.35 0.76 4.0 8.0 Q1 LP3990TL-1.2/NOPB DSBGA YZR 4 250 178.0 8.4 1.09 1.35 0.76 4.0 8.0 Q1 LP3990TL-1.35/NOPB DSBGA YZR 4 250 178.0 8.4 1.09 1.35 0.76 4.0 8.0 Q1 LP3990TL-1.5/NOPB DSBGA YZR 4 250 178.0 8.4 1.09 1.35 0.76 4.0 8.0 Q1 LP3990TL-1.8/NOPB DSBGA YZR 4 250 178.0 8.4 1.09 1.35 0.76 4.0 8.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 5-Dec-2014 Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) LP3990TL-2.5/NOPB DSBGA YZR 4 250 178.0 8.4 LP3990TL-2.8/NOPB DSBGA YZR 4 250 178.0 8.4 LP3990TLX-0.8/NOPB DSBGA YZR 4 3000 178.0 LP3990TLX-1.2/NOPB DSBGA YZR 4 3000 178.0 LP3990TLX-1.35/NOPB DSBGA YZR 4 3000 LP3990TLX-1.5/NOPB DSBGA YZR 4 LP3990TLX-1.8/NOPB DSBGA YZR 4 LP3990TLX-2.5/NOPB DSBGA YZR LP3990TLX-2.8/NOPB DSBGA YZR W Pin1 (mm) Quadrant 1.09 1.35 0.76 4.0 8.0 Q1 1.09 1.35 0.76 4.0 8.0 Q1 8.4 1.09 1.35 0.76 4.0 8.0 Q1 8.4 1.09 1.35 0.76 4.0 8.0 Q1 178.0 8.4 1.09 1.35 0.76 4.0 8.0 Q1 3000 178.0 8.4 1.09 1.35 0.76 4.0 8.0 Q1 3000 178.0 8.4 1.09 1.35 0.76 4.0 8.0 Q1 4 3000 178.0 8.4 1.09 1.35 0.76 4.0 8.0 Q1 4 3000 178.0 8.4 1.09 1.35 0.76 4.0 8.0 Q1 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LP3990MF-1.2/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0 LP3990MF-1.8 SOT-23 DBV 5 1000 210.0 185.0 35.0 LP3990MF-1.8/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0 LP3990MF-2.5 SOT-23 DBV 5 1000 210.0 185.0 35.0 LP3990MF-2.5/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0 LP3990MF-2.8/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0 LP3990MF-3.3/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0 LP3990MFX-1.2/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0 Pack Materials-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 5-Dec-2014 Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LP3990MFX-1.8/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0 LP3990MFX-3.3/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0 LP3990SD-1.2/NOPB WSON NGG 6 1000 210.0 185.0 35.0 LP3990SD-1.5/NOPB WSON NGG 6 1000 210.0 185.0 35.0 LP3990SD-1.8/NOPB WSON NGG 6 1000 210.0 185.0 35.0 LP3990TL-0.8/NOPB DSBGA YZR 4 250 210.0 185.0 35.0 LP3990TL-1.2/NOPB DSBGA YZR 4 250 210.0 185.0 35.0 LP3990TL-1.35/NOPB DSBGA YZR 4 250 210.0 185.0 35.0 LP3990TL-1.5/NOPB DSBGA YZR 4 250 210.0 185.0 35.0 LP3990TL-1.8/NOPB DSBGA YZR 4 250 210.0 185.0 35.0 LP3990TL-2.5/NOPB DSBGA YZR 4 250 210.0 185.0 35.0 LP3990TL-2.8/NOPB DSBGA YZR 4 250 210.0 185.0 35.0 LP3990TLX-0.8/NOPB DSBGA YZR 4 3000 210.0 185.0 35.0 LP3990TLX-1.2/NOPB DSBGA YZR 4 3000 210.0 185.0 35.0 LP3990TLX-1.35/NOPB DSBGA YZR 4 3000 210.0 185.0 35.0 LP3990TLX-1.5/NOPB DSBGA YZR 4 3000 210.0 185.0 35.0 LP3990TLX-1.8/NOPB DSBGA YZR 4 3000 210.0 185.0 35.0 LP3990TLX-2.5/NOPB DSBGA YZR 4 3000 210.0 185.0 35.0 LP3990TLX-2.8/NOPB DSBGA YZR 4 3000 210.0 185.0 35.0 Pack Materials-Page 3 MECHANICAL DATA NGG0006A SDE06A (Rev A) www.ti.com MECHANICAL DATA YZR0004xxx D 0.600±0.075 E TLA04XXX (Rev D) D: Max = 1.324 mm, Min =1.263 mm E: Max = 1.045 mm, Min =0.984 mm 4215042/A NOTES: A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994. B. This drawing is subject to change without notice. www.ti.com 12/12 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products. 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