LMP92018 www.ti.com SNAS514B – NOVEMBER 2011 – REVISED MAY 2013 LMP92018 Analog System Monitor and Controller Check for Samples: LMP92018 FEATURES APPLICATIONS • • • • 1 2 • • • • • 8 ANALOG VOLTAGE MONITORING CHANNELS – 10-Bit ADC with Programmable Input MUX – Internal/External Reference – Tolerates High-Source Impedance at Lower Sampling Rates 4 PROGRAMMABLE ANALOG VOLTAGE OUTPUTS – Four 10-Bit DACs – Internal/External Reference – Drives Loads up to 1nF VOLTAGE REFERENCE – User-Selectable Source: External or Internal – Internal Reference 2.5V TEMPERATURE SENSOR – ±2.5°C Accuracy 12-BIT GPIO PORT – Each Bit Individually Programmable – User-Selectable Rail SPI-COMPATIBLE BUS – User-Selectable Rail Communication Infrastructure System Monitoring and Control Industrial Monitoring and Control DESCRIPTION LMP92018 is a complete analog monitoring and control circuit which integrates an eight channel 10-bit Analog-to-Digital Converter (ADC), four 10-bit Digitalto-Analog Converters (DACs), an internal reference, an internal temperature sensor, a12-bit GPIO port, and a 10MHz SPI interface. The eight channels of the ADC can be used to monitor rail voltages, current sense amplifier outputs, health monitors or sensors while the four DACs can be used to control PA (Power Amplifier) bias points, control actuators, potentiometers, etc. Both the ADC and DACs can use either the internal 2.5V reference or an external reference independently allowing for flexibility in system design. The built-in digital temperature sensor enables accurate (±2.5°C) local temperature measurement whose value is captured in the user accessible register. Block Diagram IN[7:0] OUT3 VDD OUT0 8 DAC DAC DAC DAC Multiplexer ADC Temp. Sensor Int/Ext Ref LMP92018 SPI Interface GPIO 4 12 REF GPIO[11:0] VGPIO CSB SCLK DIN DOUT DRDYB VIO GND 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2011–2013, Texas Instruments Incorporated LMP92018 SNAS514B – NOVEMBER 2011 – REVISED MAY 2013 www.ti.com DESCRIPTION (CONTINUED) The LMP92018 also includes a 12-bit GPIO port which allows for the resources of the microcontroller to be further extended, thus providing even more flexibility and reducing the number of signal interfacing to the microcontroller. Both the GPIO port and the SPI compatible interface have independent supply pins enabling the LMP92018 to interface with low voltage microcontrollers. The LMP92018 is available in a space saving 36-pin WQFN package and is specified over the full -30°C to +85°C temperature range. Typical Application 5V 48V 5V VDD REF IN[7:0] Scaled Voltage Sensing Ratiometric Sensing Voltage Sense Channels 8 LM94023 LMP8640 1.8V Temp VIO Analog Sensors Current sensing ROUT<10k DRDYB SPI 4 Voltage Source + - LMP92018 uC CSB SCLK DIN DOUT Servo OUT[3:0] Actuator Control Analog Voltage Control 4 PA Bias Control 3.3V VGPIO Digital Control GPIO[11:0] Bidirectional Digital Bus 12 Digital Status Indicators 2 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LMP92018 LMP92018 www.ti.com SNAS514B – NOVEMBER 2011 – REVISED MAY 2013 IN[7:0] OUT3 VDD OUT0 8 DAC DAC DAC DAC Multiplexer ADC Temp. Sensor Int/Ext Ref LMP92018 SPI Interface GPIO 4 12 REF GPIO[11:0] VGPIO CSB SCLK DIN DOUT DRDYB VIO GND Overview The LMP92018 has a flexible, feature-rich functionality which makes it ideally suited for many analog monitoring and control applications, for example, base-station PA subsystems. This device provides the analog interface between a programmable supervisor, such as a microcontroller, and an analog system whose behavior is to be monitored and controlled by the supervisor. To facilitate the analog monitoring functionality, the device contains a single 10-bit ADC preceded by a 8-input multiplexor. The analog control functionality is served by four 10-bit voltage output DACs. Additional digital monitoring and control can be realized via the General Purpose I/O port GPIO[11:0]. Two more blocks are present for added functionality: a local temperature sensor and an internal reference voltage generator. 8-CHANNEL ANALOG SENSE WITH 10-BIT ADC The user can monitor up to 8 external voltages with the 10-bit ADC and its 8-channel input MUX. Typically these voltages will be generated by the analog sensors, instrumentation amplifiers, current sense amplifiers, or simply resistive dividers if high potentials need to be measured. PROGRAMMABLE ANALOG CONTROL VOLTAGE OUTPUTS Four identical individually programmable 10-bit DAC blocks are available to generate analog voltages, which can be used to control bias conditions of external circuits, position of servos, etc. INTERNAL DIGITAL TEMPERATURE SENSOR An on-board digital temperature sensor is available to report the device's own temperature. The temperature sensor output is stored in the internal register for user readback via the SPI interface. INTERNAL VOLTAGE REFERENCE SOURCE The user can choose to enable the internal reference of 2.5V to use with the ADC and/or DACs. The internal reference source can also drive an external load. 12-BIT GENERAL PURPOSE I/O The GPIO port can be used to expand the microcontroller capabilities. This port is memory mapped to the internal register, which in turn is accessible via the SPI interface. Each bit is individually programmable as an input or an output Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LMP92018 3 LMP92018 SNAS514B – NOVEMBER 2011 – REVISED MAY 2013 www.ti.com SPI INTERFACE The microcontroller communicates with LMP92018 via a popular SPI interface. This interface provides the user full access to all Data, Status and Control registers of the device. REF IN7 IN6 IN5 IN4 IN3 IN2 IN1 IN0 36 35 34 33 32 31 30 29 28 Connection Diagram VDD 1 27 GPIO0 GND 2 26 GPIO1 GND 3 25 GPIO2 VGPIO 4 24 GPIO3 VIO 5 23 GPIO4 CSB 6 22 GPIO5 SCLK 7 21 GPIO6 DIN 8 20 GPIO7 DOUT 9 19 DRDYB 14 15 16 17 18 GPIO10 GPIO9 GPIO8 13 OUT0 GND 12 OUT1 GPIO11 11 10 OUT3 OUT2 DAP Figure 1. 36-Pin WQFN (Top View) See NJK0036A Package PIN DESCRIPTIONS Name Pin Function VDD 1 Supply rail VGPIO 4 GPIO rail VIO 5 SPI rail GND 2, 3 14 Device Ground * Die Attach Pad. For best thermal conductivity and best noise immunity DAP should be soldered to the PCB pad which is connected directly to circuit common node (GND). DAP ESD Structures ESD+ ESD+ IN[7:0] 4 35:28 Analog input Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LMP92018 LMP92018 www.ti.com SNAS514B – NOVEMBER 2011 – REVISED MAY 2013 PIN DESCRIPTIONS (continued) Name Pin Function OUT[3:0] 10:13 Analog output DOUT 9 SPI Data Output GPIO[11:0] 15:18; 20:27 General Purpose Digital I/O. Logic level is referenced to VGPIO pin. CSB 6 SPI Chip Select, Active LO SCLK 7 SPI Data Clock DIN 8 SPI Data Input DRBYB 19 Data Ready, open-drain active LO ESD Structures ESD+ ESD+ REF 36 ADC/DAC Voltage Reference Input or Output These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) (3) VDD Relative to GND −0.3V to 6.0V VIO Relative to GND −0.3V to VDD VGPIO Relative to GND −0.3V to VDD Voltage between any 2 pins (4) 6.0V Current in or out of any pin (4) 5mA 32mA, TA = 125°C Current through VDD 44mA, TA = 85°C Current through VGPIO 20mA, TA = 125°C 54mA, TA = 125°C Current through GND 66mA, TA = 85°C Junction Temperature +150°C −65°C to +150°C Storage Temperature Range Human Body Model ESD Susceptibility (5) 2500V Machine Model 200V Charged Device Model (1) (2) (3) (4) (5) 1500V “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The recommended Operating Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. All voltages are measured with respect to GND = 0V, unless otherwise specified. If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications. When the input voltage (VIN) at any pin exceeds power supplies (VIN < GND or VIN > VDD), the current at that pin must not exceed 5mA, and the voltage (VIN) at that pin relative to any other pin must not exceed 6.0V. See Pin Descriptions for additional details of input circuit structures. The Human Body Model (HBM) is a 100 pF capacitor charged to the specified voltage then discharged through a 1.5kΩ resistor into each pin. The Machine Model (MM) is a 200 pF capacitor charged to specified voltage then discharged directly into each pin. The Charged Device Model (CDM) is a specified circuit characterizing an ESD event that occurs when a device acquires charge through some triboelectric (frictional) or electrostatic induction process and then abruptly touches a grounded object or surface. Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LMP92018 5 LMP92018 SNAS514B – NOVEMBER 2011 – REVISED MAY 2013 www.ti.com Operating Conditions (1) (2) −40°C to 125°C Operating Ambient Temperature VDD Voltage Range 4.75V to 5.25V VIO Voltage Range 1.8V to VDD VGPIO Voltage Range 1.8V to VDD DAC Output Load C 0nF to 1nF θJA 25.2°C/W θJC 2.4°C/W (1) (2) “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The recommended Operating Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. All voltages are measured with respect to GND = 0V, unless otherwise specified. Electrical Characteristics Unless otherwise noted, these specifications apply for VDD=4.75V to 5.25V, REF=VDD, TA=25°C. Boldface limits are over the temperature range of −30°C ≤ TA ≤ 85°C unless otherwise noted. DAC input code range 12 to 1012. DAC output CL = 200 pF unless otherwise noted. Symbol Parameter Conditions Min Typ Max Units 10 10 Bits −0.9 +1 ADC CHARACTERISTICS Resolution with No Missing Codes DNL Differential Non-Linearity INL Integral Non-Linearity −1 1 OE Offset Error −2 +2 OEDRIFT Offset Error Temperature Drift OEMTCH Offset Error Match (1) −1 1 Gain Error −2 2 GE GEDRIFT Gain Error Temperature Drift GEMTCH Gain Error Match (1) SINAD THD SFDR PSRR Signal-to-Noise Ratio Total Harmonic Distortion Spurious Free Dynamic Range Power Supply Rejection Ratio 0.001 LSB/°C 0.001 −1 10 kHz Sine Wave 58 10 kHz Sine Wave, up to 5th harmonic −69 10 kHz Sine Wave 70 LSB LSB LSB/°C 1 LSB dB dBc Offset Error change with VDD −150 Gain Error change with VDD −150 dB DAC CHARACTERISTICS 10 RL = 100k −0.5 +0.5 Integral Non-Linearity RL = 100k −2 +2 OE Offset Error (2) RL = 100k Offset Error Temperature Drift FSE Full-Scale Error GE Gain Error (3) Gain Error Temperature Drift Zero Code Output Bits Bits Differential Non-Linearity ZCO 6 10 INL GEDRIFT (3) 10 Monotonicity DNL OEDRIFT (1) (2) Resolution LSB 10 RL = 100k 1 µV/°C VDD = 5.25V, REF=5, RL = 100k, CODE=3FFh -0.4 +0.3 RL = 100k −0.2 +0.2 RL = 100k 1.4 IOUT = 200 µA 7 IOUT = 1mA 31 mV %FS ppm/° C mV Device Specification is guaranteed by characterization and is not tested in production. DAC Offset is the y-intercept of the straight line defined by DAC output at code 0d12 and 0d1011points of the measured transfer characteristic. DAC Gain Error is the difference in slope of the straight line defined by DAC output at code 0d12 and 0d1011 points of transfer characteristic, and that of the ideal characteristic. Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LMP92018 LMP92018 www.ti.com SNAS514B – NOVEMBER 2011 – REVISED MAY 2013 Electrical Characteristics (continued) Unless otherwise noted, these specifications apply for VDD=4.75V to 5.25V, REF=VDD, TA=25°C. Boldface limits are over the temperature range of −30°C ≤ TA ≤ 85°C unless otherwise noted. DAC input code range 12 to 1012. DAC output CL = 200 pF unless otherwise noted. Symbol FSO Parameter Full Scale Output at code 3FFh Conditions Min IOUT = 200 µA 4.975 IOUT = 1mA 4.975 RL = 100k 4.975 Typ Max Units V IOS Output Short Circuit Current (Source) (4) VDD = 5V, OUT = 0V, Input Code =3 FFh −67 IOS Output Short Circuit Current (Sink) (4) VDD = 5V, OUT = DREF, Input Code = 000h 76 IO Continuous Output Current per Channel (to prevent damage) TA = 85° C 10 TA = 125° C 6.5 CL Maximum Load Capacitance RL = 2k or ∞ 1000 Enabled 1.7 Ω Disabled >20 MΩ ROUT DC Output Impedance mA pF ANALOG INPUT CHARACTERISTICS VIN FS Input Range ILEAK ADC in HOLD or Power Down CINA Input Capacitance −1 In Acquisition mode 33 In Conversion mode 3 REF V +1 µA pF REFERENCE CHARACTERISTICS ADC Reference Input Range 2.5 VDD DAC Reference Input Range 2.5 VDD DAC Reference Input Resistance 50 DAC Reference Input Current IVREF(ADC) ADC Reference Current, during conversion, average value IVREF(PD) REF pin Current in Powerdown V External Reference, REF = VDD REF Output Voltage kΩ 125 µA 1 µA 10 µA 2.5 Internal Reference Tolerance –0.15 V 0.15 % REF Output Temperature Drift 17 ppm/°C REF Output Maximum Current 1 mA REF Output Load Regulation REF Output Rail Regulation –0.6 4.75V≤VDD≤5.25V % ±0.04 % 0.0625 °C TEMPERATURE SENSOR Resolution Temperature Error (5) −40°C to +125°C −2.5 +2.5 °C 0.3x VGPIO V DIGITAL INPUT CHARACTERISTICS (GPIO[11:0]) VIH Input HIGH Voltage VIL Input LO Voltage 0.7x VGPIO Hysteresis (4) (5) IIND Digital Input Current CIND Input Capacitance 250 ±0.005 mV ±1 4 µA pF Indicates the typical internal short circuit current limit. Sustained operation at this level will lead to device damage. Device Specification is guaranteed by characterization and is not tested in production. Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LMP92018 7 LMP92018 SNAS514B – NOVEMBER 2011 – REVISED MAY 2013 www.ti.com Electrical Characteristics (continued) Unless otherwise noted, these specifications apply for VDD=4.75V to 5.25V, REF=VDD, TA=25°C. Boldface limits are over the temperature range of −30°C ≤ TA ≤ 85°C unless otherwise noted. DAC input code range 12 to 1012. DAC output CL = 200 pF unless otherwise noted. Symbol Parameter Conditions Min Typ Max Units DIGITAL INPUT CHARACTERISTICS (CSB, DIN, SCLK) VIH Input HIGH Voltage VIL Input LO Voltage 0.7 x VIO V 0.3 x VIO Hysteresis 250 IIND Digital Input Current CIND Input Capacitance ±0.005 V mV ±1 4 µA pF DIGITAL OUTPUT CHARACTERISTICS (GPIO[11:0]) VOL Output LO Voltage VOH Output HI Voltage IOZH, IOZL TRI-STATE Output Leakage Current COUT Output Capacitance IOUT = 200 µA 0.01 0.4 IOUT = 1.6 mA VGPIO = VDD = 5V 0.07 0.4 IOUT = 200µA VGPIO-0.2 IOUT = 1.6 mA VGPIO = VDD = 5V VGPIO-0.5 V V VGPIO=VDD ±5 4 µA pF DIGITAL OUTPUT CHARACTERISTICS (DOUT) VOL Output LO Voltage VOH Output HI Voltage IOZH, IOZL TRI-STATE Output Leakage Current COUT Output Capacitance IOUT = 200 µA 0.01 0.4 V IOUT = 1.6 mA VIO = 3.3V 0.07 0.6 V IOUT = 200 µA VIO-0.2 IOUT = 1.6 mA VIO = 3.3V VIO-0.5 V VGPIO = 1.8V =VDD ±5 4 µA pF DIGITAL OUTPUT CHARACTERISTICS (DRDYB) VOH_MAX VOL Maximum Output HI Voltage Output LO Voltage IOUT = 1.6 mA VIO = 3.3V to VDD VIO-0.5 Force 0V or VDD µA 0.01 V POWER SUPPLY CHARACTERISTICS VDD VGPIO Supply Voltage Range 4.75 GPIO Rail Range 1.8 5 VDD 5.5 1.8 VDD V VIO SPI Rail Range IDD Supply Current, Conversion Mode OUT[3:0] pins RL = ∞ 4 mA PWRCONV Power Consumption, Conversion Mode OUT[3:0] pins RL = ∞ 21 mW 50 µA 2.7 V IPD VPOR Supply Current, Power-Down Mode Power-On Reset (6) 1.9 AC ELECTRICAL CHARACTERISTICS tTRACK ADC Track Time Dictated by SPI bus activity t8+9×t1 µs tHOLD ADC Hold Time Dictated by SPI bus activity 15×t1 µs ts (6) (7) 8 DAC Settling Time (7) 25%FS to 75%FS code change, RL = 2K, CL = 200 pF 20 µs During the power up the supply rail must ramp up beyond VPOR MIN for the device to acquire default state. After the supply rail has reached the nominal level, the rail can drop as low as VPOR MAX for the current state to be maintained. Device Specification is guaranteed by characterization and is not tested in production. Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LMP92018 LMP92018 www.ti.com SNAS514B – NOVEMBER 2011 – REVISED MAY 2013 Electrical Characteristics (continued) Unless otherwise noted, these specifications apply for VDD=4.75V to 5.25V, REF=VDD, TA=25°C. Boldface limits are over the temperature range of −30°C ≤ TA ≤ 85°C unless otherwise noted. DAC input code range 12 to 1012. DAC output CL = 200 pF unless otherwise noted. Symbol tCONV Parameter Conditions Min Typ Temperature Conversion Time Max Units 25.85 ms SPI TIMING CHARACTERISTICS t1 SPI Clock Period during ADC data access 178 12500 ns t1 SPI Clock Period during Temperature Sensor access 178 5000 ns t1 SPI Clock Period for all transactions not involving ADC or Temperature Sensor 100 tr SCLK Rise Time 2 ns tf SCLK Fall Time 2 ns t2 SCLK HIGH Time 8 ns t3 SCLK LOW Time 8 ns t4 CSB set-up time to SCLK falling edge 5 ns t5 DIN Set-up time 5 ns t6 DIN Hold time 4 ns t7 CSB hold time after 24th falling edge of SCLK 10 ns t8 CSB High Pulse Width 30 ns tDH DOUT hold time after SCLK Rising Edge tDD DOUT Delay after SCLK Rising Edge t11 SCLK Delay after CSB Rising Edge CL=30pF, VIO=1.8 10 CL=30pF, 3V≤VIO≤5.25V 5 ns ns CL=30pF 40 3 tDOZ CSB Rising Edge to DOUT TRISTATE tZDO CSB Falling Edge to DOUT active ns 4 sink/source 200uA, CL=150pF ns 5 10 ns 14 ns SPI Interface Timing Diagram | | t1 70% SCLK 1 70% 30% 2 t3 70% tr CSB t8 DIN DOUT PD0 D23 D22 PD23 PD22 70% 23 24 tf | | | | | t2 70% t11 D1 D0 PD1 PD0 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LMP92018 9 LMP92018 SNAS514B – NOVEMBER 2011 – REVISED MAY 2013 www.ti.com 70% SCLK 30% CSB 30% 30% t4 t7 70% CSB 30% SDO tZDO tDOZ 70% SCLK SDI 30% 70% 30% t5 SCLK SDO 10 70% t6 70% 70% 30% 70% 30% tDH tDD Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LMP92018 LMP92018 www.ti.com SNAS514B – NOVEMBER 2011 – REVISED MAY 2013 Typical Performance Characteristics ADC: INL 1.0 0.8 0.8 0.6 0.6 0.4 0.4 0.2 0.2 INL (lsb) DNL (lsb) ADC: DNL 1.0 0.0 -0.2 0.0 -0.2 -0.4 -0.4 -0.6 -0.6 -0.8 -0.8 -1.0 -1.0 0 256 512 768 OUTPUT CODE 1024 0 256 512 768 OUTPUT CODE Figure 2. Figure 3. DAC: INL 1.0 1.0 0.8 0.8 0.6 0.6 0.4 0.4 0.2 0.2 INL (lsb) DNL (lsb) DAC: DNL 0.0 -0.2 0.0 -0.2 -0.4 -0.4 -0.6 -0.6 -0.8 -0.8 -1.0 -1.0 0 1002003004005006007008009001000 INPUT CODE 0 256 Figure 4. 0.4 1024 ADC: INL vs. Temperature 0.5 Min DNL Max DNL 0.4 0.3 0.2 0.2 0.1 0.1 INL (lsb) 0.3 0.0 -0.1 -0.1 -0.2 -0.3 -0.3 -0.4 -0.4 -0.5 Min INL Max INL 0.0 -0.2 -30 512 768 INPUT CODE Figure 5. ADC: DNL vs. Temperature 0.5 DNL (lsb) 1024 -0.5 -10 10 30 50 TEMPERATURE (°C) 70 90 Figure 6. -30 -10 10 30 50 TEMPERATURE (°C) 70 90 Figure 7. Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LMP92018 11 LMP92018 SNAS514B – NOVEMBER 2011 – REVISED MAY 2013 www.ti.com Typical Performance Characteristics (continued) DAC: DNL vs. Temperature 0.5 Min DNL Max DNL 0.3 0.3 0.2 0.2 0.1 0.1 0.0 -0.1 0.0 -0.1 -0.2 -0.2 -0.3 -0.3 -0.4 -0.4 -0.5 -0.5 -30 -10 Min INL Max INL 0.4 INL (lsb) DNL (lsb) 0.4 DAC: INL vs. Temperature 0.5 10 30 50 TEMPERATURE (°C) 70 90 -30 -10 Figure 8. 70 90 Figure 9. OUTx Output Load Regulation Temperature Sensor Error TEMPERATURE SENSOR ERROR (°C) 20 DEVIATION FROM MIDSCALE (mV) 10 30 50 TEMPERATURE (°C) 15 10 5 0 -5 -10 -15 -20 1.5 1.0 0.5 0.0 -0.5 -10 -8 -6 -4 -2 0 2 4 6 8 10 DAC OUTPUT CURRENT (mA) -40 -20 Figure 10. 0 20 40 60 80 100 120 TEMPERATURE (°C) Figure 11. Internal Reference Output Temperature Drift REFERENCE ERROR (mV) 15 10 5 0 -5 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (°C) Figure 12. 12 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LMP92018 LMP92018 www.ti.com SNAS514B – NOVEMBER 2011 – REVISED MAY 2013 INSTRUCTION SET The following is a complete listing of the instruction set supported by the LMP92018. Where applicable the default state or register content is indicated in bold type. The digital interface (SPI) protocol is described in SERIAL INTERFACE. The interface timing diagram is in SPI Interface Timing Diagram NOTE: the tables in following sections detail the data transfers of 2 subsequent SPI frames . The FRAME 1 column shows the user input into pin DIN of the device. The FRAME 2 column in the device output at DOUT. TEMPERATURE SENSOR CONFIGURE A single bit, TSS, controls the mode of operation of the internal temperature sensor. The bit can be set and tested via the SPI transactions shown in the following table. The internal temperature sensor is described in DIGITAL TEMPERATURE SENSOR. FRAME 1: DIN Command Bit→ FRAME 2: DOUT Payload Command Payload 23 22:16 15:1 0 23 22:16 15:1 0 READ 1 0010000 x x 1 0010000 000000000000000 TSS WRITE 0 0010000 000000000000000 TSS 0 0010000 000000000000000 0 x Don't Care 1: Temperature Sensor in Continuous Conversion Mode TSS 0: Temperature Sensor In One Shot Mode REFERENCE CONFIGURE The internal reference mode of operation is controlled by a 3 bit sequence, CREF. The sequence can be set and tested via the SPI transactions shown in the following table. The reference block is described in INTERNAL VOLTAGE REFERENCE SOURCE. FRAME 1: DIN Command Bit→ FRAME 2: DOUT Payload Command Payload 23 22:16 15:3 2:0 23 22:16 15:3 2:0 READ 1 0010001 x x 1 0010001 0000000000000 CREF WRITE 0 0010001 0000000000000 CREF 0 0010001 0000000000000 000 x Don't care Reference Mode Selector 000: AREF external, DREF internal 001: AREF and DREF internal; REF pin is internally disconnected 010: AREF and DREF external CREF 011: AREF internal, DREF external 100: Deep Sleep 101: AREF and DREF internal; REF driven by internal reference 110: Deep Sleep 111: Deep Sleep Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LMP92018 13 LMP92018 SNAS514B – NOVEMBER 2011 – REVISED MAY 2013 www.ti.com DAC CONFIGURE The individual DACs can be enabled by setting a corresponding bit in the 4–bit CDAC word. The CDAC word can be set and tested via the SPI transactions shown in the following table. The DAC block is described in PROGRAMMABLE ANALOG OUTPUT SUBSYSTEM. FRAME 1: DIN Command Bit→ FRAME 2: DOUT Payload Command Payload 23 22:16 15:4 3:0 23 22:16 15:4 3:0 READ 1 0011000 x x 1 0011000 000000000000 CDAC WRITE 0 0011000 000000000000 CDAC 0 0011000 000000000000 0000 x Don't care 1: enables DAC corresponding to bit position CDAC 0: disables corresponding DAC e.g. CDAC=[0101] enables DAC2 and DAC0 UPDATE ALL DACs All 4 DAC channels' outputs can be simultaneously set to the same level corresponding to a 10–bit DDATA code. The sequence in the following table provides a WRITE only functionality. The DAC block is described in PROGRAMMABLE ANALOG OUTPUT SUBSYSTEM. FRAME 1: DIN Command Bit→ FRAME 2: DOUT Payload Command Payload 23 22:16 15:12 11:2 1:0 23 22:16 15:12 11:2 1:0 0 0011001 0000 DDATA 00 0 0011001 0000 0000000000 00 WRITE x Don't care DDATA DDATA will be loaded into all all DACs' input registers simultaneously. DDATA is a 10–bit unsigned integer. GENERAL CONFIGURATION The device can indicate to the new ADC conversion data availability via the DRDYB pin. This functionality is enabled by setting the internal DRDY bit. The bit can be set and tested via the SPI transactions shown in the following table. Details of the DRDYB pin functionality are described in Conversion Sequence and DIGITAL TEMPERATURE SENSOR FRAME 1: DIN Command Bit→ FRAME 2: DOUT Payload Command Payload 23 22:16 15:1 0 23 22:16 15:1 0 READ 1 0011110 x x 1 0011110 000000000000000 DRDY WRITE 0 0011110 000000000000000 DRDY 0 0011110 000000000000000 0 x Don't Care DRDY 1: Disables the DRDYB pin function 0: Enables the DRDYB pin function GPIO CONFIGURE Individual bits of the general purpose digital I/O port can be configured to drive (output), or sense (input) only. Setting a corresponding bit in the 12–bit CGPIO word will enable that pin to drive. The sequences in the following table provide a READ and WRITE capability for the internal CGPIO register. The GPIO block is described in GENERAL PURPOSE DIGITAL I/O. 14 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LMP92018 LMP92018 www.ti.com SNAS514B – NOVEMBER 2011 – REVISED MAY 2013 FRAME 1: DIN Command Bit→ FRAME 2: DOUT Payload Command Payload 23 22:16 15:12 11:0 23 22:16 15:12 11:0 READ 1 0011111 x x 1 0011111 0000 CGPIO WRITE 0 0011111 0000 CGPIO 0 0011111 0000 000000000000 x Don't Care 1: sets corresponding GPIO pin as output CGPIO 0: sets corresponding GPIO pin as input e.g. CGPIO=[000011110000] enables GPIO[7:4] pins as outputs, all other GPIO pins are inputs STATUS Internal bit, RDY, indicates when the device has completed its power-up sequence. The RDY bit can be tested via the SPI transaction shown in the following table. FRAME 1: DIN Command Bit→ FRAME 2: DOUT Payload Command Payload 23 22:16 15:1 0 23 22:16 15:1 0 1 0100000 x x 1 0100000 000000000000000 RDY READ x Don't Care Internal Power On Reset circuit sets this bit RDY 1: device ready 0: device not ready GPI STATE The logic state present at the GPIO pins of the device is always reported in the SGPI register. The SGPI register contents can be tested via the SPI transaction shown in the following table. The GPIO block is described in GENERAL PURPOSE DIGITAL I/O. FRAME 1: DIN Command Bit→ FRAME 2: DOUT Payload Command Payload 23 22:16 15:12 11:0 23 22:16 15:12 11:0 1 0110000 x x 1 0110000 0000 SGPI READ x Don't Care SGPI Each bit Indicates the state at the corresponding GPIO pins of the device GPO DATA The GPIO pins configured to drive, will drive the state indicated in the CGPO register. The CGPO register can be set or tested via the SPI transactions shown in the following table. The GPIO block is described in GENERAL PURPOSE DIGITAL I/O. FRAME 1: DIN Command Bit→ FRAME 2: DOUT Payload Command Payload 23 22:16 15:12 11:0 23 22:16 15:12 11:0 READ 1 0110001 x x 1 0110001 0000 CGPO WRITE 0 0110001 0000 CGPO 0 0110001 0000 12'b0 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LMP92018 15 LMP92018 SNAS514B – NOVEMBER 2011 – REVISED MAY 2013 x www.ti.com Don't Care Each bit will be forced at the corresponding GPIO pin of the device. Bits corresponding to GPIO pins configured as inputs will be ignored. CGPO[11:0]=0x000 CGPO VENDOR ID The 16–bit ID sequence is factory set, and can only be tested via the SPI transaction shown in the table below. FRAME 1: DIN Command Bit→ READ FRAME 2: DOUT Payload Command Payload 23 22:16 15:0 23 22:16 15:0 1 1000000 x 1 1000000 ID x Don't Care ID Vendor ID number. ID = 0x0028. VERSION/STEPPING Version and Stepping words are factory set and can only be tested via the SPI transaction shown in the table below. FRAME 1: DIN Command Bit→ READ FRAME 2: DOUT Payload Command Payload 23 22:16 15:4 3:0 23 22:16 15:4 3:0 1 1000001 x x 1 1000001 VER STEP x Don't Care VER Indicates the device version number. VER=0x000 STEP Indicates stepping number. STEP = 0x0 DAC DATA REGISTER ACCESS Each DAC's input data register, DDATA, is individually addressable, and its contents can be updated without affecting remaining 3 DACs. The content of each DDATA can be tested and set via the SPI transactions shown in the following table. The DAC block is described in PROGRAMMABLE ANALOG OUTPUT SUBSYSTEM. FRAME 1: DIN Command Bit→ FRAME 2: DOUT Payload Command Payload 23 22:18 17:16 15:12 11:2 1:0 23 22:18 17:16 15:12 11:2 1:0 READ 1 10100 ADR x x x 1 10100 ADR 0000 DDATA 00 WRITE 0 10100 ADR 0000 DDATA 00 0 10100 ADR 0000 10'b0 00 x Don't Care DAC address: 00: DAC0 ADR 01: DAC1 10: DAC2 11: DAC3 DDATA 16 DAC input data. DDATA is a 10–bit unsigned integer. DDATA=0x000 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LMP92018 LMP92018 www.ti.com SNAS514B – NOVEMBER 2011 – REVISED MAY 2013 ADC INPUT MUX SELECT DATA READ COMMAND The selection of the analog input, and the read-back of the ADC conversion result are completed by the SPI transaction shown in the following table. The ADC block is described in ANALOG SENSE SUBSYSTEM. FRAME 1: DIN Command Bit→ READ FRAME 2: DOUT Payload Command Payload 23 22:19 18:16 15:12 11:2 1:0 23 22:19 18:16 15:12 11:2 1:0 1 1100 ADR x x x 1 1100 ADR 0000 ADATA 00 x Don't Care ADC Input Address: 000: IN0 001: IN1 010: IN2 ADR 011: IN3 100: IN4 101: IN5 110: IN6 111: IN7 ADATA ADC output Data. ADATA is a 10–bit unsigned integer. TEMPERATURE SENSOR OUTPUT REGISTER The contents of the internal temperature sensor output register can be tested by the SPI transaction shown in the following table. The internal temperature sensor is described in DIGITAL TEMPERATURE SENSOR. FRAME 1: DIN Command Bit→ READ x TDATA FRAME 2: DOUT Payload Command Payload 23 22:16 15:12 11:0 23 22:16 15:12 11:0 1 1110000 x x 1 1110000 0000 TDATA Don't Care Temperature Sensor Output Data. TDATA is a 12–bit signed integer. NOOP — No Operation NOOP offers no functionality of its own. It is provided as the means of completing the pending READ operation i.e. “pushing out” the data requested in the previous transaction. FRAME 1: DIN Bit→ NOOP x FRAME 2: DOUT Command Payload Command 23:16 15:0 23:16 Payload 15:0 00000000 x 00000000 16'b0 Don't Care Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LMP92018 17 LMP92018 SNAS514B – NOVEMBER 2011 – REVISED MAY 2013 www.ti.com FUNCTIONAL DESCRIPTION ANALOG SENSE SUBSYSTEM The device is capable of monitoring up to 8 externally applied voltages. The system is centered around a 10-bit SAR ADC fronted by an 8-input mux. Sampling and Conversion The external voltage is sampled onto the internal CHOLD capacitor during the TRACK period, see Figure 13. Once acquired, the stored charge is measured using the Successive Approximation Register (SAR) method. The timing of the internal state machine is governed by the user defined signals CSB and SCLK. The sequence of the events is described in Conversion Sequence. Attention should be paid to the output impedance of the sensed voltage source and the capacitance present at the INx input of the device (which is dominated by CHOLD during TRACK time). The combined circuit's RC limits the bandwidth and settling time of the input signal. At maximum SPI bus data rate, it is recommended to limit the output resistance ROUT of the signal source to assure the accuracy of the conversion. During the HOLD period (duration of t HOLD specified in Electrical Characteristics ) , all mux switches are OFF, and the charge captured on CHOLD is measured to produce an ADC output code. This charge is never lost during the conversion, unless the SCLK is so slow that the charge is lost due to the internal capacitor's leakage. Under normal conditions the charge stored is modified only during TRACK period. Below is a typical ADC output code as a function of input voltage at device pin INx, x=0...7: ADATA = INT V x 1023) (AREF INX (1) In the expression above AREF is the reference voltage input to the internal ADC. See INTERNAL VOLTAGE REFERENCE SOURCE. Sampling Switch ROUT< 4k INx VDD/2 CHOLD + - Voltage Source Device Pin Figure 13. ADC During TRACK Period Sampling Transient As noted in Sampling and Conversion the charge acquired during TRACK period is maintained throughout the conversion process. Since the successive sample operations will involve different input potentials an instantaneous current will flow at the beginning of TRACK period. This always leads to temporary disturbance of the input potential. This current, and resulting disturbance, will vary with the magnitude of the sampled signal and source impedance ROUT, see Figure 13. If ROUT is excessive, and resulting RC time constant of the input circuit too long, the preceding sample may affect the new sample's accuracy. If high ROUT cannot be avoided, another method of improving the acquisitin accuracy is to lengthen the TRACK time. The ADC TRACK time is fully controlled by the user inputs CSB and SCLK, see Figure 14. The time allotted for the CHOLD to settle can be arbitrarily adjusted via the length of the CSB=High period and the frequency of SCLK, subject to limitations on CSB and SCLK timing as shown in Electrical Characteristics . 18 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LMP92018 LMP92018 www.ti.com SNAS514B – NOVEMBER 2011 – REVISED MAY 2013 Conversion Sequence The ADC conversion sequence and output activity are shown in Figure 14. The ADC readback occupies 2 SPI frames. The first frame is used to issue a read command and connect the ADC input to the specified device input pin INx. At the end of the first frame, at the rising edge of the CSB, the ADC sampling capacitor is connected to the signal source, INx, and the TRACK period begins. The second frame executes the SAR algorithm (the HOLD period) on the acquired sample and shifts the resulting data out through the DOUT output. The TRACK period extends for 9 SCLK cycles, then the mux disconnects the sampling capacitor from the signal source, and the SAR operation begins. The data is shifted out MSB first. Once the SAR operation is completed, the ADC powers down for the remainder of the second frame. If DRDYB output pin functionality is enabled, see GENERAL CONFIGURATION, then DRDYB output will be low while ADC output data is present at DOUT. If the ADC is not in TRACK or HOLD, the internal PD (Power Down) signal of the ADC is asserted thus powering down all the active circuits of the ADC, and opening all analog input mux switches. See the PD period in the Figure 14. Frame 1 Frame 2 CSB DIN DOUT READ IN0 dummy payload COMMAND PAYLOAD Echo Previous previous DATA IF ANY READ IN0 ADATA TRACK HOLD PD CSB 1 9 12 SCLK DRDYB Figure 14. ADC Sequence Diagram ADC Reference Selection By default, the ADC operates from the external reference voltage applied at the REF pin of the device. It should be noted that due to the architecture of the ADC the DC current flowing into the REF input is zero during conversion. However, the transient currents ( see IVREF in Electrical Characteristics ) during the HOLD time can be significant. For further details of reference source selection see INTERNAL VOLTAGE REFERENCE SOURCE Selection of the ADC reference source automatically dictates the attenuation level of the input signal. Figure 15 shows the ADC input configuration during the TRACK period when the REF pin is chosen as the source of the reference voltage. The entire CHOLD available is used to acquire the signal. The transfer function of the ADC in this configuration remains as shown in Sampling and Conversion Sampling Switch 15 pF INx VDD/2 15 pF Device Pin Figure 15. ADC Sampling when AREF is Externally Supplied Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LMP92018 19 LMP92018 SNAS514B – NOVEMBER 2011 – REVISED MAY 2013 www.ti.com In contrast, the Figure 16 shows the sampling capacitor during TRACK period when the internally generated reference is selected as the reference source of the ADC. In this configuration ½CHOLD is used to sample the input signal effectively attenuating it by a factor of 2. The resulting overall ADC transfer function becomes: ADATA = INT (2 xVAREF x 1023) INX (2) 15 pF Sampling Switch INx VDD/2 15 pF Device Pin Figure 16. ADC Sampling when AREF is Internally Supplied PROGRAMMABLE ANALOG OUTPUT SUBSYSTEM This subsystem consists of 4 identical DACs whose output is a function of the user programmable registers DACx. This functionality is described in DAC Core. The DAC input registers are individually addressable, as described DAC DATA REGISTER ACCESS. The user can also update all of the DAC input registers to the same value with a single SPI command. See UPDATE ALL DACs Each DAC channel can be individually enabled/disabled via the SPI interface command. See DAC CONFIGURE. When a channel is disabled, its output OUTx is in HiZ state, but the DAC input register still maintains its data. User can select the source of the reference input to all DACs. This functionality is described in DAC Reference Selection DAC Core The DAC core is based on a Resistive String architecture which guarantees monotonicity of its transfer function. The input data is single-registered, meaning that the OUTx of the DAC is updated as soon as the data is updated in the DAC input data register at the end of the SPI transaction. The functional diagram of the DAC Core is shown in Figure 17 VDD DREF 0 1 R R R DDATAx DECODER 10 Buffer OUTx R ä(R) = 200k R 0 1 0 1 PD Device Pin Figure 17. DAC Block Diagram 20 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LMP92018 LMP92018 www.ti.com SNAS514B – NOVEMBER 2011 – REVISED MAY 2013 The ideal DAC core transfer function from DATAx to OUTx , x=0...3, can be expressed as: DDATAx OUTx = DREF 1024 ) ( (3) The above expression is subject to non-idealities of the resistor string and limitations of the output buffer. These limitations are tabulated in Electrical Characteristics In Figure 17, the PD (Power Down) signal is asserted when the given channel is disabled via the SPI command. The PD causes the DAC buffer bias currents to shut down, and it breaks the current path through the resistive string. DAC Reference Selection All DAC channels operate from the same, user selectable, reference source. In Figure 17, DREF input can be supplied by the external source, applied to the REF pin of the device, or from the internal reference generator block. The reference block functionality is described in INTERNAL VOLTAGE REFERENCE SOURCE. Reference selection automatically forces configuration of the DACs' output buffers. If the external reference source, which is DREF driven by the REF device pin, is selected then all of the DAC output buffers are in 1x configuration, as seen inFigure 18. In the external reference mode, each active DAC presents a resistive load to the source attached to the device's REF pin, see Figure 17 and Figure 21. The overall DAC transfers function remains as shown in DAC Core + - 600 Figure 18. DAC Buffer when DREF Externally Supplied If the internal reference generator is selected to drive the DAC's DREF input, then all of the DACs' buffers are automatically forced into 2x gain configuration as shown in Figure 19. This results in an overall transfer function of the DACs to change to: OUTx = 2 x DREF (DDATAx ) 1024 (4) + - 100k 100k Figure 19. DAC Buffer when DREF Internally Supplied DIGITAL TEMPERATURE SENSOR The local temperature sensor (TS) operates in one of the 2 possible modes: Continuous or One-Shot. The user selects the mode of operation via the SPI instruction, see TEMPERATURE SENSOR CONFIGURE. The output of the temperature sensor is a 12 bit signed integer, where each LSB represents 0.0625°C. Temperature sensor's output code (TDATA) examples are shown in Table 1. Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LMP92018 21 LMP92018 SNAS514B – NOVEMBER 2011 – REVISED MAY 2013 www.ti.com Table 1. Temperature Readout Examples Temperature TDATA 125°C 0111.1101.0000 25°C 0001.1001.0000 0.0625°C 0000.0000.0001 0°C 0000.0000.0000 −0.0625°C 1111.1111.1111 −40°C 1101.1000.0000 In Continuous mode, the temperature sensor operates in the background and independently of the SPI bus activity. Subsequent temperature conversion results are stored in the output register which can be accessed by the user via the SPI interface. In One-Shot mode temperature sensor is inactive until the user issues an instruction, via SPI interface, to read the temperature sensor data. The temperature conversion commences at the rising edge of CSB following the read instruction. After the delay of tCONV, the new temperature data is available in the temperature sensor output register. If configured, the DRDYB output indicates when the temperature conversion has been completed, see Figure 20. The SPI instruction for accessing the temperature data is described in TEMPERATURE SENSOR OUTPUT REGISTER In Figure 20 below a One-Shot temperature read transaction is shown. The temperature readback occupies 2 SPI frames: the first frame is used to issue temperature sensor read instruction, the second frame is used for the data readback. The falling edge of the DRDYB signal indicates the instance the new temperature data is present in the output register. The DRDYB is deasserted by the rising edge of the CSB. NOTE: The DRDYB output in One-Shot temperature conversion mode is asynchronous to the SCLK of the SPI interface. DRDYB functionality is not provided in the Continuous mode of the temperature sensor operation. READ TS COMMAND CSB 1 8 DIN 24 12 1 24 arb. SCLK arb. arbitrary activity arbitrary activity DOUT arb. TDATA DRDYB tCONV Figure 20. One-Shot Temperature Read Sequence INTERNAL VOLTAGE REFERENCE SOURCE The device has a built in precision 2.5V reference block which can be used to provide reference potential to either the ADC (AREF) or the DACs (DREF), both at once, or to external load via REF pin. The precision reference is always isolated from its loads by individual buffers, see Figure 21. The CREF register sets the reference block mode of operation. The SPI instruction to update or read contents of the CREF register is shown in REFERENCE CONFIGURE. The switch activity due to the CREF content is tabulated in Table 2. The modes corresponding to CREF=(100) or (110) or (111) are the Deep Sleep modes. In these modes the internal temperature sensor, the ADC, the DACs, and the reference block buffers (but not the 2.5V reference) are powered down. 22 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LMP92018 LMP92018 www.ti.com SNAS514B – NOVEMBER 2011 – REVISED MAY 2013 CREF A REF B C D Reference AREF E DREF SPI Control Word Device Pin Figure 21. Reference Selector Diagram Table 2. Reference Selector Functionality (1 to CLOSE Switch) Switch CREF A B C D E 000 1 0 0 0 1 001 0 0 0 1 1 010 1 1 0 0 0 011 0 1 0 1 0 100 0 0 0 0 0 101 0 0 1 1 1 110 0 0 0 0 0 111 0 0 0 0 0 GENERAL PURPOSE DIGITAL I/O The GPIO[11:0] port is memory mapped to registers SGPI and CGPO. Both registers are accessible through the SPI interface. The SGPI register content reflects at all times the digital state at the GPIOx device pins. The format of the read command of the General Purpose Digital I/O is shown in GPI STATE. The GPIOx pins can be configured as outputs by setting the individual bits in the CGPIO registers. Each bit in CGPIO register enables corresponding output buffer in the GPIOx port. See GPIO CONFIGURE. Once the drive is enabled, the logic state at the outputs is dictated by the contents of the CGPO register. See GPO DATA. The functional diagram of the General Purpose Digital I/O is shown in Figure 22. Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LMP92018 23 LMP92018 SNAS514B – NOVEMBER 2011 – REVISED MAY 2013 www.ti.com SGPI[x] GPIO[x] CGPO[x] EN CGPIO[x] SPI Control Word Device Pin Figure 22. General Purpose Digital I/O Diagram SERIAL INTERFACE The 4-wire interface is compatible with SPI, QSPI and MI- CROWIRE, as well as most DSPs. See the SPI Interface Timing Diagram for timing information of the read and write sequences. The serial interface uses four signals CSB, SCLK, DIN and DOUT. A bus transaction is initiated by the falling edge of the CSB. Once CSB is low, the input data is sampled at the DIN pin by the falling edge of the SCLK, and shifted into the internal shift register (FIFO). The output data is put out on the DOUT pin on the rising edge of SCLK. At least 24 SCLK cycles are required for a valid transfer to occur. If CSB is raised before 24th rising edge of the SCLK, the transfer is aborted and preceding data ignored. If the CSB is held low after the 24th falling edge of the SCLK, the data will continue to flow through the internal shift register (FIFO) and out the DOUT pin. When CSB transitions high, the internal controller decodes the FIFO contents — most recent 24 bits that were received before the rising edge of CSB. While CSB is high, DOUT is in a high-Z state. At the falling edge of CSB, DOUT presents the MSB of the data present in the shift register. DOUT is updated on every subsequent falling edge of SCLK (note — the first DOUT transition will happen on the first rising edge AFTER the first falling edge of SCLK when CSB is low). The 24 bits of data contained in the FIFO are interpreted as an 8 bit COMMAND word followed by 16 bits of DATA. The general format of the 24 bit data stream is shown in Figure 23. The full Instruction Set is tabulated in Instruction Set. COMMAND/PAYLOAD DECODE CSB DIN COMMAND 8 bits PAYLOAD 16 bits Figure 23. General SPI Frame Format SPI Write SPI write operation occupies a single 24–bit frame, as shown in Figure 24. Write operation always starts with a leading 0 (zero) in the 8–bit COMMAND sequence. The format of the data transfer and user instruction set is shown in Instruction Set. Note that write operation also produces DOUT activity. The DOUT output echoes back the previous frame's COMMAND byte, followed by 16 zeros. 24 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LMP92018 LMP92018 www.ti.com SNAS514B – NOVEMBER 2011 – REVISED MAY 2013 Frame 1 Frame 2 CSB DIN DOUT HiZ WRITE COMMAND 8 bits DATA 16 bits Prior COMMAND 8 bits PAYLOAD 16 bits Next Command 8 bits HiZ WRITE COMMAND 8 bits PAYLOAD 16 bits All zero 16 bits HiZ Figure 24. SPI Write Transaction SPI Read The read operation requires all 4 wires of the SPI interface: SCLK, CSB, DIN, DOUT. The simplest read operation occurs automatically during any valid transaction on the SPI bus since DOUT pin always shifts out the leading 8 bits (COMMAND) of the previous transaction — this is regardless of the RW bit setting in the COMMAND byte. This functionality gives the user an easy method of verifying the SPI link. Reading of the specific content requires 2 SPI frames, as shown in Figure 25. The first frame is used to issue a read command, which always begins with RW bit set in the COMMAND byte. The second frame echoes back the first frame's COMMAND byte, followed by the 16–bit PAYLOAD containing the requested data. Consult Instruction Set for the COMMAND format and returned data alignment within PAYLOAD. Frame 1 Frame 2 CSB DIN DOUT HiZ READ COMMAND 8 bits Arbitrary 16 bits Prior COMMAND 8 bits PAYLOAD 16 bits HiZ Next Command 8 bits PAYLOAD 16 bits READ COMMAND 8 bits PAYLOAD 16 bits HiZ Figure 25. SPI Read Transaction SPI Daisy Chain It is possible to control multiple LMP92018s with a single master equipped with one SPI interface. This is accomplished by connecting the multiple LMP92018 devices in a Daisy Chain. The scheme is depicted in Figure 26. A chain of arbitrary length can be constructed since individual devices do not count the data bits shifted in. Instead, they wait to decode the contents of their respective shift registers until CSB is raised high. SYNC CLK (1) (2) (3) SPI/QSPI MICROWIRE CSB CSB CSB MASTER SCLK SCLK SCLK DIN DOUT DIN DOUT DIN DOUT LMP92018 LMP92018 LMP92018 MOSI MISO Figure 26. SPI Daisy Chain Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LMP92018 25 LMP92018 SNAS514B – NOVEMBER 2011 – REVISED MAY 2013 www.ti.com A typical bus cycle for this scheme is initiated by the falling CSB. After the 24 SCLK cycles new data starts to appear at the DOUT pin of the first device in the chain, and starts shifting into the second device. After the 72 SCLK cycles following the falling CSB edge, all three devices in this example will contain new data in their input shift registers. Raising CSB will begin the process of decoding data in each device. When in the Daisy Chain the full READ and WRITE capability of every device is maintained. A sample of SPI data transfer appropriate for a 3 device Daisy Chain is shown in Figure 27. 72 Clock Cycles CSB MOSI DATA (3) DATA (2) DATA (1) Figure 27. SPI Daisy Chain Transaction 26 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LMP92018 LMP92018 www.ti.com SNAS514B – NOVEMBER 2011 – REVISED MAY 2013 Application Circuit Example 5V 0.01 10u + 0.1 499 VDD REF LM4050-4.1 10u 0.01 + 0.1 48V 222k IN0 3.3V 3.3V 1n 10k 10k 5V DRDYB 3.33k IN1 Details of Current Sense Omitted LM8640 1n 12V LMP92018 3.33k LM8262 OUT1 uC To Analog Input 3.3V 10k VIO 4.99k CSB SCLK 1.8V DIN DOUT VGPIO GPIO0 GPIO1 From Digital Output To Digital Input GND Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LMP92018 27 LMP92018 SNAS514B – NOVEMBER 2011 – REVISED MAY 2013 www.ti.com REVISION HISTORY Changes from Revision A (May 2013) to Revision B • 28 Page Changed layout of National Data Sheet to TI format .......................................................................................................... 27 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LMP92018 PACKAGE OPTION ADDENDUM www.ti.com 3-May-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) LMP92018SQ/NOPB ACTIVE WQFN NJK 36 1000 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 125 L92018SQ LMP92018SQE/NOPB ACTIVE WQFN NJK 36 250 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 125 L92018SQ LMP92018SQX/NOPB ACTIVE WQFN NJK 36 2500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 125 L92018SQ (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. 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Addendum-Page 1 Samples PACKAGE MATERIALS INFORMATION www.ti.com 14-Nov-2014 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing LMP92018SQ/NOPB WQFN NJK 36 LMP92018SQE/NOPB WQFN NJK LMP92018SQX/NOPB WQFN NJK SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 1000 330.0 16.4 6.3 6.3 1.5 12.0 16.0 Q2 36 250 178.0 16.4 6.3 6.3 1.5 12.0 16.0 Q2 36 2500 330.0 16.4 6.3 6.3 1.5 12.0 16.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Nov-2014 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMP92018SQ/NOPB WQFN NJK 36 1000 367.0 367.0 38.0 LMP92018SQE/NOPB WQFN NJK 36 250 213.0 191.0 55.0 LMP92018SQX/NOPB WQFN NJK 36 2500 367.0 367.0 38.0 Pack Materials-Page 2 MECHANICAL DATA NJK0036A SQA36A (Rev A) www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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