NXP HEF4952B Dual 3-channel analog multiplexer/demultiplexer with supplementary switch Datasheet

HEF4952B
Dual 3-channel analog multiplexer/demultiplexer with
supplementary switches
Rev. 03 — 16 December 2009
Product data sheet
1. General description
The HEF4952B is a dual 3-channel analog multiplexer/demultiplexer with supplementary
switches and common select logic. Each switch features three independent inputs/outputs
(pins nY0, nY1 and nY2) an input/output nY3 that can be connected to nY2 or VSS and an
input/output (nZ) common to nY0, nY1 and nY2. Three digital select inputs (S1, S2 and
S3) are common to both switches. Inputs include clamp diodes, this enables the use of
current limiting resistors to interface inputs in excess of VDD.
VSS and VDD are the digital control supply pins.
The HEF4952B is suitable for use over the full industrial (−40 °C to +85 °C) temperature
range.
2. Features
„
„
„
„
„
„
„
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Schmitt-trigger action at control inputs
Small signal switch
Standardized symmetrical output characteristics
Operates across the full industrial temperature range −40 °C to +85 °C
Complies with JEDEC standard JESD 13-B
3. Applications
„
„
„
„
Industrial
Analog multiplexing and demultiplexing
Digital multiplexing and demultiplexing
Signal gating
4. Ordering information
Table 1.
Ordering information
All types operate from −40 °C to +85 °C.
Type number
HEF4952BT
Package
Name
Description
Version
SO16
plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
HEF4952B
NXP Semiconductors
Dual 3-channel analog multiplexer/demultiplexer
5. Functional diagram
VDD
15
16
S1
S3
1Y0
7
14
S2
1Z
9
3-TO-5
DECODER
LOGIC
LEVEL
CONVERTER
12
1Y1
1Y2
10
11
VSS
1Y3
VEE
VSS
2
1
3
5
6
2Z
2Y0
2Y1
2Y2
2Y3
VSS
001aad872
Fig 1.
Functional diagram
HEF4952B_3
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 03 — 16 December 2009
2 of 15
HEF4952B
NXP Semiconductors
Dual 3-channel analog multiplexer/demultiplexer
logic level
converter
1Z
S1
1Y0
1SY0
S2
1Y1
1SY1
1Y2
S3
1SY2
1Y3
1SY3
1SY4
VSS
2Z
2Y0
2SY0
2Y1
2SY1
2Y2
2SY2
2Y3
2SY3
2SY4
VSS
001aad873
Fig 2.
Logic diagram
HEF4952B_3
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 03 — 16 December 2009
3 of 15
HEF4952B
NXP Semiconductors
Dual 3-channel analog multiplexer/demultiplexer
6. Pinning information
6.1 Pinning
HEF4952B
2Y0
1
16 1Y0
2Z
2
15 1Z
2Y1
3
14 1Y1
VEE
4
13 VDD
2Y2
5
12 1Y2
2Y3
6
11 1Y3
S1
7
10 S3
VSS
8
9
S2
001aad871
Fig 3.
Pin configuration
6.2 Pin description
Table 2.
Pin description
Symbol
Pin
VEE
4
supply voltage
VSS
8
ground supply voltage
S1, S2, S3
7, 9, 10
select input
1Y0, 1Y1, 1Y2, 1Y3, 2Y0, 2Y1, 2Y2, 2Y3
16, 14, 12, 11, 1, 3, 5, 6
independent input or output
1Z, 2Z
15, 2
common output or input
VDD
13
supply voltage
HEF4952B_3
Product data sheet
Description
© NXP B.V. 2009. All rights reserved.
Rev. 03 — 16 December 2009
4 of 15
HEF4952B
NXP Semiconductors
Dual 3-channel analog multiplexer/demultiplexer
7. Functional description
7.1 Function table
Table 3.
Function table
Input
Switch
S3
S2
S1
nSY0
nSY1
nSY2
nSY3
nSY4
L
L
L
open
nY1 to nZ
open
open
nY3 to VSS
L
L
H
nY0 to nZ
open
open
open
nY3 to VSS
L
H
L
open
open
nY2 to nZ
open
nY3 to VSS
L
H
H
nY0 to nZ
open
nY2 to nZ
open
nY3 to VSS
H
L
L
open
nY1 to nZ
open
nY2 to nY3
open
H
L
H
nY0 to nZ
open
open
nY2 to nY3
open
H
H
L
open
open
nY2 to nZ
nY2 to nY3
open
H
H
H
open
open
open
nY2 to nY3
open
[1]
H = HIGH voltage level;
L = LOW voltage level.
8. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VSS = 0 V (ground).
Symbol
Parameter
VDD
supply voltage
Conditions
[1]
Min
Max
Unit
−0.5
+18
V
−18
+0.5
V
VEE
supply voltage
referenced to VDD
IIK
input clamping current
pins Sn;
VI < −0.5 V or VI > VDD + 0.5 V
VI
input voltage
−0.5
VDD + 0.5
V
II/O
input/output current
-
±10
mA
-
±10
mA
IDD
supply current
-
50
mA
Tstg
storage temperature
−65
+150
°C
Tamb
ambient temperature
−40
+85
°C
-
500
mW
-
100
mW
Ptot
total power dissipation
Tamb = −40 °C to +85 °C
P
power dissipation
per output
[2]
[1]
To avoid drawing VDD current out of terminal Z, when switch current flows into terminals Y, the voltage drop across the bidirectional
switch must not exceed 0.4 V. If the switch current flows into terminal Z, no VDD current will flow out of terminals Y, and in this case there
is no limit for the voltage drop across the switch, but the voltages at Y and Z may not exceed VDD or VEE.
[2]
For SO16 package: Ptot derates linearly with 8 mW/K above 70 °C.
HEF4952B_3
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 03 — 16 December 2009
5 of 15
HEF4952B
NXP Semiconductors
Dual 3-channel analog multiplexer/demultiplexer
9. Recommended operating conditions
Table 5.
Recommended operating conditions
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDD
supply voltage
see Figure 4
5
-
15
V
VEE
supply voltage
see Figure 4
VI
input voltage
Tamb
ambient temperature
in free air
-15
-
0
V
0
-
VDD
V
−40
-
+85
°C
001aad874
15
VDD − VSS
(V)
10
operating area
5
0
0
Fig 4.
5
10
VDD − VEE (V)
15
Operating area as a function of the supply voltages
10. Static characteristics
Table 6.
Static characteristics
VSS = VEE = 0 V; VI = VSS or VDD unless otherwise specified.
Symbol
Parameter
Conditions
VDD
II
input leakage
current
IS(OFF)
OFF-state
leakage current
Y port; per channel;
see Figure 5
IDD
supply current
IO = 0 A
CI
input
capacitance
Sn inputs
Tamb = −40 °C
Tamb = 85 °C
Unit
Min
Max
Min
Max
Min
Max
15 V
-
±0.3
-
±0.3
-
±1.0
μA
15 V
-
-
-
200
-
-
nA
5V
-
20
-
20
-
150
μA
10 V
-
40
-
40
-
300
μA
15 V
-
80
-
80
-
600
μA
-
-
-
-
7.5
-
-
pF
HEF4952B_3
Product data sheet
Tamb = 25 °C
© NXP B.V. 2009. All rights reserved.
Rev. 03 — 16 December 2009
6 of 15
HEF4952B
NXP Semiconductors
Dual 3-channel analog multiplexer/demultiplexer
10.1 Test circuits
VDD
S1 to S3
VDD or VSS
nZ
Y0
1
nYn
2
switch
IS
VSS = VEE
VO
VI
001aak653
Fig 5.
Test circuit for measuring OFF-state leakage current nYn port
10.2 On resistance
Table 7.
ON resistance
Tamb = 25 °C; ISW = 200 μA; VSS = VEE = 0 V.
Symbol
Parameter
Conditions
VDD − VEE
Typ
Max
Unit
RON
ON resistance
VI = 0 V; see Figure 6 and Figure 7
10 V
45
150
Ω
VI = 2.5 V; see Figure 6 and Figure 7
10 V
65
365
Ω
VI = 5.0 V; see Figure 6 and Figure 7
10 V
110
360
Ω
VI = 2.5 V; see Figure 6
10 V
10
-
Ω
ΔRON
ON resistance mismatch
between channels
10.2.1 On resistance waveform and test circuit
V
VDD
VDD or VSS
VSW
S1 to S3
nZ
nYn
VSS = VEE
ISW
VI
001aak654
RON = VSW / ISW.
Fig 6.
Test circuit for measuring RON
HEF4952B_3
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 03 — 16 December 2009
7 of 15
HEF4952B
NXP Semiconductors
Dual 3-channel analog multiplexer/demultiplexer
001aad876
120
RON
(Ω)
80
VDD = 10 V
40
0
0
2
4
6
VI (V)
Fig 7.
Typical RON as a function of input voltage
11. Dynamic characteristics
Table 8.
Dynamic characteristics
Tamb = 25 °C; VSS = VEE = 0 V; for test circuit see Figure 10.
Symbol
Parameter
Conditions
tPHL
HIGH to LOW propagation delay
nYn, nZ to nZ, nYn; VI = 1.0 V;
see Figure 8
tPLH
tPZL
tPZH
LOW to HIGH propagation delay
OFF-state to LOW
propagation delay
OFF-state to HIGH
propagation delay
nYn, nZ to nZ, nYn; VI = 1.0 V;
see Figure 8
Sn to nYn, nZ; VI =VEE; see Figure 9
Sn to nYn, nZ; VI = 1.0 V; see Figure 9
HEF4952B_3
Product data sheet
VDD
Typ
Max
Unit
5V
5
-
ns
10 V
3
6
ns
15 V
2
-
ns
5V
5
-
ns
10 V
3
6
ns
15 V
2
-
ns
5V
125
-
ns
10 V
50
100
ns
15 V
35
-
ns
5V
125
-
ns
10 V
50
100
ns
15 V
35
-
ns
© NXP B.V. 2009. All rights reserved.
Rev. 03 — 16 December 2009
8 of 15
HEF4952B
NXP Semiconductors
Dual 3-channel analog multiplexer/demultiplexer
11.1 Waveforms and test circuit
VI
nYn or nZ
input
VM
VEE
tPLH
tPHL
VO
nZ or nYn
output
VM
VEE
001aak655
Measurement points are given in Table 9.
Fig 8.
nYn, nZ to nZ, nYn propagation delays
VDD
Sn input
VM
VSS
tPZL
nYn or nZ output
LOW-to-OFF
OFF-to-LOW
VO
90 %
10 %
VEE
tPZH
VO
90 %
nYn or nZ output
HIGH-to-OFF
OFF-to-HIGH
10 %
VEE
switch ON
switch OFF
switch ON
001aak656
Measurement points are given in Table 9.
Fig 9.
Enable and disable times
Table 9.
Measurement points
Supply voltage
Input
Output
VDD
VM
VM
5 V to 15 V
0.5VDD
0.5VDD
HEF4952B_3
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 03 — 16 December 2009
9 of 15
HEF4952B
NXP Semiconductors
Dual 3-channel analog multiplexer/demultiplexer
tW
VI
negative
pulse
0V
90 %
VM
10 %
tf
tr
tr
tf
VI
positive
pulse
0V
VM
10 %
90 %
VM
VM
tW
1.0 V
VDD VI
PULSE
GENERATOR
VI
VO
S1
RL
open
DUT
RT
CL
VSS
VEE
001aak780
Test data is given in Table 10.
Definitions:
DUT = Device Under Test.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including test jig and probe.
RL = Load resistance.
Fig 10. Test circuit for measuring switching times
Table 10.
Test data
Input
Load
S1 position
nYn, nZ
Sn
tr, tf
VM
CL
RL
tPHL, tPLH
tPZH
tPZL
Other
VI or VEE
VDD or VSS
≤ 20 ns
0.5VDD
50 pF
10 kΩ
VEE
VEE
1.0 V
VEE
Table 11. Dynamic power dissipation PD
PD can be calculated from the formulas shown; VEE = VSS = 0 V; tr = tf ≤ 20 ns; Tamb = 25 °C.
Symbol
Parameter
VDD
Typical formula for PD (μW)
PD
dynamic power
dissipation
5V
PD = 1300 × fi + Σ(fo × CL) × VDD2
Where:
fi = input frequency in MHz;
10 V
PD = 6100 × fi + Σ(fo × CL) × VDD
fo = output frequency in MHz;
15 V
PD = 15600 × fi + Σ(fo × CL) ×
2
VDD2
CL = output load capacitance in pF;
VDD = supply voltage in V;
Σ(fo × CL) = sum of the outputs.
HEF4952B_3
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 03 — 16 December 2009
10 of 15
HEF4952B
NXP Semiconductors
Dual 3-channel analog multiplexer/demultiplexer
11.2 Transfer characteristics
Table 12. Control input characteristics
VSS = VEE = 0 V unless otherwise specified.
Symbol Parameter
VT+
positive-going threshold voltage
Conditions
Tamb = 25 °C
Tamb = −40 °C to +85 °C
Unit
Min
Max
Min
Max
VDD = 5 V
-
2.90
-
3.00
V
VDD = 10 V
-
4.37
-
4.50
V
-
1.00
-
V
VT−
negative-going threshold voltage
VDD = 5 V
1.03
VDD = 10 V
2.10
-
2.00
-
V
VH
hysteresis voltage
VDD = 5 V
0.16
-
0.10
-
V
VDD = 10 V
0.11
-
0.10
-
V
HEF4952B_3
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 03 — 16 December 2009
11 of 15
HEF4952B
NXP Semiconductors
Dual 3-channel analog multiplexer/demultiplexer
12. Package outline
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
c
y
HE
v M A
Z
16
9
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
1
L
8
e
0
detail X
w M
bp
2.5
5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
Z (1)
mm
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
1.27
6.2
5.8
1.05
1.0
0.4
0.7
0.6
0.25
0.25
0.1
0.7
0.3
0.01
0.019 0.0100 0.39
0.014 0.0075 0.38
0.039
0.016
0.028
0.020
inches
0.010 0.057
0.069
0.004 0.049
0.16
0.15
0.05
0.244
0.041
0.228
0.01
0.01
0.028
0.004
0.012
θ
o
8
o
0
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT109-1
076E07
MS-012
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
Fig 11. Package outline SOT109-1 (SO16)
HEF4952B_3
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 03 — 16 December 2009
12 of 15
HEF4952B
NXP Semiconductors
Dual 3-channel analog multiplexer/demultiplexer
13. Revision history
Table 13.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
HEF4952B_3
20091216
Product data sheet
-
HEF4952B_2
Modifications:
•
•
•
•
Title changed from 8-channel analog multiplexer/demultiplexer.
Section 1 “General description” modified.
Section 8 “Limiting values” IIK conditions updated.
Abbreviations section removed.
HEF4952B_2
20091002
Product data sheet
-
HEF4952B_1
HEF4952B_1
20060320
Product data sheet
-
-
HEF4952B_3
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 03 — 16 December 2009
13 of 15
HEF4952B
NXP Semiconductors
Dual 3-channel analog multiplexer/demultiplexer
14. Legal information
14.1 Data sheet status
Document status[1][2]
Product status[3]
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
Definition
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
14.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
14.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
14.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
15. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
HEF4952B_3
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 03 — 16 December 2009
14 of 15
HEF4952B
NXP Semiconductors
Dual 3-channel analog multiplexer/demultiplexer
16. Contents
1
2
3
4
5
6
6.1
6.2
7
7.1
8
9
10
10.1
10.2
10.2.1
11
11.1
11.2
12
13
14
14.1
14.2
14.3
14.4
15
16
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 1
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional description . . . . . . . . . . . . . . . . . . . 5
Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended operating conditions. . . . . . . . 6
Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
On resistance . . . . . . . . . . . . . . . . . . . . . . . . . . 7
On resistance waveform and test circuit. . . . . . 7
Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
Waveforms and test circuit . . . . . . . . . . . . . . . . 9
Transfer characteristics . . . . . . . . . . . . . . . . . 11
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 13
Legal information. . . . . . . . . . . . . . . . . . . . . . . 14
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 14
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Contact information. . . . . . . . . . . . . . . . . . . . . 14
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 16 December 2009
Document identifier: HEF4952B_3
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