PHILIPS BT16273DGG 16-bit d-type flip-flop Datasheet

INTEGRATED CIRCUITS
74ABT16273
74ABTH16273
16-bit D-type flip-flop
Product specification
Supersedes data of 1995 Sep 28
IC23 Data Handbook
1998 Feb 27
Philips Semiconductors
Product specification
74ABT16273
74ABTH16273
16-bit D-type flip-flop
FEATURES
DESCRIPTION
• 16-bit D-type edge triggered flip-flops
• Output capability: +64mA/–32mA
• TTL input and output switching levels
• Live insertion/extraction permitted
• Power-up reset
• 74ABTH16273 incorporates bus-hold data inputs which eliminate
The 74ABT16273 high-performance BiCMOS device combines low
static and dynamic power dissipation with high speed and high
output drive.
This part is a 16-bit edge triggered D-type flip-flop with non-inverting
high drive outputs. This device can be used as two 8-bit flip-flops or
one 16-bit flip-flop. When the clock (CP) goes High, the data on the
D inputs is stored and the Q outputs display the stored data.
This device also features a master reset (MR) that resets all
flip-flops to the Low state when MR is set to the Low state.
the need for external pull-up resistors to hold unused inputs
• Latch-up protection exceeds 500mA per JEDEC Std 17
• ESD protection exceeds 2000V per MIL STD 883 Method 3015
Two options are available, 74ABT16273 which does not have the
bus-hold feature and 74ABTH16273 which incorporates the
bus-hold feature.
and 200V per Machine Model
QUICK REFERENCE DATA
SYMBOL
CONDITIONS
Tamb = 25°C; GND = 0V
PARAMETER
tPLH
tPHL
Propagation delay
An to Bn or Bn to An
CL = 50pF;
VCC = 5.0V
CIN
Input capacitance
VI = 0V or VCC
Quiescent su
supply
ly current
Outputs High; VCC = 5.5V
Outputs low; VCC = 5.5V
ICCH
ICCL
TYPICAL
UNIT
2.5
2.0
ns
4
pF
200
µA
8
mA
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
DWG NUMBER
48-Pin Plastic SSOP Type III
–40°C to +85°C
74ABT16273 DL
BT16273 DL
SOT370-1
48-Pin Plastic TSSOP Type II
–40°C to +85°C
74ABT16273 DGG
BT16273 DGG
SOT362-1
48-Pin Plastic SSOP Type III
–40°C to +85°C
74ABTH16273 DL
BH16273 DL
SOT370-1
48-Pin Plastic TSSOP Type II
–40°C to +85°C
74ABTH16273 DGG
BH16273 DGG
SOT362-1
PIN NUMBER
SYMBOL
NAME AND
FUNCTION
1, 24
1MR, 2MR
2, 3, 5, 6, 8, 9, 11, 12,13,
14, 16, 17, 19, 20, 22, 23
1Q0-1Q7
2Q0-2Q7
Data outputs
47, 46, 44, 43, 41, 40, 38, 37,
36, 35, 33, 32, 30, 29, 27, 26
1D0-1D7
2D0-2D7
Data inputs
25, 48
1CP, 2CP
Clock pulse input
(active rising edge)
4, 10, 15, 21, 28, 34, 39, 45
GND
Ground (0V)
7, 18, 31, 42
VCC
Positive supply
voltage
LOGIC SYMBOL
47
PIN DESCRIPTION
46
44
43
41
40
38
37
Master reset input
(active-Low)
1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7
48
CP
1
MR
1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7
2
3
5
6
8
9
11
12
36
35
33
32
30
29
27
26
2D0 2D21 2D2 2D3 2D4 2D5 2D6 2D7
25
CP
24
MR
2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7
13
14
16
17
19
20
22
23
SH00052
1998 Feb 27
2
853-1793 19027
Philips Semiconductors
Product specification
74ABT16273
74ABTH16273
16-bit D-type flip-flop
LOGIC SYMBOL (IEEE/IEC)
1MR
1
CP
48
2MR
24
2CP
25
1D0
47
1D1
46
PIN CONFIGURATION
1MR
1
48
CP
C1
1Q0
2
47
1D0
R2
!Q1
3
46
1D1
C2
GND
4
45
GND
1Q2
5
44
1D2
1D3
R1
1∇
1D
2
1Q0
3
!Q1
1D2
44
1D3
43
6
1Q3
1D4
41
8
1Q4
1D5
40
9
1Q5
1D6
1D7
2D0
2D1
2D2
2D3
5
38
11
37
12
36
2∇
2D
35
13
14
33
16
32
17
1Q2
6
43
7
42
VCC
1Q4
8
41
1D4
1Q5
9
40
1D5
GND
10
39
GND
1Q6
11
38
1D6
1Q7
12
37
1D7
2Q0
13
36
2D0
2Q1
14
35
2D1
GND
15
34
GND
2Q2
16
33
2D2
2Q3
17
32
2D3
VCC
18
31
VCC
2Q4
19
30
2D4
1Q6
1Q7
2Q0
2Q1
2Q2
2Q3
2D4
30
19
2Q4
2D5
29
20
2Q5
2D6
27
22
2Q6
2D7
26
23
2Q7
SH00053
FUNCTION TABLE
2Q5
20
29
2D5
GND
21
28
GND
2Q6
22
27
2D6
2Q7
23
26
2D7
2MR
24
25
2CP
SH00054
Inputs
Output
operating
mode
nMR
nCP
nDX
nQ0-nQ7
L
X
X
L
Reset (clear)
H
↑
h
H
Load “1”
H
↑
I
L
Load “0”
H
L
X
Q0
Retain state
H = High voltage level
h = high voltage level one set-up time prior to the Low-to-High
clock transition
L = Low voltage level
I = Low voltage level one set-up time prior to the Low-to-High
clock transition
X = Don’t care
↑ = Low-to-High clock transition
Q0 = Output as it was
1998 Feb 27
1Q3
VCC
3
Philips Semiconductors
Product specification
74ABT16273
74ABTH16273
16-bit D-type flip-flop
LOGIC DIAGRAM
nD1
nD0
nD2
nD3
nD4
nD5
nD6
nD7
nCP
D
Q
D
CP
Q
D
CP
RD
RD
Q
Q
D
CP
D
CP
RD
Q
RD
Q
D
CP
D
CP
RD
Q
RD
Q
D
CP
CP
RD
RD
nMR
nQ0
nQ1
nQ2
nQ3
nQ4
nQ5
nQ6
n = 1 or 2
nQ7
SH00055
ABSOLUTE MAXIMUM RATINGS1, 2
PARAMETER
SYMBOL
VCC
IIK
RATING
UNIT
–0.5 to –7.0
V
–18
mA
–1.2 to +7.0
V
VO < 0
–50
mA
Output in Off or High state
–0.5 to +5.5
V
Output in Low state
128
Output in High state
–64
DC supply voltage
DC input diode current
VI < 0
voltage3
VI
DC input
IOK
DC output diode current
VOUT
CONDITIONS
DC output
voltage3
IOUT
O
DC output current
Tstg
Storage temperature range
mA
–65 to +150
°C
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
VCC
PARAMETER
LIMITS
DC supply voltage
UNIT
MIN
MAX
4.5
5.5
V
0
VCC
V
VI
Input voltage
VIH
High-level input voltage
VIL
Input voltage
0.8
V
IOH
High-level output current
–32
mA
IOL
Low-level output current
64
mA
0
10
ns/V
–40
+85
°C
∆t/∆v
Input transition rise or fall rate; Outputs enabled
Tamb
Operating free-air temperature range
1998 Feb 27
2.0
4
V
Philips Semiconductors
Product specification
74ABT16273
74ABTH16273
16-bit D-type flip-flop
DC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
VIK
Input clamp voltage
Temp = -40°C
to +85°C
Temp = +25°C
TYP
MAX
0.9
–1.2
VCC = 4.5V; IIK = –18mA
MIN
MAX
–1.2
VCC = 4.5V; IOH = –3mA; VI = VIL or VIH
2.5
2.9
2.5
VCC = 5.0V; IOH = –3mA; VI = VIL or VIH
3.0
3.4
3.0
VCC = 4.5V; IOH = –32mA; VIL or VIH
2.0
UNIT
V
V
VOH
High-level output voltage
VOL
Low-level output voltage
VCC = 4.5V; IOL = 64mA; VI = VIL or VIH
0.42
0.55
0.55
VRST
Power-up output
voltage3
VCC = 5.5V; IO = 1mA; VI = GND or VCC
0.13
0.55
0.55
V
Input leakage
g current
74ABT16273
5V; VI = VCC or GND
VCC = 5
5.5V;
±0 1
±0.1
±1
±1
µA
µ
±0.01
±1
±1
µA
0.01
1
1
µA
–2
–3
–5
µA
II
Control
pins
VCC = 5.5V; VI = VCC or GND
II
Input
In
ut leakage current
74ABTH16273
2.4
VCC = 5.5V; VI = VCC
Data pins
VCC = 5.5V; VI = 0
IHOLD
IOFF
IO
ICEX
ICCH
Bus Hold
B
H ld currentt inputs
i
t 4
74ABTH16273
VCC = 4.5V; VI = 0.8V
35
35
VCC = 4.5V; VI = 2.0V
–75
–75
VCC = 5.5V; VI = 0 to 5.5V
±800
Power-off leakage
current
VCC= 0.0V; VO or VI 4.5V
output current1
VCC = 5.5V; VO = 2.5V
Output High leakage
current
Quiescent supply current
ICCL
2.0
±5.0
±100
–70
–180
VCC = 5.5V; VO = 5.5V; VI = GND or VCC
5.0
VCC = 5.5V; Outputs High, VI = GND or VCC
µA
±100
µA
–180
mA
50
50
µA
0.2
1
1
VCC = 5.5V; Outputs Low, VI = GND or VCC
8
19
19
–50
–50
mA
∆ICC
Additional supply current
per input pin2
74ABT16273
VCC = 5.5V; One input at 3.4V.
Other inputs at VCC or GND
5
100
100
µA
∆ICC
Additional supply current
per input pin2
74ABTH16273
VCC = 5.5V; One input at 3.4V.
Other inputs at VCC or GND
0.2
1
1
mA
NOTES:
1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
2. This is the increase in supply current for each input at 3.4V.
3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.
4. This is the bus hold overdrive current required to force the input to the opposite logic state.
AC CHARACTERISTICS
GND = 0V; tR = tF = 2.5ns; CL = 50pF; RL = 500Ω;
LIMITS
SYMBOL
PARAMETER
UNIT
MIN
TYP
MAX
MIN
MAX
1
1.5
1.2
2.5
2.0
3.4
2.7
1.5
1.2
4.0
3.0
ns
Propagation delay
nMR to nQx
2
1.9
3.7
4.3
1.9
5.3
ns
Maximum clock frequency
1
150
240
tPLH
tPHL
Propagation delay
nCP to nQx
tPHL
fMAX
1998 Feb 27
Tamb = –40 to +85 °C
VCC = +5.0V ±0.5V
Tamb = +25°C
VCC = +5.0V
WAVEFORM
5
150
MHz
Philips Semiconductors
Product specification
74ABT16273
74ABTH16273
16-bit D-type flip-flop
AC SETUP REQUIREMENTS
GND = 0V; tR = tF = 2.5ns; CL = 50pF; RL = 500Ω
LIMITS
SYMBOL
PARAMETER
Tamb = +25°C
VCC = +5.0V
WAVEFORM
Tamb = –40 to +85 °C
VCC = +5.0V ±0.5V
UNIT
MIN
TYP
MIN
3
2.0
2.0
1.0
1.0
2.0
2.0
ns
Hold time, High or Low
nDx to nCP
3
0
0
–0.6
–0.6
0
0
ns
tW(H)
tW(L)
Clock pulse width
High or Low
1
3.3
3.3
1.2
1.0
3.3
3.3
ns
tW(L)
Master Reset pulse width, Low
2
3.3
1.1
3.3
ns
tREC
Recovery time
nMR + nCP
2
2.0
0.0
2.0
ns
tS(H)
tS(L)
Setup time, High or Low
nDx to nCP
th(H)
th(L)
AC WAVEFORMS
VM = 1.5V, VIN = GND to 2.7V
nDx
1/fMAX
ÉÉÉ ÉÉÉÉÉÉÉ
ÉÉÉ
ÉÉÉ ÉÉÉÉÉÉÉ
ÉÉÉ
ÉÉÉ ÉÉÉÉÉÉÉ
ÉÉÉ
VM
VM
ts(H)
nCP
VM
VM
VM
VM
th(H)
VM
ts(L)
0V
th(L)
0V
tW(H)
nCP
tW(L)
tPHL
VM
0V
VOH
nQx
VM
tPLH
VM
NOTE: The shaded areas indicate when the input is
permitted to change for predictable output performance.
VM
VOL
SH00058
SH00056
Waveform 3. Data Setup and Hold Times
Waveform 1. Propagation Delay, Clock Input to Output, Clock
Pulse Width, and Maximum Clock Frequency
nMR
VM
VM
0V
tw(L)
tREC
VM
nCP
0V
tPHL
VOH
nQx
VM
VOL
SH00057
Waveform 2. Master Reset Pulse Width, Master Reset to Output
Delay and Master Reset to Clock Recovery Time
1998 Feb 27
6
Philips Semiconductors
Product specification
74ABT16273
74ABTH16273
16-bit D-type flip-flop
TEST CIRCUIT AND WAVEFORM
tW
90%
VCC
90%
VM
NEGATIVE
PULSE
AMP (V)
VM
10%
10%
0V
PULSE
GENERATOR
VIN
VOUT
D.U.T.
RT
CL
RL
tTHL (tF)
tTLH (tR)
tTLH (tR)
tTHL (tF)
90%
POSITIVE
PULSE
AMP (V)
90%
VM
VM
10%
Test Circuit for Outputs
10%
tW
0V
VM = 1.5V
Input Pulse Definition
DEFINITIONS
RL = Load resistor; see AC CHARACTERISTICS for value.
CL = Load capacitance includes jig and probe capacitance;
see AC CHARACTERISTICS for value.
RT = Termination resistance should be equal to ZOUT of
pulse generators.
INPUT PULSE REQUIREMENTS
FAMILY
74ABT16
Amplitude
Rep. Rate
tW
tR
tF
3.0V
1MHz
500ns
2.5ns
2.5ns
SH00059
1998 Feb 27
7
Philips Semiconductors
Product specification
74ABT16273
74ABTH16273
16-bit D-type flip-flop
SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm
1998 Feb 27
8
SOT370-1
Philips Semiconductors
Product specification
74ABT16273
74ABTH16273
16-bit D-type flip-flop
TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1mm
1998 Feb 27
9
SOT362-1
Philips Semiconductors
Product specification
74ABT16273
74ABTH16273
Data sheet status
Data sheet
status
Product
status
Definition [1]
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
 Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
print code
Document order number:
yyyy mmm dd
10
Date of release: 05-96
9397-750-03489
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