STMicroelectronics AN4192 In the latest generation of cpus for modern desktop and notebook platform Datasheet

AN4192
Application note
Power MOSFETs:
best choice guide for VRM applications
By Filadelfo Fusillo, Filippo Scrimizzi
Introduction
In the latest generation of CPUs for modern desktop and notebook platforms, the VRMs
(voltage regulator modules) must have some specific features in order to reach high
performance in terms of power management. This target can be reached by analyzing all
the design parameters and their optimization, with a particular focus on the MOSFET
electrical characteristics and configuration.
The power stage must deliver very low core voltage (typically 1.2 V - 1.3 V) to the CPU at
high current levels (up to 160 A), with ever-increasing switching frequencies (up to 500 - 700
kHz). In order to match these requirements, the basic topology used in the VRMs is the
“multiphase synchronous buck converter”, which typically steps down to 12 V input voltage,
providing the desired core voltage.
November 2012
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Contents
AN4192
Contents
1
Synchronous buck converter: a brief introduction . . . . . . . . . . . . . . . . 6
2
High-side MOSFET selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3
2.0.1
QG,SW and fSW impact on the efficiency . . . . . . . . . . . . . . . . . . . . . . . . 10
2.0.2
QG,SW impact on the HS switching behavior . . . . . . . . . . . . . . . . . . . . . 12
2.1
RDS(on) and conduction losses minimization . . . . . . . . . . . . . . . . . . . . . . 14
2.2
Gate drive network optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Low-side FET selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.1
RDS(on) and conduction losses minimization . . . . . . . . . . . . . . . . . . . . . 20
3.2
CGD (Miller capacitance) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.3
LS body-drain diode Qrr (reverse recovery charge) . . . . . . . . . . . . . . . . . 24
3.4
RG and LS gate-source bouncing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.5
RC snubber network settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.6
Phase node spike - VCORE relationship . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4
Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5
Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
6
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
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List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
HS FETs electrical parameters comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
MOSFET electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Main electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Device electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
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List of figures
AN4192
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
Figure 45.
Figure 46.
Figure 47.
Figure 48.
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Synchronous buck converter simplified schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
HS/LS gate-source voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Multiphase synchronous buck converter schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Gate charge waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2-phase synchronous buck converter schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Efficiency comparison @ 440 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Efficiency @ 300 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
MOSFET equivalent circuit during Miller plateau . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
MOS1 (CGD = 76 pF) - HS turn-off waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
MOS1 (CGD = 150 pF) - HS turn-off waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Single-phase synchronous buck converter schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Efficiency comparison @ Vout = 1.25 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
HS turn-off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
HS turn-on (phase node spike) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Typical phase node waveform (without RC snubber network) . . . . . . . . . . . . . . . . . . . . . . 15
Asymmetric HS gate drive circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3-phase synchronous buck converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Phase node waveform - standard configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Phase node waveform - HS asymmetric gate drive configuration . . . . . . . . . . . . . . . . . . . 17
Efficiency comparison @ Vout = 1.26 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Efficiency vs. Iout @ Vout = 1.25 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Buck converter schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Impact of the stray inductances on the phase node ringing . . . . . . . . . . . . . . . . . . . . . . . . 21
Low-CRSS LS FET phase node waveform @ 80 A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
High-CRSS LS FET phase node waveform @ 80 A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Single-phase synchronous buck converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Reverse recovery charge waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Body-drain diode reverse recovery current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Single-phase synchronous buck converter schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Standard LS waveforms @ 20 A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
LS with monolithic Schottky diode waveforms @ 20 A . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2-phase synchronous buck converter schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Monolithic Schottky impact on the efficiency @ 610 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . 28
LS FET during HS turn-on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Low ext. RG (2 Ω) LS FET waveforms during HS turn-on . . . . . . . . . . . . . . . . . . . . . . . . . 30
High ext. RG (4.7 Ω) LS FET waveforms during HS turn-on. . . . . . . . . . . . . . . . . . . . . . . . 30
Low RG,LS(INT) (1.5 Ω) LS FET waveforms @ full load . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
High RG,LS(INT) (3 Ω) LS FET waveforms @ full load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2-phase synchronous buck converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Low RG,LS(INT) (1.3 Ω) waveforms @ full load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
High RG,LS(INT) waveforms @ full load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Simplified LS FET circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Single-phase synchronous buck converter schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
1 x LS vs. 2 x LS (LS G-S ringing improvement) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
LS gate-source bouncing reduction for bigger die size LS FETs . . . . . . . . . . . . . . . . . . . . 35
LS FET with RC snubber network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Phase node waveform and fRING evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Original configuration waveforms @ 20 A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
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Figure 49.
Figure 50.
Figure 51.
Figure 52.
Figure 53.
Figure 54.
Figure 55.
Figure 56.
List of figures
RG,HS(EXT) = 0 Ω - RG,HS(EXT) = 1.8 Ω/original snubber waveforms @ 20 A. . . . . . . . . . . . 38
RG,HS(EXT) = 2.2 Ω - RG,HS(EXT) = 1.8 Ω/ original snubber waveforms @ 20 A. . . . . . . . . . 39
RG,HS(EXT) = 2.2 Ω - RG,HS(EXT) = 1.8 Ω/ RSNUB = 1 Ω waveforms @ 20 A . . . . . . . . . . . . 40
Phase node improvement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3-phase synchronous buck converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Phase node waveform @ 2.5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Phase node waveform @ 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Phase node spike - VOUT chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
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Synchronous buck converter: a brief introduction
1
AN4192
Synchronous buck converter: a brief introduction
The basic topology of a single-phase synchronous buck converter (SBC) is shown in
Figure 1; SW1 is the main (or high-side) FET, SW2 is the synchronous (or low-side) FET, L
and C are the output filters.
Figure 1.
Synchronous buck converter simplified schematic
AM16445V1
Comparing this topology to the standard buck converter, the main difference is the
synchronous rectifier (SW2) instead of the free-wheeling diode; as VDS(on) < VF,DIODE, a
strong reduction of the ON-state losses is guaranteed.
SW1 and SW2 are driven in a “synchronous” way: in other words, the control IC generates
the gate driving signals, avoiding the simultaneous conduction of the two FETs (crossconduction or shoot-through). So, when SW1 is in the ON-state, SW2 is turned off and vice
versa. Obviously, to prevent HS and LS gate-source voltages overlapping and any crossconduction issue, there are some time intervals (fixed by the control IC) where HS and LS
FETs are in the OFF-state (deadtime).
In Figure 2, the typical waveforms of a single-phase synchronous buck converter are
represented. When the HS FET (SW1) is turned on, its drain current rises with a positive
slope:
dI L
Vin – V core
-------- = --------------------------L
dt
during HS ton. When HS switches off, the LS FET remains in the HOLD state: the energy
stored in L can't become zero immediately, so it freewheels through the LS body-drain diode
(from source to drain, VDS,LS = -0.7 V). When the LS turns on, the load current diverts from
the body diode to the LS channel, with a negative slope:
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Synchronous buck converter: a brief introduction
dI
Vcore
-------L- = – ------------dt
L
Figure 2.
HS/LS gate-source voltages
AM16446V1
The load current doesn't become zero (the output coil doesn't discharge completely): the
converter works in continuous current mode (CCM). After the LS turns off, the load current
re-flows through the LS body diode (deadtime) and then another switching cycle begins.
As the input voltage is typically 12 V and the core voltage is 1.2 - 1.3 V, the converter duty
cycle is small (0.1- 0.2%): then, the HS FET is on for a shorter time, while the LS FET has
longer ton.
Modern VRM topologies should have some additional features:
●
High switching frequencies working capability
●
Ever-increasing output current to be delivered to the load
●
Input and output current ripple minimized.
To match these requirements, the “multiphase” approach (Figure 3) is universally used,
developed by interleaving more single-phase SBCs, connected together in the output
capacitor pins. In this way, we obtain some advantages:
a)
Each phase can manage up to 25 - 30 A (according to the layout and cooling down
characteristics): so, it is possible to handle high currents, with improved efficiency.
Moreover, the device reliability increases.
b)
The total load current is given by adding all the phase currents: this causes a
strong reduction of the output current ripple.
c)
Input and output filter component size and dimension can be minimized; the
converter working capability at high switching frequencies increases.
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Synchronous buck converter: a brief introduction
Figure 3.
AN4192
Multiphase synchronous buck converter schematic
AM16447V1
The maximum output current establishes the number of the phases that must be interleaved
in the VRM (see point (a) above). The MOSFET selection must be equal in each phase, for
the converter symmetry and right current balance; however, it is possible to use one or more
HS or LS FETs in order to minimize some converter power losses.
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2
High-side MOSFET selection
High-side MOSFET selection
For the right choice of high-side FET, the following MOSFET electrical parameters must be
considered:
1.
Qg (total gate charge): it impacts the HS switching speed (at turn-on and turn-off) and
then the switching losses. Moreover, slightly bigger intrinsic capacitances, slowing
down the HS turn-on, may smooth the phase node ringing (overshoot and high
frequency oscillations on the phase node at HS turn-on).
2.
RDS(on) (ON-state drain-source resistance): when the converter duty cycle is low, the
HS stays on for a short time, so the minimization of RDS(on) doesn't impact greatly on
the efficiency. However, the higher the VRM output voltage (i.e. there are 3.3 V or 5 V
sections in the notebook platforms), the bigger the RDS(on) impact.
3.
RG,HS (external gate resistance) and gate drive network settings: the right RG,HS value
should be a trade-off between high switching speed and efficiency (low RG,HS) and the
phase node ringing improvement (high RG,HS). Some gate drive network
configurations, such as “asymmetric gate drive”, are able to enhance the converter
switching behavior with limited consequences on the efficiency.
Figure 4.
Gate charge waveform
AM16448V1
In Figure 4, the simplified gate charge waveform for N-MOS (neglecting the parasitic effects)
is illustrated, which represents the VGS behavior as a function of time. The switching
transient is the interval [t0,t2], when vDS(t) and iD(t) are simultaneously bigger than zero. At t
= t0, the gate-source capacitance (Cgs) is charged and the drain current starts to increase.
During [t0,t1], the drain current increases linearly until it reaches its final value (IOUT). At t =
t1, the gate-source capacitance (Cgs) is totally charged, the drain-source voltage begins to
fall (we assume that the falling edge is linear) and the gate current flows through the Miller
(or transfer) capacitance. For t > t2, the switching losses are negligible because the
MOSFET is in the ohmic zone, with a constant RDS(on).
The charge amount QG,SW = QGD + QGS2 is needed to turn on the FET: it is also called
“switching charge”. The high-side FET switching losses (for a single-phase synchronous
buck converter) can be expressed as:
Equation 1
Q G, SW
1
P SW = --- ⋅ V IN ⋅ I OUT ⋅ fSW ⋅ -------------------2
I GATE
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High-side MOSFET selection
AN4192
where fSW is the converter switching frequency, and IGATE is the total gate current, provided
by the driver to the HS FET during turn-on and turn-off transients. Looking at (1), two main
parameters impact the HS switching losses, playing a crucial role in converter performance
optimization:
1.
The higher the fSW, the more relevant the switching losses.
2.
The bigger the QG,SW (and the slower the HS switching speed), the higher the PSW.
In the following examples, we can see the impact of the above mentioned parameters on the
converter performance.
2.0.1
QG,SW and fSW impact on the efficiency
Four different 30 V HS FETs are compared in a 2-phase synchronous buck converter (VIN =
12 V, VOUT = 1.5 V, IOUT = 44 A, 1 x HS, 2 x LS, fSW = 440 kHz). External HS and LS gate
resistances are present in the layout (RG,HS = 2.2 Ω, RG,LS = 2.2 Ω), whereas no RC
snubber network is used. The low-side FET is the same for all configurations (called “Low
Side”).
Here below (Figure 5), the converter schematic is shown, while in Table 1 the main electrical
parameters of the HS FETs (RDSon, BVDSS, etc.) are reported.
Figure 5.
2-phase synchronous buck converter schematic
AM16449V1
As shown in the following table, the “High-side 2” has the lowest “switching charge” (-49%
compared to “High-side 3"). In Figure 6, the efficiency curves at fSW = 440 kHz are
compared.
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High-side MOSFET selection
Table 1.
HS FETs electrical parameters comparison
BV [V]
RDS(on) [mΩ]
Qg,SW [nC]
9.2 / 10.5
6.85
7.3 / 8.3
4.65
High-side 3
7.6 / 9.5
9.25
High-side 4
7.0 / 9.0
7
High-side 1
High-side 2
30
Figure 6.
Efficiency comparison @ 440 kHz
AM16450V1
As can be clearly seen, the high-side 2 has the best efficiency in the whole current range,
because of the switching loss minimization (see (1)).
Now, let's consider the converter performance, with the same MOSFET configurations, at
two different switching frequencies: 300 kHz and 440 kHz. Increasing fSW, the converter
efficiency decreases, as some power losses increase with the frequency (switching losses,
HS/LS gate drive and LS reverse recovery losses, etc.…). Furthermore, the importance of a
high switching speed rises when the switching frequency increases. In Figure 6 and
Figure 7, the efficiency curves at 300 kHz and 440 kHz are illustrated.
Figure 7.
Efficiency @ 300 kHz
AM16451V1
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High-side MOSFET selection
AN4192
At fSW = 300 kHz, the different “switching charge” values don't strongly affect the efficiency
curves (1.2% efficiency improvement of “high-side 2” vs. “high-side 4”). But, if we step up
the switching frequency to 440 kHz, the HS FET with the lowest QG,SW (“high-side 2”) has
the best efficiency in the overall current range, due to the switching losses reduction.
Then, high-side FETs with very low QG,SW make the design more efficient and are the best
solution in high frequency VRM applications.
2.0.2
QG,SW impact on the HS switching behavior
QG,SW, particularly QGD, also affects the high-side switching behavior during turn-on and
turn-off. Referring to the gate charge image (Figure 4), during the “Miller plateau” (from t1 to
t2) the MOSFET works in the active region (VDS > VDS,SAT), so the gate-source voltage is
constant while the drain current is the full load current. In this time interval, the MOSFET
drain-source voltage drops from high level to zero (at turn-on) or rises from zero to high level
(at turn-off) (see Figure 8). Since CGS is fully charged, the gate current flows only through
CGD, so there is a strong relationship between VDS falling edge slope and QGD:
Equation 2
dVDS
IG
-------------- = ---------dt
V GD
IG is the total gate charging current. The bigger the Miller capacitance, the lower the VDS
slope, and vice versa.
Figure 8.
MOSFET equivalent circuit during Miller plateau
AM16452V1
In order to show the CGD impact on the HS switching performance, two 30 V FETs (MOS1,
CGD = 76 pF @ 25 V and MOS2, CGD = 150 pF @ 25 V) are compared as high-side FETs in
a two-phase synchronous buck converter (VIN = 12 V, VOUT = 1.5 V, IOUT = 44 A, 1 x HS, 2 x
LS, fSW = 440 kHz). External HS and LS gate resistances are present in the layout (RG,HS =
2.2 Ω, RG,LS = 2.2 Ω), whereas no RC snubber network is used.
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High-side MOSFET selection
Figure 9.
MOS1 (CGD = 76 pF) - HS turn-off waveforms
AM16453V1
Figure 10. MOS1 (CGD = 150 pF) - HS turn-off waveforms
AM16454V1
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High-side MOSFET selection
AN4192
In Figure 9 and 10, the HS turn-off waveforms of the two FETs are shown. Higher CGD
values reduce the HS VDS maximum spike (18.4 V vs. 23.1 V) and
dVDS,HS
--------------------dt
(2.1 V/ns vs. 3.9 V/ns); furthermore, the VGS falling edge slope is slower (the Miller plateau
is more visible and VGS fall time is higher). Obviously, the main design rule is that VDS,HS
must be lower than the HS breakdown voltage (typically, VDS,HS(max) ≤0.8 * BVDS,HS to
increase MOSFET reliability).
The Miller capacitance value should be the correct trade-off between efficiency
improvement at high fSW (low QG,Sw and QGD) and HS maximum voltage stress reduction
(high QGD).
2.1
RDS(on) and conduction losses minimization
Considering a single-phase synchronous buck converter with a single HS device, the HS
conduction losses are shown in the following formula:
Equation 3
P HS,COND = D ⋅ R DS ( on ) T ⋅ I
2
D,HS
where D is the converter duty cycle, RDS(on) is the ON-state drain-source resistance,
evaluated at the operating temperature (T °C), and ID,HS is the HS drain current. As D is low
(0.1% - 0.2%), this term is not the most important in converter performance enhancement.
However, a slight efficiency enhancement can be noted at high output currents, when a
lower RDSon high-side FET is used.
Figure 11. Single-phase synchronous buck converter schematic
AM16455V1
In Figure 11, a single-phase synchronous buck converter schematic (VIN = 12 V, VOUT =
1.25 V, IOUT,MAX = 20 A, fSW = 270 kHz, 1 x HS, 1 x LS) is shown, where two different highside FETs (“high-side 5” and “high-side 6”) are compared with a fixed LS device. External
gate resistances are connected to HS (2.2 Ω) and LS (1.8 Ω) FETs. An RC snubber network
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High-side MOSFET selection
(RSNUB = 1 Ω, CSNUB = 6.8 nF) is used to smooth the phase node ringing. The main
MOSFET electrical parameters are reported in Table 2.
Table 2.
MOSFET electrical parameters
BV [V]
High-side 5
RDS(on) [mΩ]
Qg,SW [nC]
11.0 / 13.0
8
8 / 10.5
7.9
30
High-side 6
Figure 12. Efficiency comparison @ Vout = 1.25 V
AM16456V1
As shown in Figure 12, at medium and high load currents, “high-side 6” assures the best
efficiency results, due to its lower RDS(on) (+0.8% at full load).
In some applications (i.e. notebooks), there are some functional blocks that generate 3.3
V/5 V as output voltages. In these cases, the HS tON becomes longer, because of the duty
cycle enlargement, making the HS conduction losses more important. In this case, the HS
and LS device features tend to be quite similar in order to reach the right trade-off between
conduction and switching losses.
2.2
Gate drive network optimization
Typically, the HS and LS gate drive networks are developed by a single external resistor
(RG,EXT), connected between the driver and the MOSFET gate pin, which acts both as turnon and turn-off resistor. The HS external gate resistor choice should be the correct trade-off
between switching speed increase and efficiency improvement at high fSW (low RG,EXT) and
HS switching behavior optimization and phase node ringing reduction (high RG,EXT).
An optimization of the gate drive circuits can help to improve the phase node switching
behavior without negative consequences on the converter efficiency. When the HS turns on,
due to the energy previously stored in the stray inductances, there is an overvoltage stress
between LS drain-source (Figure 13 and 14). Furthermore, after the first overshoot in the
phase node, there are high frequency oscillations (50-100 MHz) due to the LC circuit formed
by the LS COSS and the stray inductances. The phase node ringing (Figure 15) is mainly
related to the LS intrinsic capacitances, the LS RC snubber network (see Section 3.5: RC
snubber network settings): however, it depends also on the HS turn-on speed.
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Figure 13. HS turn-off
Figure 14. HS turn-on (phase node spike)
AM16457V1
AM16458V1
Figure 15. Typical phase node waveform (without RC snubber network)
AM16459V1
Slowing down the HS turn-on is useful in order to reduce the phase node ringing, so a
higher RG,EXT should be used. But, the higher the RG,EXT, the bigger the switching losses
(particularly at turn-off) become: a low RG,EXT is helpful because it reduces the HS
switching losses at turn-off. The “asymmetric gate drive circuit” tries to make a trade-off
between these two different requirements (Figure 16). RG1 is the turn-on gate resistor, D is
a diode and RG2 is the turn-off gate resistor:
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●
When the HS turns on, D is reverse biased so the gate voltage is applied to the gate
through RG1. So, its value may be selected high enough, in order to lower the HS
switching speed and therefore the phase node spike.
●
At HS turn-off, D is forward biased offering a low-resistance path to the HS discharging
current. RG2 is the turn-off resistor because RG1 is shorted. If RG2 is 0 Ω, the HS
switching speed at turn-off is the highest and the impact on the switching losses is
minimized.
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High-side MOSFET selection
Figure 16. Asymmetric HS gate drive circuit
AM16460V1
Figure 17. 3-phase synchronous buck converter
AM16461V1
Let's now consider a 3-phase synchronous buck converter (Figure 17) (VIN = 12 V, VOUT =
1.25 V, fSW = 270 kHz, 2 x HS, 2 x LS, IOUT = 75 A). External gate resistances are
connected to HS (2.2 Ω) and LS (2.2 Ω) FETs. An RC snubber network (RSNUB = 2.2 Ω,
CSNUB = 4.7 nF) is used to smooth the phase node. Two different HS driving configurations
(standard with RG,EXT = 2.2 Ω, “asymmetric gate drive” with RG1 = 3.9 Ω, RG1 = 1.8 Ω) are
compared in terms of phase node ringing and efficiency comparison. In Figure 18 and 19
the phase node waveforms of the two configurations are shown.
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Figure 18. Phase node waveform - standard configuration
AM16462V1
Figure 19. Phase node waveform - HS asymmetric gate drive configuration
AM16463V1
Looking at the previous waveforms, due to the reduced HS turn-on speed, there is a clear
reduction of the phase node spike (21 V vs. 24.4 V), when the HS asymmetric gate drive is
used. Moreover, the LS gate-source bouncing, induced at HS turn-on, is smoothed.
Comparing the efficiency curves (Figure 20), the asymmetric gate drive has slightly better
efficiency (+0.7% at full load). This can be explained considering that:
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1.
The HS turn-off resistor is smaller (1.8 Ω vs. 2.2 Ω) and consequently the switching
losses at turn-off are lower.
2.
Even if the HS turn-on resistor is bigger, the switching losses at turn-on are negligible.
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High-side MOSFET selection
Figure 20. Efficiency comparison @ Vout = 1.26 V
AM16464V1
The “asymmetric gate driving” approach can be used to reduce voltage stresses on the
phase node without detrimental effects on the converter efficiency. The drawbacks are the
number of devices (one resistor + one Schottky diode) and the cost increase.
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Low-side FET selection
3
AN4192
Low-side FET selection
The low-side FET performance can be enhanced by properly choosing the following
MOSFET electrical parameters:
1.
RDS(on) (ON-state drain-source resistance): as the LS FET is in the ON-state for a
longer time, the conduction losses, strictly related to the RDS(on) value, are the most
important power dissipation contribution. Based on the converter layout and the output
current requirements, one or more paralleled LS FETs can be used.
2.
CGD (Miller capacitance): it affects the LS switching behavior, in terms of phase node
spike and dVphase/dt. On the other hand, too high CGD values increase the LS
“switching charge” (QG,SW): in high frequency applications or when more LS FETs are
paralleled to reduce the RDSon, this may increase the switching and gate drive losses,
even if the LS switches at nearly ZVS (due to its body diode conduction).
3.
QRR (LS body-drain diode reverse recovery charge): during the deadtime (when the HS
and LS are in the HOLD state), the load current flows through the body-drain diode
(forward biased). When the HS turns on, the excess charge stored in the LS body diode
(QRR) must be removed before the phase node turns high.
4.
RG (external and intrinsic gate resistance): when no additional smoothing effects are
present (i.e. snubber network), the higher the RG, the lower the Vphase,max. The
drawback is the LS G-S spurious ringing that may induce the LS spurious turn-on
again.
Furthermore, the LS FET performance is also influenced by the RC snubber network
setting, connected between LS drain and source, which helps to smooth the phase node
noise. Another important aspect is the spurious LS gate-source bouncing, induced by the
fast rising edge of the phase node through the Miller capacitance; it is analyzed with a
particular focus on the different solutions to reduce these parasitic oscillations. Finally, the
converter output voltage (and the converter duty cycle) affects the phase node noise
behavior: the higher the VOUT, the lower the phase node overshoot, during the HS turn-on.
3.1
RDS(on) and conduction losses minimization
The LS conduction losses are given by:
Equation 4
2
P COND,LS = R DS ( on ) T ⋅ I D ⋅ ( 1 – D )
As the converter duty cycle (for typical VRM applications) is very low (0.1 - 0.2%), the LS
FET is in the ON-state for a longer time: the conduction losses are the most important power
dissipation term. The RDS(on) minimization is crucial for the optimization of the LS
performance. Bigger die sizes are preferred, even though the device cost is a constraint. If
the output current to be delivered to the load is high, more LS can be used in parallel.
To better understand the impact of the RDS(on) on the converter efficiency, two LS FETs are
compared in a 3-phase buck converter (VIN = 12 V, VOUT = 1.25 V, fSW = 300 kHz, 2 x HS, 2
x LS, IOUT = 75 A; see Figure 21). External gate resistances are connected to HS (2.2 Ω)
and LS (2.2 Ω) FETs. An RC snubber network (RSNUB = 2.2 Ω, CSNUB = 4.7 nF) is used to
smooth the phase node.
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In the following table the main electrical parameters of the two tested LS FETs are reported.
The high-side FET used is called “HS”.
Table 3.
Main electrical parameters
BV [V]
RDS(on) [mΩ]
Qg,SW [nC]
HS
25
13
8.5
LS1
30
6
15
LS2
25
5.2
18
As shown in the previous table, the “LS1” has higher RDS(on), but slightly lower total gate
charge. In Figure 21 the relevant efficiency curves are depicted; at low output currents, the
LS1, due to its slightly lower Qg and then switching/gate drive losses, has higher efficiency.
But, at medium and heavy load conditions, the RDS(on) improvement makes “LS2” the best
in terms of efficiency.
Figure 21. Efficiency vs. Iout @ Vout = 1.25 V
AM16465V1
3.2
CGD (Miller capacitance)
The Miller capacitance (Cgd) plays a crucial role in the LS switching behavior improvement.
As already known, before the HS turns on, the load current flows through the LS body-drain
diode (deadtime) (Figure 22, green trace, I2).
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Figure 22. Buck converter schematic
AM16466V1
When the HS turns on (the load current is I1), the phase node goes from low to high level in
a few nanoseconds: depending on several factors, an overvoltage (plus high frequency
oscillations) event may appear on the LS drain-source voltage (phase node ringing): if the
maximum spike is higher than the breakdown voltage (BVDSS), the MOSFET safety and
reliability can worsen. This issue is related to three main factors:
1.
When the HS turns on, VDS,LS rises from -0.7 V (body-drain diode conduction) to
supply voltage. If the HS switches sharply (very low QG,SW), high dVDS,LS/dt and phase
node spike is measured on the LS FET.
2.
During the deadtime, when the load current flows through the LS body-drain diode,
parasitic voltage drops (VL1 and VL2) appear across the PCB stray inductances
(connected to LS drain and source, Figure 23). So, the parasitic voltage drops, and VL1
and VL2 increase the VDS,LS maximum value, creating potential issues for MOSFET
safety and reliability, if the maximum spike is higher than the BVDSS guaranteed in the
datasheet.
3.
During the deadtime, the LS body-drain diode is forward biased (VDS,LS = -0.7 V). This
excess stored charge must be removed before the LS can sustain the supply voltage; in
order to reverse bias the body diode, a “reverse recovery current” flows (from drain to
source) immediately after the HS turn-on. The larger this current is, the higher the
phase node spike is. In the next section, there is a more thorough analysis of the
benefits given by a “soft” LS body-drain diode.
Figure 23. Impact of the stray inductances on the phase node ringing
AM16467V1
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Low-side FET selection
In Figure 24 and 25, two phase node waveforms of high-CRSS (CRSS = 315 pF) and lowCRSS (CRSS = 190 pF) devices are compared. These FETs are mounted on a 3-phase VRM
(fSW = 500 kHz, VOUT = 1.4 V, RG,HS = RG,LS = 2.2 Ω, CSNUB = 4.7 nF, RSNUB = 2.2 Ω) and
the load current is 80 A.
Figure 24. Low-CRSS LS FET phase node waveform @ 80 A
AM16468V1
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Figure 25. High-CRSS LS FET phase node waveform @ 80 A
AM16469V1
As shown in previous images, the “high-CRSS” device has lower phase node spike (18.8 V
vs. 30.7 V of the low-CRSS FET).
The right value of the Miller capacitance allows a good improvement on the LS switching
behavior, reducing the maximum phase node spike, without detrimental effects on other
device features (shoot-through issue, LS gate-source bouncing). Increasing the CRSS value,
we obtain some important effects on LS performance:
3.3
a)
Low-side FET intrinsic slow-down.
b)
“Intrinsic and VDS linked” R-C snubber (Rgate - CRSS) effect (Rgate is the total gate
resistance): at HS turn-on, the Miller capacitance is in series with the total gate
resistance, creating an “intrinsic” snubber. The capacitive effect is linked to the
applied VDS across the LS FET.
c)
Higher CRSS value causes a “sub-threshold” conduction, which helps to divert the
load current from the body diode (during the deadtime) to the channel, reducing
the reverse recovery process stresses.
LS body-drain diode Qrr (reverse recovery charge)
During the deadtime, when both HS and LS FETs are in the OFF-state, the load current
cannot immediately drop to zero so it flows through the LS body-drain diode, that is forward
biased (VDS,LS = -0.7 V). In Figure 26, the red arrow represents the load current flowing
through the body diode. The charge stored in the body diode depends mainly on the load
current amplitude and the deadtime length. This charge must be removed before the LS can
sustain voltage (OFF-state). In Figure 27, from T0 to T1, the body diode current becomes
negative, depleting the excess charge stored. In this period, the LS body diode acts as the
energy source, delivering energy to other components. When the stored charge is totally
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Low-side FET selection
removed, the voltage drop across the LS diode becomes equal to the steady-state reverse
biased value and, after its turn-on, the HS FET provides all the load current.
Figure 26. Single-phase synchronous buck converter
AM16470V1
Figure 27. Reverse recovery charge waveforms
AM16471V1
The “reverse recovery” charge process causes power dissipation, which depends on the
charge amount to be recovered (Qrr), the switching frequency and the converter input
voltage:
Equation 5
P rr = Q rr ⋅ Vin ⋅ f SW
In standard technical literature, the “reverse recovery losses” are added to the HS losses: in
fact, as previously explained, during the reverse recovery process, the LS body diode
transfers energy to the HS FET, which, in other words, must provide not only the load current
but also the diode reverse recovery current.
The body-drain diode optimization plays a crucial role not only for the efficiency
improvement but also for the LS switching performance. In fact, reducing Qrr (the excess
charge stored during deadtime), the LS body diode transfers less energy (smaller reverse
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recovery current and losses) to the HS FET and consequently the phase node overshoot is
lower.
Typically, to reach this target, a monolithic Schottky diode is integrated inside the same
MOSFET structure. This solution eliminates the parasitic effects induced by the stray
inductances, which impact negatively on the MOSFET + external Schottky (discrete)
configuration. The only drawback is the MOSFET RDS(on) increase due to the Schottky
integration and reduction of the active area. The MOSFET with the monolithic Schottky
integrated has lower Qrr and VFEC (forward-biased voltage drop), reducing, at the same
time, the LS diode conduction losses.
Table 4.
Device electrical parameters
BV [V]
LS
Qrr [nC]
VFEC [V]
Id = 12.5 A
Id = 12.5 A
56
0.85
516
0.68
30
LD + Sch
Figure 28. Body-drain diode reverse recovery current
AM16919V1
In a single-phase buck converter demonstration board (VIN = 12 V, VOUT = 1.25 V, fSW = 270
kHz, 1 x HS, 1 x LS, IOUT = 20 A, Figure 29), LS and LS+Sch. are compared (Table 4 and
Figure 28): the two devices have the same die size but one LS has a monolithic Schottky
diode integrated. External gate resistances are connected to HS (2.2 Ω) and LS (1.8 Ω)
FETs. An RC snubber network (CSNUB = 6.8 nF, RSNUB = 1.8 Ω) is used to improve the
switching behavior.
As shown in the converter waveforms at full load (20 A) (Figure 30 and 31), the monolithic
Schottky diode integrated helps to smooth the phase node ringing: in fact, for the LS+SCH.
device, there is about 10% of Vphase decrease (24.2 V vs. 21.7 V).
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Figure 29. Single-phase synchronous buck converter schematic
AM16472V1
Figure 30. Standard LS waveforms @ 20 A
AM16473V1
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Figure 31. LS with monolithic Schottky diode waveforms @ 20 A
AM16474V1
The efficiency improvement caused by an optimized LS body diode can be appreciated only
if the converter switching frequency increases: in fact, the higher the fSW, the larger the
reverse recovery losses (see (5)). We compare the above mentioned LS FETs (LS and
LS+Sch.) in a 2-phase synchronous buck converter (VIN = 12 V, VOUT = 1.5 V, fSW = 610
kHz, 2 x HS, 2 x LS, IOUT = 60 A - Figure 32). External gate resistances are connected to
HS (2.2 Ω) and LS (2.2 Ω) FETs. No snubber network is mounted on the board.
As can be seen in Figure 33, at high output currents, due to lower diode conduction and
reverse recovery losses, the solution with LS+Sch. has higher efficiency (+1.5% at full load).
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Low-side FET selection
Figure 32. 2-phase synchronous buck converter schematic
AM16475V1
Figure 33. Monolithic Schottky impact on the efficiency @ 610 kHz
AM16476V1
Therefore, the choice of an LS FET with monolithic Schottky integrated in the same die is
best in high frequency VRM applications, both in terms of efficiency enhancement and
device switching behavior improvement.
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Low-side FET selection
3.4
AN4192
RG and LS gate-source bouncing
Now, the impact of the intrinsic and external gate resistances on the overall converter
behavior is analyzed.
The intrinsic gate resistance of a MOSFET mainly affects its switching speed and
consequently the switching losses. So, for a HS FET, it is mandatory to have a total gate
resistance (RG,HS(EXT) + RG,HS(INT)) not too big in order to diminish the HS switching losses
(major losses contribution), particularly at high fSW.
On the other hand, the LS FET turns on and off with nearly zero voltage drop across it
(because, before its turn-on and after turn-off, the current flows through the LS body-drain
diode, so VDS,LS = -0.7 V); therefore, the switching losses are not comparable to the
conduction ones. The right RG value should be chosen considering the trade-off between
phase node spike smoothing (high RG) and CdV/dt spurious turn-on immunity (low RG). In
fact, when the HS turns on, a high dVphase/dt appears across the LS device (its value
depends also on the HS switching speed).
Figure 34. LS FET during HS turn-on
AM16477V1
A capacitive current flows through the Miller capacitance (Cgd):
Equation 6
dV phase
I gd = C gd ⋅ ---------------------dt
During the OFF-state, the LS gate is pulled down to GND through the driver sink resistance
(RDRV). So, if RDRV + RG,LS(EXT) + RG,LS(INT) << Zgs, most of the capacitive current flows in
the resistive path towards GND. As a consequence, a “spurious” voltage drop appears
between LS gate and source:
Equation 7
dV phase
V gs,LS = ( R DRV + R G,LS(EXT) + R G,LS(INT) ) ⋅ Cgd ⋅ ---------------------dt
If Vgs,LS is higher than the LS threshold voltage, the FET may turn on, creating a lowimpedance path, between phase node and GND. There is a potential risk of a “crossconduction” (or shoot-through) event, because the HS is turned on and a low impedance
path between VDD and GND exists.
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Due to the above mentioned issue, in most VRM applications, one common design
guideline is to reduce the total gate resistance.
Figure 35. Low ext. RG (2 Ω) LS FET waveforms during HS turn-on
AM16478V1
Increasing RG,LS(EXT), there are three main effects on the LS switching behavior:
●
A higher induced voltage appears between gate and source (7) (see Figure 36).
●
Longer VGS, LS fall time (130 ns vs. 83 ns), due to the input time constant enlargement
(the LS VGS bounces before reaching zero level).
●
Phase node overshoot reduction, because of the intrinsic LS slow-down.
Figure 36. High ext. RG (4.7 Ω) LS FET waveforms during HS turn-on
AM16479V1
Generally, the higher the RG,LS(EXT), the lower the efficiency, due to bigger gate drive losses.
In particular, the efficiency loss is much higher when more LS FETs are paralleled or bigger
die size devices are used (more capacitances to be switched on/off). For the above
mentioned issues, typically, the more common RG,LS(EXT) values are 0 - 2.2 Ω.
In the same way, by increasing the LS intrinsic gate resistance (RG,LS(EXT)), the spurious
gate-source voltage tends to grow (see Figure 37 and 38).
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Figure 37. Low RG,LS(INT) (1.5 Ω) LS FET waveforms @ full load
AM16480V1
In these images the LS gate-source waveforms for two 30 V LS devices are depicted: the
first has RG,LS(INT) = 1.5 Ω, the second has 3 Ω. The spurious LS G-S voltage drop rises (5.5
V vs. 2.7 V), if only for a very short time (2-3 ns).
Figure 38. High RG,LS(INT) (3 Ω) LS FET waveforms @ full load
AM16481V1
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Figure 39. 2-phase synchronous buck converter
AM16482V1
In a 2-phase synchronous buck converter (Figure 39) (VIN = 12 V, VOUT = 1.5 V, IOUT = 44 A,
1 x HS, 2 x LS, fSW = 440 kHz), two LS FETs with different RG,INT values (RG1 = 1.3 Ω, RG2
= 2.8 Ω) are compared. External HS and LS gate resistances are present in the layout
(RG,HS = 2.2 Ω, RG,LS = 2.2 Ω).
Higher intrinsic gate resistance is helpful to smooth the phase node overshoot, when no RC
snubber network is connected in parallel to the LS FET. In Figure 40 and 41 the phase node
waveforms of the two LS FETs tested at full load conditions (IOUT = 44 A) are compared.
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Figure 40. Low RG,LS(INT) (1.3 Ω) waveforms @ full load
AM16483V1
Figure 41. High RG,LS(INT) waveforms @ full load
AM16484V1
As shown in the previous images, there is a 10% reduction on the phase node spike, due to
the intrinsic LS slow-down.
It is important to underline that the same benefit in terms of phase node spike reduction is
not evident with an RC snubber network mounted on the board, which provides the
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strongest smoothing effect. Another important phenomenon that affects the LS switching
performance is the LS gate-source spurious oscillations. When the HS turns on, spurious
ringing appears between LS gate and source, caused by high dVphase/dt and the parasitic
effects due to the PCB stray inductances (at all the MOSFET pins).
Figure 42. Simplified LS FET circuit
AM16485V1
To reduce the phase node spike and therefore LS gate-source parasitic fluctuations, the
“filter effect” provided by the MOSFET intrinsic output capacitance (COSS = CGD + CDS) is
important. In fact, COSS works as an “intrinsic” capacitive snubber between drain and
source.
Figure 43. Single-phase synchronous buck converter schematic
AM16486V1
In a single-phase buck converter demonstration board (VIN = 12 V, VOUT = 1.25 V, fSW = 270
kHz, 1 x HS, 1 x LS, IOUT = 20 A, Figure 43), the benefits given by two paralleled 30 V FETs
(doubled Cgs) in terms of LS G-S induced ringing are evaluated. External gate resistances
are connected to HS (2.2 Ω) and LS (2.2 Ω) FETs. An RC snubber network (CSNUB = 6.8 nF,
RSNUB = 1.8 Ω) is used to improve the switching behavior. As shown in Figure 44 (purple
trace: 2 x LS - yellow trace: 1 x LS), the two paralleled LS FETs have smoothed high
frequency LS oscillations, both in the highest and in the lowest spike.
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Figure 44. 1 x LS vs. 2 x LS (LS G-S ringing improvement)
AM16487V1
The conspicuous reduction of the LS gate-source bouncing (especially for the high
frequency oscillation after the first spike) provided by the increased COSS is obtained also
using a bigger die size LS device, as shown in Figure 45 (light green trace: LS1, dark green
trace: LS2).
Figure 45. LS gate-source bouncing reduction for bigger die size LS FETs
AM16488V1
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3.5
Low-side FET selection
RC snubber network settings
In high frequency converters, designers must choose the right electric topology and device
in order to minimize the switching noise. In particular, when the HS turns on, the LS body
diode that was delivering the whole load current must be in the HOLD state. Due to the body
diode reverse recovery process and stray inductances, an overshoot may appear on the
phase node voltage, affecting the MOSFET reliability. Furthermore, the positive and
negative spikes on the phase node waveforms are also dangerous for other electronic
components surrounding the LS FET.
The simplest way to reduce these switching oscillations is by connecting an RC snubber
network across the LS FET. Theoretically, a simple capacitive snubber would be useful to
smooth the switching noise; but, a series resistance is added to decrease the current
amplitude during the capacitor discharging and to dissipate the energy at turn-off (when an
overvoltage event occurs).
Figure 46. LS FET with RC snubber network
AM16489V1
The right RSNUB and CSNUB selection depends on several factors: overshoot reduction,
damping effect and energy losses in the snubber circuit:
1
E = --- ⋅ V SNUB ⋅
2
2
DD
Typically, the snubber resistor is equal to the characteristic impedance of the freely
oscillating circuit L-C:
Equation 8
R SNUB =
L stray
--------------C oss
where Lstray includes the PCB and package inductances. Its value can be extrapolated by
the phase node waveform, measuring the ringing oscillation fRING (Figure 47) and using (9):
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Figure 47. Phase node waveform and fRING evaluation
AM16490V1
Equation 9
1
L stray = -------------------------------------------------------2
2
f RING ⋅ 4π ⋅ C OSS
The snubber capacitor value is a trade-off between the over-damping effect (reduction of the
number of oscillations) (high CSNUB) and limited energy losses (low CSNUB). Typically, the
snubber network constant time (τ SNUB) is chosen as:
Equation 10
3
τ SNUB = R SNUB ⋅ C SNUB = -------------fRING
The correct fine tuning of the snubber components, together with a suitable selection of the
external gate resistors, allows a sensible reduction of the phase node overshoot. For
example, let's consider a single-phase synchronous buck converter (VIN = 12 V, VOUT = 1.25
V, fSW = 270 kHz, 1 x HS, 1 x LS, IOUT = 20 A, with the following original configuration:
CSNUB = 6.8 nF, RSNUB = 1.8 Ω, RG,HS(EXT) = 0 Ω, RG,LS(EXT) = 0 Ω) . Moreover, a very low
QG,SW HS FET is used to maximize the switching speed and emphasize the phase node
ringing issue. In Figure 48, the waveforms for the original configuration are shown: the
maximum phase node spike is 33.6 V.
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Figure 48. Original configuration waveforms @ 20 A
AM16491V1
As a first step, the LS external gate resistance is increased to 1.8 Ω (“Configuration 1"); in
Figure 49 the relevant waveforms are depicted. The phase node overshoot is 31 V.
Figure 49. RG,HS(EXT) = 0 Ω - RG,HS(EXT) = 1.8 Ω/original snubber waveforms @ 20 A
AM16492V1
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Low-side FET selection
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Subsequently, the external HS gate resistor becomes 2.2 Ω, while the other components
remain unchanged (“Configuration 2”). A further reduction of the phase node spike is
achieved (30.1 V). In Figure 50, the waveforms at full load conditions are reported.
Finally, the snubber resistor value is decreased from 1.8 Ω to 1 Ω, to emphasize the CSNUB
effect (“Configuration 3”). The gate resistors are unmodified (Figure 51).
Figure 50. RG,HS(EXT) = 2.2 Ω - RG,HS(EXT) = 1.8 Ω/ original snubber waveforms @ 20 A
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Low-side FET selection
Figure 51. RG,HS(EXT) = 2.2 Ω - RG,HS(EXT) = 1.8 Ω/ RSNUB = 1 Ω waveforms @ 20 A
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Therefore, the last configuration is the best in terms of phase node ringing smoothing (12%,
from 33.6 V to 29. 6 V, see Figure 52).
The increased LS gate resistor value (1.8 Ω) doesn't negatively effect the LS gate-source
bouncing and the potential shoot-through risks: this spurious voltage is higher than VTH,min
(1 V) for only 1.7 ns; it is not enough to charge the MOSFET input capacitance and turn-on
of the device itself.
Figure 52. Phase node improvement
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3.6
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Phase node spike - VCORE relationship
Let's consider the impact of a different output voltage on the phase node ringing. In
Figure 53 the schematic of a 3-phase synchronous buck converter (VIN = 12 V, VOUT = 1.25
V, fSW = 270 kHz, 2 x HS, 2 x LS, IOUT = 75 A) is depicted. External gate resistances are
connected to HS (2.2 Ω) and LS (2.2 Ω) FETs. An RC snubber network (RSNUB = 2.2 Ω,
CSNUB = 4.7 nF) is used to smooth the phase node.
Figure 53. 3-phase synchronous buck converter
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Adjusting a 6-pin DIP switch configuration, it is possible to change the converter output
voltage, from 2.5 V to 3.3 V. In Figure 54 and 55, the relevant waveforms are reported.
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Low-side FET selection
Figure 54. Phase node waveform @ 2.5 V
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Figure 55. Phase node waveform @ 3.3 V
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As shown in the previous images, by increasing the output voltage the phase node spike
decreases (Figure 56). This is due to the higher HS ON-state interval and to its lower
switching speed.
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Conclusion
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Figure 56. Phase node spike - VOUT chart
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4
Conclusion
The main electrical parameters for correct MOSFET selection in VRM applications are QG
and intrinsic capacitances for high-side FETs, while RDS(on), QRR and CGD are crucial for LS
FETs.
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5
Bibliography
Bibliography
1.
2.
3.
Section 1: Synchronous buck converter: a brief introduction
a)
C.S.Mitter, device considerations for high current, low voltage synchronous buck
converter.
b)
Fairchild Semiconductor AN6005, Synchronous buck converter power losses
calculation.
c)
STMicroelectronics AN2170, MOSFET device effects on phase node ringing in
VRM power converters.
Section 2: High-side MOSFET selection
a)
K.S.Oh (Fairchild Semiconductor AN9010), MOSFET Basics.
b)
C.Cavallaro, S.Musumeci, R.Pagano, A.Raciti, K.Shenai, Analysis, modeling and
simulation of LV MOSFETs in synchronous rectifier buck-converter applications.
c)
Fairchild Semiconductor AN6005, Synchronous buck converter power losses
calculation.
d)
T.Wu, Cdv/dt induced turn-on in synchronous buck regulators.
Section 3: Low-side FET selection
a)
STMicroelectronics AN2170, MOSFET device effects on phase node ringing in
VRM power converters.
b)
C.Cavallaro, S.Musumeci, R.Pagano, A.Raciti, K.Shenai, Analysis, modeling and
simulation of LV MOSFETs in synchronous rectifier buck-converter applications.
c)
STMicroelectronics AN2239, Maximizing synchronous buck converter efficiency
with standard STripFETsTM with integrated Schottky diodes.
d)
S.Mappus, dV/dt immunity improved in synchronous buck converter.
e)
F.Wu,H.Gao,Li Sun,K.Zhao, Suppression of gate oscillation of Power MOSFET
with bridge topology.
f)
G.Belverde, C.Guastella, M.Melito, S.Musumeci, A.Raciti, S.Pagano, Advanced
characterization of LV Power MOSFETs in synchronous-rectifier buck-converter
applications.
g)
Q.Zhao,G.Stojcic, Characterization of CdV/dt induced power losses in
synchronous buck DC-DC converters.
h)
O.Djekic,M.Brkovic,A.Roy, High frequency synchronous buck converter for LV
applications.
i)
S.Havanur (A&O Semiconductor AN100-1), Snubber design for noise reduction in
switching circuits.
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Revision history
6
AN4192
Revision history
Table 5.
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Document revision history
Date
Revision
13-Nov-2012
1
Changes
Initial release.
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