TI1 ISO7810DWR High-performance, 8000-vpk reinforced single-channel digital isolator Datasheet

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ISO7810, ISO7810F
SLLSEP1B – JULY 2015 – REVISED JUNE 2016
ISO7810x High-Performance, 8000-VPK Reinforced Single-Channel Digital Isolator
1 Features
3 Description
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The ISO7810x device is a high-performance, singlechannel digital isolator with 8000 VPK isolation
voltage. This device has reinforced isolation
certifications according to VDE, CSA, CQC, and TUV.
The isolator provides high electromagnetic immunity
and low emissions at low power consumption, while
isolating CMOS or LVCMOS digital I/Os.
1
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•
•
•
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Signaling Rate: Up to 100 Mbps
Wide Supply Range: 2.25 V to 5.5 V
2.25 V to 5.5 V Level Translation
Wide Temperature Range: –55°C to 125°C
Low Power Consumption, Typical 1.8 mA at
1 Mbps
Low Propagation Delay: 10.7 ns Typical
(5 V Supplies)
Industry leading CMTI (Min): ±100 kV/μs
Robust Electromagnetic Compatibility (EMC)
System-Level ESD, EFT, and Surge Immunity
Low Emissions
Isolation Barrier Life: > 40 Years
SOIC-16 Wide Body (DW) and Extra-Wide Body
(DWW) Package Options
Safety-Related Certifications:
– 8000 VPK Reinforced Isolation per DIN V VDE
V 0884-10 (VDE V 0884-10):2006-12
– 5.7 kVRMS Isolation for 1 minute per UL 1577
– CSA Component Acceptance Notice 5A, IEC
60950-1 and IEC 60601-1 End Equipment
Standards
– CQC Certification per GB4943.1-2011
– TUV Certification per EN 61010-1 and EN
60950-1
– All DW Package Certifications Complete;
DWW Package Certifications Complete per
UL, VDE, and TUV and Planned for CSA and
CQC
The isolation channel has a logic input and output
buffer separated by silicon dioxide (SiO2) insulation
barrier. If the input power or signal is lost, the default
output is high for the ISO7810 and low for the
ISO7810F device. See the Device Functional Modes
section for further details.
Used in conjunction with isolated power supplies, this
device helps prevent noise currents on a data bus or
other circuits from entering the local ground and
interfering with or damaging sensitive circuitry.
Through innovative chip design and layout
techniques, electromagnetic compatibility of the
ISO7810x device has been significantly enhanced to
ease system-level ESD, EFT, surge, and emissions
compliance. The ISO7810x device is available in 16pin SOIC wide-body (DW) and extra-wide body
(DWW) packages.The DWW package option comes
with enable pin which can be used to put the output
in high impedance state for multi-master driving
applications and to reduce power consumption.
Device Information(1)
PART NUMBER
ISO7810
ISO7810F
Industrial Automation
Motor Control
Power Supplies
Solar Inverters
Medical Equipment
Hybrid Electric Vehicles
BODY SIZE (NOM)
10.30 mm × 7.50 mm
DWW (16)
10.30 mm × 14.0 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
2 Applications
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•
•
•
•
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PACKAGE
DW (16)
Simplified Schematic
VCC1
Isolation
Capacitor
VCC2
IN
OUT
EN2 (DWW package only)
GND1
GND2
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ISO7810, ISO7810F
SLLSEP1B – JULY 2015 – REVISED JUNE 2016
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Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
6.13
6.14
6.15
6.16
6.17
6.18
1
1
1
2
4
5
Absolute Maximum Ratings ..................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 6
Power Rating............................................................. 6
Insulation Characteristics ......................................... 7
Regulatory Information.............................................. 8
Safety Limiting Values .............................................. 8
Electrical Characteristics—5-V Supply ..................... 9
Supply Current Characteristics—5-V Supply .......... 9
Electrical Characteristics—3.3-V Supply .............. 10
Supply Current Characteristics—3.3-V Supply ..... 10
Electrical Characteristics—2.5-V Supply .............. 11
Supply Current Characteristics—2.5-V Supply ..... 11
Switching Characteristics—5-V Supply................. 12
Switching Characteristics—3.3-V Supply.............. 12
Switching Characteristics—2.5-V Supply.............. 13
Insulation Characteristics Curves ......................... 14
6.19 Typical Characteristics .......................................... 15
7
8
Parameter Measurement Information ................ 16
Detailed Description ............................................ 18
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
18
18
19
20
Applications and Implementation ...................... 21
9.1 Application Information............................................ 21
9.2 Typical Application .................................................. 21
10 Power Supply Recommendations ..................... 23
11 Layout................................................................... 24
11.1 Layout Guidelines ................................................. 24
11.2 Layout Example .................................................... 24
12 Device and Documentation Support ................. 25
12.1
12.2
12.3
12.4
12.5
12.6
12.7
Documentation Support ........................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
25
25
25
25
25
25
25
13 Mechanical, Packaging, and Orderable
Information ........................................................... 26
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (September 2015) to Revision B
Page
•
Changed Features From: Low Power Consumption, Typical 1.8 mA per Channel at 1 Mbps To: Low Power
Consumption, Typical 1.8 mA at 1 Mbps................................................................................................................................ 1
•
Changed Features From: Low Propagation Delay: 11 ns Typical To: Low Propagation Delay: 10.7 ns Typical ................. 1
•
Changed Features From: Safety and Regulatory Approvals To: Safety-Related Certifications ........................................... 1
•
Added the extra-wide body package (16 pin SOIC [DWW]) option........................................................................................ 1
•
Changed the INA, OUTA, VCCI, and VCCO pin names to IN, OUT, VCC1, and VCC2 (respectively) and updated the pin
out drawings, Pin Functions table, and other figures to match ............................................................................................. 4
•
Moved Junction temperature From Recommended Operating Conditions To Absolute Maximum Ratings ......................... 5
•
Changed the Thermal Information values for the DW package and add the values for the DWW package ........................ 6
•
Changed the values in the Power Rating table ..................................................................................................................... 6
•
Moved Insulation Characteristics to the Specifications section ............................................................................................. 7
•
Changed CIO Specification From: 2 pF To: ~0.75 pF ............................................................................................................ 7
•
Moved Regulatory Information to the Specifications section ................................................................................................. 8
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Moved Safety Limiting Values to the Specifications section ................................................................................................. 8
•
Changed the minimum CMTI value from 50 to 100 and deleted the maximum value in the 5-V and 3.3-V electrical
characteristics tables. Also added VCM to the test conditions ................................................................................................ 9
•
Changed the maximum value for the supply current, AC parameter at 100 Mbps in all of the electrical characteristics
tables ..................................................................................................................................................................................... 9
•
Changed the minimum CMTI value from 70 to 100 and deleted the maximum value in the 2.5-V electrical
characteristics table. Also added VCM to the test conditions ................................................................................................ 11
•
Added the disable and enable propagation delay parameters to all of the switching characteristics tables ...................... 12
2
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Revision History (continued)
•
Changed tfs To: tDO in Switching Characteristics—5-V Supply............................................................................................. 12
•
Changed tfs To: tDO in Switching Characteristics—3.3-V Supply.......................................................................................... 12
•
Changed tfs To: tDO in Switching Characteristics—2.5-V Supply.......................................................................................... 13
•
Added the Insulation Characteristics Curves section ........................................................................................................... 14
•
Added the lifetime projection curves for the DW and DWW packages in the Insulation Characteristics Curves section.... 14
•
Added Figure 15 in the Parameter Measurement Information section ................................................................................ 17
•
Changed text "dual-channel digital isolator" To: "single-channel digital isolator" in Application Information ...................... 21
•
Changed text "DC-DC converters" To: "transformer driver" in the Typical Application section ........................................... 21
•
Changed Figure 20 .............................................................................................................................................................. 21
Changes from Original (July 2015) to Revision A
•
Page
Changed From: 1-page Product Preview To: Production datasheet ..................................................................................... 1
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5 Pin Configuration and Functions
DW Package
16-Pin SOIC
Top View
DWW Package
16-Pin SOIC
Top View
GND1 1
16 GND2
VCC1
1
16 VCC2
GND1 2
15 GND2
15
VCC1
3
14 VCC2
NC
3
IN
4
13 OUT
NC
4
NC
5
12
NC
IN
5
NC
6
11
NC
NC
6
11
NC
GND1 7
10
NC
NC
7
10
NC
NC
8
NC
9 GND2
ISOLATION
2
ISOLATION
NC
GND1 8
14
NC
13
EN2
12 OUT
9 GND2
Pin Functions
PIN
NAME
EN2
NO.
I/O
DW
DWW
—
13
I
DESCRIPTION
Output enable 2. Output pin on side 2 is enabled when EN2 is high or open and in
high-impedance state when EN2 is low.
GND1
1, 7
2, 8
—
Ground connection for VCC1
GND2
9, 16
9, 15
—
Ground connection for VCC2
IN
4
5
I
Input channel
NC
2, 5, 6, 8, 10,
11, 12, 15
3, 4, 6, 7, 10,
11, 14
—
Not connected
OUT
13
12
O
Output channel
VCC1
3
1
—
Power supply, side 1
VCC2
14
16
—
Power supply, side 2
4
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6 Specifications
6.1 Absolute Maximum Ratings
See
(1)
Supply voltage (2)
VCC1, VCC2
Voltage
IN, OUT, EN2
MIN
MAX
–0.5
6
–0.5
VCC + 0.5
UNIT
V
(3)
V
Output current, IO
–15
15
mA
Junction temperature, TJ
–55
150
°C
Storage temperature, Tstg
–65
150
°C
(1)
(2)
(3)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values except differential I/O bus voltages are with respect to the local ground terminal (GND1 or GND2) and are peak
voltage values.
Maximum voltage must not exceed 6 V.
6.2 ESD Ratings
VESD
(1)
(2)
Electrostatic discharge
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins (1)
±6000
V
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins (2)
±1500
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN
VCC1, VCC2
IOH
Supply voltage
NOM
2.25
High-level output current
VCC2 = 5 V
–4
VCC2 = 3.3 V
–2
VCC2 = 2.5 V
–1
MAX
UNIT
5.5
V
mA
VCC2 = 5 V
4
VCC2 = 3.3 V
2
IOL
Low-level output current
VIH
High-level input voltage
0.7 × VCC1
VCC1
V
VIL
Low-level input voltage
0
0.3 × VCC1
V
tui
Input pulse duration
7
DR
Signaling rate
0
TA
Ambient temperature
VCC2 = 2.5 V
mA
1
–55
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ns
25
100
Mbps
125
°C
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6.4 Thermal Information
ISO7810x
THERMAL METRIC (1)
DW (SOIC)
DWW (SOIC)
16 PINS
16 PINS
UNIT
89
92.2
°C/W
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
Junction-to-case(top) thermal resistance
51.5
53.8
°C/W
RθJB
Junction-to-board thermal resistance
53.6
62.9
°C/W
ψJT
Junction-to-top characterization parameter
22.5
23.9
°C/W
ψJB
Junction-to-board characterization parameter
23.1
62.2
°C/W
RθJC(bottom)
Junction-to-case(bottom) thermal resistance
—
—
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Power Rating
PARAMETER
PD
Maximum power dissipation
PD1
Maximum power dissipation by side-1
PD2
Maximum power dissipation by side-2
6
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TEST CONDITIONS
MIN
VCC1 = VCC2 = 5.5 V, TJ = 150°C,
CL = 15 pF, input a 50 MHz 50% duty
cycle square wave
TYP
MAX
UNIT
50
mW
12.5
mW
37.5
mW
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6.6 Insulation Characteristics
PARAMETER
SPECIFICATION
TEST CONDITIONS
UNIT
DW
DWW
Shortest terminal-to-terminal distance through air
>8
>14.5
mm
Shortest terminal-to-terminal distance across the package surface
>8
>14.5
mm
CLR
External clearance (1)
CPG
External creepage
DTI
Distance through the insulation
Minimum internal gap (internal clearance)
>21
>21
μm
CTI
Comparative tracking index
DIN EN 60112 (VDE 0303-11); IEC 60112; UL 746A
>600
>600
V
I
I
Rated mains voltage ≤ 600 VRMS
I–IV
I–IV
Rated mains voltage ≤ 1000 VRMS
I–III
I–IV
(1)
Material group
Overvoltage category per IEC
60664-1
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
(2)
VIOTM
Maximum transient isolation
voltage
VTEST = VIOTM
t = 60 s (qualification)
t= 1 s (100% production)
8000
8000
VPK
VIOSM
Maximum surge isolation voltage (3)
Test method per IEC 60065, 1.2/50 µs waveform,
VTEST = 1.6 × VIOSM = 12800 VPK (qualification)
8000
8000
VPK
VIORM
Maximum repetitive peak isolation
voltage
2121
2828
VPK
VIOWM
Maximum isolation working voltage
1500
2000
VRMS
2121
2828
VDC
Method a, After Input/Output safety test subgroup 2/3,
VPR = VIORM × 1.2, t = 10 s, Partial discharge < 5 pC
2545
3394
Method a, After environmental tests subgroup 1,
VPR = VIORM × 1.6, t = 10 s, Partial Discharge < 5 pC
3394
4525
Method b1,After environmental tests subgroup 1,
VPR = VIORM × 1.875, t = 1 s (100% Production test)
Partial discharge < 5 pC
3977
5303
VIO = 0.4 × sin (2πft), f = 1 MHz
~0.75
~0.75
pF
>1012
>1012
Ω
11
11
VPR
Input-to-output test voltage
Time dependent dielectric breakdown (TDDB) test; see Figure 1 and
Figure 2
VPK
CIO
Barrier capacitance, input to
output (4)
RIO
Isolation resistance, input to
output (4)
VIO = 500 V, TA = 25°C
VIO = 500 V, 100°C ≤ TA ≤ max
>10
>10
Ω
RS
Isolation resistance
VIO = 500 V at TS
>109
>109
Ω
Pollution degree
2
2
Climatic category
55/125/21
55/125/21
5700
5700
UL 1577
VISO
(1)
(2)
(3)
(4)
Withstanding isolation voltage
VTEST = VISO = 5700 VRMS, t = 60 s (qualification);
VTEST = 1.2 × VISO = 6840 VRMS , t = 1 s (100% production)
VRMS
Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care
should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on
the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases.
Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications.
This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by
means of suitable protective circuits.
Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
All pins on each side of the barrier tied together creating a two-terminal device.
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6.7 Regulatory Information
DW package certifications are complete. DWW package certifications completed for UL, VDE, and TUV and planned for CSA
and CQC.
VDE
CSA
UL
Certified according to DIN V
VDE V 0884-10 (VDE V
0884-10):2006-12 and DIN
EN 60950-1 (VDE 0805 Teil
1):2011-01
Approved under CSA
Component Acceptance
Notice 5A, IEC 60950-1 and
IEC 60601-1
Recognized under UL 1577
Component Recognition
Program
Reinforced insulation
Maximum transient isolation
voltage, 8000 VPK;
Maximum repetitive peak
isolation voltage, 2121
VPK(DW package), 2828 VPK
(DWW package);
Maximum surge isolation
voltage, 8000 VPK
Certificate number:
40040142
Reinforced insulation per
CSA 60950-1-07+A1+A2
and IEC 60950-1 2nd Ed.,
800 VRMS max working
voltage (pollution degree 2,
material group I);
2 MOPP (Means of Patient
Protection) per CSA 606011:14 and IEC 60601-1 Ed.
3.1,
250 VRMS (354 VPK) max
working voltage
Master contract number:
220991
Single protection, 5700
VRMS
File number: E181974
CQC
Certified according to GB
4943.1-2011
TUV
Certified according to EN 610101:2010 (3rd Ed) and EN 609501:2006/A11:2009/A1:2010/A12:2011
/A2:2013
5700 VRMS Reinforced insulation per
EN 61010-1:2010 (3rd Ed) up to
working voltage of 600 VRMS (DW
package) and 1000 VRMS (DWW
package)
Reinforced Insulation,
Altitude ≤ 5000 m, Tropical
Climate, 250 VRMS maximum 5700 VRMS Reinforced insulation per
working voltage
EN 609501:2006/A11:2009/A1:2010/A12:2011
/A2:2013 up to working voltage of
800 VRMS (DW package) and 1450
VRMS (DWW package)
Certificate number:
CQC15001121716
Client ID number: 77311
6.8 Safety Limiting Values
Safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry. A failure of
the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat
the die and damage the isolation barrier potentially leading to secondary system failures.
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
DW PACKAGE
IS
Safety input, output, or supply
current
PS
Safety input, output, or total
power
TS
Maximum safety temperature
RθJA = 89°C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C, see Figure 3
255
RθJA = 89°C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C, see Figure 3
390
RθJA = 89°C/W, VI = 2.75 V, TJ = 150°C, TA = 25°C, see Figure 3
511
RθJA = 89°C/W, TJ = 150°C, TA = 25°C, see Figure 5
mA
1404
mW
150
°C
DWW PACKAGE
IS
Safety input, output, or supply
current
PS
Safety input, output, or total
power
TS
Maximum safety temperature
RθJA = 92.2°C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C, see Figure 4
246
RθJA = 92.2°C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C, see Figure 4
377
RθJA = 92.2°C/W, VI = 2.75 V, TJ = 150°C, TA = 25°C, see Figure 4
493
RθJA = 92.2°C/W, TJ = 150°C, TA = 25°C, see Figure 6
mA
1356
mW
150
°C
The maximum safety temperature is the maximum junction temperature specified for the device. The power
dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines
the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Information is that of a
device installed on a high-K test board for leaded surface mount packages. The power is the recommended
maximum input voltage times the current. The junction temperature is then the ambient temperature plus the
power times the junction-to-air thermal resistance.
8
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6.9 Electrical Characteristics—5-V Supply
VCC1 = VCC2 = 5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
VCC2 – 0.4
VCC2 – 0.2
MAX
UNIT
VOH
High-level output voltage
IOH = –4 mA; see Figure 13
VOL
Low-level output voltage
IOL = 4 mA; see Figure 13
VI(HYS)
Input threshold voltage hysteresis
IIH
High-level input current
VIH = VCC1 at IN or EN2
IIL
Low-level input current
VIL = 0 V at IN or EN2
–10
μA
CMTI
Common-mode transient immunity
VI = VCC1 or 0 V, VCM = 1500 V; see Figure 16
100
kV/μs
CI
Input capacitance
(1)
(1)
0.2
V
0.4
V
10
μA
0.1 × VCC1
V
VI = VCC/2 + 0.4 × sin (2πft), f = 1 MHz, VCC = 5 V
2
pF
Measured from input pin to ground.
6.10 Supply Current Characteristics—5-V Supply
VCC1 = VCC2 = 5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
Supply current - disable
(DWW package only)
TEST CONDITIONS
MIN
TYP
MAX
EN2 = 0 V, VI = 0 V (Devices with suffix F),
VI = VCC1 (Devices without suffix F)
ICC1
0.6
1.1
ICC2
0.16
0.3
EN2 = 0 V, VI = VCC1 (Devices with suffix F),
VI = 0 V (Devices without suffix F)
ICC1
1.8
2.7
ICC2
0.16
0.3
VI = 0 V (Devices with suffix F),
VI = VCC1 (Devices without suffix F)
ICC1
0.6
1.1
ICC2
0.6
1.1
VI = VCC1 (Devices with suffix F),
VI = 0 V (Devices without suffix F)
ICC1
1.8
2.7
ICC2
0.7
1.1
ICC1
1.2
1.9
ICC2
0.6
1.1
ICC1
1.2
1.9
ICC2
1.1
1.6
ICC1
1.3
2
ICC2
5.7
7.3
Supply current - DC signal
1 Mbps
Supply current - AC signal
SUPPLY
CURRENT
Input signal switching with square
wave clock input;
CL = 15 pF
10 Mbps
100 Mbps
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UNIT
mA
mA
mA
9
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6.11 Electrical Characteristics—3.3-V Supply
VCC1 = VCC2 = 3.3 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
VCC2 – 0.4
VCC2 – 0.2
MAX
UNIT
VOH
High-level output voltage
IOH = –2 mA; see Figure 13
VOL
Low-level output voltage
IOL = 2 mA; see Figure 13
VI(HYS)
Input threshold voltage hysteresis
IIH
High-level input current
VIH = VCC1 at IN or EN2
IIL
Low-level input current
VIL = 0 V at IN or EN2
–10
μA
CMTI
Common-mode transient immunity
VI = VCC1 or 0 V, VCM = 1500 V; see Figure 16
100
kV/μs
0.2
V
0.4
V
10
μA
0.1 × VCC1
V
6.12 Supply Current Characteristics—3.3-V Supply
VCC1 = VCC2 = 3.3 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
Supply current - disable
(DWW package only)
SUPPLY
CURRENT
TEST CONDITIONS
MAX
ICC1
0.6
1.1
ICC2
0.16
0.3
EN2 = 0 V, VI = VCC1 (Devices with suffix F),
VI = 0 V (Devices without suffix F)
ICC1
1.8
2.7
ICC2
0.16
0.3
VI = 0 V (Devices with suffix F),
VI = VCC1 (Devices without suffix F)
ICC1
0.6
1.1
ICC2
0.6
1
VI = VCC1 (Devices with suffix F),
VI = 0 V(Devices without suffix F)
ICC1
1.8
2.7
ICC2
0.6
1.1
ICC1
1.2
1.9
ICC2
0.6
1.1
ICC1
1.2
1.9
ICC2
0.9
1.4
ICC1
1.3
2
ICC2
4.1
5.4
1 Mbps
Input signal switching with square
wave clock input;
CL = 15 pF
10 Mbps
100 Mbps
10
TYP
EN2 = 0 V, VI = 0 V (Devices with suffix F),
VI = VCC1 (Devices without suffix F)
Supply current - DC signal
Supply current - AC signal
MIN
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UNIT
mA
mA
mA
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6.13 Electrical Characteristics—2.5-V Supply
VCC1 = VCC2 = 2.5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
VCC2 – 0.4
VCC2 – 0.2
MAX
UNIT
VOH
High-level output voltage
IOH = –1 mA; see Figure 13
VOL
Low-level output voltage
IOL = 1 mA; see Figure 13
VI(HYS)
Input threshold voltage hysteresis
IIH
High-level input current
VIH = VCC1 at IN or EN2
IIL
Low-level input current
VIL = 0 V at IN or EN2
–10
μA
CMTI
Common-mode transient immunity
VI = VCC1 or 0 V, VCM = 1500 V; see Figure 16
100
kV/μs
0.2
V
0.4
V
10
μA
0.1 x VCC1
V
6.14 Supply Current Characteristics—2.5-V Supply
VCC1 = VCC2 = 2.5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
Supply current, - disable
(DWW package only)
TEST CONDITIONS
MIN
TYP
MAX
EN2 = 0 V, VI = 0 V (Devices with suffix F),
VI = VCC1 (Devices without suffix F)
ICC1
0.6
1.1
ICC2
0.16
0.3
EN2 = 0 V, VI = VCC1 (Devices with suffix F),
VI = 0 V (Devices without suffix F)
ICC1
1.8
2.7
ICC2
0.16
0.3
VI = 0 V (Devices with suffix F),
VI = VCCx (Devices without suffix F)
ICC1
0.6
1.1
ICC2
0.6
1
VI = VCCx (Devices with suffix F),
VI = 0 V(Devices without suffix F)
ICC1
1.8
2.7
ICC2
0.6
1.1
ICC1
1.2
1.9
ICC2
0.6
1.1
ICC1
1.2
1.9
ICC2
0.9
1.3
ICC1
1.3
2
ICC2
3.3
4.4
Supply current - DC signal
1 Mbps
Supply current - AC signal
SUPPLY
CURRENT
Input signal switching with square
wave clock input;
CL = 15 pF
10 Mbps
100 Mbps
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UNIT
mA
mA
mA
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6.15 Switching Characteristics—5-V Supply
VCC1 = VCC2 = 5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
MIN
TYP
MAX
6
10.7
16
ns
0.6
4.6
ns
4.5
ns
2.4
3.9
ns
2.4
3.9
ns
tPHZ
Disable propagation delay, high-to-high impedance output for
ISO7810DWW and ISO7810FDWW
12
20
ns
tPLZ
Disable propagation delay, low-to-high impedance output for
ISO7810DWW and ISO7810FDWW
12
20
ns
tPZH
Enable propagation delay,
high impedance-to-high output
ISO7810DWW
10
20
ns
ISO7810FDWW
2
2.5
μs
Enable propagation delay,
high impedance-to-low output
ISO7810DWW
2
2.5
μs
10
20
ns
0.2
9
μs
tPLH, tPHL
Propagation delay time
PWD
Pulse width distortion (1) |tPHL – tPLH|
tsk(pp)
Part-to-part skew time (2)
tr
Output signal rise time
tf
Output signal fall time
tPZL
tDO
See Figure 13
See Figure 13
See Figure 14
ISO7810FDWW
Measured from the time VCC
goes below 1.7 V. See Figure 15
Default output delay time from input power loss
tie
(1)
(2)
TEST CONDITIONS
16
Time interval error
2
1
– 1 PRBS data at 100 Mbps
UNIT
ns
Also known as pulse skew.
tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
6.16 Switching Characteristics—3.3-V Supply
VCC1 = VCC2 = 3.3 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
tPLH, tPHL
TEST CONDITIONS
Propagation delay time
(1)
See Figure 13
PWD
Pulse width distortion
tsk(pp)
Part-to-part skew time (2)
|tPHL – tPLH|
tr
Output signal rise time
tf
Output signal fall time
tPHZ
Disable propagation delay, high-to-high impedance output for
ISO7810DWW and ISO7810FDWW
tPLZ
Disable propagation delay, low-to-high impedance output for
ISO7810DWW and ISO7810FDWW
See Figure 13
tPZH
Enable propagation delay,
high impedance-to-high output
ISO7810DWW
tPZL
Enable propagation delay,
high impedance-to-low output
ISO7810DWW
See Figure 14
ISO7810FDWW
ISO7810FDWW
tDO
Default output delay time from input power loss
Measured from the time VCC
goes below 1.7 V. See Figure 15
tie
Time interval error
216 – 1 PRBS data at 100 Mbps
(1)
(2)
12
MIN
TYP
MAX
6
10.8
16
UNIT
ns
0.7
4.7
ns
4.5
ns
1.3
3
ns
1.3
3
ns
17
32
ns
17
32
ns
17
32
ns
2
2.5
μs
2
2.5
μs
17
32
ns
0.2
9
μs
1
ns
Also known as pulse skew.
tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
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6.17 Switching Characteristics—2.5-V Supply
VCC1 = VCC2 = 2.5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
MIN
TYP
MAX
UNIT
7.5
11.7
17.5
ns
0.7
4.7
ns
4.5
ns
1.8
3.5
ns
1.8
3.5
ns
tPHZ
Disable propagation delay, high-to-high impedance output for
ISO7810DWW and ISO7810FDWW
22
45
ns
tPLZ
Disable propagation delay, low-to-high impedance output for
ISO7810DWW and ISO7810FDWW
22
45
ns
tPZH
Enable propagation delay,
high impedance-to-high output
ISO7810DWW
18
45
ns
ISO7810FDWW
2
2.5
μs
tPZL
Enable propagation delay,
high impedance-to-low output
ISO7810DWW
2
2.5
μs
18
45
ns
0.2
9
μs
tPLH, tPHL
Propagation delay time
PWD
Pulse width distortion (1) |tPHL – tPLH|
tsk(pp)
Part-to-part skew time (2)
tr
Output signal rise time
tf
Output signal fall time
tDO
tie
(1)
(2)
TEST CONDITIONS
See Figure 13
See Figure 13
See Figure 14
ISO7810FDWW
Default output delay time from input power loss
Measured from the time VCC goes
below 1.7 V. See Figure 15
16
Time interval error
2
– 1 PRBS data at 100 Mbps
1
ns
Also known as pulse skew.
tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
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6.18 Insulation Characteristics Curves
1.E+11
87.5%
Safety Margin Zone: 2400 VRMS, 63 Years
Operating Zone: 2000 VRMS, 34 Years
TDDB Line (<1 PPM Fail Rate)
1.E+10
1.E+9
1.E+9
1.E+8
1.E+8
Time to Fail (s)
Time to Fail (s)
1.E+10
1.E+11
Safety Margin Zone: 1800 VRMS, 254 Years
Operating Zone: 1500 VRMS, 135 Years
TDDB Line (<1 PPM Fail Rate)
1.E+7
1.E+6
1.E+5
87.5%
1.E+7
1.E+6
1.E+5
1.E+4
1.E+4
1.E+3
1.E+3
20%
1.E+2
1.E+2
1.E+1
500
1.E+1
400
20%
1500 2500 3500 4500 5500 6500 7500 8500 9500
Stress Voltage (VRMS)
TA upto 150°C
Operating lifetime = 135 years
Stress-voltage frequency = 60 Hz
Isolation working voltage = 1500 VRMS
TA upto 150°C
Figure 1. Reinforced Isolation Capacitor Lifetime Projection
for Devices in DW Package
Operating lifetime = 34 years
Stress-voltage frequency = 60 Hz
Isolation working voltage = 2000 VRMS
Figure 2. Reinforced Isolation Capacitor Lifetime Projection
for Devices in DWW Package
600
600
VCC1 = VCC2 = 2.75 V
VCC1 = VCC2 = 3.6 V
VCC1 = VCC2 = 5.5 V
500
Safety Limiting Current (mA)
Safety Limiting Current (mA)
1400 2400 3400 4400 5400 6400 7400 8400 9400
Stress Voltage (VRMS)
400
300
200
100
0
VCC1 = VCC2 = 2.75 V
VCC1 = VCC2 = 3.6 V
VCC1 = VCC2 = 5.5 V
500
400
300
200
100
0
0
50
100
150
Ambient Temperature (qC)
200
0
50
D003
Figure 3. Thermal Derating Curves for Safety Limiting
Current for DW Package
100
150
Ambient Temperature (qC)
1600
Power
Power
1400
Safety Limiting Power (mW)
1400
Safety Limiting Power (mW)
D004
Figure 4. Thermal Derating Curves for Safety Limiting
Current for DWW Package
1600
1200
1000
800
600
400
200
1200
1000
800
600
400
200
0
0
0
50
100
150
Ambient Temperature (qC)
200
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0
50
D005
Figure 5. Thermal Derating Curve for Safety Limiting Power
for DW Package
14
200
100
150
Ambient Temperature (qC)
200
D006
Figure 6. Thermal Derating Curve for Safety Limiting Power
for DWW Package
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6.19 Typical Characteristics
8
ICC1 at 2.5 V
ICC2 at 2.5 V
ICC1 at 3.3 V
ICC2 at 3.3 V
ICC1 at 5 V
ICC2 at 5 V
8
Supply Current (mA)
Supply Current (mA)
12
4
0
ICC1 at 2.5 V
ICC2 at 2.5 V
ICC1 at 3.3 V
ICC2 at 3.3 V
ICC1 at 5 V
ICC2 at 5 V
6
4
2
0
0
25
50
TA = 25°C
75
100
Data Rate (Mbps)
125
150
0
CL = 15 pF
75
100
Data Rate (Mbps)
125
150
D002
CL = No Load
Figure 8. Supply Current vs Data Rate (With No Load)
6
1.0
VCC at 2.5V
VCC at 3.3V
VCC at 5.0V
0.9
5
Low-Level Output Voltage (V)
High-Level Output Voltage (V)
50
TA = 25°C
Figure 7. Supply Current vs Data Rate (With 15-pF Load)
4
3
2
VCC at 2.5V
VCC at 3.3V
VCC at 5.0V
1
0
-15
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
-10
-5
High-Level Output Current (mA)
0
0
15
VCC1 Rising
VCC1 Falling
VCC2 Rising
VCC2 Falling
14
Propagation Delay Time (ns)
2.10
D001
Figure 10. Low-Level Output Voltage vs Low-Level Output
Current
2.25
2.15
15
TA = 25°C
Figure 9. High-Level Output Voltage vs High-level Output
Current
2.20
5
10
Low-Level Output Current (mA)
D001
TA = 25°C
Power Supply Under Voltage Threshold (V)
25
D001
2.05
2.00
1.95
1.90
1.85
1.80
13
12
11
10
9
7
1.75
6
1.70
-50
5
-60
0
50
100
Free-Air Temperature (oC )
150
tPLH at 2.5 V
tPHL at 2.5 V
tPHL at 3.3 V
tPLH at 3.3 V
tPLH at 5 V
tPHL at 5 V
8
-30
D001
Figure 11. Power Supply Undervoltage Threshold vs FreeAir Temperature
0
30
60
Free-Air Temperature (oC )
90
120
D006
Figure 12. Propagation Delay Time vs Free-Air Temperature
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7 Parameter Measurement Information
Isolation Barrier
IN
Input
Generator
(See Note A)
VI
VCC1
50
VI
OUT
50%
50%
0V
tPLH
tPHL
CL
See Note B
VO
VOH
90%
50%
VO
50%
10%
VOL
tf
tr
A.
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3
ns, tf ≤ 3ns, ZO = 50 Ω. At the input, 50 Ω resistor is required to terminate Input Generator signal. It is not needed in
actual application.
B.
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 13. Switching Characteristics Test Circuit and Voltage Waveforms
VCC2
VCC
Isolation Barrier
IN
0V
VI
VO
tPZL
0V
tPLZ
VOH
EN
0.5 V
VO
50%
VOL
50
OUT
VCC
VO
VCC / 2
VCC / 2
VI
0V
tPZH
EN
CL
See Note B
VI
VCC / 2
VCC / 2
VI
CL
See Note B
IN
Input
Generator
(See Note A)
±1%
OUT
Isolation Barrier
Input
Generator
(See Note A)
3V
RL = 1 k
RL = 1 k
±1%
VOH
50%
VO
0.5 V
tPHZ
50
A.
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 10 kHz, 50% duty cycle, tr ≤ 3
ns, tf ≤ 3 ns, ZO = 50 Ω.
B.
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
0V
Figure 14. Enable and Disable Propagation Delay Time Test Circuit and Waveform
16
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Parameter Measurement Information (continued)
VI
VCC
VCC
Isolation Barrier
IN = 0 V (Devices without suffix F)
IN = VCC (Devices with suffix F)
IN
1.7 V
VI
OUT
t
VO
0V
DO
default high
VOH
CL
VO
See Note A
50%
VOL
default low
Copyright © 2016, Texas Instruments Incorporated
A.
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 15. Default Output Delay Time Test Circuit and Voltage Waveforms
VCC2
VCC1
S1
Isolation Barrier
C = 0.1 µF ±1%
IN
C = 0.1 µF ±1%
Pass-fail criteria:
The output must
remain stable.
OUT
+
EN
CL
See Note A
GND1
A.
+
VCM ±
VOH or VOL
±
GND2
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 16. Common-Mode Transient Immunity Test Circuit
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8 Detailed Description
8.1 Overview
The ISO7810x device has an ON-OFF Keying (OOK) modulation scheme to transmit the digital data across a
silicon dioxide based isolation barrier. The transmitter sends a high frequency carrier across the barrier to
represent one digital state and sends no signal to represent the other digital state. The receiver demodulates the
signal after advanced signal conditioning and produces the output through a buffer stage. These devices also
incorporates advanced circuit techniques to maximize the CMTI performance and minimize the radiated
emissions due the high frequency carrier and IO buffer switching. The conceptual block diagram of a digital
capacitive isolator, Figure 17, shows a functional block diagram of a typical channel.
8.2 Functional Block Diagram
Transmitter
Receiver
EN
TX IN
OOK
Modulation
TX Signal
Conditioning
Oscillator
SiO2 based
Capacitive
Isolation
Barrier
RX Signal
Conditioning
Envelope
Detection
RX OUT
Emissions
Reduction
Techniques
Copyright © 2016, Texas Instruments Incorporated
Figure 17. Conceptual Block Diagram of a Digital Capacitive Isolator
Figure 18 shows how the ON/OFF keying scheme works.
TX IN
Carrier signal through
isolation barrier
RX OUT
Figure 18. On-Off Keying (OOK) Based Modulation Scheme
18
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8.3 Feature Description
The ISO7810 is available in both default output state options to enable a variety of application uses. Table 1
provides an overview of the device features.
Table 1. Device Features
PART NUMBER
(1)
MAXIMUM DATA RATE
DEFAULT OUTPUT
ISO7810
5700 VRMS / 8000 VPK
RATED ISOLATION
(1)
100 Mbps
High
ISO7810F
5700 VRMS / 8000 VPK
(1)
100 Mbps
Low
See the Regulatory Information section for detailed isolation ratings.
8.3.1 Electromagnetic Compatibility (EMC) Considerations
Many applications in harsh industrial environment are sensitive to disturbances such as electrostatic discharge
(ESD), electrical fast transient (EFT), surge and electromagnetic emissions. These electromagnetic disturbances
are regulated by international standards such as IEC 61000-4-x and CISPR 22. Although system-level
performance and reliability depends, to a large extent, on the application board design and layout, the ISO7810x
device incorporates many chip-level design improvements for overall system robustness. Some of these
improvements include:
• Robust ESD protection cells for input and output signal pins and inter-chip bond pads.
• Low-resistance connectivity of ESD cells to supply and ground pins.
• Enhanced performance of high voltage isolation capacitor for better tolerance of ESD, EFT and surge events.
• Bigger on-chip decoupling capacitors to bypass undesirable high energy signals through a low impedance
path.
• PMOS and NMOS devices isolated from each other by using guard rings to avoid triggering of parasitic
SCRs.
• Reduced common mode currents across the isolation barrier by ensuring purely differential internal operation.
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8.4 Device Functional Modes
Table 2 lists the ISO7810x functional modes.
Table 2. Function Table (1)
VCC1
INPUT
(IN) (2)
VCC2
PU
PU
OUTPUT
(OUT)
COMMENTS
H
H
L
L
Open
Default
Default mode: When IN is open, the corresponding channel output goes to the
default logic state. Default = High for ISO7810 and Low for ISO7810F.
Normal Operation:
A channel output assumes the logic state of the input.
PD
PU
X
Default
Default mode: When VCC1 is unpowered, a channel output assumes the logic
state based on the selected default option. Default = High for ISO7810 and Low
for ISO7810F.
When VCC1 transitions from unpowered to powered-up, a channel output
assumes the logic state of the input.
When VCC1 transitions from powered-up to unpowered, channel output
assumes the selected default state.
X
PD
X
Undetermined
When VCC2 is unpowered, a channel output is undetermined (3).
When VCC2 transitions from unpowered to powered-up, a channel output
assumes the logic state of its input
(1)
(2)
(3)
PU = Powered up (VCC ≥ 2.25 V); PD = Powered down (VCC ≤ 1.7 V); X = Irrelevant; H = High level; L = Low level
A strongly driven input signal can weakly power the floating VCC via an internal protection diode and cause undetermined output.
The outputs are in undetermined state when 1.7 V < VCC1, VCC2 < 2.25 V.
8.4.1 Device I/O Schematics
Input (Devices with F suffix)
Input (Devices without F suffix)
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
1.5 M
985
985
IN
IN
1.5 M
Output
Enable
VCC2
VCC2
VCC2
VCC2
VCC2
2M
~20
1970
OUT
EN2
Figure 19. Device I/O Schematics
20
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9 Applications and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The ISO7810x device is a high-performance, single-channel digital isolator with a 5.7-kVRMS isolation voltage.
The device uses single-ended CMOS-logic switching technology. The supply voltage range is from 2.25 V to 5.5
V for both supplies, VCC1 and VCC2. When designing with digital isolators, keep in mind that because of the
single-ended design structure, digital isolators do not conform to any specific interface standard and are only
intended for isolating single-ended CMOS or TTL digital signal lines. The isolator is typically placed between the
data controller (that is, μC or UART), and a data converter or a line transceiver, regardless of the interface type
or standard.
9.2 Typical Application
The ISO7810F device can be used with Texas Instruments' gate driver and transformer driver to create an
isolated MOSFET/IGBT drive circuit.
VIN
3.3 V
0.1 F
2
Vcc
D2
1:2.2
3
MBR0520L
VSOURCE
SN6501
10 F 1 F
D1
GND
0.1 F
1
10 F
GND
MBR0520L
5
4
ISO Barrier
L1
D1
VOUT
0.22 F
0.22 F
0.1 F
2
2
DVCC
5
XOUT
6
MSP430F2132
XIN
1
P3.0
3
11
4
1,7
DVSS
4
0.1 F
0.1 F
VCC1
VCC2
14
ISO7810F OUT 13
GND1
GND2
9,16
VREF
IN-
OUTH
UCC27611
3
Q1
6
VDD
IN+
OUTL
10
C1
5
1
4
GND
IN
7
Copyright © 2016, Texas Instruments Incorporated
Figure 20. Low-Side Isolated Gate Driver Circuit
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Typical Application (continued)
9.2.1 Design Requirements
For this design example, use the parameters listed in Table 3.
Table 3. Design Parameters
PARAMETER
VALUE
Supply voltage
2.25 V to 5.5 V
Decoupling capacitor between VCC1 and GND1
0.1 µF
Decoupling capacitor from VCC2 and GND2
0.1 µF
9.2.2 Detailed Design Procedure
Unlike optocouplers, which require external components to improve performance, provide bias, or limit current,
the ISO7810x device only requires two external bypass capacitors to operate.
VCC1
VCC2
GND1 1
GND1
16 GND2
GND2
0.1 µF
0.1 µF
NC
2
15
NC
VCC1
3
14 VCC2
IN
4
NC
5
NC
GND2
IN
ISOLATION
GND1
OUT
13 OUT
12
NC
6
11
NC
GND1 7
10
NC
GND1
NC
8
9 GND2
GND2
Figure 21. Typical ISO7810DW Circuit Hook-up
9.2.3 Application Curve
The following typical eye diagram of the ISO7810x device indicates low jitter and wide open eye at the maximum
data rate of 100 Mbps.
Figure 22. Eye Diagram at 100 Mbps PRBS, 5 V, and 25°C
22
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ISO7810, ISO7810F
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SLLSEP1B – JULY 2015 – REVISED JUNE 2016
10 Power Supply Recommendations
To help ensure reliable operation at data rates and supply voltages, a 0.1-μF bypass capacitor is recommended
at input and output supply pins (VCC1 and VCC2). The capacitors should be placed as close to the supply pins as
possible. If only a single primary-side power supply is available in an application, isolated power can be
generated for the secondary-side with the help of a transformer driver such as Texas Instruments' SN6501. For
such applications, detailed power supply design and transformer selection recommendations are available in
SN6501 data sheet (SLLSEA0) .
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11 Layout
11.1 Layout Guidelines
A minimum of four layers is required to accomplish a low EMI PCB design (see Figure 23). Layer stacking should
be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency
signal layer.
• Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their
inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits
of the data link.
• Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for
transmission line interconnects and provides an excellent low-inductance path for the return current flow.
• Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of
approximately 100 pF/in2.
• Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links
usually have margin to tolerate discontinuities such as vias.
If an additional supply voltage plane or signal layer is needed, add a second power or ground plane system to
the stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also the
power and ground plane of each power system can be placed closer together, thus increasing the high-frequency
bypass capacitance significantly.
For detailed layout recommendations, see the application note, Digital Isolator Design Guide (SLLA284).
11.1.1 PCB Material
For digital circuit boards operating at less than 150 Mbps, (or rise and fall times greater than 1 ns), and trace
lengths of up to 10 inches, use standard FR-4 UL94V-0 printed circuit board. This PCB is preferred over cheaper
alternatives because of lower dielectric losses at high frequencies, less moisture absorption, greater strength and
stiffness, and the self-extinguishing flammability-characteristics.
11.2 Layout Example
High-speed traces
10 mils
Ground plane
40 mils
Keep this
space free
from planes,
traces, pads,
and vias
FR-4
0r ~ 4.5
Power plane
10 mils
Low-speed traces
Figure 23. Layout Example
24
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SLLSEP1B – JULY 2015 – REVISED JUNE 2016
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation, see the following:
• Isolation Glossary , SLLA353
• ISO784xx Quad-Channel Digital Isolator EVM User Guide, SLAU602
• Shelf-Life Evaluation of Lead-Free Component Finishes, SZZA046
• SN6501 Transformer Driver for Isolated Power Supplies, SLLSEA0
• UCC2753x 2.5-A and 5-A, 35-VMAX VDD FET and IGBT Single-Gate Driver, SLUSBA7
• MSP430F2132 Mixed Signal Microcontroller, SLAS578
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 4. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
ISO7810
Click here
Click here
Click here
Click here
Click here
ISO7810F
Click here
Click here
Click here
Click here
Click here
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates — go to the product folder for your device on ti.com. In the
upper right-hand corner, click the Alert me button to register and receive a weekly digest of product information
that has changed (if any). For change details, check the revision history of any revised document.
12.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
26
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PACKAGE OPTION ADDENDUM
www.ti.com
2-Sep-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
ISO7810DW
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-55 to 125
ISO7810
ISO7810DWR
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-55 to 125
ISO7810
ISO7810DWW
ACTIVE
SOIC
DWW
16
45
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-55 to 125
ISO7810
ISO7810DWWR
ACTIVE
SOIC
DWW
16
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-55 to 125
ISO7810
ISO7810FDW
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-55 to 125
ISO7810F
ISO7810FDWR
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-55 to 125
ISO7810F
ISO7810FDWW
ACTIVE
SOIC
DWW
16
45
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-55 to 125
ISO7810F
ISO7810FDWWR
ACTIVE
SOIC
DWW
16
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-55 to 125
ISO7810F
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
(4)
2-Sep-2016
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Aug-2016
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
10.75
10.7
2.7
12.0
16.0
Q1
ISO7810DWR
SOIC
DW
16
2000
330.0
16.4
ISO7810DWWR
SOIC
DWW
16
1000
330.0
24.4
18.0
10.0
3.0
20.0
24.0
Q1
ISO7810FDWR
SOIC
DW
16
2000
330.0
16.4
10.75
10.7
2.7
12.0
16.0
Q1
ISO7810FDWWR
SOIC
DWW
16
1000
330.0
24.4
18.0
10.0
3.0
20.0
24.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Aug-2016
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ISO7810DWR
SOIC
DW
16
2000
367.0
367.0
38.0
ISO7810DWWR
SOIC
DWW
16
1000
367.0
367.0
45.0
ISO7810FDWR
SOIC
DW
16
2000
367.0
367.0
38.0
ISO7810FDWWR
SOIC
DWW
16
1000
367.0
367.0
45.0
Pack Materials-Page 2
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