ON NCP382LMN20A-ATXG Fixed current-limiting power-distribution switch Datasheet

NCP382
Fixed Current-Limiting
Power-Distribution
Switches
The NCP382 is a single input dual outputs high side
power−distribution switch designed for applications where heavy
capacitive loads and short−circuits are likely to be encountered. The
device includes an integrated 80 mW, P−channel MOSFET. The
device limits the output current to a desired level by switching into a
constant−current mode when the output load exceeds the current−limit
threshold or a short is present. The current−limit threshold is internally
fixed. The power−switches rise and fall times are controlled to
minimize current ringing during switching.
The FLAG logic output asserts low during overcurrent or
overtemperature conditions. The switch is controlled by a logic enable
input active high or low.
•
•
•
MARKING
DIAGRAMS
1
1
DFN8 3x3
CASE 506BW
XXXXX
XXXXX
ALYWG
G
8
Features
•
•
•
•
•
•
•
•
•
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2.5 V – 5.5 V Operating Range
80 mW High−Side MOSFET
Current Limit: Fixed 500 mA, 1 A, 1.5 A and 2 A
Undervoltage Lock−Out (UVLO)
Soft−Start Prevents Inrush Current
Thermal Protection
Soft Turn−Off
Enable Active High or Low (EN or EN)
Compliance to IEC61000−4−2 (Level 4)
♦ 8.0 kV (Contact)
♦ 15 kV (Air)
UL Listed − File No. E343275
IEC60950 − Edition 2 − Amendment 1 Certified (CB Scheme)
These are Pb−Free Devices
8
1
SOIC−8 NB
CASE 751
1
XXXXXX
ALYWX
G
XXXXX = Specific Device Code
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
Typical Applications
• Laptops
• USB Ports/Hubs
• TVs
© Semiconductor Components Industries, LLC, 2012
February, 2012 − Rev. 8
1
Publication Order Number:
NCP382/D
NCP382
USB
DATA
USB INPUT
5V
OUT1
IN
Rfault
1 mF
NCP382
100 kW
FLAG1
D+
D−
USB
VBUS Port
GND
120 mF
USB
DATA
FLAG1
EN1
EN1
FLAG2
FLAG2
EN2
D+
D−
USB
VBUS Port
GND
OUT2
EN2
GND
120 mF
Figure 1. Typical Application Circuit
GND
1
IN
2
EN1
3
EN2
4
8 FLAG1
DFN8
7 OUT1
6 OUT2
5 FLAG2
GND
1
8
FLAG1
IN
2
7
OUT1
EN1
3
6
OUT2
EN2
4
5
FLAG2
SOIC−8
(Top View)
Figure 2. Pin Connections
PIN FUNCTION DESCRIPTION
Pin Name
Type
Description
EN1
I
Enable 1 input, logic low/high (i.e. EN or EN) turns on power switch.
EN2
I
Enable 2 input, logic low/high (i.e. EN or EN) turns on power switch.
GND
P
Ground connection.
IN
P
Power−switch input voltage; connect a 1 mF or greater ceramic capacitor from IN to GND as close as possible to
the IC.
FLAG1
O
Active−low open−drain output 1, asserted during overcurrent or overtemperature conditions. Connect a 10 kW or
greater resistor pull−up, otherwise leave unconnected.
FLAG2
O
Active−low open−drain output 2, asserted during overcurrent or overtemperature conditions. Connect a 10 kW or
greater resistor pull−up, otherwise leave unconnected.
OUT1
O
Power−switch output1; connect a 1 mF ceramic capacitor from OUT1 to GND, as close as possible to the IC.
This minimum value is recommended for USB requirement in terms of load transient response and strong short
circuits.
OUT2
O
Power−switch output2; connect a 1 mF ceramic capacitor from OUT2 to GND, as close as possible to the IC.
This minimum value is recommended for USB requirement in terms of load transient response and strong short
circuits.
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NCP382
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
From IN to OUT1, From IN to OUT2 Supply Voltage (Note 1)
VIN , VOUT1,VOUT2
−7.0 to +7.0
V
VIN, VOUT1, VOUT2, VEN1, VEN2,
VFLAG1, VFLAG2
−0.3 to +7.0
V
ISINK
1.0
mA
ESD IEC
15 Air, 8 contact
kV
Human Body Model (HBM) ESD Rating are (Note 2)
ESD HBM
2000
V
Machine Model (MM) ESD Rating are (Note 2)
ESD MM
200
V
IN, OUT1,OUT2, EN1, EN2, FLAG1, FLAG2 (Note 1)
FLAG1, FLAG2 sink current
ESD Withstand Voltage (IEC 61000−4−2) (output only, when
bypassed with 1.0 mF capacitor minimum)
Latch−up protection (Note 3)
− Pins IN, OUT1, OUT2, FLAG1, FLAG2
− EN1, EN2
LU
Maximum Junction Temperature (Note 4)
mA
100
TJ
−40 to + TSD
°C
Storage Temperature Range
TSTG
−40 to + 150
°C
Moisture Sensitivity (Note 5)
MSL
Level 1
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. According to JEDEC standard JESD22−A108.
2. This device series contains ESD protection and passes the following tests:
Human Body Model (HBM) +/−2.0 kV per JEDEC standard: JESD22−A114 for all pins.
Machine Model (MM) +/−200 V per JEDEC standard: JESD22−A115 for all pins.
3. Latch up Current Maximum Rating: $100 mA per JEDEC standard: JESD78 class II.
4. A thermal shutdown protection avoids irreversible damage on the device due to power dissipation.
5. Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J−STD−020.
OPERATING CONDITIONS
Symbol
VIN
VENX
TA
ISINK
CIN
COUTX
RqJA
Parameter
Min
Operational Power Supply
Enable Voltage
Ambient Temperature Range
Max
Unit
2.5
5.5
V
0
5.5
−40
Typ
25
FLAG sink current
Decoupling input capacitor
Decoupling output capacitor
Thermal Resistance Junction−to−Air
TJ
Junction Temperature Range
IOUTX
Recommended Maximum DC
current
PD
Conditions
Power Dissipation Rating (Note 8)
USB port per Hub
+85
°C
1
mA
1
mF
120
mF
DFN−8 package (Notes 6 and 7)
140
°C/W
SOIC−8 package (Notes 6 and 7)
210
°C/W
−40
DFN−8 package
SOIC−8 package
TA v 25°C
TA = 85°C
25
+125
°C
2
A
1.5
A
DFN−8 package
850
mW
SOIC−8 package
570
mW
DFN−8 package
428
mW
SOIC−8 package
285
mW
6. A thermal shutdown protection avoids irreversible damage on the device due to power dissipation.
7. The RqJA is dependent of the PCB heat dissipation. Announced thermal resistance is the unless PCB dissipation and can be improve with
final PCB layout.
8. The maximum power dissipation (PD) is given by the following formula:
T
*T
PD +
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3
JMAX
R qJA
A
NCP382
ELECTRICAL CHARACTERISTICS Min & Max Limits apply for TA between −40°C to +85°C and TJ up to + 125°C for VIN between
2.5 V to 5.5 V (Unless otherwise noted). Typical values are referenced to TA = + 25°C and VIN = 5 V.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
110
mW
POWER SWITCH
RDS(on)
RDS(on)
TR
Static drain−source on−state resistance
(SOIC−8 Package)
Static drain−source on−state resistance
(DFN8 Package)
Output rise time
TJ = 25°C, VIN = 3.6 V to 5 V
VIN = 5 V
Output fall time
140
TJ = 25°C, VIN = 3.6 V to 5 V
VIN = 5 V
–40°C < TJ < 125°C
VIN = 5 V
CLOAD = 1 mF,
RLOAD = 100 W (Note 9)
VIN = 2.5 V
TF
80
–40°C < TJ < 125°C
80
95
mW
100
0.3
1.0
1.5
0.2
0.65
1.0
VIN = 5 V
0.1
0.5
VIN = 2.5 V
0.1
0.5
ms
ENABLE INPUT ENx OR ENx
VIH
High−level input voltage
VIL
Low−level input voltage
1.2
IENx
Input current
VENx = 0 V, VENx = 5 V
TON
Turn on time
CLOAD = 1 mF, RLOAD = 100 W (Note 9)
TOFF
Turn off time
V
0.4
V
−0.5
0.5
mA
1.0
3.0
ms
1.0
3.0
ms
A
CURRENT LIMIT
IOCP
Current−limit threshold (Maximum DC
output current IOUTX delivered to load)
VIN = 5 V, Fixed 0.5 A
0.5
0.6
0.7
VIN = 5 V, Fixed 1.0 A
1.0
1.2
1.4
VIN = 5 V, Fixed 1.5 A
1.5
1.75
2.0
VIN = 5 V, Fixed 2 A
2
2.25
2.5
TDET
Response time to short circuit
VIN = 5 V
2.0
TREG
Regulation time
2.0
3.0
4.0
ms
TOCP
Over current protection time
14
20
26
ms
ms
UNDERVOLTAGE LOCKOUT
VUVLO
IN pin low−level input voltage
VIN rising
2.0
2.35
2.5
V
VHYST
IN pin hysteresis
TJ = 25°C
25
40
60
mV
TRUVLO
Re−arming Time
VIN rising
5.0
10
15
ms
2.0
3.0
mA
mA
SUPPLY CURRENT
IINOFF
Low−level output supply current
IINON
High−level output supply current
IREV
Reverse leakage current
VIN = 5 V, No load on OUTX, Device OFF
VENX = 0 V or VENX = 5 V
0.5 A
TJ = 25°C
TJ = 85°C
95
100
1 and 1.5 A
TJ = 25°C
TJ = 85°C
115
125
2A
TJ = 25°C
TJ = 85°C
130
140
VOUTX = 5 V,
VIN = 0 V
TJ = 25°C
1.0
2.0
mA
400
mV
FLAG PIN
FLAGX output low voltage
IFLAGX = 1 mA
ILEAK
VOL
Off−state leakage
VFLAGX = 5 V
TFLG
FLAGX deglitch
FLAGX de−assertion time due to
overcurrent
TFOCP
FLAGX deglitch
FLAGX assertion due to overcurrent
0.02
1
mA
4
6
9
ms
6
8
12
ms
THERMAL SHUTDOWN
TSD
Thermal shutdown threshold
140
°C
TSDOCP
Thermal regulation threshold
125
°C
Thermal regulation rearming threshold
115
°C
TRSD
9. Parameters are guaranteed for CLOAD and RLOAD connected to the OUTX pin with respect to the ground.
10. DFN package only.
11. Guaranteed by characterization.
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4
NCP382
VIN
IN
1 mF
OUT1
NCP382
C LOAD
RLOAD
C LOAD
RLOAD
OUT2
GND
Figure 3. Test Configuration
VENx
50%
TR
VENx
VOUTx
TF
90%
10%
TOFF
TON
VOUTx
90%
10%
Figure 4. Voltage Waveform
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5
10%
NCP382
BLOCK DIAGRAM
EN1
EN block
Control logic
and timer
Flag
Current
Limiter
/FLAG 1
Gate Driver
GND
OUT 1
IN
Oscilator
VREF
UVLO
TSD
Blocking control
Channel 1
Blocking control
Channel 2
OUT 2
Current
Limiter
Gate Driver
Flag
/FLAG 2
EN2
EN block
Control logic
and timer
Figure 5. Block Diagram
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6
NCP382
FUNCTIONAL DESCRIPTION
VOUTX
Overview
The NCP382 is a dual high side power distribution
switches designed to protect the input supply voltage in case
of heavy capacitive loads, short circuit or over current. In
addition, the high side MOSFETs are turned off during
undervoltage or thermal shutdown condition. Thanks to the
soft start circuitry, NCP382 is able to limit large current and
voltage surges.
Thermal
Regulation
Threshold
IOUTX
IOCP
Overcurrent Protection
TOCP
NCP382 switches into a constant current regulation mode
when the output current is above the IOCP threshold.
Depending on the load, the output voltage is decreased
accordingly.
− In case of hot plug with heavy capacitive load, the
output voltage is brought down to the capacitor voltage.
The NCP382 will limit the current to the IOCP threshold
value until the charge of the capacitor is completed.
Then, the device enters in timer regulation mode, described
in 2 phases:
− Off−phase: Power MOSFET is off during TOCP to allow
the die temperature to drop.
− On−phase: regulation current mode during TREG. The
current is regulated to the IOCP level.
The timer regulation mode allows the device to handle
high thermal dissipation (in case of short circuit for
example) within temperature operating condition.
NCP382 stays in on−phase/off−phase loop until the over
current condition is removed or enable pin is toggled.
Remark: other regulation modes can be available for
different applications. Please contact our On Semiconductor
representative for availability.
Drop due to
capacitor charge
IOUTX
IOCP
FLAG Indicator
Figure 6. Heavy Capacitive Load
The FLAG pin is an open−drain MOSFET asserted low
during overcurrent or overtemperature conditions. When an
overcurrent fault is detected on the power path, FLAG pin
is asserted low at the end of the associate deglitch time
(TFOCP). Thanks to this feature, the FLAG pin is not tied
low during the charge of a heavy capacitive load or a voltage
transient on output. The FLAG pin remains low until the
fault is removed. Then, the FLAG pin goes high at the end
of TFGL
− In case of overload, the current is limited to the IOCP
value and the voltage value is reduced according to the
load by the following relation:
I OCP
TREG
Figure 8. Short−Circuit
VOUTX
V OUTX + R LOAD2
Timer
Regulation
Mode
(eq. 1)
VOUTX
Undervoltage Lock−out
IOCP x RLOAD
Thanks to a built−in under voltage lockout (UVLO)
circuitry, the output remains disconnected from input until
VIN voltage is above VUVLO. This circuit has a VHYST
hysteresis witch provides noise immunity to transient
condition.
IOUTX
IOCP
Figure 7. Overload
Thermal Sense
Thermal shutdown turns off the power MOSFET if the die
temperature exceeds TSD. A built-in hysteresis prevents the
part from turning on until the die temperature cools at
TRSD.
− In case of short circuit or huge load, the current is
limited to the IOCP value within TDET time until the
short condition is removed. If the output remains
shorted or tied to a very low voltage, the junction
temperature of the chip exceeds TSDOCP value and the
device enters in thermal shutdown (MOSFET is
turned−off).
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7
NCP382
Enable Input
leakage current IREV from OUTX to IN. In this mode, anode
of the body diode is connected to IN pin and cathode is
connected to OUTX pin. In operating condition, anode of
the body diode is connected to OUTX pin and cathode is
connected to IN pin preventing the discharge of the power
supply.
Enable pin must be driven by a logic signal (CMOS or
TTL compatible) or connected to the GND or VIN. A logic
low on ENX or high on ENX turns−on the device. A logic
high on ENX or low on ENX turns off device and reduces
the current consumption down to IINOFF.
Blocking Control
The blocking control circuitry switches the bulk of the
power MOS. When the part is off, the body diode limits the
APPLICATION INFORMATION
Power Dissipation
Power dissipation in regulation mode can be calculated by
taking into account the drop VIN −VOUTX link to the load by
the following relation:
The junction temperature of the device depends on
different contributing factors such as board layout, ambient
temperature, device environment, etc... Yet, the main
contributor in term of junction temperature is the power
dissipation of the power MOSFET. Assuming this, the
power dissipation and the junction temperature in normal
mode can be calculated with the following equations:
P D + R DS(on)
PD
RDS(on)
IOUTx
ǒǒI
2
) ǒI OUT2Ǔ
Ǔ
2
R qJA ) T A
ǒǒVIN * RLOAD1
I OCPǓ ) ǒV IN * R LOAD2
I OCP
PD
VIN
RLOADX
IOCP
(eq. 2)
= Power dissipation (W)
= Power MOSFET on resistance (W)
= Output current in channel X (A)
TJ + PD
TJ
RqJA
TA
Ǔ
OUT1
PD +
Ǔ
I OCPǓ
(eq. 4)
= Power dissipation (W)
= Input Voltage (V)
= Load Resistance on channel X (W)
= Output regulated current (A)
PCB Recommendations
The NCP382 integrates two PMOS FET rated up to 2 A,
and the PCB design rules must be respected to properly
evacuate the heat out of the silicon. The DFN8 PAD1 must
be connected to ground plane to increase the heat transfer if
necessary. Of course, in any case, this pad must not connect
to any other potential. By increasing PCB area, the RqJA of
the package can be decreased, allowing higher current.
(eq. 3)
= Junction temperature (°C)
= Package thermal resistance (°C/W)
= Ambient temperature (°C)
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8
NCP382
Figure 9. USB Host Typical Application
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9
NCP382
ORDERING INFORMATION
Active
Enable
Level
Evaluation
Board
UL
2367
IEC6095
0 Ed2
(CB
Scheme)
0.5 A
NCP382LM
N05AGEVB
N
N
N
1.0 A
NCP382LM
N10AGEVB
N
N
N
1.5 A
NCP382LM
N15AGEVB
N
N
N
Over
Current
Limit
IEC6095
0 Ed2
Ad1
Device
Marking
NCP382LMN05AATXG
382
L05
NCP382LMN10AATXG
382
L10
NCP382LMN15AATXG
382
L15
NCP382LMN20AATXG
382
L20
2.0 A
NCP382LM
N20AGEVB
N
N
N
NCP382HMN05AATXG
382
H05
0.5 A
NCP382HM
N05AGEVB
N
N
N
NCP382HMN10AATXG
382
H10
1.0 A
NCP382HM
N10AGEVB
N
N
N
NCP382HMN15AATXG
382
H15
1.5 A
NCP382HM
N15AGEVB
N
N
N
NCP382HMN20AATXG
382
H20
2.0 A
NCP382HM
N20AGEVB
N
N
N
NCP382LD05AA
R2G
382L05
0.5 A
NCP382LD
05AAGEVB
Y
Y
Y
NCP382LD10AA
R2G
382L10
1.0 A
NCP382LD
10AAGEVB
Y
Y
Y
NCP382LD15AA
R2G
382L15
1.5 A
NCP382LD
15AAGEVB
Y
Y
Y
NCP382HD05AA
R2G
382H05
0.5 A
NCP382HD
05AAGEVB
Y
Y
Y
NCP382HD10AA
R2G
382H10
1.0 A
NCP382HD
10AAGEVB
Y
Y
Y
NCP382HD15AA
R2G
382H15
1.5 A
NCP382HD
15AAGEVB
Y
Y
Y
ENx
Low
ENx
High
ENx
Low
ENx
High
Package
Shipping†
DFN8
(Pb−Free)
3000 /
Tape / Reel
SOIC−8
(Pb−Free)
2500 /
Tape / Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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10
NCP382
PACKAGE DIMENSIONS
DFN8, 3x3, 0.65P
CASE 506BW
ISSUE O
A
B
D
L
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.15 AND
0.30mm FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
L
L1
PIN ONE
REFERENCE
2X
0.10 C
2X
0.10 C
DETAIL A
ÉÉÉ
ÉÉÉ
ÉÉÉ
OPTIONAL
CONSTRUCTIONS
E
ÉÉ
ÉÉ
EXPOSED Cu
TOP VIEW
(A3)
DETAIL B
0.05 C
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
L1
MOLD CMPD
DETAIL B
A
OPTIONAL
CONSTRUCTIONS
MILLIMETERS
MIN
MAX
0.80
1.00
0.00
0.05
0.20 REF
0.25
0.35
3.00 BSC
2.30
2.50
3.00 BSC
1.55
1.75
0.65 BSC
0.20
−−−
0.35
0.45
0.00
0.15
0.05 C
NOTE 4
SIDE VIEW
C
RECOMMENDED
SOLDERING FOOTPRINT*
SEATING
PLANE
D2
DETAIL A
1
8X
A1
ÇÇÇÇÇÇÇ
ÇÇÇÇÇÇÇ
2.50
4
L
E2
8X
K
e/2
8
5
e
BOTTOM VIEW
8X
8X
0.62
3.30
1.75
ÇÇÇÇÇÇÇ
ÇÇÇÇÇÇÇ
b
1
0.10 C A B
0.05 C
0.65
PITCH
NOTE 3
8X
0.40
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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11
NCP382
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
−X−
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
−Y−
K
G
C
N
DIM
A
B
C
D
G
H
J
K
M
N
S
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
D
0.25 (0.010)
M
Z Y
S
X
S
M
J
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
SOLDERING FOOTPRINT*
1.52
0.060
7.0
0.275
4.0
0.155
0.6
0.024
1.270
0.050
SCALE 6:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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