Sample & Buy Product Folder Technical Documents Support & Community Tools & Software Reference Design OPA171-Q1, OPA2171-Q1, OPA4171-Q1 SBOS556B – JUNE 2011 – REVISED DECEMBER 2014 OPAx171-Q1 36-V, Single-Supply, General-Purpose Operational Amplifier 1 Features 3 Description • • The OPA171-Q1 family of devices is a 36-V, singlesupply, low-noise operational amplifier (op amp) with the ability to operate on supplies ranging from 2.7 V (±1.35 V) to 36 V (±18 V). This device is available in micro-packages and offers low offset, drift, and bandwidth with low quiescent current. The single, dual, and quad versions all have identical specifications for maximum design flexibility. 1 • • • • • • • • • • • • Qualified for Automotive Applications AEC-Q100 Test Guidance With the Following: – Device Temperature Grade 1: –40°C to 125°C Ambient Operating Temperature Range – Device HBM ESD Classification Level H2 – Device CDM ESD Classification Level C3A (OPA171-Q1) and C6 (OPA2171-Q1, OPA4171-Q1) Supply Range: 2.7 to 36 V, ±1.35 to ±18 V Low Noise: 14 nV/√Hz Low Offset Drift: ±0.3 µV/°C (typ) RFI Filtered Inputs Input Range Includes the Negative Supply Input Range Operates to Positive Supply Rail-to-Rail Output Gain Bandwidth: 3 MHz Low Quiescent Current: 475 µA per Amplifier High Common-Mode Rejection: 120 dB (typ) Low Input Bias Current: 8 pA Industry-Standard Package: – 5-Pin Small-Outline Transistor [SOT (SOT-23) - DBV] Package Unlike most op amps, which are specified at only one supply voltage, the OPAx171-Q1 family of devices is specified from 2.7 to 36 V. Input signals beyond the supply rails do not cause phase reversal. The OPAx171-Q1 family of devices is stable with capacitive loads up to 300 pF. The input can operate 100 mV below the negative rail and within 2 V of the top rail during normal operation. The device can operate with full rail-to-rail input 100 mV beyond the top rail, but with reduced performance within 2 V of the top rail. The OPAx171-Q1 op amp is specified from –40°C to 125°C. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) OPA171-Q1 SOT (5) 2.90 mm × 1.60 mm OPA2171-Q1 SOIC (8) 4.90 mm × 3.91 mm SOIC (14) 8.65 mm × 3.91 mm TSSOP (14) 5.00 mm × 4.40 mm 2 Applications OPA4171-Q1 • • • • • • • • • (1) For all available packages, see the orderable addendum at the end of the datasheet. Tracking Amplifier in Power Modules Merchant Power Supplies Transducer Amplifiers Bridge Amplifiers Temperature Measurements Strain Gauge Amplifiers Precision Integrators Battery-Powered Instruments Test Equipment Space Offset Voltage vs Common-mode Voltage 1000 Offset Voltage vs Power Supply 10 Typical Units Shown 800 350 VSUPPLY = ±1.35V to ±18V 10 Typical Units Shown 600 250 200 150 0 VOS (mV) VOS (mV) 400 -200 -400 -600 50 -50 -150 -800 VCM = -18.1V -250 -1000 -20 -15 -10 -5 0 VCM (V) 5 10 15 20 -350 0 2 4 6 8 10 12 14 16 18 20 VSUPPLY (V) 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA. OPA171-Q1, OPA2171-Q1, OPA4171-Q1 SBOS556B – JUNE 2011 – REVISED DECEMBER 2014 www.ti.com Table of Contents 1 2 3 4 5 6 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 4 5 5 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information — OPA171-Q1 and OPA2171Q1 ............................................................................. 6.5 Thermal Information — OPA4171-Q1....................... 6.6 Electrical Characteristics........................................... 6.7 Typical Characteristics .............................................. 7 7.3 Feature Description................................................. 14 7.4 Device Functional Modes........................................ 16 8 Application and Implementation ........................ 17 8.1 Application Information............................................ 17 8.2 Typical Application .................................................. 18 9 Power Supply Recommendations...................... 20 10 Layout................................................................... 20 10.1 Layout Guidelines ................................................. 20 10.2 Layout Example .................................................... 21 11 Device and Documentation Support ................. 21 5 5 5 7 Detailed Description ............................................ 14 7.1 Overview ................................................................. 14 7.2 Functional Block Diagram ....................................... 14 11.1 11.2 11.3 11.4 11.5 Documentation Support ........................................ Related Links ........................................................ Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 21 21 21 22 22 12 Mechanical, Packaging, and Orderable Information ........................................................... 22 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (September 2012) to Revision B Page • Added the Handling Ratings table, Feature Description section, Device Functional Modes section, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ............................................................... 1 • Added the OPA2171-Q1 and OPA4171-Q1 devices to the data sheet ................................................................................ 1 Changes from Original (June, 2011) to Revision A Page • Added second bullet to Features: AEC-Q100 Test Guidance With the Following Results: –Device Temperature Grade1: -40°C to 125°C Ambient Operating Temperature Range –Device HBM ESD Classification Level H2 –Device CDM ESD Classification Level C3A ......................................................................................................................... 1 • Added classification levels to ESD ratings in Absolute Maximum Ratings table. .................................................................. 4 • Added row to Absolute Maximum Ratings table: Latch-up per JESD78D with Class 1 value. .............................................. 4 2 Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated Product Folder Links: OPA171-Q1 OPA2171-Q1 OPA4171-Q1 OPA171-Q1, OPA2171-Q1, OPA4171-Q1 www.ti.com SBOS556B – JUNE 2011 – REVISED DECEMBER 2014 5 Pin Configuration and Functions DBV Package 5-Pin SOT23 OPA171-Q1 Top View OUT 1 V- 2 +IN 3 5 4 D Package 8-Pin SOIC OPA2171-Q1 Top View V+ -IN OUT A 1 8 V+ –IN A 2 7 OUT B +IN A 3 6 –IN B V– 4 5 +IN B Pin Functions — DBV (5) and D (8) Packages PIN OPA171-Q1 DBV (5) OPA2171-Q1 D (8) I/O +IN 3 — I Noninverting input +IN A — 3 I Noninverting input, channel A +IN B — 5 I Noninverting input, channel B –IN 4 — I Inverting input –IN A — 2 I Inverting input, channel A –IN B — 6 I Inverting input, channel B OUT 1 — O Output OUT A — 1 O Output, channel A OUT B — 7 O Output, channel B V+ 5 7 — Positive (highest) power supply V– 2 4 — Negative (lowest) power supply NAME Copyright © 2011–2014, Texas Instruments Incorporated DESCRIPTION Submit Documentation Feedback Product Folder Links: OPA171-Q1 OPA2171-Q1 OPA4171-Q1 3 OPA171-Q1, OPA2171-Q1, OPA4171-Q1 SBOS556B – JUNE 2011 – REVISED DECEMBER 2014 www.ti.com D and PW Packages 14-Pin SOIC and TSSOP OPA4171-Q1 Top View OUT A 1 14 OUT D -IN A 2 13 -IN D +IN A 3 12 +IN D V+ 4 11 V- +IN B 5 10 +IN C -IN B 6 9 -IN C OUT B 7 8 OUT C Pin Functions — D (14) and PW (14) Packages PIN I/O DESCRIPTION NAME D (14), PW (14) +IN A 3 I Noninverting input, channel A +IN B 5 I Noninverting input, channel B +IN C 10 I Noninverting input, channel C +IN D 12 I Noninverting input, channel D –IN A 2 I Inverting input, channel A –IN B 6 I Inverting input, channel B –IN C 9 I Inverting input, channel C –IN D 13 I Inverting input, channel D OUT A 1 O Output, channel A OUT B 7 O Output, channel B OUT C 8 O Output, channel C OUT D 14 O Output, channel D V+ 4 — Positive (highest) power supply V– 11 — Negative (lowest) power supply 6 Specifications 6.1 Absolute Maximum Ratings Over operating free-air temperature range, unless otherwise noted. (1) MIN MAX UNIT 40 V Supply voltage Signal input terminals Voltage (V–) – 0.5 (V+) + 0.5 V ±10 mA 150 °C 150 °C 150 °C Current Output short circuit (2) Continuous Operating temperature –55 Junction temperature Latch-up per JESD78D Class 1 Storage temperature, Tstg (1) (2) 4 –65 Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. Short-circuit to ground, one amplifier per package. Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated Product Folder Links: OPA171-Q1 OPA2171-Q1 OPA4171-Q1 OPA171-Q1, OPA2171-Q1, OPA4171-Q1 www.ti.com SBOS556B – JUNE 2011 – REVISED DECEMBER 2014 6.2 ESD Ratings VALUE UNIT OPA171-Q1 IN DBV PACKAGE V(ESD) Electrostatic discharge Human body model (HBM), per AEC Q100-002 (1) ±4000 Charged device model (CDM), per AEC Q100-011 ±500 V OPA2171-Q1 IN D PACKAGE AND OPA4171-Q1 IN D AND PW PACKAGES V(ESD) (1) Electrostatic discharge Human body model (HBM), per AEC Q100-002 (1) ±2000 Charged device model (CDM), per AEC Q100-011 ±1000 V AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN Supply voltage (V+ – V–) Specified temperature NOM MAX UNIT 4.5 (±2.25) 36 (±18) V –40 125 °C 6.4 Thermal Information — OPA171-Q1 and OPA2171-Q1 OPA171-Q1 THERMAL METRIC (1) OPA2171-Q1 DBV D 5 PINS 8 PINS RθJA Junction-to-ambient thermal resistance 277.3 116.1 RθJC(top) Junction-to-case(top) thermal resistance 193.3 69.8 RθJB Junction-to-board thermal resistance 121.2 56.6 ψJT Junction-to-top characterization parameter 51.8 22.5 ψJB Junction-to-board characterization parameter 109.5 56.1 (1) UNIT °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. 6.5 Thermal Information — OPA4171-Q1 OPA4171-Q1 THERMAL METRIC (1) D PW 14 PINS 14 PINS RθJA Junction-to-ambient thermal resistance 93.2 106.9 RθJC(top) Junction-to-case(top) thermal resistance 51.8 24.4 RθJB Junction-to-board thermal resistance 49.4 59.3 ψJT Junction-to-top characterization parameter 13.5 0.6 ψJB Junction-to-board characterization parameter 42.2 54.3 (1) UNIT °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. 6.6 Electrical Characteristics At TA = 25°C, VS = 2.7 to 36 V, VCM = VOUT = VS / 2, and RLOAD = 10 kΩ connected to VS / 2, unless otherwise noted. The specified temperature range is TA = –40°C to 125°C. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 0.25 ±1.8 mV 0.3 ±2 mV 0.3 (1) µV/°C ±3 µV/V OFFSET VOLTAGE VOS Input offset voltage Input offset voltage over temperature dVOS/dT Input offset voltage drift (over temperature) PSRR Input offset voltage over temperature vs power supply VS = 4 to 36 V 1 Channel separation, DC (1) ±2 5 µV/V Not production tested. Copyright © 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: OPA171-Q1 OPA2171-Q1 OPA4171-Q1 5 OPA171-Q1, OPA2171-Q1, OPA4171-Q1 SBOS556B – JUNE 2011 – REVISED DECEMBER 2014 www.ti.com Electrical Characteristics (continued) At TA = 25°C, VS = 2.7 to 36 V, VCM = VOUT = VS / 2, and RLOAD = 10 kΩ connected to VS / 2, unless otherwise noted. The specified temperature range is TA = –40°C to 125°C. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ±15 pA ±3.5 nA INPUT BIAS CURRENT IB Input bias current ±8 Input bias current over temperature IOS Input offset current ±4 pA Input offset current over temperature ±3.5 nA NOISE Input voltage noise en f = 0.1 Hz to 10 Hz Input voltage noise density 3 µVPP f = 100 Hz 25 nV/√Hz f = 1 kHz 14 nV/√Hz INPUT VOLTAGE Common-mode voltage range (2) VCM (V–) – 0.1 Common-mode rejection ratio (over temperature) CMRR (V+) – 2 V VS = ±2 V, (V–) – 0.1 V < VCM < (V+) – 2 V 90 104 dB VS = ±18 V, (V–) – 0.1 V < VCM < (V+) – 2 V 104 120 dB INPUT IMPEDANCE Differential Common-mode 100 || 3 MΩ || pF 6 || 3 1012Ω || pF 130 dB 3.0 MHz 1.5 V/µs OPEN-LOOP GAIN Open-loop voltage gain (over temperature) AOL VS = +4V to +36V, (V–) + 0.35V < VO < (V+) – 0.35V 110 FREQUENCY RESPONSE GBP Gain bandwidth product SR Slew rate G=1 To 0.1%, VS = ±18 V, G = 1, 10-V step tS Settling time To 0.01% (12 bit), VS = ±18 V, G = 1, 10-V step Overload recovery time V±IN × Gain > VS Total harmonic distortion + noise G = 1, f = 1 kHz, VO = 3 VRMS VO Voltage output swing from rail (over temperature) RL = 10 kΩ, AOL ≥ 110 dB ISC Short-circuit current CLOAD Capacitive load drive RO Open-loop output resistance THD+N 6 µs 10 µs 2 µs 0.0002% OUTPUT (V–) + 0.35 Sourcing (V+) – 0.35 25 Sinking mA –35 See the Typical Characteristics section f = 1 MHz, IO = 0 A V pF Ω 150 POWER SUPPLY VS Specified voltage range IQ Quiescent current per amplifier IO = 0 A 2.7 Quiescent current per amplifier (over temperature) IO = 0 A 475 36 V 595 µA 650 µA TEMPERATURE (2) 6 Specified range –40 125 °C Operating range –55 150 °C The input range can be extended beyond (V+) – 2 V up to V+. See the and Detailed Description sections for additional information. Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated Product Folder Links: OPA171-Q1 OPA2171-Q1 OPA4171-Q1 OPA171-Q1, OPA2171-Q1, OPA4171-Q1 www.ti.com SBOS556B – JUNE 2011 – REVISED DECEMBER 2014 6.7 Typical Characteristics VS = ±18V, VCM = VS/2, RLOAD = 10kΩ connected to VS/2, and CL = 100pF, unless otherwise noted. Table 1. Characteristic Performance Measurements DESCRIPTION FIGURE Offset Voltage Production Distribution Figure 1 Offset Voltage Drift Distribution Figure 2 Offset Voltage vs Temperature Figure 3 Offset Voltage vs Common-Mode Voltage Figure 4 Offset Voltage vs Common-Mode Voltage (Upper Stage) Figure 5 Offset Voltage vs Power Supply Figure 6 IB and IOS vs Common-Mode Voltage Figure 7 Input Bias Current vs Temperature Figure 8 Output Voltage Swing vs Output Current (Maximum Supply) Figure 9 CMRR and PSRR vs Frequency (Referred-to Input) Figure 10 CMRR vs Temperature Figure 11 PSRR vs Temperature Figure 12 0.1Hz to 10Hz Noise Figure 13 Input Voltage Noise Spectral Density vs Frequency Figure 14 THD+N Ratio vs Frequency Figure 15 THD+N vs Output Amplitude Figure 16 Quiescent Current vs Temperature Figure 17 Quiescent Current vs Supply Voltage Figure 18 Open-Loop Gain and Phase vs Frequency Figure 19 Closed-Loop Gain vs Frequency Figure 20 Open-Loop Gain vs Temperature Figure 21 Open-Loop Output Impedance vs Frequency Figure 22 Small-Signal Overshoot vs Capacitive Load (100-mV Output Step) Figure 23, Figure 24 No Phase Reversal Figure 25 Positive Overload Recovery Figure 26 Negative Overload Recovery Figure 27 Small-Signal Step Response (100 mV) Figure 28, Figure 29 Large-Signal Step Response Figure 30, Figure 31 Large-Signal Settling Time (10-V Positive Step) Figure 32 Large-Signal Settling Time (10-V Negative Step) Figure 33 Short-Circuit Current vs Temperature Figure 34 Maximum Output Voltage vs Frequency Figure 35 Channel Separation vs Frequency Figure 36 Copyright © 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: OPA171-Q1 OPA2171-Q1 OPA4171-Q1 7 OPA171-Q1, OPA2171-Q1, OPA4171-Q1 SBOS556B – JUNE 2011 – REVISED DECEMBER 2014 25 Distribution Taken From 3500 Amplifiers 14 Percentage of Amplifiers (%) Percentage of Amplifiers (%) 16 www.ti.com 12 10 8 6 4 2 0 Distribution Taken From 110 Amplifiers 20 15 10 5 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2 -1200 -1100 -1000 -900 -800 -700 -600 -500 -400 -300 -200 -100 0 100 200 300 400 500 600 700 800 900 1000 1100 1200 0 Offset Voltage Drift (mV/°C) Offset Voltage (mV) Figure 2. Offset Voltage Drift Distribution Figure 1. Offset Voltage Production Distribution 1000 600 5 Typical Units Shown 10 Typical Units Shown 800 400 400 VOS (mV) Offset Voltage (mV) 600 200 0 -200 200 0 -200 -400 -400 -600 -600 -800 -800 VCM = -18.1V -1000 -75 -50 -25 0 25 50 75 100 125 150 -20 -15 -10 0 -5 Figure 3. Offset Voltage vs Temperature 10000 5 10 15 20 VCM (V) Temperature (°C) Figure 4. Offset Voltage vs Common-mode Voltage 350 10 Typical Units Shown 8000 VSUPPLY = ±1.35V to ±18V 10 Typical Units Shown 250 6000 150 2000 VOS (mV) VOS (mV) 4000 0 -2000 -4000 Normal Operation -250 -8000 -10000 15.5 -50 -150 VCM = +18.1V -6000 50 -350 16 16.5 17 17.5 18 18.5 0 2 4 6 VCM (V) Figure 5. Offset Voltage vs Common-mode Voltage (Upper Stage) 8 Submit Documentation Feedback 8 10 12 14 16 18 20 VSUPPLY (V) Figure 6. Offset Voltage vs Power Supply Copyright © 2011–2014, Texas Instruments Incorporated Product Folder Links: OPA171-Q1 OPA2171-Q1 OPA4171-Q1 OPA171-Q1, OPA2171-Q1, OPA4171-Q1 SBOS556B – JUNE 2011 – REVISED DECEMBER 2014 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 10000 IB+ -IB +IB -IOS VCM = -18.1V IB- 1000 Input Bias Current (pA) IB and IOS (pA) www.ti.com IB IOS 100 10 IOS 1 VCM = 16V 0 -20 -18 -12 0 -6 6 12 18 20 -75 -50 0 -25 VCM (V) Figure 7. IB and IOS vs Common-Mode Voltage 75 100 125 150 Figure 8. Input Bias Current vs Temperature Common-Mode Rejection Ratio (dB), Power-Supply Rejection Ratio (dB) 17 Output Voltage (V) 50 140 18 16 15 14.5 -14.5 -15 -40°C +25°C +85°C +125°C -16 -17 120 100 80 60 40 +PSRR -PSRR CMRR 20 0 -18 0 2 4 6 8 10 12 14 1 16 10 100 1k 10k 100k 1M 10M Frequency (Hz) Output Current (mA) Figure 9. Output Voltage Swing vs Output Current (Maximum Supply) Figure 10. CMRR and PSRR vs Frequency (Referred-to Input) 30 3 Power-Supply Rejection Ratio (mV/V) Common-Mode Rejection Ratio (mV/V) 25 Temperature (°C) 20 10 0 -10 VS = 2.7V -20 VS = 4V VS = 36V -30 2 1 0 -1 -2 VS = 2.7V to 36V VS = 4V to 36V -3 -75 -50 -25 0 25 50 75 100 125 150 -75 -50 -25 0 25 50 75 100 Temperature (°C) Temperature (°C) Figure 11. CMRR vs Temperature Figure 12. PSRR vs Temperature Copyright © 2011–2014, Texas Instruments Incorporated 125 150 Submit Documentation Feedback Product Folder Links: OPA171-Q1 OPA2171-Q1 OPA4171-Q1 9 OPA171-Q1, OPA2171-Q1, OPA4171-Q1 SBOS556B – JUNE 2011 – REVISED DECEMBER 2014 www.ti.com 1mV/div Voltage Noise Density (nV/ÖHz) 1000 100 10 1 Time (1s/div) 1 10 100 1k 10k 100k 1M Frequency (Hz) Figure 13. 0.1- to 10-Hz Noise Figure 14. Input Voltage Noise Spectral Density vs Frequency -120 0.0001 G = +1, RL = 10kW G = -1, RL = 2kW 0.00001 10 100 1k 10k -140 20k Total Harmonic Distortion + Noise (%) Total Harmonic Distortion + Noise (%) -100 0.001 0.1 BW = 80kHz 0.01 -100 0.001 -120 0.0001 G = +1, RL = 10kW G = -1, RL = 2kW 0.00001 0.01 -140 0.1 1 10 20 Output Amplitude (VRMS) Frequency (Hz) Figure 15. THD+N Ratio vs Frequency Figure 16. THD+N vs Output Amplitude 0.65 0.6 0.6 0.55 0.5 IQ (mA) 0.55 IQ (mA) -80 Total Harmonic Distortion + Noise (dB) -80 VOUT = 3VRMS BW = 80kHz Total Harmonic Distortion + Noise (dB) 0.01 0.5 0.45 0.45 0.4 0.35 0.4 0.3 0.35 0.25 Specified Supply-Voltage Range -75 -50 -25 0 25 50 75 100 125 Temperature (°C) Figure 17. Quiescent Current vs Temperature 10 Submit Documentation Feedback 150 0 4 8 12 16 20 24 28 32 36 Supply Voltage (V) Figure 18. Quiescent Current vs Supply Voltage Copyright © 2011–2014, Texas Instruments Incorporated Product Folder Links: OPA171-Q1 OPA2171-Q1 OPA4171-Q1 OPA171-Q1, OPA2171-Q1, OPA4171-Q1 www.ti.com SBOS556B – JUNE 2011 – REVISED DECEMBER 2014 180 180 25 Gain 20 135 135 15 Phase 45 45 Gain (dB) 90 Phase (°) Gain (dB) 10 90 5 0 -5 -10 0 0 G = 10 G=1 G = -1 -15 -45 10M -45 1 10 100 1k 10k 100k 1M -20 10k 100k 1M Figure 19. Open-Loop Gain and Phase vs Frequency 3 Figure 20. Closed-Loop Gain vs Frequency 5 Typical Units Shown VS = 2.7V VS = 4V VS = 36V 100k 10k ZO (W) 2 1.5 1 1k 100 10 0.5 1 0 1m -75 -50 -25 0 25 50 75 100 150 125 1 10 100 Temperature (°C) 10k 100k 1M 10M Figure 22. Open-Loop Output Impedance vs Frequency 50 RL = 10kW ROUT = 0W 40 40 ROUT = 25W 35 35 ROUT = 50W 30 25 20 15 ROUT = 0W 10 ROUT = 25W 5 ROUT = 50W G = +1 +18V Overshoot (%) 45 45 1k Frequency (Hz) Figure 21. Open-Loop Gain vs Temperature 50 Overshoot (%) 100M 1M 2.5 AOL (mV/V) 10M Frequency (Hz) Frequency (Hz) 30 25 20 RI = 10kW 15 ROUT -18V RF = 10kW G = -1 +18V OPA171 RL CL 10 ROUT OPA171 CL 5 -18V 0 0 0 100 200 300 400 500 600 700 800 900 1000 0 100 200 300 400 500 600 700 800 900 1000 Capacitive Load (pF) Capacitive Load (pF) Figure 23. Small-Signal Overshoot vs Capacitive Load (100mV Output Step) Figure 24. Small-Signal Overshoot vs Capacitive Load (100mV Output Step) Copyright © 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: OPA171-Q1 OPA2171-Q1 OPA4171-Q1 11 OPA171-Q1, OPA2171-Q1, OPA4171-Q1 SBOS556B – JUNE 2011 – REVISED DECEMBER 2014 www.ti.com +18V Output VOUT OPA171 VIN 5V/div 5V/div -18V 37VPP Sine Wave (±18.5V) 20kW +18V 2kW OPA171 Output VOUT VIN -18V G = -10 Time (5ms/div) Time (100ms/div) Figure 25. No Phase Reversal Figure 26. Positive Overload Recovery RL = 10kW CL = 100pF +18V OPA171 RL CL 20mV/div -18V VIN 5V/div G = +1 20kW +18V 2kW OPA171 VOUT VIN VOUT -18V G = -10 Time (1ms/div) Time (5ms/div) Figure 27. Negative Overload Recovery Figure 28. Small-Signal Step Response (100 mV) G = +1 RL = 10kW CL = 100pF RI = 2kW RF = 2kW 2V/div 20mV/div CL = 100pF +18V OPA171 CL -18V G = -1 Time (20ms/div) Figure 29. Small-Signal Step Response (100 mV) Time (5ms/div) Figure 30. Large-Signal Step Response 12 Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated Product Folder Links: OPA171-Q1 OPA2171-Q1 OPA4171-Q1 OPA171-Q1, OPA2171-Q1, OPA4171-Q1 www.ti.com SBOS556B – JUNE 2011 – REVISED DECEMBER 2014 10 G = -1 RL = 10kW CL = 100pF G = -1 2V/div D From Final Value (mV) 8 6 4 12-Bit Settling 2 0 -2 (±1/2LSB = ±0.024%) -4 -6 -8 -10 Time (4ms/div) 0 4 8 12 16 20 24 28 32 36 Time (ms) Figure 31. Large-Signal Step Response Figure 32. Large-Signal Settling Time (10-V Positive Step) 10 45 ISC, Sink 40 6 4 35 12-Bit Settling 2 ISC (mA) D From Final Value (mV) 50 G = -1 8 0 -2 (±1/2LSB = ±0.024%) 30 25 20 -4 15 -6 10 -8 5 ISC, Source 0 -10 0 4 8 12 16 20 24 28 32 36 -75 -50 -25 Time (ms) 0 25 50 75 100 125 150 Temperature (°C) Figure 33. Large-Signal Settling Time (10-V Negative Step) Figure 34. Short-Circuit Current vs Temperature 15 -60 VS = ±15V 10 Channel Separation (dB) Output Voltage (VPP) 12.5 Maximum output voltage without slew-rate induced distortion. 7.5 VS = ±5V 5 2.5 -70 -80 -90 -100 -110 VS = ±1.35V 0 -120 10k 100k 1M 10M 10 100 1k Frequency (Hz) Figure 35. Maximum Output Voltage vs Frequency Copyright © 2011–2014, Texas Instruments Incorporated 10k 100k Frequency (Hz) Figure 36. Channel Separation vs Frequency Submit Documentation Feedback Product Folder Links: OPA171-Q1 OPA2171-Q1 OPA4171-Q1 13 OPA171-Q1, OPA2171-Q1, OPA4171-Q1 SBOS556B – JUNE 2011 – REVISED DECEMBER 2014 www.ti.com 7 Detailed Description 7.1 Overview The OPAx171-Q1 family of operational amplifiers provide high overall performance, making them ideal for many general-purpose applications. The excellent offset drift of only 1.5 μV/°C (maximum) provides excellent stability over the entire temperature range. In addition, the device offers very good overall performance with high CMRR, PSRR, AOL, and superior THD. 7.2 Functional Block Diagram OPA171-Q1 + PCH FF Stage ± Ca Cb +IN + + PCH Input Stage ±IN ± + 2 ± nd Output Stage Stage OUT ± + NCH Input Stage ± 7.3 Feature Description 7.3.1 Operating Characteristics The OPAx171-Q1 family of devices is specified for operation from 2.7 to 36 V (±1.35 to ±18 V). Many of the specifications apply from –40°C to 125°C. Parameters that can exhibit significant variance with regard to operating voltage or temperature are shown in the section. 7.3.2 Phase-Reversal Protection The OPAx171-Q1 family of devices has an internal phase-reversal protection. Many op amps exhibit a phase reversal when the input is driven beyond its linear common-mode range. This condition is most often encountered in noninverting circuits when the input is driven beyond the specified common-mode voltage range, causing the output to reverse into the opposite rail. The input of the OPAx171 family of devices prevents phase reversal with excessive common-mode voltage. Instead, the output limits into the appropriate rail. Figure 37 shows this performance. 14 Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated Product Folder Links: OPA171-Q1 OPA2171-Q1 OPA4171-Q1 OPA171-Q1, OPA2171-Q1, OPA4171-Q1 www.ti.com SBOS556B – JUNE 2011 – REVISED DECEMBER 2014 Feature Description (continued) +18V Output OPA171 5V/div -18V 37VPP Sine Wave (±18.5V) Output Time (100ms/div) Figure 37. No Phase Reversal 7.3.3 Capacitive Load and Stability The dynamic characteristics of the OPAx171-Q1 family of devices have been optimized for commonly encountered operating conditions. The combination of low closed-loop gain and high capacitive loads decreases the phase margin of the amplifier and can lead to gain peaking or oscillations. As a result, heavier capacitive loads must be isolated from the output. The simplest way to achieve this isolation is to add a small resistor (for example, ROUT equal to 50 Ω) in series with the output. Figure 38 and Figure 39 show small-signal overshoot versus capacitive load for several values of ROUT. Also, for details of analysis techniques and application circuits, refer to the Applications Bulletin AB-028 (SBOA015), available for download from TI.com. 50 45 ROUT = 0W 40 40 ROUT = 25W 35 35 ROUT = 50W 30 25 20 15 ROUT = 0W 10 ROUT = 25W 5 ROUT = 50W G = +1 +18V Overshoot (%) Overshoot (%) 50 RL = 10kW 45 30 25 20 RI = 10kW 15 ROUT -18V RF = 10kW G = -1 +18V OPA171 RL CL 10 ROUT OPA171 CL 5 -18V 0 0 0 100 200 300 400 500 600 700 800 900 1000 0 100 200 300 400 500 600 700 800 900 1000 Capacitive Load (pF) Capacitive Load (pF) Figure 38. Small-Signal Overshoot versus Capacitive Load (100-mV Output Step) Figure 39. Small-Signal Overshoot versus Capacitive Load (100-mV Output Step) Copyright © 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: OPA171-Q1 OPA2171-Q1 OPA4171-Q1 15 OPA171-Q1, OPA2171-Q1, OPA4171-Q1 SBOS556B – JUNE 2011 – REVISED DECEMBER 2014 www.ti.com 7.4 Device Functional Modes 7.4.1 Common-Mode Voltage Range The input common-mode voltage range of the OPAx171 family of devices extends 100 mV below the negative rail and within 2 V of the top rail for normal operation. This device can operate with full rail-to-rail input 100 mV beyond the top rail, but with reduced performance within 2 V of the top rail. The typical performance in this range is summarized in Table 2. Table 2. Typical Performance Range PARAMETER MIN Input Common-Mode Voltage TYP (V+) – 2 Offset voltage vs Temperature Common-mode rejection MAX UNIT (V+) + 0.1 V 7 mV 12 µV/°C 65 dB Open-loop gain 60 dB GBW 0.7 MHz Slew rate 0.7 V/µs Noise at f = 1kHz 30 nV/√Hz 16 Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated Product Folder Links: OPA171-Q1 OPA2171-Q1 OPA4171-Q1 OPA171-Q1, OPA2171-Q1, OPA4171-Q1 www.ti.com SBOS556B – JUNE 2011 – REVISED DECEMBER 2014 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The OPAx171-Q1 operational amplifier provides high overall performance, making it ideal for many generalpurpose applications. The excellent offset drift of only 2 µV/°C provides excellent stability over the entire temperature range. In addition, the device offers very-good overall performance with high CMRR, PSRR, and AOL. As with all amplifiers, applications with noisy or high-impedance power supplies require decoupling capacitors close to the device pins. In most cases, 0.1-µF capacitors are adequate. 8.1.1 Electrical Overstress Designers often ask questions about the capability of an op amp to withstand electrical overstress. These questions tend to focus on the device inputs, but may involve the supply voltage pins or even the output pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin. Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them from accidental ESD events both before and during product assembly. These ESD protection diodes also provide in-circuit, input overdrive protection, as long as the current is limited to 10 mA as stated in the Absolute Maximum Ratings table. Figure 40 shows how a series input resistor can be added to the driven input to limit the input current. The added resistor contributes thermal noise at the amplifier input and its value should be kept to a minimum in noise-sensitive applications. V+ IOVERLOAD 10mA max OPA171 VOUT VIN 5kW Figure 40. Input Current Protection An ESD event produces a short duration, high-voltage pulse that is transformed into a short duration, highcurrent pulse as it discharges through a semiconductor device. The ESD protection circuits are designed to provide a current path around the operational amplifier core to prevent it from being damaged. The energy absorbed by the protection circuitry is then dissipated as heat. When the operational amplifier connects into a circuit, the ESD protection components are intended to remain inactive and not become involved in the application circuit operation. However, circumstances may arise where an applied voltage exceeds the operating voltage range of a given pin. Should this condition occur, there is a risk that some of the internal ESD protection circuits may be biased on, and conduct current. Any such current flow occurs through ESD cells and rarely involves the absorption device. If the ability of the supply to absorb this current is uncertain, external zener diodes may be added to the supply pins. The zener voltage must be selected such that the diode does not turn on during normal operation. However, the zener voltage should be low enough so that the zener diode conducts if the supply pin begins to rise above the safe operating supply voltage level. Copyright © 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: OPA171-Q1 OPA2171-Q1 OPA4171-Q1 17 OPA171-Q1, OPA2171-Q1, OPA4171-Q1 SBOS556B – JUNE 2011 – REVISED DECEMBER 2014 www.ti.com 8.2 Typical Application 8.2.1 Capacitive Load Drive Solution Using an Isolation Resistor The OPA171-Q1 device can be used capacitive loads such as cable shields, reference buffers, MOSFET gates, and diodes. The circuit uses an isolation resistor (RISO) to stabilize the output of an op amp. RISO modifies the open loop gain of the system to ensure the circuit has sufficient phase margin. +VS VOUT RISO + VIN + ± CLOAD -VS Figure 41. Unity-Gain Buffer with RISO Stability Compensation 8.2.1.1 Design Requirements The design requirements are: • Supply voltage: 30 V (±15 V) • Capacitive loads: 100 pF, 1000 pF, 0.01 μF, 0.1 μF, and 1 μF • Phase margin: 45° and 60° 8.2.1.2 Detailed Design Procedure shows a unity-gain buffer driving a capacitive load. Equation 1 shows the transfer function for the circuit in . Not shown in is the open-loop output resistance of the op amp, Ro. 1 + CLOAD × RISO × s T(s) = 1 + Ro + RISO × CLOAD × s (1) The transfer function in Equation 1 has a pole and a zero. The frequency of the pole (fp) is determined by (Ro + RISO) and CLOAD. Components RISO and CLOAD determine the frequency of the zero (fz). A stable system is obtained by selecting RISO such that the rate of closure (ROC) between the open-loop gain (AOL) and 1/β is 20 dB/decade. Figure 42 depicts the concept. The 1/β curve for a unity-gain buffer is 0 dB. 18 Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated Product Folder Links: OPA171-Q1 OPA2171-Q1 OPA4171-Q1 OPA171-Q1, OPA2171-Q1, OPA4171-Q1 www.ti.com SBOS556B – JUNE 2011 – REVISED DECEMBER 2014 Typical Application (continued) 120 AOL 100 1 fp 2 u u RISO R o Gain (dB) 80 60 u CLOAD 40 dB 1 fz 2 u u RISO u CLOAD 40 1 dec 1/ 20 ROC 20 dB dec 0 10 100 1k 10k 100k 10M 1M 100M Frequency (Hz) Figure 42. Unity-Gain Amplifier with RISO Compensation ROC stability analysis is typically simulated. The validity of the analysis depends on multiple factors, especially the accurate modeling of Ro. In addition to simulating the ROC, a robust stability analysis includes a measurement of overshoot percentage and AC gain peaking of the circuit using a function generator, oscilloscope, and gain and phase analyzer. Phase margin is then calculated from these measurements. shows the overshoot percentage and AC gain peaking that correspond to phase margins of 45° and 60°. For more details on this design and other alternative devices that can be used in place of the OPA171, refer to the Precision Design, Capacitive Load Drive Solution using an Isolation Resistor (TIPD128). Table 3. Phase Margin versus Overshoot and AC Gain Peaking PHASE MARGIN OVERSHOOT AC GAIN PEAKING 45° 23.3% 2.35 dB 60° 8.8% 0.28 dB 8.2.1.3 Application Curves The OPA171-Q1 device meets the supply voltage requirements of 30 V. The OPA171-Q1 device was tested for various capacitive loads and RISO was adjusted to achieve an overshoot corresponding to . shows the test results. 10000 Isolation Resistor, RISO (:) 45q Phase Margin 60q Phase Margin 1000 100 10 1 0.01 0.1 1 10 Capacitive Load (nF) 100 1000 D001 Figure 43. RISO vs CLOAD Copyright © 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: OPA171-Q1 OPA2171-Q1 OPA4171-Q1 19 OPA171-Q1, OPA2171-Q1, OPA4171-Q1 SBOS556B – JUNE 2011 – REVISED DECEMBER 2014 www.ti.com 9 Power Supply Recommendations The OPAx171-Q1 family of devices is specified for operation from 4.5 V to 36 V (±2.25 V to ±18 V); many specifications apply from –40°C to 125°C. Parameters that can exhibit significant variance with regard to operating voltage or temperature are presented in the Typical Characteristics section. CAUTION Supply voltages larger than 40 V can permanently damage the device; see the Absolute Maximum Ratings table. Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or highimpedance power supplies. For detailed information on bypass capacitor placement, see the Layout section. 10 Layout 10.1 Layout Guidelines For best operational performance of the device, use good printed circuit board (PCB) layout practices, including: • Noise can propagate into analog circuitry through the power pins of the circuit as a whole and op amp itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources local to the analog circuitry. – Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as close to the device as possible. A single bypass capacitor from V+ to ground is applicable for singlesupply applications. • Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes. A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital and analog grounds paying attention to the flow of the ground current. See Circuit Board Layout Techniques, SLOA089, for detailed information. • In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If it is not possible to keep them separate, it is much better to cross the sensitive trace perpendicular as opposed to in parallel with the noisy trace. • Place the external components as close to the device as possible. As shown in Figure 44, keeping RF and RG close to the inverting input minimizes parasitic capacitance. • Keep the length of input traces as short as possible. Always remember that the input traces are the most sensitive part of the circuit. • Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce leakage currents from nearby traces that are at different potentials. 20 Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated Product Folder Links: OPA171-Q1 OPA2171-Q1 OPA4171-Q1 OPA171-Q1, OPA2171-Q1, OPA4171-Q1 www.ti.com SBOS556B – JUNE 2011 – REVISED DECEMBER 2014 10.2 Layout Example RIN + VIN VOUT RG RF (Schematic Representation) Place components close to device and to each other to reduce parasitic errors Run the input traces as far away from the supply lines as possible VS+ RF NC NC ±IN V+ +IN OUT V± NC RG GND VIN GND RIN Only needed for dual-supply operation GND VS± (or GND for single supply) Use low-ESR, ceramic bypass capacitor VOUT Ground (GND) plane on another layer Figure 44. Operational Amplifier Board Layout for Noninverting Configuration 11 Device and Documentation Support 11.1 Documentation Support 11.1.1 Related Documentation For related documentation see the following: • Applications Bulletin AB-028, SBOA015 • Capacitive Load Drive Solution using an Isolation Resistor, TIDU032 • Circuit Board Layout Techniques, SLOA089 11.2 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 4. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY OPA171-Q1 Click here Click here Click here Click here Click here OPA2171-Q1 Click here Click here Click here Click here Click here OPA4171-Q1 Click here Click here Click here Click here Click here 11.3 Trademarks All trademarks are the property of their respective owners. Copyright © 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: OPA171-Q1 OPA2171-Q1 OPA4171-Q1 21 OPA171-Q1, OPA2171-Q1, OPA4171-Q1 SBOS556B – JUNE 2011 – REVISED DECEMBER 2014 www.ti.com 11.4 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.5 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 22 Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated Product Folder Links: OPA171-Q1 OPA2171-Q1 OPA4171-Q1 PACKAGE OPTION ADDENDUM www.ti.com 14-Nov-2015 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) OPA171AQDBVRQ1 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 OULQ OPA2171AQDGKRQ1 PREVIEW VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAUAG Level-2-260C-1 YEAR -40 to 125 2171 OPA2171AQDRQ1 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 2171AQ OPA4171AQDRQ1 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 OPA4171Q1 OPA4171AQPWRQ1 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 O4171Q1 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 14-Nov-2015 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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OTHER QUALIFIED VERSIONS OF OPA171-Q1, OPA2171-Q1, OPA4171-Q1 : • Catalog: OPA171, OPA2171, OPA4171 • Enhanced Product: OPA2171-EP NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product • Enhanced Product - Supports Defense, Aerospace and Medical Applications Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 18-Feb-2015 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) OPA171AQDBVRQ1 SOT-23 DBV 5 3000 180.0 8.4 OPA2171AQDRQ1 SOIC D 8 2500 330.0 OPA4171AQDRQ1 SOIC D 14 2500 330.0 OPA4171AQPWRQ1 TSSOP PW 14 2000 330.0 3.23 3.17 1.37 4.0 8.0 Q3 12.4 6.4 5.2 2.1 8.0 12.0 Q1 16.4 6.5 9.0 2.1 8.0 16.0 Q1 12.4 6.9 5.6 1.6 8.0 12.0 Q1 Pack Materials-Page 1 W Pin1 (mm) Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 18-Feb-2015 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) OPA171AQDBVRQ1 SOT-23 DBV 5 3000 202.0 201.0 28.0 OPA2171AQDRQ1 SOIC D 8 2500 367.0 367.0 35.0 OPA4171AQDRQ1 SOIC D 14 2500 367.0 367.0 38.0 OPA4171AQPWRQ1 TSSOP PW 14 2000 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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