TI1 LP3923TL-VB/NOPB Cellular phone power management unit Datasheet

LP3923
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SNVS567B – APRIL 2010 – REVISED MAY 2013
LP3923 Cellular Phone Power Management Unit
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FEATURES
KEY SPECIFICATIONS
•
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1
2
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Integrated Li-Ion Battery Charger with Power
FET, Thermal Regulation and 28V OVP
Six Low-Noise LDOs, Two LILO LDOs
– 3 x 300 mA
– 4 x 150 mA
– 1 x 80 mA
One High Efficiency Synchronous Magnetic
Buck Regulators, IOUT 700 mA
– High Efficiency PFM Mode @low IOUT
– Auto Mode PFM/PWM Switch
– Low Inductance 2.2 µH @ 2 MHz Clock
I2C-compatible Interface for Controlling LDO
Outputs and Charger Operation
Thermal Shutdown with Early Warning Alarm
Under-Voltage Lockout
30-bump 3.0 x 2.5 mm DSBGA Package
APPLICATIONS
•
50 mA to 1200 mA Charging Current
3.0V to 5.5V Input Voltage Range
135 mV typ. Dropout Voltage @ 300 mA LDOs
2% (typ.) Output Voltage accuracy on LDOs
700 mA (typ.) Buck Regulator
DESCRIPTION
The LP3923 is a fully Integrated Power Management
Unit (PMU) designed for CDMA cellular phones.
The LP3923 PMU contains a fully integrated Li-Ion
battery charger with power FET and over-voltageprotection (OVP), one Buck regulator, 8 low-noise
low-dropout (LDO) voltage regulators, and a highspeed serial interface to program on/off conditions
and output voltages of individual regulators, and to
read status information of the PMU. Two LILO (lowinput, low-output) type LDOs with separate power
input provide an application option for pre-regulated
high efficient power management for longer battery
life.
Cellular Handsets
System Diagram
AC Adapter/
USB
I/O
Interface
of
Baseband
Processor
Li - Ion Charger
+
-
Ichg
Monitor
Buck
BB Processor
Power Domains
Serial
Interface
8 x LDO
Memory
Control
RF
Peripheral
Devices
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010–2013, Texas Instruments Incorporated
LP3923
SNVS567B – APRIL 2010 – REVISED MAY 2013
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DESCRIPTION (CONTINUED)
The Li-Ion charger can safely charge and maintain a single cell Li-Ion battery operating from an AC adapter. The
charger integrates a power FET, a reverse current blocking diode, a sense resistor with current monitor output,
and requires only a few external components. Charging is thermally regulated to obtain the most efficient
charging rate for a given ambient temperature.
A built-in Over-Voltage Protection (OVP) circuit at the charger inputs protects the PMU from input voltages up to
+28V, eliminating the need for any external protection circuitry.
Buck regulator has an automatic switch to PFM mode at low load conditions providing very good efficiency at low
output currents. An external divider circuitry provides user defined buck output voltage.
A-type LDO regulators provide excellent PSRR and very low noise, 10 µV typ., ideally suited for supplying
voltage to RF and other analog sections.
2
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Typical Application Diagram
-
CHG_IN
AC Adapter or USB
VIN1
+
10 µF
VIN2
VBATT
10 µF
28V OVP & Rev.
Current Blocking
CORE
1.8V/3.0V
@300 mA
LDO1
LDO1
LILO
1 µF
1 µF
LDO3
ACOK_N
LDO2
LILO
IMON
1 µF
Charger
R3
LDO3
C3
LDO3
FLASH
1.8V/3.0V
@300 mA
LDO2
LDO3
D-type
VBATT
1 µF
DIGI
3.0V
@300 mA
SEL
1.5k
LDO3
1.5k
TCXO_EN
SDA
LDO4
SCL
Serial Interface
&
Control
PON_N
LDO4
A-type
TCXO
3.0V
@80 mA
1 µF
RX_EN
PS_HOLD
LDO5
RESET_N
VBATT
LDO5
A-type
PWR_ON
1 µF
RX
3.0V
@150 mA
HF_PWR
BUCK/CORE
0.8V...2.5V
@700 mA
500k
500k
TX_EN
LDO6
LDO6
A-type
SW
1 µF
TX
3.0V
@150 mA
2.2 µH
C1
R1
FB
Buck
10 µF
C2
R2
LP3923
GNDB
LDO7
LDO7
A-type
1 µF
GP
3.0V
@150 mA
Thermal
Shutdown
VBATT
LDO8
VINB
LDO8
D-type
VIBRATOR
3.0V
@150 mA
1 µF
UVLO
GND
10 µF
Voltage
Reference
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Device Pin Diagram
5
LDO7
LDO3
LDO8
GND
BATT
CHG_IN
4
VIN2
TX_EN
IMON
SDA
SCL
ACOK_N
3
LDO6
RX_EN
RESET_N
PON_N
PWR_ON
FB
2
LDO5
TCXO_EN
PS_HOLD
SEL
HF_PWR
GNDB
1
LDO4
LDO2
VIN1
LDO1
SW
VINB
A
B
C
D
E
F
Table 1. LP3923 PIN DESCRIPTIONS (1)
(1)
4
Pin Number
Name
Type
A1
LDO4
A
Description
LDO4 Output
A2
LDO5
A
LDO5 Output
A3
LDO6
A
LDO6 Output
A4
VIN2
P
Input for LDO3 -LDO8
A5
LDO7
A
LDO7 Output
B1
LDO2
A
LDO2 Output
B2
TCXO_EN
DI
Enable control input for LDO4. HIGH = Enable, LOW = Disable (SLEEP
Mode).
B3
RX_EN
DI
Enable control input for LDO5. HIGH = Enable, LOW = Disable.
B4
TX_EN
DI
Enable control input for LDO6. HIGH = Enable, LOW = Disable.
B5
LDO3
A
LDO3 Output
C1
VIN1
P
Input for LDO1 and LDO2
C2
PS_HOLD
DI
Power Supply Hold Input
C3
RESET_N
DO
Reset Output. Pin stays LOW during power up sequence
C4
IMON
A
Charging current monitor output. This pin presents an analog voltage
representation of the charging current.
C5
LDO8
A
LDO8 Output
D1
LDO1
A
LDO1 Output
D2
SEL
DI
LDO1 and LDO2 default voltage selection.
D3
PON_N
DO
State of PWR_ON inverted. Digital output referred to LDO3.
D4
SDA
DI/O
Serial Interface, Data Input/Output
Open Drain output, external pull up resistor is needed, typ. 1.5 kΩ.
D5
GND
G
IC Ground pin
E1
SW
A
Buck Output
A: Analog Pin D: Digital Pin I: Input Pin DI/O: Digital Input/Output Pin G: Ground O: Output Pin P: Power Connection
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Table 1. LP3923 PIN DESCRIPTIONS(1) (continued)
E2
HF_PWR
DI
Power up sequence starts when this pin is set HIGH. Internal 500 kΩ pulldown resistor.
E3
PWR_ON
DI
Power up sequence starts when this pin is set HIGH.
Internal 500 kΩ pull-down resistor.
E4
SCL
DI
Serial Interface Clock input.
E5
BATT
P
Main battery connection. Used both as a power connection for current
delivery to the battery and as a voltage sense connection to monitor the
battery charge level.
External pull up resistor is needed, typ. 1.5 kΩ.
F1
VINB
P
Input for Buck
F2
GNDB
G
Power Ground for Buck
F3
FB
A
Buck Feedback pin
F4
ACOK_N
DO
F5
CHG_IN
P
AC Adapter indicator, LOW when VCHG_IN is above its trip point
DC power input to charger block from AC adapter or USB
Device Description
The LP3923 Charge Management and Regulator Unit is designed to supply charger and voltage output
capabilities for mobile systems, e.g. CDMA handsets. The device provides a Li-Ion charging function and 8 or 9
regulated outputs. Communication with the device is via an I2C compatible serial interface that allows function
control and status read-back.
The battery charge management section provides a programmable CC/CV linear charge capability and end of
charging current threshold. Following a normal charge cycle a maintenance mode utilizing programmable restart
voltage levels enables the battery voltage to be maintained at the correct level. Power dissipation is thermally
regulated to obtain optimum charge levels over the ambient temperature range.
CHARGER FEATURES
• Pre-charge, CC, CV and Maintenance modes
• Integrated FET
• Integrated Reverse Current Blocking Diode
• Integrated Sense Resistor
• Thermal Regulation
• Charging Current Monitor Output
• Programmable charging current 50 mA - 1200 mA with 50 mA steps
• Default CC mode current 400 mA
• Pre-charging current fixed 50 mA
• Termination voltage 4.1V, 4.2V (default), 4.3V and 4.4V
• Restart level 50 mV, 100 mV (default), 150 mV and 200 mV below Termination voltage
• End of Charge 0.05C, 0.1C, 0.15C (default) and 0.2C
• Input voltage operating range 4.5 - 6.8V
REGULATORS
Eight low dropout linear regulators provide programmable voltage outputs with current capabilities of 80 mA, 150
mA, and 300 mA as given in the table below. LDO1 and LDO2 are supplied either by the VBATT (SEL=GND) or
by buck regulator’s output (SEL=VBATT). If the supply voltage is low (supply from buck), then LDO1 and LDO2
are going to be low-input low-output (LILO) LDOs.
Buck regulator can provide 700 mA (typ.) of current. If the buck is used for supplying LDO1 and LDO2 it won’t be
able to supply external devices. If LDO1 and LDO2 are supplied by VBATT, then buck can be used as an output
power channel for digital loading with the default output voltage value of 1.8V
Under voltage lockout oversees device start up with a preset level of 3.0V( typ.).
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Table 2. LDOs and Buck Default Voltages (for options LP3923TL/X and LP3923TL/X-VI)
Device
Type
Current
(mA)
Enable
control
Input
Output(V)
Startup
default
SEL=BATT
Buck
(1)
700
SI
VINB=BATT
Input
Output(V)
Startup
default
SEL=GND
2.0
(1)
ON
VINB=BATT
1.8 (1)
ON
LDO1
LILO
300
SI
VIN1=VBUCK
1.8
ON
VIN1=BATT
3
ON
LDO2
LILO
300
SI
VIN1=VBUCK
1.8
ON
VIN1=BATT
3
ON
LDO3
D
300
-
VIN2=BATT
3
ON
VIN2=BATT
3
ON
LDO4
A
80
TCXO_EN
VIN2=BATT
3
OFF
VIN2=BATT
3
OFF
LDO5
A
150
RX_EN
VIN2=BATT
3
OFF
VIN2=BATT
3
OFF
LDO6
A
150
TX_EN
VIN2=BATT
3
OFF
VIN2=BATT
3
OFF
LDO7
A
150
SI
VIN2=BATT
3
ON
VIN2=BATT
3
ON
LDO8
D
150
SI
VIN2=BATT
3
OFF
VIN2=BATT
3
OFF
Voltage is set by the external resistors.
Table 3. LDOs and Buck Default Voltages (for options LP3923TL/X-VB and LP3923TL/X-VC)
Device
Type
Current
(mA)
Enable
control
Input
Output(V)
Startup
default
SEL=BATT
Buck
(1)
700
SI
VINB=BATT
Input
Output(V)
Startup
default
SEL=GND
2.0
(1)
ON
VINB=BATT
1.8 (1)
ON
LDO1
LILO
300
SI
VIN1=VBUCK
1.8
ON
VIN1=BATT
3
OFF
LDO2
LILO
300
SI
VIN1=VBUCK
1.8
ON
VIN1=BATT
3
OFF
LDO3
D
300
-
VIN2=BATT
3
ON
VIN2=BATT
3
ON
LDO4
A
80
TCXO_EN
VIN2=BATT
3
OFF
VIN2=BATT
3
OFF
LDO5
A
150
RX_EN
VIN2=BATT
3
OFF
VIN2=BATT
3
OFF
LDO6
A
150
TX_EN
VIN2=BATT
3
OFF
VIN2=BATT
3
OFF
LDO7
A
150
SI
VIN2=BATT
3
ON
VIN2=BATT
3
ON
LDO8
D
150
SI
VIN2=BATT
3
OFF
VIN2=BATT
3
OFF
Voltage is set by the external resistors.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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Absolute Maximum Ratings (1) (2) (3)
CHG_IN (VBATT=2.8-5.5V)
−0.3V to +28V
VBATT=VIN1-2, BATT, HF_PWR, VINB
−0.3V to +6.0V
−0.3V to VBATT+0.3V, max 6.0V
All other inputs
Junction Temperature (TJ-MAX)
150°C
Storage Temperature
−40°C to +150°C
Max Continuous Power Dissipation (4)
PD-MAX (5)
Internally Limited
ESD (6)
BATT, VIN1, VIN2, HF_PWR, CHG_IN, PWR_ON, VINB
(1)
(2)
(3)
(4)
(5)
(6)
8 kV HBM
All voltages are with respect to the potential at the GND pin.
Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which
operation of the device is ensured. Operating Ratings do not imply specified performance limits. For specified performance limits and
associated test conditions, see the Electrical Characteristics tables.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
Care must be exercised where high power dissipation is likely. The maximum ambient temperature may have to be derated. Maximum
ambient temperature (TA-MAX) is dependant on the maximum operating junction temperature (TJ-MAX-OP), the maximum power
dissipation of the device in the application (PD-MAX), and the junction to ambient thermal resistance of the package in the application
(θJA). This relationship is given by the following equation: TA-MAX = TJ-MAX-OP - (θJA x PD-MAX)
Internal Thermal Shutdown circuitry protects the device from permanent damage.
The human-body model is 100 pF discharged through 1.5 kΩ. The machine model is a 200 pF capacitor discharged directly into each
pin, MIL-STD-883 3015.7.
Operating Ratings (1) (2)
CHG_IN (3)
4.5 to 6.8V
VBATT = VIN1-2, BATT, VINB
3.0V to 5.5V
HF_PWR, PWR_ON
0V to 5.5V
ACOK_N, SDA, SCL, RX_EN, TX_EN, TCXO_EN, PS_HOLD, RESET_N
0V to (VLDO + 0.3V)
All other pins
0V to VBATT + 0.3V)
−40°C to +125°C
Junction Temperature (TJ)
Ambient Temperature (TA) (4)
(1)
(2)
(3)
(4)
−40°C to +85°C
Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which
operation of the device is ensured. Operating Ratings do not imply specified performance limits. For specified performance limits and
associated test conditions, see the Electrical Characteristics tables.
All voltages are with respect to the potential at the GND pin.
Full charging current is ensured for CHG_IN = 4.5 to 6.8V, but particularly at higher input voltages. Increased power dissipation may
cause the thermal regulation to limit the current to a safe level, resulting in longer charging time.
All limits are specified. All electrical characteristics having room-temperature limits are tested during production with TJ = 25°C. All hot
and cold limits are ensured by correlating the electrical characteristics to process and temperature variations and applying statistical
process control.
Thermal Properties (5)
Junction-to-Ambient Thermal Resistance (θJA)
(Jedec Standard Thermal PCB)
DSBGA 30
(5)
39°C/W
Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power
dissipation exists, special care must be paid to thermal dissipation issues in board design.
General Electrical Characteristics
Unless otherwise noted, VIN (= VIN1 = VIN2 = VINB = BATT) = 3.6V, GND = 0V, CVIN1–2 = CVINB = 10 µF, CLDOx = 1 µF.
Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the
entire junction temperature range for operation, TA = TJ = −40°C to +125°C. (1)
(1)
All limits are specified. All electrical characteristics having room-temperature limits are tested during production with TJ = 25°C. All hot
and cold limits are ensured by correlating the electrical characteristics to process and temperature variations and applying statistical
process control.
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General Electrical Characteristics (continued)
Unless otherwise noted, VIN (= VIN1 = VIN2 = VINB = BATT) = 3.6V, GND = 0V, CVIN1–2 = CVINB = 10 µF, CLDOx = 1 µF.
Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the
entire junction temperature range for operation, TA = TJ = −40°C to +125°C.(1)
Symbol
Parameter
Conditions
IQ(STANDBY)
Standby Supply
Current
VIN = 3.6V, UVLO on, internal logic circuit
on, all other circuits off.
IQ(SLEEP)
Sleep Mode
Current
@ 0 load
Typ
Limit
Min
Units
Max
2
10
µA
Buck, LDO1, LDO2, LDO3 and LDO7
enabled
130
400
µA
POWER MONITOR FUNCTIONS
Battery Under-Voltage Lockout
VUVLO-R
Under Voltage
Lock-out Rising
VIN Rising
3.00
2.85
3.15
VUVLO-F
Under Voltage
Lock-out Falling
VIN Falling (LP3923-VC)
2.80
2.65
2.95
V
THERMAL SHUTDOWN
Higher Threshold
See (2)
160
°C
LOGIC AND CONTROL INPUTS
VIL
Input Low Level
VIH
Input High Level
PS_HOLD, SDA, SCL, RX_EN, TCXO_EN,
TX_EN
0.25*
VLDO3
V
PWR_ON, HF_PWR, SEL
0.25*
VBATT
V
PS_HOLD, SDA, SCL, RX_EN, TCXO_EN,
TX_EN
0.75*
VLDO3
V
PWR_ON, HF_PWR, SEL
0.75*
VBATT
V
IIL
Logic Input
Current
All logic inputs except PWR_ON, HF_PWR.
0V ≤ VINPUT ≤ VBATT
RIN
Input Resistance
PWR_ON and HF_PWR Pull-Down
resistance to GND (3)
–5
+5
µA
500
kΩ
LOGIC AND CONTROL OUTPUTS
VOL
Output Low Level PON_N, RESET_N, SDA, ACOK_N
IOUT = 2 mA
VOH
Output High
Level
(2)
(3)
PON_N, RESET_N, ACOK_N
IOUT = −2 mA
(Not applicable to Open Drain Output SDA)
0.25*
VLDO3
V
0.75*
VLDO3
V
Ensured by design.
Ensured by design.
LDO1, LDO2 (LILO) Electrical Characteristics
Unless otherwise noted, if SEL=GND, then VIN=VIN1=BATT=3.6V, if SEL=BATT, then VIN=VIN1=VBUCK, GND = 0V, CV!N1-2
= 10 µF, CLDOx= 1 µF. Note VINMIN is the greater of 3.0V or VOUT +0.5V. Typical values and limits appearing in normal type
apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, TA = TJ
= −40°C to +125°C. (1)
Symbol
VOUT
Parameter
Output Voltage Accuracy
Default Output Voltage
(1)
8
Conditions
Typical
IOUT = 1 mA, VOUT = 3.0V
SEL = GND
3.0
SEL = BATT
1.8
Limit
Min
Max
−2
+2
−3
+3
Unit
s
%
V
All limits are specified. All electrical characteristics having room-temperature limits are tested during production with TJ = 25°C. All hot
and cold limits are ensured by correlating the electrical characteristics to process and temperature variations and applying statistical
process control.
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LDO1, LDO2 (LILO) Electrical Characteristics (continued)
Unless otherwise noted, if SEL=GND, then VIN=VIN1=BATT=3.6V, if SEL=BATT, then VIN=VIN1=VBUCK, GND = 0V, CV!N1-2
= 10 µF, CLDOx= 1 µF. Note VINMIN is the greater of 3.0V or VOUT +0.5V. Typical values and limits appearing in normal type
apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, TA = TJ
= −40°C to +125°C.(1)
Symbol
Parameter
Conditions
Limit
Typical
Min
Unit
s
Max
Output Current
VINMIN ≤ VIN ≤ 5.5V
Output Current Limit
VOUT = 0V
600
VDO
Dropout Voltage
IOUT =300 mA (2) (3)
135
ΔVOUT
Line Regulation
VINMIN ≤ VIN ≤ 5.5V
IOUT = 1 mA
2
Load Regulation
1 mA ≤ IOUT ≤ 300 mA
5
PSRR
Power Supply Ripple
Rejection Ratio
F = 10 kHz, COUT = 1 µF,
VOUT = 3.0V, IOUT = 20 mA (2)
60
dB
tSTART-UP
Start-Up Time from Shutdown
COUT = 1 µF, IOUT = 300 mA (2)
35
µs
TTransient
Start-Up Transient
Overshoot
COUT = 1 µF, IOUT = 300 mA (2)
IOUT
(2)
(3)
300
mA
180
mV
mV
30
mV
Ensured by design.
Dropout voltage is the input-to-output voltage difference at which the output voltage is 100 mV below its nominal value. This
specification does not apply in cases it implies operation with an input voltage below the 2.5V minimum appearing under Operating
Ratings. For example, this specification does not apply for devices having 1.5V outputs because the specification would imply operation
with an input voltage at or about 1.5V.
LDO3 (D-Type) Electrical Characteristics
Unless otherwise noted, VIN=VIN2=BATT=3.6V, GND = 0V, CV!N1-2 = 10 µF, CLDOx= 1 µF. Note VINMIN is the greater of 3.0V or
VOUT +0.5V. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply
over the entire junction temperature range for operation, TA = TJ = −40°C to +125°C. (1)
Symbol
VOUT
Parameter
Output Voltage Accuracy
Conditions
Typical
IOUT = 1 mA, VOUT = 3.0V
Default Output Voltage
Limit
Min
Max
−2
+2
−3
+3
Units
%
3.0
V
Output Current
VINMIN ≤ VIN ≤ 5.5V
Output Current Limit
VOUT = 0V
600
VDO
Dropout Voltage
IOUT = 300 mA (2) (3)
135
ΔVOUT
Line Regulation
VINMIN ≤ VIN ≤ 5.5V
IOUT = 1 mA
2
Load Regulation
1 mA ≤ IOUT ≤ 300 mA
5
eN
Output Noise Voltage
10 Hz ≤ f ≤ 100 kHz,
COUT = 1 µF (2)
35
µVRMS
PSRR
Power Supply Ripple Rejection
Ratio
F = 10 kHz,
COUT = 1 µF,
IOUT = 20 mA (2)
60
dB
tSTART-UP
Start-Up Time from Shut-down
COUT = 1 µF, IOUT = 300 mA (2)
35
TTransient
Start-Up Transient Overshoot
COUT = 1 µF, IOUT = 300 mA (2)
IOUT
(1)
(2)
(3)
300
mA
250
mV
mV
µs
30
mV
All limits are specified. All electrical characteristics having room-temperature limits are tested during production with TJ = 25°C. All hot
and cold limits are ensured by correlating the electrical characteristics to process and temperature variations and applying statistical
process control.
Ensured by design.
Dropout voltage is the input-to-output voltage difference at which the output voltage is 100 mV below its nominal value. This
specification does not apply in cases it implies operation with an input voltage below the 2.5V minimum appearing under Operating
Ratings. For example, this specification does not apply for devices having 1.5V outputs because the specification would imply operation
with an input voltage at or about 1.5V.
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LDO4 (A-Type) Electrical Characteristics
Unless otherwise noted, VIN=VIN2=BATT=3.6V, GND = 0V, CV!N1-2 = 10 µF, CLDOx= 1 µF, TCXO_EN high. Note VINMIN is the
greater of 3.0V or VOUT +0.5V. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing in
boldface type apply over the entire junction temperature range for operation, TA = TJ = −40°C to +125°C. (1)
Symbol
VOUT
Parameter
Output Voltage Accuracy
Conditions
Typical
IOUT = 1 mA, VOUT = 3.0V
Default Output Voltage
Limit
Min
Max
−2
+2
−3
+3
3.0
Units
%
V
Output Current
VINMIN ≤ VIN ≤ 5.5V
Output Current Limit
VOUT = 0V
400
VDO
Dropout Voltage
IOUT =80 mA (2) (3)
60
ΔVOUT
Line Regulation
VINMIN + ≤ VIN ≤ 5.5V, IOUT = 1 mA
1
Load Regulation
1 mA ≤ IOUT ≤ 80 mA
5
eN
Output Noise Voltage
10 Hz ≤ f ≤ 100 kHz,
COUT = 1 µF (2)
10
µVRMS
PSRR
Power Supply Ripple Rejection
Ratio
F = 10 kHz,
COUT = 1 µF, IOUT = 20 mA (2)
75
dB
tSTART-UP
Start-Up Time from Shut-down
COUT = 1 µF, IOUT = 80 mA (2)
35
TTransient
Start-Up Transient Overshoot
COUT = 1 µF, IOUT = 80 mA (2)
IOUT
(1)
80
85
mA
mV
mV
µs
30
mV
All limits are specified. All electrical characteristics having room-temperature limits are tested during production with TJ = 25°C. All hot
and cold limits are ensured by correlating the electrical characteristics to process and temperature variations and applying statistical
process control.
Ensured by design.
Dropout voltage is the input-to-output voltage difference at which the output voltage is 100 mV below its nominal value. This
specification does not apply in cases it implies operation with an input voltage below the 2.5V minimum appearing under Operating
Ratings. For example, this specification does not apply for devices having 1.5V outputs because the specification would imply operation
with an input voltage at or about 1.5V.
(2)
(3)
LDO5, LDO6, LDO7 (A-Type) Electrical Characteristics
Unless otherwise noted, VIN=VIN2=BATT=3.6V, GND = 0V, CV!N1-2 = 10 µF, CLDOx= 1 µF, RX_EN, TX_EN high. Note VINMIN is
the greater of 3.0V or VOUT +0.5V. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing in
boldface type apply over the entire junction temperature range for operation, TA = TJ = −40°C to +125°C. (1)
Symbol
VOUT
Parameter
Output Voltage Accuracy
Conditions
Typical
IOUT = 1 mA, VOUT = 3.0V
Default Output Voltage
VINMIN ≤ VIN ≤ 5.5V
Output Current Limit
VOUT = 0V
400
VDO
Dropout Voltage
IOUT = 150 mA (2) (3)
100
ΔVOUT
Line Regulation
VINMIN ≤ VIN ≤ 5.5V
IOUT = 1 mA
1
Load Regulation
1 mA ≤ IOUT ≤ 150 mA
5
Output Noise Voltage
10 Hz ≤ f ≤ 100 kHz,
COUT = 1 µF (2)
eN
PSRR
(1)
(2)
(3)
10
Power Supply Ripple Rejection
Ratio
Min
Max
−2
+2
−3
+3
3.0
Output Current
IOUT
Limit
F = 10 kHz, COUT = 1 µF, IOUT = 20 mA
Units
%
V
150
150
mA
mV
mV
10
µVRMS
75
dB
(2)
All limits are specified. All electrical characteristics having room-temperature limits are tested during production with TJ = 25°C. All hot
and cold limits are ensured by correlating the electrical characteristics to process and temperature variations and applying statistical
process control.
Ensured by design.
Dropout voltage is the input-to-output voltage difference at which the output voltage is 100 mV below its nominal value. This
specification does not apply in cases it implies operation with an input voltage below the 2.5V minimum appearing under Operating
Ratings. For example, this specification does not apply for devices having 1.5V outputs because the specification would imply operation
with an input voltage at or about 1.5V.
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LDO5, LDO6, LDO7 (A-Type) Electrical Characteristics (continued)
Unless otherwise noted, VIN=VIN2=BATT=3.6V, GND = 0V, CV!N1-2 = 10 µF, CLDOx= 1 µF, RX_EN, TX_EN high. Note VINMIN is
the greater of 3.0V or VOUT +0.5V. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing in
boldface type apply over the entire junction temperature range for operation, TA = TJ = −40°C to +125°C.(1)
Symbol
tSTART-UP
TTransient
Parameter
Start-Up Time from Shut-down
Start-Up Transient Overshoot
Conditions
Typical
COUT = 1 µF, IOUT = 150 mA (2)
COUT = 1 µF, IOUT = 150 mA
Limit
Min
Units
Max
35
µs
(2)
30
mV
LDO8 (D-Type) Electrical Characteristics
Unless otherwise noted, VIN=VIN2=BATT=3.6V, GND = 0V, CV!N1-2 = 10 µF, CLDOx= 1 µF. Note VINMIN is the greater of 3.0V or
VOUT +0.5V. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply
over the entire junction temperature range for operation, TA = TJ = −40°C to +125°C. (1)
Symbol
VOUT
Parameter
Output Voltage Accuracy
Conditions
Typical
IOUT = 1 mA, VOUT = 3.0V
Default Output Voltage
VINMIN ≤ VIN ≤ 5.5V
Output Current Limit
VOUT = 0V
400
VDO
Dropout Voltage
IOUT = 150 mA (2) (3)
125
ΔVOUT
Line Regulation
VINMIN ≤ VIN ≤ 5.5V, IOUT = 1 mA
2
Load Regulation
1 mA ≤ IOUT ≤ 150 mA
5
eN
Output Noise Voltage
10 Hz ≤ f ≤ 100 kHz, COUT = 1 µF (2)
PSRR
Power Supply Ripple Rejection F = 10 kHz, COUT = 1 µF, IOUT = 20 mA
Ratio
tSTART-UP
Start-Up Time from Shut-down
COUT = 1 µF, IOUT = 150 mA (2)
TTransient
Start-Up Transient Overshoot
COUT = 1 µF, IOUT = 150 mA (2)
(1)
(2)
(3)
Max
−2
+2
−3
+3
Units
%
3.0
Output Current
IOUT
Limit
Min
V
150
mA
140
mV
mV
35
µVRMS
60
dB
(2)
35
µs
30
mV
All limits are specified. All electrical characteristics having room-temperature limits are tested during production with TJ = 25°C. All hot
and cold limits are ensured by correlating the electrical characteristics to process and temperature variations and applying statistical
process control.
Ensured by design.
Dropout voltage is the input-to-output voltage difference at which the output voltage is 100 mV below its nominal value. This
specification does not apply in cases it implies operation with an input voltage below the 2.5V minimum appearing under Operating
Ratings. For example, this specification does not apply for devices having 1.5V outputs because the specification would imply operation
with an input voltage at or about 1.5V.
Buck Converter Electrical Characteristics
Unless otherwise noted, VIN = VINB = 3.6V, GND = 0V, CVINB = 10 µF. Typical values and limits appearing in normal type
apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, TA = TJ
= −40°C to +125°C. (1) (2)
Symbol
Parameter
Conditions
Typ
Limit
Min
Max
Units
VFB
Feedback Voltage (BUCK)
3.0V ≤VIN≤ 5.5V
0.5
0.485
0.515
V
VOUT,PWM
Output Voltage
3.0V ≤VIN≤ 5.5V, IOUT = 150mA
External resistor divider
accuracy not considered.
RFB1=390kΩ RFB2=150kΩ (3)
1.8
1.746
1.854
V
(1)
(2)
(3)
All limits are specified. All electrical characteristics having room-temperature limits are tested during production with TJ = 25°C. All hot
and cold limits are ensured by correlating the electrical characteristics to process and temperature variations and applying statistical
process control.
Buck output voltage accuracy depends on the accuracy of the external feedback resistors. Resistor values should be chosen for the
divider network to ensure that at the desired output voltage the FB pin is at the specified value of 0.5V. See Buck Converter Application
Information.
Ensured by design.
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Buck Converter Electrical Characteristics (continued)
Unless otherwise noted, VIN = VINB = 3.6V, GND = 0V, CVINB = 10 µF. Typical values and limits appearing in normal type
apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, TA = TJ
= −40°C to +125°C.(1)(2)
Symbol
VOUT,PFM
Parameter
Conditions
Output Voltage regulation
in PFM mode relative to
regulation in PWM mode
Limit
Min
Units
Max
See (3)
Line Regulation
3.0V ≤ VIN ≤ 5.5V, IOUT = 10
mA
VOUT
Typ
1.5
%
0.14
%/V
Load Regulation
100 mA ≤ IOUT ≤ 300 mA
ILIM_PWM
Switch Peak Current Limit
PWM Mode
1150
RDSON(P)
P Channel FET on
Resistance
VIN = 3.6V
IDS = 100 mA
310
mΩ
RDSON(N)
N Channel FET on
Resistance
160
mΩ
fOSC
Internal Oscillator
Frequency
PWM Mode
Efficiency
TSTUP
Start Up Time
0.0013
2
%/mA
800
1500
1.9
IOUT = 5 mA, PFM Mode
VOUT = 1.8V (3)
88
IOUT = 300 mA, PWM Mode
VOUT = 1.8V (3)
90
IOUT = 0 (3), VOUT = 1.8V
140
mA
2.1
MHz
%
µs
Charger Electrical Characteristics
Unless otherwise noted, VCHG_IN = 5V, VIN= BATT = 3.6V, CCHG_IN = 1 μF, VBATT = 30 µF. Typical values and limits appearing
in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for
operation, TA = TJ = −25°C to +85°C. (1) (2)
Symbol
VCHG_IN
VOK_CHG
Parameter
Conditions
Typical
AC wall adapter input
voltage operating range
CHG_IN OK trip-point.
VCHG_IN - VBATT (Rising)
150
VCHG_IN - VBATT (Falling)
40
VTERM
Battery charging
termination voltage
tolerance
VTERM = 4.2V, ICHG = 50 mA
VTERM is measured at 10% of the programmed
ICHG current
ICHG
CHG_IN programmable
full-rate charging current
Limit
Units
Min
Max
4.5
6.8
V
mV
-0.35
+0.35
-1
+1
6.8V ≥ VCHG_IN ≥ 4.5V
VBATT < VCHG_IN − VOK_CHG
VFULL_RATE < VBATT < VTERM (3)
50
1200
mA
Full rate charging current
tolerance
ICHG = 400 mA
−10
+10
%
IPREEQUAL
Pre-charging current
2.2V < VBATT < VFULL_RATE
50
30
70
mA
VFULL_RATE
Full-rate qualification
threshold
VBATT rising, transition from pre-charging to fullrate charging
2.8
2.7
2.9
VBATT rising, transition from pre-charging to fullrate charging (LP3923-VC)
3.0
2.9
3.1
(1)
(2)
(3)
12
%
V
All limits are specified. All electrical characteristics having room-temperature limits are tested during production with TJ = 25°C. All hot
and cold limits are ensured by correlating the electrical characteristics to process and temperature variations and applying statistical
process control.
Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power
dissipation exists, special care must be paid to thermal dissipation issues in board design.
Full charging current is ensured for CHG_IN = 4.5 to 6.8V, but particularly at higher input voltages. Increased power dissipation may
cause the thermal regulation to limit the current to a safe level, resulting in longer charging time.
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Charger Electrical Characteristics (continued)
Unless otherwise noted, VCHG_IN = 5V, VIN= BATT = 3.6V, CCHG_IN = 1 μF, VBATT = 30 µF. Typical values and limits appearing
in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for
operation, TA = TJ = −25°C to +85°C.(1)(2)
Symbol
Parameter
Conditions
Typical
Limit
Min
IEOC
End-of-charging
current, % of full-rate
current
0.1C option selected
VRESTART
Restart threshold voltage
From VTERM voltage (4.2V, −100 mV options
selected)
−100
IMON
IMON Voltage 1
ICHG = 100 mA
0.247
IMON Voltage 2
ICHG = 400 mA
0.988
CBATT
TREG
Capacitance on BATT
Regulated junction
temperature
10
See (4)
See
Units
Max
(4)
%
−70
−130
0.840
1.127
30
1000
mV
V
µF
115
°C
Detection and Timing (one combined timer)
TPOK
Power OK deglitch time
VCHG > VBATT + VOK_CHG
30
ms
TPC_FULL
Deglitch time
From pre-charging to full-rate charging
210
ms
TCHG
Charge timer
Pre-charge mode
1
disabled
2
CC mode/CV mode (combined timer)
Hrs
5
8
TEOC
(4)
Deglitch time for end- ofcharge transition
210
ms
Ensured by design.
Serial Interface
Unless otherwise noted, VIN = BATT = 3.6V, GND = 0V, CVIN1–2 = 10 µF CLDOx = 1 µF and VLDO3 = 3.0V. Typical values and
limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction
temperature range for operation, TA = TJ = −40°C to +125°C. (1) (2)
Symbol
Parameter
Conditions
Typ
Limit
Min
Max
Unit
s
400
kHz
fCLK
Clock Frequency
tBF
Bus-Free Time between START and STOP
1.3
µs
tHOLD
Hold Time Repeated START Condition
0.6
µs
tCLK-LP
CLK Low Period
1.3
µs
tCLK-HP
CLK High Period
0.6
µs
tSU
Set-Up Time Repeated START Condition
0.6
µs
tDATA-HOLD
Data Hold Time
50
ns
tDATA-SU
Data Set-Up Time
100
ns
tSU
Set-Up Time for STOP Condition
0.6
µs
tTRANS
Maximum Pulse Width of Spikes that Must Be
Suppressed by the Input Filter of Both DATA & CLK
Signals
(1)
(2)
50
ns
All limits are specified. All electrical characteristics having room-temperature limits are tested during production with TJ = 25°C. All hot
and cold limits are ensured by correlating the electrical characteristics to process and temperature variations and applying statistical
process control.
Ensured by design.
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POWER UP AND POWER DOWN SEQUENCES
(1)
CHG_IN is edge sensitive and HF_PWR is level sensitive at startup in STANDBY mode and level sensitive in
POWER-ON-RESET mode.
(2)
PWR_ON is level sensitive at startup. PS_HOLD must be asserted before PWR_ON goes LOW to keep PMU
powered. PWR_ON input is not monitored after PMU is powered up (PS_HOLD asserted).
(3)
PON_N is a direct inversion of PWR_ON input when LDO3 is powered up (no power-on switch debouncing on
PON_N output).
(4)
The input signal which activates Power Up sequence (either PWR_ON or CHG_IN or HF_PWR) must be on when
PS_HOLD is asserted.
(5)
Time delay between the PS_HOLD going low and the start of Power Down sequence depends on PS_HOLD_DELAY
setting (0=35ms, 1=350ms) (typ.).
Figure 1. Power Up and Power Down Timing Diagram
14
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SNVS567B – APRIL 2010 – REVISED MAY 2013
LP3923 Serial Port Communication: Slave Address Code: 7h'7E
Table 4. Control Registers (1)
Addr
Register
(Default value)*
D7
D6
D5
D4
D3
D2
D1
D0
8h'00
OP_EN1
(01000111)
BUCK_
PWM
EN_
BUCK
X
X
EN_LDO8
EN_LDO7
EN_LDO2
EN_LDO1
8h'01
LDO1PGM O/P
SEL=BATT
(00001100)
SEL=GND
(00011011)
X
X
X
LDO1_
V1_OP[4]
LDO1_
V1_OP[3]
LDO1_
V1_OP[2]
LDO1_
V1_OP[1]
LDO1_
V1_OP[0]
8h'02
LDO2 Program O/P
SEL=BATT
(00001100)
SEL=GND
(00011011)
X
X
X
LDO2_
V2_OP[4]
LDO2_
V2_OP[3]
LDO2_
V2_OP[2]
LDO2_
V2_OP[1]
LDO2_
V2_OP[0]
8h'03
LDO3 PGM O/P
(00011011)
X
X
X
LDO3_
V3_OP[4]
LDO3_
V3_OP[3]
LDO3_
V3_OP[2]
LDO3_
V3_OP[1]
LDO3_
V3_OP[0]
8h'04
LDO4 PGM O/P
(00011011)
X
X
X
LDO4_
V4_OP[4]
LDO4_
V4_OP[3]
LDO4_
V4_OP[2]
LDO4_
V4_OP[1]
LDO4_
V4_OP[0]
8h'05
LDO5 PGM O/P
(00011011)
X
X
X
LDO5_
V5_OP[4]
LDO5_
V5_OP[3]
LDO5_
V5_OP[2]
LDO5_
V5_OP[1]
LDO5_
V5_OP[0]
8h'06
LDO6 PGM O/P
(00011011)
X
X
X
LDO6_
V6_OP[4]
LDO6_
V6_OP[3]
LDO6_
V6_OP[2]
LDO6_
V6_OP[1]
LDO6_
V6_OP[0]
8h'07
LDO7 PGM O/P
(00011011)
X
X
X
LDO7_
V7_OP[4]
LDO7_
V7_OP[3]
LDO7_
V7_OP[2]
LDO7_
V7_OP[1]
LDO7_
V7_OP[0]
8h'08
LDO8 PGM O/P
(00011011)
X
X
X
LDO8_
V8_OP[4]
LDO8_
V8_OP[3]
LDO8_
V8_OP[2]
LDO8_
V8_OP[1]
LDO8_
V8_OP[0]
8h'0C
Status1
Trig.PWR_ON(10000010)
Trig.HF_PWR(01000010)
Trig.-CHG_IN
(00100010)
PWR_ON
TRIG
HF_PWR
TRIG
CHG_IN
TRIG
X
TSD_H
TSD_L
FF
X
8h'10
CHARGER Control 1
(00010 001)
X
X
Force_
EOC
EN_EOC
X
EN_CHG
8h'11
CHARGER Control 2
(00000111)
X
X
X
PROG_
ICHG[4]
PROG_
ICHG[3]
PROG_
ICHG[2]
PROG_
ICHG[1]
PROG_
ICHG[0]
8h'12
CHARGER Control 3
(00011001)
X
X
VTERM[
1]
VTERM[0]
PROG_
EOC[1]
PROG_
EOC[0]
PROG_
VSTRT[1]
PROG_
VSTART[0]
8h'13
CHARGER Status 1
(0000 0000)
BATT_
OVER_OUT
CHGIN_
OK_OUT
EOC
TOUT_
FULLRATE
TOUT_
PRECHG
X
FULLRATE
PRECHG
8h'14
CHARGER Status 2
(00000000)
X
X
X
X
X
X
TOUT_
CONSTV
BAD_BATT
8h'1C
MISC Control1
(00000000)
X
X
X
X
X
X
EN_
APU_TSD
PS_HOLD_
DELAY
(1)
PROG_
PROG_
CHGTIME[1 CHGTIME[0
]
]
X — Not used.
BOLD locations are Read Only type.
NOTE: All Control registers apart from Charger Control registers (h'10 — h'12) are reset to default at the end of every Power Down
sequence.
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Table 5. Register 0x00 – OP_EN1
BUCK_PWM
0 - Auto mode PFM/PWM
1 - Buck forced PWM mode
EN_BUCK
0 - disable Buck
1 - enable Buck
EN_LDO8
0 - disable LDO8
1 - enable LDO8
EN_LDO7
0 - disable LDO7
1 - enable LDO7
EN_LDO2
0 - disable LDO2 on LP3923TL/X and -VI; enable on LP3923TL/X-VB
1 - enable LDO2 on LP3923TL/X and -VI; disable on LP3923TL/X-VB
EN_LDO1
0 - disable LDO1 on LP3923TL/X and -VI; enable on LP3923TL/X-VB
1 - enable LDO1 on LP3923TL/X and -VI; disable on LP3923TL/X-VB
Table 6. Register 0x0C (Read Only) – Status 1
PWR_ON_TRIG
0 - system was not powered on by PWR_ON input
1 - system was powered on by PWR_ON input
HF_PWR_TRIG
0 - system was not powered on by HF_PWR input
1 - system was powered on by HF_PWR input
CHG_IN_TRIG
0 - system was not powered on by connecting AC adapter
1 - system was powered on by connecting AC adapter
TSD_H
0 - Thermal Shutdown threshold not exceeded
1 - Thermal Shutdown threshold exceeded (cause Power Down sequence)
TSD_L
0 - chip temperature has not been over TSD early warning threshold
1 - chip temperature has been over TSD early warning threshold
FF
0 - Buck output voltage out of range
1 - Buck output voltage within range
Table 7. Register 0x13 (Read Only) – CHARGER Status 1
BATT_OVER_OUT
0 - battery voltage is in normal range
1- battery voltage is over critical limit
CHGIN_OK_OUT
0 - voltage is not connected to AC adapter input
1 - voltage is connected to AC adapter input
EOC
0 - charging current is above EOC current level
1 - charging current is below EOC current level
TOUT_FULLRATE
0 - no time out occurred in Constant Current mode
1 - time out occurred in Constant Current mode
TOUT_PRECHG
0 - no time out occurred in pre-charge mode
1 - time out occurred in pre-charge mode
FULLRATE
0 - charger is not in CC or CV mode
1 - charger is in CC or CV mode
PRECHG
0 - charger is not in pre-charge mode
1 - charger is in pre-charge mode
Table 8. Register 0x14 (Read Only) – CHARGER Status 2
TOUT_CONSTV
0 - no time out occurred in Constant Voltage mode
1 - time out occurred in Constant Voltage mode
BAD_BATT
0 - charger has not detected a bad battery
1 - charger has detected a bad battery
16
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Table 9. Register 0x1C – MISC Control 1
EN_APU_TSD
0 - do not start PMU automatically after TSD event
1 - start PMU automatically after TSD event
PS_HOLD_DELAY
0 - PMU powerdown after PS_HOLD has been low for 35 ms
1 - PMU powerdown after PS_HOLD has been low for 350 ms
LDO OUTPUT VOLTAGE PROGRAMMING
The following table summarizes the supported output voltages for LP3923. Default voltages after start-up
sequences have been highlighted in bold.
(1)
Data Code LDO_Vx_OP[x]
LDOx [V]
Data Code LDO_Vx_OP[x]
LDOx [V]
8h'00
1.20
8h'10
2.20
8h'01
1.25
8h'11
2.40
8h'02
1.30
8h'12
2.50
8h'03
1.35
8h'13
2.60
8h'04
1.40
8h'14
2.65
8h'05
1.45
8h'15
2.70
8h'06
1.50
8h'16
2.75
8h'07
1.55
8h'17
2.80
8h08
1.60
8h'18
2.85
2.90
8h'09
1.65
8h'19
8h'0A
1.70
8h'1A
2.95
8h'0B
1.75
8h'1B
3.00 (1)
8h'0C
1.80 (1)
8h'1C
3.05
8h'0D
1.85
8h'1D
3.10
8h'0E
1.90
8h'1E
3.20
8h'0F
2.00
8h'1F
3.3
See Table 1.
CHARGING CURRENT PROGRAMMING
Table 10. The following table summarizes the supported currents for LP3923.
PROG_ ICHG[4]
PROG_ ICHG[3]
PROG_ ICHG[2]
PROG_ ICHG[1]
PROG_ ICHG[0]
ICHG (mA)
0
0
0
0
0
50
0
0
0
0
1
100
0
0
0
1
0
150
0
0
0
1
1
200
0
0
1
0
0
250
0
0
1
0
1
300
0
0
1
1
0
350
0
0
1
1
1
400 (Default)
0
1
0
0
0
450
0
1
0
0
1
500
0
1
0
1
0
550
0
1
0
1
1
600
0
1
1
0
0
650
0
1
1
0
1
700
0
1
1
1
0
750
0
1
1
1
1
800
1
0
0
0
0
850
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Table 10. The following table summarizes the supported currents for LP3923.
(continued)
PROG_ ICHG[4]
PROG_ ICHG[3]
PROG_ ICHG[2]
PROG_ ICHG[1]
PROG_ ICHG[0]
ICHG (mA)
1
0
0
0
1
900
1
0
0
1
0
950
1
0
0
1
1
1000
1
0
1
0
0
1050
1
0
1
0
1
1100
1
0
1
1
0
1150
1
0
1
1
1
1200
Table 11. Charging Termination Voltage Programming
VTERM[1]
VTERM[0]
VTERM
0
0
4.1
0
1
4.2 (Default)
1
0
4.3
1
1
4.4
Table 12. End of Charging Current Programming
(1)
PROG_EOC[1]
PROG_EOC[0]
IEOC (1)
0
0
0.05C
0
1
0.1C
1
0
0.15C (Default)
1
1
0.2C
C is the programmed charging current.
Table 13. Charging Restart Voltage Programming
PROG_VRSTRT[1]
PROG_VRSTRT[0]
0
0
Restart Voltage (V)
VTERM −50 mV
0
1
VTERM −100 mV (Default)
1
0
VTERM −150 mV
1
1
VTERM −200 mV
Table 14. Charge Timer Programming
PROG_CHGTIME[1]
PROG_CHGTIME[0]
Charging Timer (Hrs)
0
0
Disabled
0
1
2
1
0
5 (Default)
1
1
8
BATTERY CHARGE MANAGEMENT
A charge management system allowing safe charge and maintenance of a Li-Ion battery is implemented on the
LP3923. It has a CC/CV linear charge capability with programmable battery regulation voltage and end of
charging current threshold. A maintenance mode utilizing programmable restart voltage levels enables the
battery voltage to be maintained at the correct level. The charging current in the constant voltage mode is
programmable from 50 mA to 1.2A in 50 mA steps.
If PMU is started without a battery, and the battery is attached later, the charging current should be programmed
once more; otherwise, the charging current will be the same as without a battery.
18
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If the battery is deeply depleted and the overdischarge protection circuit is active, during startup the charger may
detect that the battery is not present. This can cause the charger to select a non-default charging current (LDO
mode default charging current).
CHARGER FUNCTION
Following the correct detection of an input voltage at the charger pin the charger enters a pre-charge mode. In
this mode a constant current of 50 mA is available to charge the battery to 2.8V. At this voltage level the charge
management applies the full rate constant current to raise the battery voltage to the termination voltage level
(default 4.2V). The full-rate charging current may be programmed to a different level at this stage. When
termination voltage (VTERM) is reached, the charger is in constant voltage mode and a constant voltage of 4.2V
is maintained. This mode is complete when the end of charging current (default 0.15C) is detected and the
charge management enters the maintenance mode. In maintenance mode the battery voltage is monitored for
the restart level (default VTERM - 100 mV) and the charge cycle is re-initiated to re-establish the termination
voltage level.
THERMAL SHUTDOWN
The Thermal Shutdown (TSD) function monitors the chip temperature to protect the chip from temperature
damage caused, for example, by excessive power dissipation. If the temperature exceeds a higher threshold
value of +160°C, the TSD_H bit in the Register 0x0C is set, and the chip will automatically run the Power Down
sequence.
The restart operation after Thermal Shutdown can be initiated only after the chip has cooled down to the +90°C
threshold. The APU_TSD_EN bit in the Register 0x1C is controlling the restart. If this bit is cleared (default) then
a Power On sequence is initiated normally through PWR_ON, CHG_IN or VBUS. If APU_TSD_EN is written to
logic 1 then an automatic Power Up sequence is initiated. All register settings preserved in such case. Power On
can be activated only if the junction temperature is less than the early warning lower threshold +90°C.
The temperature monitoring function has two charger threshold values that result in protective actions. When a
lower threshold of +105°C is exceeded, the TSD_L bit in Register 0x0C will be set, bit will reset it if the
temperature has decreased to lower than 15°C below the threshold.
When a upper charger threshold of +115°C is exceeded, the charger will reduce charging current to protect the
chip.
Parameter
Typ
Unit
Higher Threshold (1)
160
°C
Charger Early Warning
(1)
105
°C
Early Warning Hysteresis (1)
15
°C
Charger Thermal Regulation
115
°C
(1)
Ensured by design.
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TERMINATION AND RESTART
The termination and restart voltage levels are determined by the data in the VTERM[1:0] and PROG_VSTRT[1:0]
bits in the control register. The restart voltage is programmed relative to the selected termination voltage.
VBATT < VFULL_RATE
4.5V 7 VCHG_IN 7 6.8V
Charger OFF
zero current
Precharge Mode
50 mA constant current
VBATT < VFULL_RATE
From any mode:
VCHG_IN < 4.5V
or VCHG_IN > 6.8V
VBATT < VTERM
2
or I C disable received
Full Rate Mode
selectable constant current (C)
VBATT = VTERM
ICHG > EOC
Full Rate Mode
4.2V constant voltage
ICHG 7 EOC
VBATT < VRESTART
Maintenance Mode
zero current
BATTERY VOLTAGE / CHARGING CURRENT
Figure 2. Simplified Charger Functional State Diagram (when EOC is enabled)
1C
4.2V Default
Battery Voltage
VRESTART (4.10V Default)
VFULLRATE
Charging Current
50 mA
IEOC (0.15C Default)
TIME
Figure 3. Charging Cycle Diagram
20
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IMON CHARGING CURRENT MONITOR
Charging current is monitored within the charger section and a proportional voltage representation of the
charging current is presented at the IMON output pin. The output voltage relationship to the actual charging
current is represented in the following graph and by the equation:
VIMON(mV) = (2.47 x ICHG(mA))
(1)
IMON VOLTAGE (V)
2.964
1.729
0.247
100
700
1200
CHARGE CURRENT (mA)
Figure 4.
Note that this function is not available if there is no input at CHG_IN or if the charger is off due to the input at
CHG_IN being less than the compliance voltage.
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Buck Converter Application Information
BUCK OUTPUT VOLTAGE SELECTION
Buck output voltage can be programmed via the selection of the external feedback resistor network forming the
output feedback between the output voltage side of the inductor and the FB pin and the FB pin and GND.
L1
VOUT
SW
2.2 µH
C1
RFB1
FB
COUT
10 µF
C2
RFB2
LP3923
Figure 5. Buck Converter Components
VOUT will be adjusted to make the voltage at FB equal to 0.5V. The resistor from FB to ground (RFB2) should be
around 200 kΩ to keep the current drawn through the resistor network to a minimum but large enough that it is
not susceptible to noise. If R2 is 200 kΩ and with VFB at 0.5V, the current through the resistor feedback network
will be 2.5 µA.
The formula for output voltage selection is
RFB1
RFB2
§
©
§
©
VOUT = VFB x 1+
(2)
VOUT - output voltage (V)
VFB
- feedback voltage (0.5V)
RFB1 - feedback resistor from VOUT to FB
RFB2 - feedback resistor from FB to GND
The recommended value for C1 is 2.2 pF to 5.1 pF, and for C2 is 15 pF.
Table 15. Component Configurations for Various Output Voltage Values
VOUT [V]
RFB1 [kΩ]
RFB2 [kΩ]
C1 [pF]
C2 [pF]
L [µH]
COUT [µF]
1.4
360
200
2.2 to 5.1
15
2.2
10
1.6
390
178
2.2 to 5.1
15
2.2
10
1.8
390
150
2.2 to 5.1
15
2.2
10
2.0
453
150
2.2 to 5.1
15
2.2
10
INDUCTOR SELECTION
There are two main considerations when choosing an inductor; the inductor should not saturate, and the inductor
current ripple is small enough to achieve the desired output voltage ripple. Different saturation current rating
specs are followed by different manufacturers so attention must be given to details. Saturation current ratings are
typically given at 25°C so ratings at the application maximum ambient temperature should be requested from the
manufacturer.
There are two methods to choose the inductor saturation current rating.
Method 1
The total current is the sum of the load and the inductor ripple current. This can be written as:
ISAT = IOUTMAX + IRIPPLE
x
§ VOUT
© VIN
§
©
§
©
22
§ VIN - VOUT
© 2xL
x
§
©
1
f
§
©
ISAT = IOUTMAX +
(3)
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ILOAD = load current
IRIPPLE = average to peak inductor current
VIN
= input voltage
L
= inductor inductance
f
= switching frequency
Method 2
A more conservative approach is to choose an inductor that can handle the maximum current limit of 1500 mA.
Given a peak-to-peak current ripple (IPP) the inductor needs to be at least:
§
©
§VIN - VOUT
© IPP
x
§ VOUT
© VIN x f
§
©
L t
(4)
A 2.2 µH inductor with a saturation current rating of at least 1500 mA is recommended for most applications. The
inductor’s resistance should be less than 0.3Ω for good efficiency. The below table suggests inductors and
suppliers.
For low-cost applications, an unshielded bobbin inductor is suggested. For noise critical applications, a toroidal or
shielded-bobbin inductor should be used. A good practice is to lay out the board with overlapping footprints of
both types for design flexibility. This allows substitution of a low-noise toroidal inductor, in the event that noise
from low-cost bobbin models is unacceptable.
Table 16. Suggested Inductors and Their Suppliers (Preliminary and Untested)
Model
DO3314-222MXC
LPO3310-222MX
ELL5GM2R2N
Vendor
Dimensions (mm)
DC R(max)
Coilcraft
3.3 x 3.3 x 1.4
200 mΩ
Coilcraft
3.3 x 3.3 x 1.0
150 mΩ
Panasonic
5.2 x 5.2 x x 1.5
53 mΩ
Sumida
3.2 x 3.2 x 1.55
94 mΩ
CDRH2D142R2
INPUT CAPACITOR SELECTION
A ceramic input capacitor of 10 µF is sufficient for most applications. A larger value may be used for improved
input voltage filtering. Use X7R or X5R type capacitors, do not use Y5V. The DC bias characteristics of ceramic
capacitors must be considered when selecting case sizes of 0805 or smaller for use in the application. Smaller
case sizes in many cases exhibit a large drop in capacitance value as the DC bias increases.
The input filter capacitor supplies current to the PFET switch of the converter in the first half of each cycle and
reduces voltage ripple imposed on the input power source. A ceramic capacitor’s low ESR provides the best
noise filtering of the input voltage spikes due to this rapidly changing current. Select an input filter capacitor with
a surge current rating sufficient for the power-up surge from the input power source. The power-up surge current
is approximately the capacitor’s value (µF) times the voltage rise rate (V/µs).
The input current ripple can be calculated as:
VOUT
VIN
§
©
x 1-
VOUT
VIN
§
©
IRMS = IOUTMAX x
(5)
The worst case IRMS is:
IRMS =
IOUTMAX
2
(duty cycle = 50%)
(6)
OUTPUT CAPACITOR SELECTION
A 10 µF capacitor is recommended for use at the output of the buck converter. Use X7R or X5R type capacitors;
do not use Y5V. The DC bias characteristics of ceramic capacitors must be considered when selecting case
sizes of 0805 or smaller for use in the application. Smaller case sizes in many cases exhibit a large drop in
capacitance value as the DC bias increases. DC bias characteristics vary from manufacturer to manufacturer and
dc bias curves should be requested from them as part of the capacitor selection process.
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The output filter capacitor smooths out current flow from the inductor to the load, helps maintain a steady output
voltage during transient load changes and reduces output voltage ripple. These capacitors must be selected with
sufficient capacitance and sufficiently low ESR to perform these functions.
The output voltage ripple is caused by the charging and discharging of the output capacitor and also due to its
ESR. It can be calculated as:
Voltage peak to peak ripple due to capacitance =
VPP-C =
I PP
fx8xC
(7)
Voltage peak to peak ripple due to ESR =
VPP-ESR = IPP*RESR
(8)
Voltage peak to peak ripple, root mean squared =
VPP-RMS =
VPP-C2 + VPP-ESR2
(9)
Note that the output ripple is dependent on the inductor current ripple and the equivalent series resistance of the
output capacitor (RESR). Because these two components are out of phase the rms value is used. The RESR is
frequency dependent (as well as temperature dependent); make sure the frequency of the RESR given is the
same order of magnitude as the switching frequency.
Table 17. Suggested Capacitors And Their Suppliers
Model
Type
Vendor
Voltage Rating
Case Size
10 µF (CIN and COUT)
GRM21BR60J106k
Ceramic, X5R
MURATA
6.3V
0805
JMK212BJ106K
Ceramic, X5R
TAIYO YUDEN
6.3V
0805
C2012X5R0J106K
Ceramic, X5R
TDK
6.3V
0805
LDO Information
OPERATIONAL INFORMATION
The LP3923 has eight LDOs of which 4 are enabled by default and powered up during the power up sequence,
LDOs 1, 2, 3 and 7 are powered up during the power up sequence. LDOs 4, 5, and 6 are separately externally
enabled and will follow LDO3 in start up if their respective enable pin is pulled high. LDO1, LDO2, LDO7 and
LDO8 can be enabled/disabled via the Serial Interface
LDO3 must remain in regulation otherwise the device will power down.
The LILO-type LDO is optimized for low output voltage and for good dynamic performance to supply different fast
charging (digital) pads.
INPUT VOLTAGES
There are two input voltage pins used to power the eight LDOs on the LP3923. VIN1 is the supply for LDO1 and
LDO2. VIN2 is the supply for LDO3, LDO4, LDO5, LDO6, LDO7, and LDO8.
EXTERNAL CAPACITORS
The Low Drop Out Linear Voltage regulators on the LP3923 require external capacitors to ensure stable outputs.
The LDOs on the LP3923 are specifically designed to use small surface mount ceramic capacitors which require
minimum board space. These capacitors must be correctly selected for good performance.
INPUT CAPACITOR
Input capacitors are required for correct operation. It is recommended that a 10 µF capacitor be connected
between each of the voltage input pins and ground (this capacitance value may be increased without limit).
This capacitor must be located a distance of not more than 1 cm from the input pin and returned to a clean
analogue ground. A ceramic capacitor is recommended although a good quality tantalum or film capacitor may
be used at the input.
24
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Important: Tantalum capacitors can suffer catastrophic failures due to surge current when connected to a lowimpedance source of power (like a battery or a very large capacitor). If a tantalum capacitor is used at the input,
it must be ensured by the manufacturer to have a surge current rating sufficient for the application.
There are no requirements for the ESR (Equivalent Series Resistance) on the input capacitor, but tolerance and
temperature coefficient must be considered when selecting the capacitor to ensure the capacitance will remain
within its operational range over the entire operating temperature range and conditions.
OUTPUT CAPACITOR
Correct selection of the output capacitor is critical to ensure stable operation in the intended application.
The output capacitor must meet all the requirements specified in the recommended capacitor table over all
conditions in the application. These conditions include DC-bias, frequency and temperature. Unstable operation
will result if the capacitance drops below the minimum specified value.
The LP3923 is designed specifically to work with very small ceramic output capacitors. The LDOs on the LP3923
are specifically designed to be used with X7R and X5R type capacitors. With these capacitors, selection of the
capacitor for the application is dependant on the range of operating conditions and temperature range for that
application. (See section on CAPACITOR CHARACTERISTICS).
It is also recommended that the output capacitor be placed within 1 cm from the output pin and returned to a
clean ground line.
CAPACITOR CHARACTERISTICS
The LDOs on the LP3923 are designed to work with ceramic capacitors on the input and output to take
advantage of the benefits they offer. For capacitance values around 1µF, ceramic capacitors give the circuit
designer the best design options in terms of low cost and minimal area.
For both input and output capacitors careful interpretation of the capacitor specification is required to ensure
correct device operation. The capacitor value can change greatly dependant on the conditions of operation and
capacitor type.
In particular, to ensure stability, the output capacitor selection should take account of all the capacitor parameters
to ensure that the specification is met within the application. Capacitance value can vary with DC bias conditions
as well as temperature and frequency of operation. Capacitor values will also show some decrease over time
due to aging. The capacitor parameters are also dependant on the particular case size with smaller sizes giving
poorer performance figures in general.
As an example Figure 6 shows a typical graph showing a comparison of capacitor case sizes in a Capacitance
vs. DC Bias plot. As shown in the graph, as a result of the DC Bias condition the capacitance value may drop
below the minimum capacitance value given in the recommended capacitor table (0.7 µF in this case). Note that
the graph shows the capacitance out of spec for the 0402 case size capacitor at higher bias voltages. It is
therefore recommended that the capacitor manufacturers' specifications for the nominal value capacitor are
consulted for all conditions as some capacitor sizes (e.g. 0402) may not be suitable in the actual application.
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CAP VALUE (% OF NOM. 1 uF)
SNVS567B – APRIL 2010 – REVISED MAY 2013
0603, 10V, X5R
100%
80%
60%
0402, 6.3V, X5R
40%_
20%
_
0
1.0
2.0
_
3.0
_
4.0
_
5.0
_
DC BIAS (V)
Figure 6. Graph Showing A Typical Variation in Capacitance vs DC Bias
Ceramic capacitors have the lowest ESR values, thus making them best for eliminating high frequency noise.
The ESR of a typical 1 µF ceramic capacitor is in the range of 10 mΩ to 40 mΩ, and also meets the ESR
requirement for stability.
The temperature performance of ceramic capacitors varies by type. Capacitor type X7R is specified with a
tolerance of ±15% over the temperature range –55°C to +125°C. The X5R has a similar tolerance over the
reduced temperature range of –55°C to +85°C. Most large value ceramic capacitors (≥ 2.2 µF) are manufactured
with Z5U or Y5V temperature characteristics, which results in the capacitance dropping by more than 50% as the
temperature goes from +25°C to +85°C. Therefore X7R is recommended over these other capacitor types in
applications where the temperature will change significantly above or below +25°C.
No-Load Stability
The LDOs on the LP3923 will remain stable and in regulation with no external load.
LDO Output Capacitors, Recommended Specification (1)
(1)
26
Symbol
Parameter
Type
Typ
Min
Max
Units
CO(LDO1)
Capacitance
X5R, X7R
1.0
0.7
2.2
µF
CO(LDO2)
Capacitance
X5R, X7R
1.0
0.7
2.2
µF
CO(LDO3)
Capacitance
X5R, X7R
1.0
0.7
2.2
µF
CO(LDO4)
Capacitance
X5R, X7R
1.0
0.7
2.2
µF
CO(LDO5)
Capacitance
X5R, X7R
1.0
0.7
2.2
µF
CO(LDO6)
Capacitance
X5R, X7R
1.0
0.7
2.2
µF
CO(LDO7)
Capacitance
X5R, X7R
1.0
0.7
2.2
µF
CO(LDO8)
Capacitance
X5R, X7R
1.0
0.7
2.2
µF
The capacitor tolerance should be 30% or better over the full temperature range. X7R, or X5R capacitors should be used. These
specifications are given to ensure stability of the supply outputs and care must be taken to ensure that the capacitance remains within
these values over all conditions within the application. See Capacitor Characteristics section in Application Information.
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VBATT
-
VIN1
+
CHG_IN
AC Adapter or USB
10 µF
VIN2
BUCK OUT/VIN1
10
µF
10 µF
28V OVP & Rev.
Current Blocking
CORE
1.8V/3.0V
@300 mA
LDO1
LDO1
LILO
1 µF
1 µF
LDO3
ACOK_N
LDO2
LILO
IMON
1 µF
Charger
R3
LDO3
C3
LDO3
FLASH
1.8V/3.0V
@300 mA
LDO2
LDO3
D-type
VBATT
1 µF
DIGI
3.0V
@300 mA
SEL
1.5k
LDO3
1.5k
TCXO_EN
SDA
LDO4
SCL
Serial Interface
&
Control
PON_N
LDO4
A-type
TCXO
3.0V
@80 mA
1 µF
RX_EN
PS_HOLD
LDO5
RESET_N
VBATT
LDO5
A-type
PWR_ON
1 µF
RX
3.0V
@150 mA
HF_PWR
BUCK OUT/VIN1
1.7V...VINB
@700 mA
500k
500k
TX_EN
LDO6
LDO6
A-type
SW
1 µF
TX
3.0V
@150 mA
2.2 µH
C1
R1
FB
Buck
10 µF
C2
R2
LP3923
GNDB
LDO7
LDO7
A-type
1 µF
GP
3.0V
@150 mA
Thermal
Shutdown
VBATT
LDO8
Voltage
Reference
VINB
10 µF
LDO8
D-type
VIBRATOR
3.0V
@150 mA
1 µF
GND
UVLO
Figure 7. Typical Application Circuit
(Buck Output used as input for LILOs)
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I2C Compatible Serial Bus Interface
INTERFACE BUS OVERVIEW
The I2C compatible synchronous serial interface provides access to the programmable functions and registers on
the device.
This protocol uses a two-wire interface for bi-directional communications between the IC’s connected to the bus.
The two interface lines are the Serial Data Line (SDA), and the Serial Clock Line (SCL). These lines should be
connected to a positive supply, via a pull-up resistor of 1.5 kΩ, and remain HIGH even when the bus is idle.
Every device on the bus is assigned a unique address and acts as either a Master or a Slave depending on
whether it generates or receives the serial clock (SCL).
DATA TRANSACTIONS
One data bit is transferred during each clock pulse. Data is sampled during the high state of the serial clock
(SCL). Consequently, throughout the clock’s high period, the data should remain stable. Any changes on the
SDA line during the high state of the SCL and in the middle of a transaction, aborts the current transaction. New
data should be sent during the low SCL state. This protocol permits a single data line to transfer both
command/control information and data using the synchronous serial clock.
SDA
SCL
Data Line
Stable:
Data Valid
Change
of Data
Allowed
Figure 8. Bit Transfer
Each data transaction is composed of a Start Condition, a number of byte transfers (set by the software) and a
Stop Condition to terminate the transaction. Every byte written to the SDA bus must be 8 bits long and is
transferred with the most significant bit first. After each byte, an Acknowledge signal must follow. The following
sections provide further details of this process.
START AND STOP
The Master device on the bus always generates the Start and Stop Conditions (control codes). After a Start
Condition is generated, the bus is considered busy and it retains this status until a certain time after a Stop
Condition is generated. A high-to-low transition of the data line (SDA) while the clock (SCL) is high indicates a
Start Condition. A low-to-high transition of the SDA line while the SCL is high indicates a Stop Condition.
SDA
SCL
S
P
START CONDITION
STOP CONDITION
Figure 9. Start and Stop Conditions
In addition to the first Start Condition, a repeated Start Condition can be generated in the middle of a transaction.
This allows another device to be accessed, or a register read cycle.
ACKNOWLEDGE CYCLE
The Acknowledge Cycle consists of two signals: the acknowledge clock pulse the master sends with each byte
transferred, and the acknowledge signal sent by the receiving device.
28
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SNVS567B – APRIL 2010 – REVISED MAY 2013
The master generates the acknowledge clock pulse on the ninth clock pulse of the byte transfer. The transmitter
releases the SDA line (permits it to go high) to allow the receiver to send the acknowledge signal. The receiver
must pull down the SDA line during the acknowledge clock pulse and ensure that SDA remains low during the
high period of the clock pulse, thus signaling the correct reception of the last data byte and its readiness to
receive the next byte.
Data Output
by
Transmitter
Transmitter Stays Off the
Bus During the
Acknowledgement Clock
Data Output
by
Receiver
Acknowledgement
Signal From Receiver
SCL
1
2
3-6
7
8
9
S
Start
Condition
Figure 10. Bus Acknowledge Cycle
”ACKNOWLEDGE AFTER EVERY BYTE” RULE
The master generates an acknowledge clock pulse after each byte transfer. The receiver sends an acknowledge
signal after every byte received.
There is one exception to the “acknowledge after every byte” rule.
When the master is the receiver, it must indicate to the transmitter an end of data by not-acknowledging
(“negative acknowledge”) the last byte clocked out of the slave. This “negative acknowledge” still includes the
acknowledge clock pulse (generated by the master), but the SDA line is not pulled down.
ADDRESSING TRANSFER FORMATS
Each device on the bus has a unique slave address. The LP3923 operates as a slave device with the address
7h’7E (binary nnnnnnnn). Before any data is transmitted, the master transmits the address of the slave being
addressed. The slave device should send an acknowledge signal on the SDA line, once it recognizes its address.
The slave address is the first seven bits after a Start Condition. The direction of the data transfer (R/W) depends
on the bit sent after the slave address — the eighth bit.
When the slave address is sent, each device in the system compares this slave address with its own. If there is a
match, the device considers itself addressed and sends an acknowledge signal. Depending upon the state of the
R/W bit (1:read, 0:write), the device acts as a transmitter or a receiver.
CONTROL REGISTER WRITE CYCLE
• Master device generates start condition.
• Master device sends slave address (7 bits) and the data direction bit (r/w = '0').
• Slave device sends acknowledge signal if the slave address is correct.
• Master sends control register address (8 bits).
• Slave sends acknowledge signal.
• Master sends data byte to be written to the addressed register.
• Slave sends acknowledge signal.
• If master will send further data bytes the control register address will be incremented by one after
acknowledge signal.
• Write cycle ends when the master creates stop condition.
CONTROL REGISTER READ CYCLE
• Master device generates a start condition.
• Master device sends slave address (7 bits) and the data direction bit (r/w = '0').
• Slave device sends acknowledge signal if the slave address is correct.
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•
•
•
•
•
•
•
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Master sends control register address (8 bits).
Slave sends acknowledge signal.
Master device generates repeated start condition.
Master sends the slave address (7 bits) and the data direction bit (r/w = “1”).
Slave sends acknowledge signal if the slave address is correct.
Slave sends data byte from addressed register.
If the master device sends acknowledge signal, the control register address will be incremented by one. Slave
device sends data byte from addressed register.
Read cycle ends when the master does not generate acknowledge signal after data byte and generates stop
condition.
Address Mode (1)
Data Read
<Start Condition>
<Slave Address><r/w = ‘0’>[Ack]
<Register Addr.>[Ack]
<Repeated Start Condition>
<Slave Address><r/w = ‘1’>[Ack]
[Register Data]<Ack or NAck>
… additional reads from subsequent register address possible
<Stop Condition>
Data Write
<Start Condition>
<Slave Address><r/w = ‘0’>[Ack]
<Register Addr.>[Ack]
<Register Data>[Ack]
… additional writes to subsequent register address possible
<Stop Condition>
(1)
< > Data from master [ ] Data from slave
REGISTER READ AND WRITE DETAIL
S
Slave Address
(7 bits)
'0' A
Control Register Add.
(8 bits)
Register Data
(8 bits)
A
A P
Data transferred, byte +
Ack
R/W
From Slave to Master
A - ACKNOWLEDGE (SDA Low)
S - START CONDITION
From Master to Slave
P - STOP CONDITION
Figure 11. Register Write Format
S
Slave Address
(7 bits)
'0' A
Control Register Add.
(8 bits)
A Sr
Slave Address
(7 bits)
R/W
'1' A
R/W
Register Data
(8 bits)
A/
P
NA
Data transferred, byte +
Ack/NAck
Direction of the transfer
will change at this point
From Slave to Master
A - ACKNOWLEDGE (SDA Low)
NA - ACKNOWLEDGE (SDA High)
From Master to Slave
S - START CONDITION
Sr - REPEATED START CONDITION
P - STOP CONDITION
Figure 12. Register Read Format
30
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SNVS567B – APRIL 2010 – REVISED MAY 2013
REVISION HISTORY
Changes from Revision A (May 2013) to Revision B
•
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 30
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PACKAGE OPTION ADDENDUM
www.ti.com
8-Oct-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LP3923TL-VB/NOPB
ACTIVE
DSBGA
YZR
30
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
V020
LP3923TL-VI/NOPB
ACTIVE
DSBGA
YZR
30
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
V017
LP3923TL/NOPB
ACTIVE
DSBGA
YZR
30
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
3923
LP3923TLX-VB/NOPB
ACTIVE
DSBGA
YZR
30
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
V020
LP3923TLX/NOPB
ACTIVE
DSBGA
YZR
30
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
3923
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
8-Oct-2015
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Sep-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
LP3923TL-VB/NOPB
DSBGA
YZR
30
250
178.0
8.4
LP3923TL-VI/NOPB
DSBGA
YZR
30
250
178.0
LP3923TL/NOPB
DSBGA
YZR
30
250
178.0
LP3923TLX-VB/NOPB
DSBGA
YZR
30
3000
LP3923TLX/NOPB
DSBGA
YZR
30
3000
2.74
3.15
0.76
4.0
8.0
Q1
8.4
2.74
3.15
0.76
4.0
8.0
Q1
8.4
2.74
3.15
0.76
4.0
8.0
Q1
178.0
8.4
2.74
3.15
0.76
4.0
8.0
Q1
178.0
8.4
2.74
3.15
0.76
4.0
8.0
Q1
Pack Materials-Page 1
W
Pin1
(mm) Quadrant
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Sep-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LP3923TL-VB/NOPB
DSBGA
YZR
30
250
210.0
185.0
35.0
LP3923TL-VI/NOPB
DSBGA
YZR
30
250
210.0
185.0
35.0
LP3923TL/NOPB
DSBGA
YZR
30
250
210.0
185.0
35.0
LP3923TLX-VB/NOPB
DSBGA
YZR
30
3000
210.0
185.0
35.0
LP3923TLX/NOPB
DSBGA
YZR
30
3000
210.0
185.0
35.0
Pack Materials-Page 2
MECHANICAL DATA
YZR0030xxx
0.600±0.075
D
E
TLA30XXX (Rev C)
D: Max = 2.99 mm, Min = 2.93 mm
E: Max = 2.49 mm, Min = 2.43 mm
4215057/A
NOTES:
A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994.
B. This drawing is subject to change without notice.
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12/12
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