FDMS86550 N-Channel PowerTrench® MOSFET 60 V, 155 A, 1.65 mΩ Features General Description This N-Channel MOSFET is produced using Fairchild Semiconductor’s advanced PowerTrench® process that has been especially tailored to minimize the on-state resistance and yet maintain superior switching performance. Max rDS(on) = 1.65 mΩ at VGS = 10 V, ID = 32 A Max rDS(on) = 2.2 mΩ at VGS = 8 V, ID = 27 A Advanced Package and Silicon combination for low rDS(on) and high efficiency MSL1 robust package design Applications 100% UIL tested Primary DC-DC MOSFET RoHS Compliant Secondary Synchronous Rectifier Load Switch Bottom Top S Pin 1 D D D S S Pin 1 S D G S D S D G D D Power 56 MOSFET Maximum Ratings TA = 25 °C unless otherwise noted Symbol VDS Drain to Source Voltage Parameter VGS Gate to Source Voltage Drain Current -Continuous ID TC = 25 °C TC = 100 °C -Continuous TA = 25 °C -Pulsed PD TJ, TSTG TC = 25 °C Power Dissipation TA = 25 °C ±20 V 135 (Note 1a) 32 (Note 4) 320 (Note 3) Power Dissipation Units V 155 -Continuous Single Pulse Avalanche Energy EAS Ratings 60 937 156 (Note 1a) Operating and Storage Junction Temperature Range 2.7 -55 to +150 A mJ W °C Thermal Characteristics RθJC Thermal Resistance, Junction to Case RθJA Thermal Resistance, Junction to Ambient 0.8 (Note 1a) 45 °C/W Package Marking and Ordering Information Device Marking FDMS86550 Device FDMS86550 ©2014 Fairchild Semiconductor Corporation FDMS86550 Rev. C3 Package Power 56 Reel Size 13 ’’ 1 Tape Width 12 mm Quantity 3000 units www.fairchildsemi.com FDMS86550 N-Channel PowerTrench® MOSFET April 2014 Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics BVDSS Drain to Source Breakdown Voltage ID = 250 μA, VGS = 0 V ΔBVDSS ΔTJ Breakdown Voltage Temperature Coefficient ID = 250 μA, referenced to 25 °C IDSS Zero Gate Voltage Drain Current VDS = 48 V, VGS = 0 V 1 μA IGSS Gate to Source Leakage Current VGS = ±20 V, VDS = 0 V ±100 nA 4.5 V 60 V 31 mV/°C On Characteristics VGS(th) Gate to Source Threshold Voltage VGS = VDS, ID = 250 μA ΔVGS(th) ΔTJ Gate to Source Threshold Voltage Temperature Coefficient ID = 250 μA, referenced to 25 °C rDS(on) Static Drain to Source On Resistance gFS Forward Transconductance 2.5 3.3 -12 mV/°C VGS = 10 V, ID = 32 A 1.4 1.65 VGS = 8 V, ID = 27 A 1.7 2.2 VGS = 10 V, ID = 32 A, TJ = 125 °C 2.2 2.6 VDS = 5 V, ID = 32 A 96 mΩ S Dynamic Characteristics Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance Rg Gate Resistance VDS = 30 V, VGS = 0 V, f = 1 MHz 0.1 8235 11530 pF 2140 3000 pF 70 120 pF 0.9 2.7 Ω ns Switching Characteristics td(on) Turn-On Delay Time 43 69 tr Rise Time 43 ns td(off) Turn-Off Delay Time VDD = 30 V, ID = 32 A, VGS = 10 V, RGEN = 6 Ω 27 42 67 ns tf Fall Time 11 20 ns Qg Total Gate Charge VGS = 0 V to 10 V 110 154 nC Qg Total Gate Charge VGS = 0 V to 8 V 90 126 Qgs Gate to Source Charge Qgd Gate to Drain “Miller” Charge VDD = 30 V, ID = 32 A nC 40 nC 20 nC Drain-Source Diode Characteristics VSD Source to Drain Diode Forward Voltage trr Reverse Recovery Time Qrr Reverse Recovery Charge VGS = 0 V, IS = 2.1 A (Note 2) 0.7 1.2 VGS = 0 V, IS = 32 A (Note 2) 0.8 1.3 68 109 ns 62 99 nC IF = 32 A, di/dt = 100 A/μs V Notes: 1. RθJA is determined with the device mounted on a 1 in2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. RθJC is guaranteed by design while RθCA is determined by the user's board design. a. 45 °C/W when mounted on a 1 in2 pad of 2 oz copper. b. 115 °C/W when mounted on a minimum pad of 2 oz copper. SS SF DS DF G SS SF DS DF G 2. Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0%. 3. EAS of 937 mJ is based on starting TJ = 25 °C, L = 3 mH, IAS = 25 A, VDD = 60 V, VGS = 10 V. 100% test at L = 0.1 mH, IAS = 79 A. 4. Pulse Id refers to Figure.11 Forward Bias Safe Operation Area. ©2014 Fairchild Semiconductor Corporation FDMS86550 Rev. C3 2 www.fairchildsemi.com FDMS86550 N-Channel PowerTrench® MOSFET Electrical Characteristics TJ = 25 °C unless otherwise noted 5 NORMALIZED DRAIN TO SOURCE ON-RESISTANCE ID, DRAIN CURRENT (A) 320 VGS = 10 V VGS = 8 V 240 VGS = 7 V VGS = 6.5 V 160 VGS = 6 V VGS = 5.5 V 80 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX 0 0 1 2 3 4 VGS = 5.5 V 4 VGS = 6 V 3 VGS = 6.5 V VGS = 7 V 2 1 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX 0 80 8 SOURCE ON-RESISTANCE (mΩ) NORMALIZED DRAIN TO SOURCE ON-RESISTANCE ID = 32 A VGS = 10 V rDS(on), DRAIN TO 1.5 1.2 0.9 0 25 50 75 320 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX ID = 32 A 6 4 TJ = 125 oC 2 TJ = 25 oC 0 100 125 150 4 TJ, JUNCTION TEMPERATURE (oC) 5 6 7 8 9 10 VGS, GATE TO SOURCE VOLTAGE (V) Figure 3. Normalized On- Resistance vs Junction Temperature Figure 4. On-Resistance vs Gate to Source Voltage 320 IS, REVERSE DRAIN CURRENT (A) 320 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX 240 ID, DRAIN CURRENT (A) 240 Figure 2. Normalized On-Resistance vs Drain Current and Gate Voltage 1.8 -25 160 ID, DRAIN CURRENT (A) Figure 1. On-Region Characteristics -50 VGS = 10 V 0 5 VDS, DRAIN TO SOURCE VOLTAGE (V) 0.6 -75 VGS = 8 V VDS = 5 V 160 TJ = 150 oC TJ = 25 80 oC TJ = -55 oC 3 4 5 6 VGS = 0 V 10 TJ = 150 oC 1 TJ = 25 oC 0.1 TJ = -55 oC 0.01 0.001 0.0 0 2 100 7 0.2 0.4 0.6 0.8 1.0 VGS, GATE TO SOURCE VOLTAGE (V) VSD, BODY DIODE FORWARD VOLTAGE (V) Figure 5. Transfer Characteristics Figure 6. Source to Drain Diode Forward Voltage vs Source Current ©2014 Fairchild Semiconductor Corporation FDMS86550 Rev. C3 3 1.2 www.fairchildsemi.com FDMS86550 N-Channel PowerTrench® MOSFET Typical Characteristics TJ = 25 °C unless otherwise noted 20000 Ciss 10000 ID = 32 A 8 VDD = 20 V CAPACITANCE (pF) VGS, GATE TO SOURCE VOLTAGE (V) 10 VDD = 30 V 6 VDD = 40 V 4 Coss 1000 Crss 100 2 f = 1 MHz VGS = 0 V 0 0 30 60 90 10 0.1 120 1 10 60 VDS, DRAIN TO SOURCE VOLTAGE (V) Qg, GATE CHARGE (nC) Figure 7. Gate Charge Characteristics Figure 8. Capacitance vs Drain to Source Voltage 250 100 o ID, DRAIN CURRENT (A) IAS, AVALANCHE CURRENT (A) RθJC = 0.8 C/W TJ = 25 oC 10 TJ = 100 oC TJ = 125 oC 1 0.01 0.1 1 10 100 200 VGS = 10 V 150 VGS = 8 V 100 Limited by Package 50 0 25 1000 75 100 125 150 TC, CASE TEMPERATURE ( C) Figure 9. Unclamped Inductive Switching Capability Figure 10. Maximum Continuous Drain Current vs Case Temperature 2000 1000 5000 P(PK), PEAK TRANSIENT POWER (W) ID, DRAIN CURRENT (A) 50 o tAV, TIME IN AVALANCHE (ms) 10 μs 100 SINGLE PULSE RθJC = 0.8 oC/W TC = 25 oC 1000 10 1 THIS AREA IS LIMITED BY rDS(on) 1 ms SINGLE PULSE TJ = MAX RATED RθJC = 0.8 oC/W TC = 25 oC 0.1 0.1 100 μs 10 ms CURVE BENT TO MEASURED DATA 1 10 DC 100 200 -3 10 -2 10 -1 10 1 t, PULSE WIDTH (sec) VDS, DRAIN to SOURCE VOLTAGE (V) Figure 11. Forward Bias Safe Operating Area ©2014 Fairchild Semiconductor Corporation FDMS86550 Rev. C3 100 -4 10 Figure 12. Single Pulse Maximum Power Dissipation 4 www.fairchildsemi.com FDMS86550 N-Channel PowerTrench® MOSFET Typical Characteristics TJ = 25 °C unless otherwise noted r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE 2 1 DUTY CYCLE-DESCENDING ORDER D = 0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 0.1 t2 NOTES: ZθJC(t) = r(t) x RθJC SINGLE PULSE 0.01 -4 10 RθJC = 0.8 °C/W Peak TJ = PDM x ZθJC(t) + TC Duty Cycle, D = t1 / t2 -3 -2 10 10 -1 10 1 t, RECTANGULAR PULSE DURATION (sec) Figure 13. Transient Thermal Response Curve ©2014 Fairchild Semiconductor Corporation FDMS86550 Rev. C3 5 www.fairchildsemi.com FDMS86550 N-Channel PowerTrench® MOSFET Typical Characteristics TJ = 25 °C unless otherwise noted FDMS86550 N-Channel PowerTrench® MOSFET Dimensional Outline and Pad Layout 5.10 4.90 A 8 4.42 3.81 PKG CL B 5 8 7 6 5 1.14 KEEP OUT AREA 3.65 6.25 5.90 PKG CL 6.61 4.79 1.27 1 PIN #1 IDICATOR 4 TOP VIEW 1 2 3 4 1.27 SEE DETAIL A 0.61 3.81 5.10 LAND PATTERN RECOMMENDATION SIDE VIEW 3.81 0.10 1.27 1 C A B 0.52 0.32 (8X) (0.38) 4 (0.35) NOTES: UNLESS OTHERWISE SPECIFIED A) PACKAGE STANDARD REFERENCE: J EDEC MO-240, ISSUE A, VAR. AA, B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE BURRS OR MOLD FLASH. MOLD FLASH OR BURRS DO ES NOT EXCEED 0.10MM. D) DIMENSIONING AND TO LERANCING PER ASME Y14.5M-1994. E) IT IS RECOMMENDED TO HAVE NO TRACES OR VIAS WITHIN THE KEEP OUT AREA. F) DRAWING FILE NAME: PQFN08JREV2. E) FAIRCHILD SEMICONDUCTOR 0.75 0.55 PIN #1 INDICAT OR 4.59 4.39 8 5 4.33 4.13 0.75 0.55 BOTTOM VIEW 0.10 C 1.10 0.90 0.08 C C 0.25 0.15 0.05 0.00 SEATING PLANE DETAIL A SCALE: 2:1 Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/package/packageDetails.html?id=PN_PQDAM-008 ©2014 Fairchild Semiconductor Corporation FDMS86550 Rev. C3 6 www.fairchildsemi.com tm *Trademarks of System General Corporation, used under license by Fairchild Semiconductor. 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Fairchild will not provide any warranty coverage or other assistance for parts bought from Unauthorized Sources. Fairchild is committed to combat this global problem and encourage our customers to do their part in stopping this practice by buying direct or from authorized distributors. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative / In Design Datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production Datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. No Identification Needed Full Production Datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve the design. Obsolete Not In Production Datasheet contains specifications on a product that is discontinued by Fairchild Semiconductor. The datasheet is for reference information only. Rev. I68 ©2014 Fairchild Semiconductor Corporation FDMS86550 Rev. C3 7 www.fairchildsemi.com FDMS86550 N-Channel PowerTrench® MOSFET TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended to be an exhaustive list of all such trademarks. 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