ON NVMFD5489NLWFT3G Power mosfet Datasheet

NVMFD5489NL
Power MOSFET
60 V, 65 mW, 12 A, Dual N−Ch Logic Level
Features
•
•
•
•
•
•
•
Small Footprint (5x6 mm) for Compact Designs
Low RDS(on) to Minimize Conduction Losses
Low Capacitance to Minimize Driver Losses
175°C Operating Temperature
NVMFD5489NLWF − Wettable Flank Option for Enhanced Optical
Inspection
AEC−Q101 Qualified and PPAP Capable
This is a Pb−Free Device
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V(BR)DSS
Drain−to−Source Voltage
Gate−to−Source Voltage
Continuous Drain Current RJ−mb
(Notes 1, 2, 3, 4)
Power Dissipation
RJ−mb (Notes 1, 2, 3)
Continuous Drain Current RJA
(Notes 1, 3 & 4)
Power Dissipation
RJA (Notes 1 & 3)
Pulsed Drain Current
Tmb = 25°C
Steady
State
65 m @ 10 V
12 A
79 m @ 4.5 V
Value
Unit
VDSS
60
V
VGS
"20
V
ID
12
A
TA = 25°C
PD
23.4
Operating Junction and Storage Temperature
Source Current (Body Diode)
Single Pulse Drain−to−Source Avalanche
Energy (TJ = 25°C, IL(pk) = 19.5 A, L = 0.1 mH,
RG = 25 )
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
W
4.5
ID
A
3.2
W
1.5
IDM
62
A
TJ, Tstg
−55 to
175
°C
IS
22
A
EAS
19
mJ
TL
260
°C
Symbol
Value
RJ−mb
6.4
Junction−to−Ambient − Steady State (Note 3)
Junction−to−Ambient − Steady State
(min footprint)
Unit
161
1. The entire application environment impacts the thermal resistance values shown,
they are not constants and are only valid for the particular conditions noted.
2. Psi () is used as required per JESD51−12 for packages in which
substantially less than 100% of the heat flows to single case surface.
3. Surface−mounted on FR4 board using a 650 mm2, 2 oz. Cu pad.
4. Continuous DC current rating. Maximum current for pulses as long as 1
second are higher but are dependent on pulse duration and duty cycle.
© Semiconductor Components Industries, LLC, 2015
May, 2015 − Rev. 3
D1 D1
1
S1
G1
S2
G2
XXXXXX
AYWZZ
D1
D1
D2
D2
D2 D2
XXXXXX = 5489NL
XXXXXX = (NVMFD5489NL) or
XXXXXX = 5489LW
XXXXXX = (NVMFD5489NLWF)
A
= Assembly Location
Y
= Year
W
= Work Week
ZZ
= Lot Traceability
ORDERING INFORMATION
Package
Shipping†
NVMFD5489NLT1G
DFN8
1500/
(Pb−Free) Tape & Reel
NVMFD5489NLT3G
DFN8
5000/
(Pb−Free) Tape & Reel
NVMFD5489NLWFT1G
DFN8
1500/
(Pb−Free) Tape & Reel
NVMFD5489NLWFT3G
DFN8
5000/
(Pb−Free) Tape & Reel
°C/W
50
RJA
DFN8 5x6
(SO8FL)
CASE 506BT
Device
THERMAL RESISTANCE MAXIMUM RATINGS (Note 1)
Parameter
MARKING DIAGRAM
1
3.0
PD
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
Junction−to−Mounting Board (top) − Steady
State (Notes 2, 3)
S2
S1
11.7
TA = 100°C
TA = 25°C, tp = 10 s
G2
G1
TA = 100°C
TA = 25°C
D2
D1
8.8
Tmb = 100°C
Steady
State
Dual N−Channel
Symbol
Tmb = 100°C
Tmb = 25°C
ID MAX
60 V
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Parameter
RDS(on) MAX
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Publication Order Number:
NVMFD5489NL/D
NVMFD5489NL
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified)
Parameter
Symbol
Test Condition
Min
Drain−to−Source Breakdown Voltage
V(BR)DSS
VGS = 0 V, ID = 250 A
60
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V(BR)DSS/TJ
Reference to 25°C
ID = 250 A
Typ
Max
Unit
OFF CHARACTERISTICS
V
67
TJ = 25°C
mV/°C
1.0
Zero Gate Voltage Drain Current
IDSS
Gate−to−Source Leakage Current
IGSS
VDS = 0 V, VGS = ±20 V
VGS(TH)
VGS = VDS, ID = 250 A
VGS(TH)/TJ
Reference to 25°C
ID = 250 A
4.86
RDS(on)
VGS = 10 V, ID = 15 A
52
65
VGS = 4.5 V, ID = 7.5 A
66
79
VGS = 0 V,
VDS = 60 V
TJ = 125°C
A
10
±100
nA
2.5
V
ON CHARACTERISTICS (Note 5)
Gate Threshold Voltage
Negative Threshold Temperature Coefficient
Drain−to−Source On Resistance
1.5
mV/°C
m
CHARGES AND CAPACITANCES
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
330
VGS = 0 V, f = 1.0 MHz, VDS = 25 V
Crss
39
Total Gate Charge
QG(TOT)
12.4
Threshold Gate Charge
QG(TH)
0.31
Gate−to−Source Charge
QGS
Gate−to−Drain Charge
QGD
4.74
td(on)
7
VGS = 10 V, VDS = 48 V,
ID = 6 A
pF
80
nC
1.3
SWITCHING CHARACTERISTICS (Note 6)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
tr
td(off)
VGS = 10 V, VDS = 48 V,
ID = 6 A, RG = 2.5 tf
ns
11
31
21
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
Reverse Recovery Time
VSD
TJ = 25°C
0.83
TJ = 125°C
0.71
tRR
Charge Time
ta
Discharge Time
tb
Reverse Recovery Charge
VGS = 0 V,
IS = 10 A
24.2
VGS = 0 V, dIS/dt = 100 A/s,
IS = 10 A
QRR
1.2
V
ns
20.2
4.0
26.5
nC
nH
PACKAGE PARASITIC VALUES
Source Inductance
LS
0.93
Drain Inductance
LD
0.005
Gate Inductance
LG
Gate Resistance
RG
TA = 25°C
1.84
12
5. Pulse Test: pulse width = 300 s, duty cycle v 2%.
6. Switching characteristics are independent of operating junction temperatures.
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2
NVMFD5489NL
TYPICAL CHARACTERISTICS
VGS = 10 to 6.5 V
25
5.5 V
4.5 V
4.3 V
20
4.1 V
3.9 V
15
3.7 V
10
3.5 V
5
3.3 V
3.1 V
3.0 V
2.7 V
0
1
2
3
4
15
10
TJ = 25°C
5
TJ = 125°C
1
5
TJ = −55°C
2
3
4
5
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
VGS, GATE−TO−SOURCE VOLTAGE (V)
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
0.090
0.086
ID = 10 A
TJ = 25°C
0.082
0.078
0.074
0.070
0.066
0.062
0.058
0.054
0.050
4
5
6
7
8
9
10
0.11
0.10
TJ = 25°C
0.09
VGS = 4.5 V
0.08
0.07
VGS = 10 V
0.06
0.05
0.04
0.03
0.02
2
4
8
6
10
12
16
14
18
20
VGS, GATE−TO−SOURCE VOLTAGE (V)
ID, DRAIN CURRENT (A)
Figure 3. On−Resistance vs. VGS
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
1.0E−04
2.3
2.1
20
0
ID = 7.5 A
VGS = 10 V
1.9
1.7
1.5
1.3
1.1
0.9
1.0E−06
1.0E−08
1.0E−09
1.0E−10
1.0E−11
0.5
−50 −25
1.0E−12
25
50
75
100
125
150
175
TJ = 125°C
1.0E−07
0.7
0
TJ = 150°C
1.0E−05
IDSS, LEAKAGE (A)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (m)
0
RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED)
ID, DRAIN CURRENT (A)
VDS = 10 V
25
RDS(on), DRAIN−TO−SOURCE RESISTANCE (m)
ID, DRAIN CURRENT (A)
30
TJ = 25°C
5
10
15
20
25
30
35
40
45
50
55 60
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
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NVMFD5489NL
TYPICAL CHARACTERISTICS
TJ = 25°C
VGS = 0 V
500
C, CAPACITANCE (pF)
VGS, GATE−TO−SOURCE VOLTAGE (V)
600
400
Ciss
300
200
Coss
100
Crss
0
0
10
20
30
40
50
60
QT
9
8
7
TJ = 25°C
6
5
Qgs
4
Qgd
3
VDD = 48 V
VGS = 10 V
ID = 6 A
2
1
0
0
2
4
6
8
10
14
12
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Qg, TOTAL GATE CHARGE (nC)
Figure 7. Capacitance Variation
Figure 8. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge
10
1000
VDD = 48 V
VGS = 10 V
ID = 6 A
IS, SOURCE CURRENT (A)
9
100
td(off)
tf
tr
10
td(on)
TJ = 25°C
VGS = 0 V
8
7
6
5
4
3
2
1
0
1
1
10
0
100
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
RG, GATE RESISTANCE ()
VSD, SOURCE−TO−DRAIN VOLTAGE (V)
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
100
ID, DRAIN CURRENT (A)
t, TIME (ns)
10
100 s
1 ms
10
10 s
10 ms
dc
1
TC = 25°C
VGS = 10 V
Single Pulse
0.1
RDS(on) Limit
Thermal Limit
Package Limit
0.01
0.1
1
10
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
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4
100
NVMFD5489NL
TYPICAL CHARACTERISTICS
100
50% Duty Cycle
R(t) (°C/W)
10
1
20%
10%
5%
2%
1%
0.1
Single Pulse
0.01
0.001
0.000001
0.00001
0.0001
0.001
0.01
0.1
PULSE TIME (sec)
Figure 12. Thermal Response
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5
1
10
100
1000
NVMFD5489NL
PACKAGE DIMENSIONS
DFN8 5x6, 1.27P Dual Flag (SO8FL−Dual)
CASE 506BT
ISSUE E
2X
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED
BETWEEN 0.15 AND 0.30 MM FROM THE TERMINAL TIP.
4. PROFILE TOLERANCE APPLIES TO THE EXPOSED PAD AS WELL
AS THE TERMINALS.
5. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS.
6. SEATING PLANE IS DEFINED BY THE TERMINALS. A1 IS DEFINED
AS THE DISTANCE FROM THE SEATING PLANE TO THE LOWEST
POINT ON THE PACKAGE BODY.
7. A VISUAL INDICATOR FOR PIN 1 MUST BE LOCATED IN THIS AREA.
0.20 C
D
A
B
D1
8
7
6
ÉÉ
ÉÉ
ÉÉ
PIN ONE
IDENTIFIER
NOTE 7
1
2
2X
0.20 C
5
E1 E
4X
h
c
3
A1
4
TOP VIEW
DETAIL B
0.10 C
DETAIL A
A
SOLDERING FOOTPRINT*
0.10 C
NOTE 4
ALTERNATE
CONSTRUCTION
C
SIDE VIEW
DETAIL A
SEATING
PLANE
NOTE 6
4.56
2X
8X
D2
D3
4X
e
1
2X
2.08
0.75
0.56
L
K
4
4X
4.84
DETAIL B
1.40
2.30
M
b1
MILLIMETERS
MAX
MIN
MAX
−−−
0.90
1.10
−−−
−−−
0.05
0.33
0.42
0.51
0.33
0.42
0.51
0.20
−−−
0.33
5.15 BSC
4.70
4.90
5.10
3.90
4.10
4.30
1.50
1.70
1.90
6.15 BSC
5.70
5.90
6.10
3.90
4.15
4.40
1.27 BSC
0.45
0.55
0.65
−−−
−−−
12 _
0.51
−−−
−−−
0.56
−−−
−−−
0.48
0.61
0.71
3.25
3.50
3.75
1.80
2.00
2.20
6.59
3.70
4X
N
DIM
A
A1
b
b1
c
D
D1
D2
D3
E
E1
E2
e
G
h
K
K1
L
M
N
E2
0.70
4X
G
8
5
8X
K1
BOTTOM VIEW
b
0.10
C A B
0.05
C
4X
1.27
PITCH
5.55
1.00
NOTE 3
DIMENSION: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC
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limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
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