Honeywell HX6408-QFM 512k x 8 static ram Datasheet

HX6408
Advanced Information
HX6408
512k x 8 STATIC RAM
The 512K x 8 Radiation Hardened Static RAM is a high
The RICMOS™ V low power process is a SOI CMOS
performance 524,288 word x 8-bit static random access
technology with an 80 Å gate oxide and a minimum
memory with optional industry-standard functionality. It is
drawn feature size of 0.35 µm. Additional features
fabricated with Honeywell’s radiation hardened Silicon On
include tungsten via and contact plugs, Honeywell’s
Insulator (SOI) technology, and is designed for use in low
proprietary SHARP planarization process and a lightly
voltage systems operating in radiation environments. The
doped drain (LDD) structure for improved short
RAM operates over the full military temperature range and
channel reliability. A seven transistor (7T) memory cell
requires only a single 3.3 V ± 0.3V power supply. Power
is used for superior single event upset hardening,
consumption is typically <30 mW @ 1MHz in write mode,
while three layer metal power busing and the low
<14 mW @ 1MHz in read mode, and is less than 5 mW
collection volume SOI substrate provide improved
when in standby mode.
dose rate hardening.
Honeywell’s enhanced RICMOS™(Radiation Insensitive
CMOS) SOI V technology is radiation hardened through the
use of advanced and proprietary design, layout and process
hardening techniques.
FEATURES
ƒ
Fabricated with RICMOS™ V
Silicon On Insulator (SOI)
ƒ
0.35 mm Process (Leff = 0.28 µm)
ƒ
1
5
6
Total Dose ≥ 3x10 and 1X10 rad(SiO2)
14
-2
ƒ
Neutron ≥1x10 cm
ƒ
Dynamic and Static Transient Upset
≥1x1010 rad(Si)/s (3.3 V)
ƒ
Dose Rate Survivability ≥1x1012 rad(Si)/s
ƒ
Soft Error Rate
≤1x10-10 Upsets/bit-day (3.3 V)
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ƒ
No Latchup
ƒ
ƒ
Read/Write Cycle Times
≤20 ns, (3.3 V), -55 to 125°C
Single Power Supply,
3.3 V ± 0.3 V
ƒ
ƒ
Typical Operating Power (3.3 V)
<14 mW @ 1MHz Read
<30 mW @ 1MHz Write
<5 mW Standby mode
Operating Range is
-55°C to +125°C
ƒ
36-Lead Flat Pack Package
ƒ
Optional Low Power Sleep
Mode
ƒ
Asynchronous Operation
ƒ
CMOS Compatible I/O
HX6408
Advanced Information
36 LEAD FLAT PACK PINOUT
Address
Decoder
FUNCTIONAL DIAGRAM
An
Memory
Array
NSL
NCS
Timing \ Control
NWE
NOE
DQ(0:7)
WE • CS
NWE • CS
All controls must be enabled
for signal to pass.
# = number of buffers,
Default = 1
1 = enabled
Signal
#
A0
1
A1
2
A2
HX6408
Top View
36
(NSL)
35
A18
3
34
A17
A3
4
33
A16
A4
5
32
A15
NCS
6
31
NOE
D0
7
30
D4
D1
8
29
D5
VDD
9
28
VSS
VSS
10
27
VDD
D2
11
26
D6
D3
12
25
D7
NWE 13
24
A14
A5 14
23
A13
A6 15
22
A12
A7 16
21
A11
A8 17
20
A10
A9 18
19
NAS
Signal
SIGNAL DEFINITIONS
2
A: 0-18
Address input pins, which select a particular eight-bit word within the memory array.
DQ: 0-7
Bidirectional data pins, which serve as data outputs during a read operation and as data inputs
during a write operation.
NCS
Negative chip select, when at a low level allows normal read or write operation. When at a high level
NCS forces the SRAM to a precharge condition, holds the data output drivers in a high impedance
state. If this signal is not used it must be connected to VSS.
NWE
Negative write enable, when at a low level activates a write operation and holds the data output
drivers in a high impedance state. When at a high level NWE allows normal read operation.
NOE
Negative output enable, when at a high level holds the data output drivers in a high impedance
state. When at a low level, the data output driver state is defined by NCS, NWE and NSL. This
signal is asynchronous.
NSL
Not sleep, when at a high level allows normal operation. When at a low level NSL forces the SRAM
to a precharge condition, holds the data output drivers in a high impedance state and disables all the
input buffers except the NCS and NOE input buffers. If this signal is not used it must be connected
to VDD. This signal is asynchronous. The HX6408 may be ordered without the sleep mode option
and pin 36 is then a NC.
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HX6408
Advanced Information
TRUTH TABLE
NCS
L
L
H
X
NSL
H
H
X
L
NWE
H
L
X
X
NOE
L
X
X
X
Mode
Read
Write
Deselected
Sleep
DQ
Data Out
Data In
High Z
High Z
X: VI = VIH or VIL,
NOE=H:
High Z output state maintained for NCS=X, NWE=X
RADIATION
Total Ionizing Radiation Dose
The SRAM will meet all stated functional and electrical
specifications over the entire operating temperature
range after the specified total ionizing radiation dose.
All electrical and timing performance parameters will
remain within specifications. Total dose hardness is
assured by wafer level testing of process monitor
transistors and RAM product using 10 KeV X-ray.
Transistor gate threshold shift correlations have been
made between 10 KeV X-rays applied at a dose rate of
1x105 rad(SiO2)/min at T= 25°C and gamma rays
(Cobalt 60 source) to ensure that wafer level X-ray
testing is consistent with standard military radiation test
environments.
Transient Pulse Ionizing Radiation
The SRAM is capable of writing, reading, and retaining
stored data during and after exposure to a transient
ionizing radiation pulse, up to the specified transient
dose rate upset specification, when applied under
recommended operating conditions. It is recommended
to provide external power supply decoupling capacitors
to maintain VDD voltage levels during transient events.
The SRAM will meet any functional or electrical
specification after exposure to a radiation pulse up to
the transient dose rate survivability specification, when
applied under recommended operating conditions.
Note that the current conducted during the pulse by the
RAM inputs, outputs, and power supply may
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significantly exceed the normal operating levels. The
application design must accommodate these effects.
Neutron Radiation
The SRAM will meet any functional or timing
specification after exposure to the specified neutron
fluence under recommended operating or storage
conditions. This assumes an equivalent neutron energy
of 1 MeV.
Soft Error Rate
The SRAM is capable of meeting the specified Soft
Error Rate (SER), under recommended operating
conditions.
This hardness level is defined by the Adams 90%
worst case cosmic ray environment for
geosynchronous orbits.
Latchup
The SRAM will not latch up due to any of the above
radiation exposure conditions when applied under
recommended operating conditions. Fabrication with
the SOI substrate material provides oxide isolation
between adjacent PMOS and NMOS transistors and
eliminates any potential SCR latchup structures.
Sufficient transistor body tie connections to the p- and
n-channel substrates are made to ensure no
source/drain snapback occurs.
HX6408
Advanced Information
RADIATION HARDNESS RATINGS (1)
Parameter
Limits (2)
Units
Test Conditions
rad(SiO2)
TA=25°C
Transient Dose Rate Upset
≥3X10
≥1X106
10
≥1X10
rad(Si)/s
Transient Dose Rate Survivability
≥1X10
12
rad(Si)/s
Soft Error Rate
<1X10-10
Upsets/bit-day
Neutron Fluence
≥1X1014
N/cm2
Pulse width ≤50 ns
VDD>3.6V, TA=25°C
Pulse width ≤50 ns, Xray,VDD=3.6V,
TA=25°C
TA= 85°C, Adams 90%
worst case environment
1MeV equivalent
energy, Unbiased,
TA=25°C
Total Dose
(1)
(2)
5
Device will not latch up due to any of the specified radiation exposure conditions.
o
o
Operating conditions (unless otherwise specified): VDD=3.0V to 3.6V, TA=-55 C to 125 C
ABSOLUTE MAXIMUM RATINGS (1)
Symbol
Parameter
VDD
VPIN
TSTORE
TSOLDER
PD
IOUT
VPROT
ΘJC
Supply Voltage Range (2)
Voltage on Any Pin (2)
Storage Temperature (Zero Bias)
Soldering Temperature (5 seconds)
Maximum Power Dissipation (3)
DC or Average Output Current
EST Input Protection Voltage (4)
Thermal Resistance (Jct-to-Case)
TJ
Junction Temperature
(1)
(2)
(3)
(4)
Rating
Units
Min
Max
-0.5
-0.5
-65
4.6
VDD+0.5
150
270
2.5
25
2
V
V
°C
°C
W
mA
V
°C/W
175
°C
2000
36 Pin FP
Stresses in excess of those listed above may result in permanent damage. These are stress ratings only, and operation at these levels is
not implied. Frequent or extended exposure to absolute maximum conditions may affect device reliability.
Voltage referenced to VSS.
RAM power dissipation (IDDSB + IDDOP) plus RAM output driver power dissipation due to external loading must not exceed this
specification.
Class 2 electrostatic discharge (ESD) input protection. Tested per MIL-STD-883, Method 3015 by DSEC certified lab.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
VDD
TA
VPIN
VDDRAMP
4
Supply Voltage (referenced to VSS)
Ambient Temperature
Voltage on Any Pin (referenced to VSS)
VDD Turn on ramp time
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3.0
-55
-0.3
Description
Typ
Max
3.3
25
3.6
125
VDD+0.3
50
Units
V
°C
V
ms
HX6408
Advanced Information
DC ELECTRICAL CHARACTERISTICS
Symbol
Parameter
IDDSB
II
IOZ
Static Supply Current
TA=25°C
TA=125°C
Static Supply Current
Deselected
Dynamic Supply Current,
Selected (Write)
1 MHz
2 MHz
10 MHz
25 MHz
40 MHz
Dynamic Supply Current,
Selected (Read)
1 MHz
2 MHz
10 MHz
25 MHz
40 MHz
Dynamic Supply Current,
Deselected
Dynamic Supply Current,
Sleep
Input Leakage Current
Output Leakage Current
VIL
VIH
VOL
VOH
Low-Level Input Voltage
High-Level Input Voltage
Low-Level Output Voltage
High-Level Output Voltage
IDDOP3
IDDOPW
IDDOPR
IDDOP1
IDDOP2
(1)
(2)
Worst Case (1)
Min
Max
Units
Test Conditions
5
10
24
mA
9
18
89
160
260
mA/MHz
VDD=max, Iout=0mA,
NSL=VIH, NCS=VIL (1)
4
8
40
100
160
1.5
mA/MHz
VDD=max, Iout=0mA,
NSL=VIH, NCS=VIL (1)
mA
0.2
mA
5
10
µA
µA
0.3xVDD
V
V
V
V
VDD=max, Iout=0mA,
f=1MHz, NSL=VIH (2)
VDD=max, Iout=0mA,
f=1MHz, NSL=VIL (2)
Vss VI VDD
Vss VIO
VDD output = high Z
VDD=3.0V
VDD=3.6V
VDD=3.0V, IOL = 8mA
VDD=3.0V, IOH = 4mA
-5
-10
0.7xVDD
0.4
2.7
mA
VDD=max, Iout=0mA,
Inputs Stable
VDD=max, Iout=0mA,
f=fmax, NSL=NCS=VIH (2)
Worst case operating conditions: VDD=3.0V to 3.6V, -55°C to +125°C, post total dose at 25°C.
All inputs switching. DC average current.
CAPACITANCE (1)
Symbol
Parameter
CI
CO
Input Capacitance
Output Capacitance
Worst Case (1)
Min
Max
9
8
Units
Test Conditions
pF
pF
VI=VDD or VSS, f=1 MHz
VIO=VDD or VSS, f=1 MHz
(1) This parameter is tested during initial design characterization only.
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HX6408
Advanced Information
DATA RETENTION CHARACTERISTICS
Symbol
Parameter
Typical
(1)
VDR
Data Retention Voltage
IDR
Data Retention Current
Worst Case (2)
Min
Max
Units
2.0
V
3
mA
Test Conditions
NCS=VDR
VI=VDR or VSS
NCS=VDD=VDR
VI=VRD or VSS
(1) Typical operating conditions: TA=25°C, pre-radiation.
(2) Worst case operating conditions: TA=-55°C to +125°C, post dose at 25°C
TESTER EQUIVALENT LOAD CIRCUIT
Valid High
Output
1.9V
V1
DUT
Output
249
Valid Low
Output
V2
CL < 50 pf *
* CL = 5pf for TWQZ, TSHQZ, TPLQZ, and TGHQZ
Tester AC Timing Characteristics
Input Levels *
VDD
VSS
* Input rise and fall times <5 ns.
Output Sense
Levels
VDD/2
VDD – 0.4V
High Z = VDD/2
High Z
0.4V
(VDD/2) + 0.2V
High Z
(VDD/2) - 0.2V
6
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HX6408
Advanced Information
ASYCHRONOUS READ CYCLE AC TIMING CHARACTERISTICS (1)
Symbol
Parameter
TAVAVR
Address Read Cycle Time
TAVQV
Address Access Time
TAXQX
TSLQV
Address Change to Output Invalid Time
Chip Select Access Time
TSLQX
TSHQZ
TPHQV
TPHQX
TPLQZ
TGLQV
TGLQX
TGHQZ
Chip Select Output Enable Time
Chip Select Output Disable Time
Sleep Enable Access Time
Sleep Enable Output Enable Time
Sleep Enable Output Disable Time
Output Enable Access Time
Output Enable Output Enable Time
Output Enable Output Disable Time
(1)
(2)
(3)
Typical
(2)
300KRad
1MRad
300KRad
1MRad
Worst Case (3)
-55 to 125°C
Min
Max
20
25
ns
20
25
3
300KRad
1MRad
20
25
4
8
25
5
10
5
0
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Test conditions: input switching levels, VIL/VIH=0V/3V, input rise and fall times <1 ns/V, input and output timing reference levels shown in
the Tester AC Timing Characteristics table, capacitive output loading CL≥50 pF, or equivalent capacitive output loading CL=5 pF for
TSHQZ, TPLQZ TGHQZ. For CL>50 pF, derate access times by 0.02 ns/pF (typical).
Typical operating conditions: VDD=3.3V, TA=25°C, pre-radiation.
Worst case operating conditions: VDD=3.0V to 3.6V, TA=-55°C to 125°C, post total dose 25°C at
TAVAVR
ADDRESS
TAVQV
TAXQX
TSLQV
NCS
TSLQX
DATA OUT
HIGH
IMPEDANCE
TSHQZ
DATA VALID
TPHQX
TPLQZ
TPHQV
NSL
TGLQX
TGLQV
NOE
7
Units
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TGHQZ
HX6408
Advanced Information
ASYNCHRONOUS WRITE CYCLE AC TIMING CHARACTERISTICS (1)
Symbol
Parameter
TAVAVW
Write Cycle Time (4)
TWLWH
Write Enable Write Pulse Width
TSLWH
Chip Select to End of Write Time
TDVWH
Data Valid to End of Write Time
TAVWH
Address Valid to End of Write Time
TWHDX
TAVWL
TWHAX
TWLQZ
TWHQX
TWHWL
Data Hold after End of Write Time
Address Valid Setup to Start of Write Time
Address Valid Hold after End of Write Time
Write Enable to Output Disable Time
Write Disable to Output Enable Time
Write Disable to Write Enable Pulse Width (5)
(1)
(2)
(3)
(4)
(5)
Worst Case (3)
-55 to 125°C
Min
Max
Typical
(2)
300KRad
1MRad
300KRad
1MRad
300KRad
1MRad
300KRad
1MRad
300KRad
1MRad
20
25
15
20
16
20
12
15
20
25
0
0
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Test conditions: input switching levels, VIL/VIH=0V/3V, input rise and fall times <1 ns/V, input and output timing reference levels shown in
the Tester AC Timing Characteristics table, capacitive output loading ≥50 pF, or equivalent capacitive load 5 pF for TWLQZ.
Typical operating conditions: VDD=3.3V, TA=25°C, pre-radiation.
Worst case operating conditions: VDD=3.0V to 3.6V, -55°C to 125°C, post total dose 25°C
TAVAVW = TWLWH + TWHWL
Guaranteed but not tested
TAVAVW
ADDRESS
TAVWH
TWHAX
TAVWL
TWLWH
TWHWL
NWE
TWHQX
TWLQZ
DATA OUT
HIGH
IMPEDANCE
TDVWH
DATA IN
DATA VALID
TSLWH
NCS
TPHWH
NSL
8
ns
7
4
5
Units
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TWHDX
HX6408
Advanced Information
DYNAMIC ELECTRICAL CHARACTERISTICS
Asynchronous Operation
The RAM is asynchronous in operation. Read and
Write cycles are controlled by NWE, NCS, NSL, and
Address signals.
Read Operation
To perform a valid read operation, both chip select
and output enable (NOE) must be low and not sleep
(NSL) and write enable (NWE) must be high. The
output drivers can be controlled independently by the
NOE signal.
To perform consecutive read operations, NCS is
required to be held continuously low, NSL held
continuously high, and the toggling of the addresses
will start the new read cycle.
It is important to have the address bus free of noise
and glitches, which can cause inadvertent read
operations. The control and address signals should
have rising and falling edges that are fast (<5 ns) and
have good signal integrity (free of noise, ringing or
steps associated reflections).
For an address activated read cycle, NCS and NSL
must be valid prior to or coincident with the address
edge transition(s). Any amount of toggling or skew
between address edge transitions is permissible;
however, data outputs will become valid TAVQV time
following the latest occurring address edge transition.
The minimum address activated read cycle time is
TAVAV. When the RAM is operated at the minimum
address activated read cycle time, the data outputs
will remain valid on the RAM I/O until TAXQX time
following the next sequential address transition.
To control a read cycle with NCS, all addresses and
NSL must be valid prior to or coincident with the
enabling NCS edge transition. Address or NSL edge
transitions can occur later than the specified setup
times to NCS; however, the valid data access time will
be delayed. Any address edge transition, which
occurs during the time when NCS is low, will initiate a
new read access, and data outputs will not become
valid until TAVQV time following the address edge
transition. Data outputs will enter a high impedance
state TSHQZ time following a disabling NCS edge
transition.
To control a read cycle with NSL, all addresses and
NCS must be valid prior to or coincident with the
enabling NSL edge transition. Address or NCS edge
transitions can occur later than the specified setup
times to NSL; however, the valid data access time will
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be delayed. Any address edge transition, which
occurs during the time when NSL is high will initiate a
new read access, and data outputs will not become
valid until TAVQV time following the address edge
transition. Data outputs will enter a high impedance
state TPLQZ time following a disabling NSL edge
transition.
Write Operation
To perform a write operation, both NWE and NCS
must be low, and NSL must be high.
Consecutive write cycles can be performed by
toggling one of the control signals while the other
remains in their “write” state (NWE or NCS held
continuously low, or NSL held continuously high). At
least one of the control signals must transition to the
opposite state between consecutive write operations.
The write mode can be controlled via three different
control signals: NWE, NCS, and NSL. All three modes
of control are similar, except the NCS and NSL
controlled modes actually disable the RAM during the
write recovery pulse. NSL fully disables the RAM
decode logic and input buffers for power savings.
Only the NWE controlled mode is shown in the table
and diagram on the previous page for simplicity;
however, each mode of control provides the same
write cycle timing characteristics. Thus, some of the
parameter names referenced below are not shown in
the write cycle table or diagram, but indicate which
control pin is in control as it switches high or low. To
write data into the RAM, NWE and NCS must be held
low and NSL must be held high for at least
WLWH/TSLSH/TPHPH time. Any amount of edge
skew between the signals can be tolerated, and any
one of the control signals can initiate or terminate the
write operation. The DATA IN must be valid TDVWH
time prior to switching high.
For consecutive write operations, write pulses (NWE)
must be separated by the minimum specified
WHWL/TSHSL/TPLPL time. Address inputs must be
valid at least TAVWL/TAVSL/TAVPH time before the
enabling NWE/NCS/NSL edge transition, and must
remain valid during the entire write time. A valid data
overlap of write pulse width time of TDVWH/TDVSH/
TDVPL, and an address valid to end of write time of
TAVWH/TAVSH/TAVPL also must be provided for
during the write operation. Hold times for address
inputs and data inputs with respect to the disabling
NWE/NCS/NSL edge transition must be a minimum of
TWHAX/TSHAX/TPLPX time and TWHDX/TSHDX
HX6408
Advanced Information
/TPLDX time, respectively. The minimum write cycle
time is TAVAV.
QUALITY AND RADIATION HARDNESS ASSURANCE
Honeywell maintains a high level of product integrity
through process control, utilizing statistical process
control, a complete
“Total Quality Assurance System,” a computer data
base process performance tracking system and a
radiation-hardness assurance strategy.
The radiation hardness assurance strategy starts with
a technology that is resistant to the effects of
radiation. Radiation hardness is assured on every
wafer by irradiating test structures as well as SRAM
product, and then monitoring key parameters, which
are sensitive to ionizing radiation. Conventional MILSTD-883 TM 5005 Group E testing, which includes
total dose exposure with Cobalt 60, may also be
performed as required. This Total Quality approach
ensures our customers of a reliable product. It starts
with process development and continuing through
product qualification and screening.
SCREENING LEVELS
Honeywell offers several levels of device screening to
meet your system needs. “Engineering Devices” are
available with limited performance and screening for
operational evaluation testing. Hi-Rel Level B and S
devices undergo additional screening per the
requirements of MILSTD-883. As a QML supplier,
Honeywell also offers QML Class Q and V devices
per MIL-PRF-38535 and are available per the
applicable Standard Microcircuit Drawing (SMD). QML
devices offer ease of procurement by eliminating the
need to create detailed specifications and offer
benefits of improved quality and cost savings through
standardization.
RELIABILITY
Honeywell understands the stringent reliability
requirements for space and defense systems and has
extensive experience in reliability testing on programs
of this nature. This experience is derived from
comprehensive testing of VLSI processes. Reliability
attributes of the RICMOS™ SOI process were
characterized by testing specially designed irradiated
and non-irradiated test structures from which specific
failure mechanisms were evaluated. These specific
mechanisms included, but were not limited to, hot
carriers, electromigration and time dependent
dielectric breakdown. This data was then used to
make changes to the design models and process to
ensure more reliable products.
In addition, the reliability of the RICMOS™ SOI
process and product in a military environment is
monitored by testing
irradiated and non-irradiated circuits in accelerated
dynamic life test conditions. Packages were qualified
for product use after undergoing Groups B & D testing
as outlined in MIL-STD-883, TM 5005, Class S.
Quality conformance testing is performed as an option
on all production lots to ensure the ongoing reliability
of the product.
PACKAGING
The 512K x 8 SRAM is offered in a commercially
compatible 36-lead flat pack. This package is
constructed of multi-layer ceramic (Al2O3) and
contains internal power and ground planes.
Parentheses denote pin options. These pins are
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available as NC to conform to commercial
standards. All NC (no connect) pins should be
connected to VSS to prevent charge build up in
the radiation environment.
HX6408
Advanced Information
PACKAGE OUTLINE
COMMON DIMENSIONS
SYM
A
A1
B
C
D
E
E1
L
Q
MIN.
.102
.085
.016
.004
.910
.045
.832
---------
NOM.
.113
.095
.018
.006
.920
.050
.840
.450
.104
MAX.
.125
.105
.020
.008
.930
.055
.848
---------
ORDERING INFORMATION (1)
H
X
6408
PART NUMBER
PROCESS
X = SOI
X
S
H
SCREEN LEVEL
N
MODE (3)
V = QML Class V Equivalent (4)
Q = QML Class Q Equivalent (4)
S = Level S
E = Eng. Model (2)
N = Non-Sleep Mode
M = Sleep Mode
Source
H = Honeywell
PACKAGE DESIGNATION
X = 36 Lead FP
K = Known Good Die
- = Bare Die (no package)
TOTAL DOSE HARDNESS
5
R = 1x10 rad (SiO2)
5
F = 3x10 rad (SiO2)
6
H = 1x10 rad (SiO2)
N = No Level Guaranteed (2)
(1) Orders may be faxed to 763-954-2051. Please contact our Customer Service Representative at 763-954-2888 for further information.
(2) Engineering Device Description: Parameters are tested -55°C to 125°C, 24 hour burn-in, IDDSB = 10 mA, no radiation Guaranteed.
(3) With the Non-Sleep Mode option, Pin 36 is a no-connect (NC), and is not wirebonded to the chip. With the Sleep Mode, Pin 36 has the
NSL function.
(4) These devices are screened to QML levels but are not QML certified.
For more information about Honeywell’s family of radiation hardened integrated circuit products and services,
visit www.myspaceparts.com.
Honeywell reserves the right to make changes to any products or technology herein to improve reliability, function or design. Honeywell does not assume any
liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of
others.
Honeywell International Inc.
Aerospace Electronics Systems
Defense & Space Electronics Systems
12001 Highway 55
Plymouth, MN 55441
11
www.honeywell.com
1-800-323-8295
Form #900918
June 2005
©2005 Honeywell International Inc.
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