UL
LSI/CSI
®
LS7267
LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747
(631) 271-0400 FAX (631) 271-0405
A3800
24-BIT DUAL-AXIS QUADRATURE COUNTER
FEATURES:
OCT 2015
PIN ASSIGNMENT
TOP VIEW
LSI
YLCNTR/YLOL
1
28
FCK
2
27
YFLG1
V DD (+5V)
3
26
YFLG2
D0
4
25
YA
D1
5
24
YB
D2
6
23
XFLG2
D3
7
22
XFLG1
D4
8
21
XB
D5
9
20
XA
D6
10
19
XLCNTR/XLOL
D7
11
18
XRCNTR/XABG
V SS (GND ) 12
17
X/Y
C/D 13
16
RD
WR 14
15
CS
LS7267
• Up to 50MHz count frequency in non-quadrature mode;
Up to 5.6MHz clock frequency (22 x 106 counts/sec) in
x4 quadrature mode.
• Dual 24-bit counters to support X and Y axes in
motion control applications. • Dual 24-bit comparators.
• Digital filtering of the input quadrature clocks
• Programmable 8-bit separate filter clock prescalers
for each axis.
• Error flags for noise exceeding filter band width.
• Programmable Index Input and other programmable I/Os.
• Independent mode programmability for each axis.
• Programmable count modes:
Quadrature (x1, x2, x4) / Non-quadrature,
Normal / Modulo-N / Range Limit / Non-Recycle,
Binary / BCD.
• 8-bit 3-State data I/O bus.
• 3V to 5.5V operation (VDD - VSS).
• TTL/CMOS compatible I/Os.
• LS7267 (DIP); LS7267-S (SOIC); LS7267-TS (TSSOP)
YRCNTR/YABG
LS7267 Registers:
LS7267 has a set of registers associated with each X and Y axis. All X-axis registers have the name prefix X,
whereas all Y-axis registers have the prefix Y. Selection of a specific register for Read/Write is made from the decode
of the three most significant bits (D7 - D5) of the data-bus. CS input enables the IC for Read/Write. C/D input selects
between control and data information for Read/Write. Following is a complete list of LS7267 registers.
Preset Registers: XPR and YPR
Each of these PRs are 24-bit wide. 24-bit data can be written into a PR, one byte at a time, in a sequence of three data
write cycles.
PR
7
0 7
HI BYTE
(PR2)
0 7
MID BYTE
(PR1)
0
LO BYTE
(PR0)
Counters: XCNTR and YCNTR
Each of these CNTRs are 24-bit synchronous Up/Down counters. The count clocks for each CNTR is derived from its
associated A/B inputs. Each CNTR can be loaded with the content of its associated PR.
Output Latches: XOL and YOL
Each OL is 24-bits wide. In effect, the OLs are the output ports for the CNTRs. Data from each CNTR can be loaded
into its associated OL and then read back on the data-bus, one byte at a time, in a sequence of three data Read
cycles.
OL
7
HI BYTE
(OL2)
0 7
0 7
MID BYTE
(OL1)
0
LO BYTE
(OL0)
Byte Pointers: XBP and YBP
The Read and Write operations on an OL or a PR always accesses one byte at a time. The byte that is accessed is
addressed by one of the BPs. At the end of every data Read or Write cycle on an OL or a PR, the associated BP is
automatically incremented to address the next byte.
7267-102215-1
Flag Register: XFLAG and YFLAG
The FLAG registers hold the status information of the CNTRs and can be read on the data bus. All bits excepting
the E and the IDX bits change dynamically to represent the instantaneous status of the CNTR's. In contrast the E
and the IDX bits are latched. Once set they can only be reset via the RLD registers.
FLAG
7
6
5
4
3
2
1
0
BT: Borrow Toggle flip-flop.
Toggles every time CNTR underflows.
CT: Carry toggle flip-flop.
Toggles every time CNTR overflows.
CPT: Compare toggle flip-flop.
Toggles every time PR equals CNTR.
S: Sign flag. Set to 1 when CNTR underflows.
Reset to 0 when CNTR overflows.
E: Error latch. Set to 1 when parameter t4 or t5 is violated (see p.8 for t4 and t5)
Irrelevant in non-quadrature mode.
U/D: Up/Down flag. Set to 1 when counting up
and reset to 0 when counting down.
IDX: Index. Set to 1 when designated index input transitions to active level.
0: Not used. Always reset to 0.
Filter Clock Prescalers: XPSC and YPSC
Each PSC is an 8-bit programmable modulo-n down counter, driven by the FCK input. The division factor n is stored
into each PSC from its associated PR register low byte, PR0. The PSCs provide the ability to generate independent
filter clock frequencies for each channel used for filtering the quadrature clocks applied at the A and B inputs in
quadrature mode.The same filter clocks are also used for filtering the designated INDEX inputs.
The effective internal filter clock frequency is: fFCKn = ( fFCK/(n+1) ) , where n = PSC = 0 to h'FF and fFCK is the clock
frequency at the FCK input. For proper operation the required condition is: fFCKn > 8fQA (or 8fQB), where fQA (or fQB)
is the frequency at A (or B) input. The FCK pin is not used in non-quadrature mode and should be tied off to VDD.
Reset and Load Signal Decoders: XRLD and YRLD
Following functions can be performed by writing a control byte into an RLD: Transfer PR to CNTR, Transfer
CNTR to OL, reset CNTR, reset FLAG and reset BP.
RLD
7
6
5
4
3
2
1
0
0: NOP
1: Reset BP
0
0
1
0
: Reset CNTR
0
1
: Reset BT, CT, CPT,S, IDX
1
1
0
0
1
0
0
1
1
1
7267-091615-2
: NOP
: Reset E
: NOP
: Transfer PR to CNTR
(Note: All 24-bits are transferred in parallel)
: Transfer CNTR to OL
(Note: All 24-bits are transferred in parallel)
: Transfer PR0 to PSC
0
0
: Select RLD
0
: Select the RLD addressed by X/Y input
1
: Select both XRLD and YRLD together
(Note: D7 = 1 overrides X/Y input)
Counter Mode Registers: XCMR and YCMR
The CNTR operational mode is programmed by writing into the CMRs.
CMR
7
6
5
4
3
2
1
0
0:
1:
Binary count
BCD count
0
0
: Normal count
1
0
: Range Limit
0
1
: Non-recycle count
1
1
0
0
1
0
0
1
1
1
: Modulo-N
: Non-quadrature
: Quadrature X1
: Quadrature X2
: Quadrature X4
1
: Select CMR
0
0: Select CMR addressed by X/Y input
1: Select both XCMR and YCMR together (Note: D7=1 overrides X/Y input)
DEFINITIONS OF COUNT MODES:
Range Limit. In range limit count mode, an upper and a lower limit is set, mimicking limit switches in the mechanical counterpart. The upper limit is set by the content of the PR and the lower limit is set to be 0. The
CNTR freezes at CNTR = PR when counting up and at CNTR = 0 when counting down. At either of these limits,
the counting is resumed only when the count direction is reversed.
Non-Recycle. In non-recycle count mode, the CNTR is disabled, whenever a count overflow or underflow takes
place. The end of cycle is marked by the generation of a Carry (in Up Count) or a Borrow (in Down Count). The
CNTR is re-enabled when a reset or load operation is performed on the CNTR.
Modulo-N. In modulo-N count mode, a count boundary is set between 0 and the content of PR. When counting
up, at CNTR = PR, the CNTR is reset to 0 and the up count is continued from that point. When counting down,
at CNTR = 0, the CNTR is loaded with the content of PR and down count is continued from that point.
The modulo-N is true bidirectional in that the divide-by-N output frequency is generated in both up and down direction of counting for same N and does not require the complement of N in the UP instance. In frequency divider application, the modulo-N output frequency can be obtained at either the Compare (FLG1) or the Borrow
(FLG2) output. Modulo-N output frequency, fN = (fi / (N+ 1) ) where fi = Input count frequency and N = PR.
The information included herein is believed to be
accurate and reliable. However, LSI Computer Systems,
Inc. assumes no responsibilities for inaccuracies, nor for
any infringements of patent rights of others which may
result from its use.
7267-112612-3
Input/Output Control Register: XIOR and YIOR
The functional modes of the programmable input and output pins are configured by writing into the IORs.
IOR
7
6
5
4
3
2
1
0
0 : Disable inputs A and B
1 : Enable inputs A and B
0 : LCNTR/LOL pin is Load CNTR input
1 : LCNTR/LOL pin is Load OL input
0 : RCNTR/ABG pin is Reset CNTR input
1 : RCNTR/ABG pin is A and B Enable gate
0
0
1
0
0
1
1
1
0
1
: FLG1 pin is CARRY output; FLG2 pin is BORROW output
: FLG1 pin is COMPARE output; FLG2 pin is BORROW output
: FLG1 pin is Carry/Borrow output and FLG2 pin is U/D (FLAG register bit 5)
: FLG1 is INDX (low pulse at INDEX pin active level); FLG2 is E (FLAG register bit 4)
(For FLG1 to output INDX, IDR bit0 must be set to 1)
: Select IOR
0: Select IOR addressed by X/Y input
1: Select both XIOR and YIOR together (Note: D7=1 overrides X/Y input)
INDEX CONTROL REGISTERS: XIDR and YIDR
Either the LCNTR/LOL or the RCNTR/ABG inputs can be initialized to operate in the INDEX mode. In the
INDEX mode the index signal from an encoder, applied to one of the two inputs performs either reset_CNTR,
Load_CNTR or Load_OL operation synchronously with the quadrature clocks, the internal load or reset signal
being generated at the same angular orientation of the encoder in both CW and CCW directions. In contrast in
non-INDEX mode these signals are applied asynchronously with respect to A/B inputs and act instantaneously.
The index mode is unconditionally disabled in non-quadrature mode.
IDR
7
6
5
4
3
2
1
0
0: Disable Index mode
1: Enable Index mode
0: Negative Index Polarity
1: Positive Index Polarity
0: LCNTR/LOL pin in index mode (See Note 1)
1: RCNTR/ABG pin in index mode (See Note 2)
Not used
1
1
:
: Select IDR
0: Select IDR addressed by X/Y input
1: Select both XIDR and YIDR (Note: D7=1 overrides X/Y input)
Note 1: Function selected for this pin via IOR, becomes the operating INDEX function.
Note 2: RCNTR/ABG input must also be initialized as the reset_CNTR input via IOR
Note 3: “Enable Index mode” causes the synchronous mode for the selected input (Pin 1, 18, 19 and 28)
to be enabled. “Disable Index mode” causes the asynchronous mode for the selected pin to be enabled.
The input, however, is not disabled in either configuration.
7267-112612-4
I/O pins:
Following is a description of all the input/output pins.
YLCNTR/YLOL/ (pin 1). Input. Programmable input in
the y-axis which can be configured with the YIOR
register to function as either LD_YCNTR or LD_YOL
input. LD_YCNTR causes the YPR to be loaded into
YCNTR when the input is at active level. LD_YOL
causes YCNTR to be loaded into YOL when the input is
at active level.
In quadrature mode the input can further be initialized
with the YIDR register to function in either INDEX mode
or non-INDEX mode. The INDEX mode allows for the
direct interface with the INDEX output of an incremental
encoder. In this mode the YLCNTR/YLOL/ input is
sampled with the filter clock derived from the FCK input
clock which is used for validating the quadrature clocks
as well
In the INDEX mode the YCLNTR/YLOL/ input can be
configured for either high or low active logic levels with
the YIDR. In the non-INDEX mode the active level is not
programmable and is unconditionally set to low active.
In the non-INDEX mode YCLNTR/YLOL/ input is not
sampled with the filter clock and can be applied
asynchronously with respect to YA and YB inputs. In
non-quadrature mode the YCLNTR/YLOL/ input is
unconditionally set to the non-INDEX mode.
FCK. (pin 2). Input. A clock applied at the FCK input is
used for generating filter clocks for both X and Y axes.
The filter clocks are used for validating the quadrature
clocks (at XA, XB, YA and YB inputs), and the INDEX
signal ( at XLCNTR/XLOL/ or XRCNTR/ or
YLCNTR/YLOL/ or YRCNTR in INDEX mode). The clock
at the FCK input is divided down separately by XPSC
and YPSC prescalers to generate the filter clock for each
axis. The prescaler output frequency is given by:
fFCKn = fFCK/(n+1), where fFCK is the frequency at the FCK
input and n = [XPSC] or [YPSC].
For proper operation in the quadrature mode the
following condition of frequencies must be satisfied:
fFCKn ≥ 8fQAB, where fQAB is the clock frequency at XA or
XB or YA or YB input..
In non-quadrature mode the filter clock is not used and
the FCK input must be tied off to either VDD or VSS.
VDD (pin 3). Supply voltage positive rail. +3V to +5V.
D0 through D7 (pins 4 through 11). Inputs/Outputs. The
8-bit databus D0 through D7 is a 3-state portal for the
READ/WRITE operation in and of the device. The
databus is common to both axes. During a read
operation when both CS/ and RD/ inputs are low, the
content of either the OL or the FLAG register of the
selected axis is placed on databus. During a write
operation the content of the databus is written into the
selected register at the trailing edge of the WR/ pulse.
7267-091615-5
When CS/ is high the databus is disabled and placed in
the high impedance state.
VSS (pin 12). Supply voltage negative rail or GND.
D/C (pin 13). Input. This input selects between a control
register or a data register for read/write operation
according to Table 1. When low, a write operation
causes the content of the databus to be written into the
selected PR register. When high, a write causes the
databus to be written into the selected control register.
During a read operation, a low at the D/C input causes
the content of the selected OL to be output on the
databus while a high causes the content of the selected
FLAG register to be output on the databus.
WR/ (pin 14). Input. A low pulse at the WR/ input causes
the content of the databus to be written into the selected
register according to Table 1. The write operation is
completed at the trailing edge of the WR/ pulse.
CS/ (pin 15). Input. A low at the CS/ input enables the
device for read or write operations. When the CS/ input
is high the read and write operations are disabled and
the databus, D0-D7 is placed in the high impedance
state.
RD/ (pin 16). Input. A low at the RD/ input causes the
content of the selected register to be output on the
databus according to Table 1.
X/Y (pin 17). Input. Selects between X and Y axis for
read and write. A low at this input selects the X axis
while a high selects the Y axis.
XRCNTR/XABG (pin 18). Input. Programmable input in
the x-axis which can be configured with the XIOR
register to function as either R_XCNTR or E_XAB input.
R_XCNTR causes the XCNTR to be reset to 0 when the
input is in the active level. E_XAB causes the input to
function as the XA and XB enable/disable gate. In this
mode XA and XB become enabled when the
XRCNTR/XABG input is high and disabled when the
input is low,
In quadrature mode the input can further be initialized
with the XIDR register to function in either INDEX mode
or non-INDEX mode. In the INDEX mode the
XRCNTR/XABG is sampled with the filter clock derived
from the FCK input clock which is used for validating the
quadrature clocks as well.
When configured in the INDEX mode the
XRCNTR/XABG input must also be configured as
R_XCNTR to function correctly. In the INDEX mode the
XRCNTR/XABG input can be configured for either high
or low active logic levels for the R_XCNTR function via
the XIDR register. In the non-INDEX mode the active
level is not programmable and is unconditionally set to
low active for the R_XCNTR function.
In the non-INDEX mode XRCNTR/XABG input is not
sampled with the filter clock and can be applied
asynchronously with respect to XA and XB inputs. In
non-quadrature mode the XCNTR/XABG input is
unconditionally set to the asynchronous mode
XLCNTR/XLOL/ (pin 19). Input. This is the x-axis
functional equivalent of the YCLNTR/YLOL input. The
associated x-axis reference registers are: XCNTR, XOL,
XIOR and XIDR
XA (pin 20), XB (pin 21). Inputs. These are the A and B
count inputs in the x-axis. These inputs can be
configured to function either in quadrature mode or in
non-quadrature mode. The configuration is made with
the XCMR register. In quadrature mode, XA and XB
clocks are normally supplied from incremental encoders
with the two clocks being 90º out of phase. When XA
leads XB in phase, the counter (XCNTR) counts up;
when XA lags XB, the XCNTR counts down.
In non-quadrature mode XA functions as the count input
and XB as the count direction control input. When XB is
high positive transitions at the XA input causes the
XCNTR to count up. Conversely, when XB is low
positive transitions at the XA input causes the XCNTR to
count down.
In quadrature mode XA and XB inputs are sampled for
logic level validation and noise discrimination with an
internal filter clock derived from the FCK input clock. In
non-quadrature mode XA and XB inputs are not sampled
and the count clocks are applied directly to the XCNTR
count input bypassing the filter circuit.
XFLG1 (pin 22). Output. Programmable output in the xaxis to function as CARRY or BORROW or COMPARE
or INDX. The configuration is made with the XIOR
register. The output is generated as a low pulse when
the selected event takes place CARRY or BORROW
output is generated when the XCNTR overflows or
underflows respectively. INDX output is generated when
the designated INDEX input goes into active level.
COMPARE output is generated at XCNTR = XPR. An
exception is made in the modulo-N and range-limit
modes In these modes the COMPARE output is
generated at XCNTR = XPR only in the up count
direction.
XFLG2 (pin 23). Output. Programmable output in the xaxis to function as BORROW or UP/DN or E. The
configuration is made with the XIOR register. The
BORROW output is generated as a low pulse when the
XCNTR underflows. When configured as UP/DN the
output dynamically goes high when the XCNTR is
counting up and low when it is counting down. When
configured as E the output sets to 1 whenever the
following condition exists: t4. ≤ t3 or t5. ≤ 2t3 (see page 8).
Once set it remains set until the FLAG register bit-4 is
reset.
YA (pin25), YB (pin 24). Inputs. These are the y-axis
functional equivalents of the XA and XB inputs. They
operate on the YCNTR and are configured with the
YCMR register.
7267-042313-6
YFLG2 (pin26), Output. This is the y-axis functional
equivalent of XFLG2 .
YFLG1 (pin27), Output. This is the y-axis functional
equivalent of XFLG1
YRCNTR/YABG (pin 28). Input. This is the y-axis
functional equivalent of the XRCNTR/XABG input. The
associated y-axis reference registers are: YCNTR, YOL,
YIOR and YIDR .
LS7267
uC
CLK
Pn<0:7 >
FCK
D<0:7>
WR/
Px<0:3>
RD/
CS/
X/Y
A
A
B
B
INDEX
RCNTR/
Encoder
A Typical Application
REGISTER ADDRESSING MODES (Table 1)
D7
D6
D5
C/D
RD
WR
X/Y
CS
X
X
X
X
X
X
X
1
Disable both axes for Read/Write
X
X
X
0
1
0
0
Write to XPR byte segment addressed by XBP (Note 3)
X
X
X
0
1
1
0
Write to YPR byte segment addressed by YBP (Note 3)
0
0
0
1
1
0
0
Write to XRLD
0
0
0
1
1
1
0
Write to YRLD
1
0
0
1
1
X
0
Write to both XRLD and YRLD
0
0
1
1
1
0
0
Write to XCMR
0
0
1
1
1
1
0
Write to YCMR
1
0
1
1
1
X
0
Write to both XCMR and YCMR
0
1
0
1
1
0
0
Write to XIOR
0
1
0
1
1
1
0
Write to YIOR
1
1
0
1
1
X
0
Write to both XIOR and YIOR
1
1
1
0
0
Write to XIDR
1
1
0
Write to YIDR
X
0
Write to both XIDR and YIDR
0
1
FUNCTION
0
1
1
1
1
1
1
1
1
X
X
X
0
0
1
0
0
Read XOL byte segment addressed by XBP (Note 3)
X
X
X
0
0
1
1
0
Read YOL byte segment addressed by YBP (Note 3)
X
X
X
1
0
1
0
0
Read XFLAG
X
X
X
1
0
1
1
0
Read YFLAG
X = Don't Care
Note 4: Relevant BP is automatically incremented at the trailing edge of RD or WR pulse
Absolute Maximum Ratings:
Parameter
Symbol
Supply Voltage
VDD
Voltage at any input
VIN
Operating Temperature
TA
Storage Temperature
TSTG
Values
+7.0
VSS - 0.3 to VDD + 0.3
-25 to +80
-65 to +150
Unit
V
V
oC
oC
DC Electrical Characteristics. (TA = -25˚C to +80°C, VDD = 3V to 5.5V)
Parameter
Supply Voltage
Supply Current
Input Logic Low
Input Logic High
Output Low Voltage
Output High Voltage
Input Leakage Current
Data Bus Leakage Current
Output Source Current
Output Sink Current
7267-112612-7
Symbol
VDD
IDD
VIL
VIH
VOL
VOH
IILK
IDLK
IOSRC
IOSNK
Min. Value
3.0
0.5VDD
VDD - 0.5
1.0
5.0
Max.Value
5.5
800
0.15VDD
0.5
30
60
-
Unit
V
µA
V
V
V
V
nA
nA
mA
mA
Remarks
All clocks off
IOSNK = 5mA , VDD = 5V
IOSRC = 1mA , VDD = 5V
Data bus off
VO = VDD - 0.5V, VDD = 5V
VO = 0.5V, VDD = 5V
Transient Characteristics. (TA = -25˚C to +80˚C)
Parameter
For VDD = 3V to 5.5V:
Read Cycle (See Fig. 1)
RD Pulse Width
CS Set-up Time
CS Hold Time
C/D Set-up Time
C/D Hold Time
X/Y Set-up Time
X/Y Hold Time
Data Bus Access Time
Symbol
Min. Value
Max.Value
Unit
Remarks
tr1
tr2
tr3
tr4
tr5
tr6
tr7
tr8
80
80
0
80
10
80
10
80
-
ns
ns
ns
ns
ns
ns
ns
ns
Data Bus Release Time
tr9
-
35
ns
Back to Back Read delay
tr10
90
-
ns
Access starts when both RD
and CS are low.
Release starts when either RD
or CS is terminated.
-
Write Cycle (See Fig. 2)
WR Pulse Width
CS Set-up Time
CS Hold Time
C/D Set-up Time
C/D Hold Time
X/Y Set-up Time
X/Y Hold Time
Data Bus Set-up Time
Data Bus Hold Time
Back to Back Write Delay
tW1
tW2
tW3
tW4
tW5
tW6
tW7
tW8
tW9
tW10
45
45
0
45
10
45
10
45
10
90
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
-
Load CNTR, Reset CNTR and
Load OL Pulse Width
t11
35
-
ns
-
For VDD = 3V:
Quadrature Mode (See Fig. 3-5)
FCK High Pulse Width
FCK Low Pulse Width
FCK Frequency
Mod-n Filter Clock(FCKn)Period
t1
t2
fFCK
t3
18
18
36
27
-
ns
ns
MHz
ns
-
40
160
4t3
36
76
5
27
3.1
5t3
-
MHz
ns
ns
MHz
ns
ns
ns
FCKn frequency
fFCKn
Quadrature Separation
t4
Quadrature Clock Pulse Width
t5
Quadrature Clock frequency
fQA, fQB
Quadrature Clock to Count Delay tQ1
x1/x2/x4 Count Clock Pulse Width tQ2
Index Input Pulse Width
tidx
Index setup/hold time
tsi/thi
INDX Output Width
Carry/Borrow/Compare Output Width
tQ3
tQ3
Non-Quadrature Mode (See Fig. 6-7)
Clock A - High Pulse Width
t6
Clock A - Low Pulse Width
t7
Direction Input B Set-up Time
tbS
Direction Input B Hold Time
tbh
Gate Input (ABG) Set-up Time
tGS
Gate Input (ABG) Hold Time
tGH
Clock Frequency
fA
Clock to Carry or Borrow Out Delay
t9
Carry or Borrow Out Pulse Width
t10
Clock to Compare Out Delay
t12
7267-091615-8
18
18
18
18
20
10
20
10
18
-
-
27
20
30
ns
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
ns
-
-
t3 = (n+1) (t1+t2),
where n = PSC = 0 to FFH
t4 > t3
t5 >4t3
fQA = fQB = 1/(2t5)
tQ2 = t3
tidx > 2t3
tQ3 = (t3 - t2)
tQ3 = (t3 - t2)
-
fA = (1/ (t6 + t7) )
t10 = t7
-
Parameter
Symbol
Min. Value
Max.Value
Unit
For VDD = 5V:
Quadrature Mode (See Fig. 3-5)
FCK High Pulse Width
FCK Low Pulse Width
FCK Frequency
Mod-n Filter Clock(FCKn)Period
t1
t2
fFCK
t3
10
10
20
50
-
FCKn frequency
Quadrature Separation
Quadrature Clock Pulse Width
Quadrature Clock frequency
Quadrature Clock to Count Delay
x1/x2/x4 Count Clock Pulse Width
Index Input Pulse Width
Index setup/hold time
fFCKn
t4
t5
fQA, fQB
tQ1
tQ2
tidx
tsi/thi
22
88
4t3
20
42
5
50
5.6
5t3
-
MHz
ns
ns
MHz
ns
ns
ns
tQ3
10
-
ns
INDX output width
Carry/Borrow/Compare Output Width
tQ3
10
-
-
ns
ns
MHz
ns
ns
Remarks
-
t3 = (n+1) (t1+t2),
where n = PSC = 0 to FFH
t4 > t3
t5 > 4t3
fQA = fQB = 1/(2t5)
tQ2 = t3
tidx > 2t3
tQ3 = (t3 - t2)
tQ3 = (t3 - t2)
Non-Quadrature Mode (See Fig. 6-7)
Clock A - High Pulse Width
t6
Clock A - Low Pulse Width
t7
Direction Input B Set-up Time
tbs
Direction Input B Hold Time
tbh
Gate Input (ABG) Set-up Time
tGS
Gate Input (ABG) Hold Time
tGH
Clock Frequency
fA
10
10
12
5
12
5
-
50
ns
ns
ns
ns
ns
ns
MHz
fA
t9
t10
t12
10
-
10
15
ns
ns
ns
t10 = t7
-
Clock to Carry or Borrow Out Delay
Carry or Borrow Out Pulse Width
Clock to Compare Out Delay
7267-091615-9
-
= (1/ (t6 + t7) )
tr1
tr10
RD
tr3
tr2
CS
C/D
tr4
tr5
tr6
tr7
X/Y
tr8
tr9
DB
VALID
DATA
VALID DATA
FIGURE 1. READ CYCLE
tw1
tw10
WR
tw2
CS
C/D
tw3
tw4
tw5
tw6
tw7
tw8
tw9
X/Y
DB
INPUT DATA
INPUT DATA
FIGURE 2. WRITE CYCLE
t1
FCK
t3
FCKn
(Note 4)
A
t2
t5
t4
t4
t4
t4
B
t5
FIGURE 3. FILTER CLOCK FCK AND QUADRATURE CLOCKS A AND B
Note 4: FCKn is the final modulo-n internal filter clock, arbitrarily shown here as modulo-1.
7267-042613-10
UP
DOWN
A
tQ1
B
X4_CLK
tQ2
X2_CLK
CNTR advances
X1_CLK
Fig 4. A/B quadrature clocks and internal count clocks in X1, X2 and X4 modes
UP
DOWN
A
thi
B
tsi
INDEX
tidx
X4_CLK
CNTR
fffffd
fffffe
ffffff
0
INDX (FLG1)
1
2
3
2
1
0
ffffff
fffffe
fffffd
tQ3
CY/ (FLG1)
BW/ (FLG2)
tQ3
tQ3
CMP/ (FLG1
tQ3
Note. CMP/ signal is arbitrarily shown to be generated at CNTR = fffffe
Note. In modulo-N and range-limit modes the CMP/ output is generated in up count only
Note. INDEX signal must overlap quarter cycle of both A and B high or both A and B low. Shown here both low.
Fig 5. FLG1 and FLG2 outputs in quadrature count mode
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DOWN
UP
DIRECTION (B)
DOWN
tbh
tbs
COUNT IN (A)
tGS
tGH
GATE (ABG)
COUNT DISABLE
COUNT ENABLE
FIGURE 6. COUNT (A), DIRECTION (B) AND GATE (ABG) INPUTS IN NON-QUADRATURE MODE
A
B
t9
CY
t10
t9
CNTR DISABLED
BW
CNTR DISABLED
CNTR DISABLED
1
0
999998 999999
CNTR
2
1
0
0
999999
N
999999
N-1
N-2
CNTR ENABLED
RCNTR
CNTR ENABLED
t11
CNTR ENABLED
LCNTR
t11
FIGURE 7.
NON-RECYCLE, NON-QUADRATURE, BCD MODE
A
B
CNTR
UP
0
1
2
DOWN
3
0
1
2
1
0
3
2
1
0
3
2
t12
COMP
BW
FIGURE 8. MODULO - N, NON-QUADRATURE (Shown with N = 3)
A
B
CNTR
DOWN
UP
0
1
2
3
4 (CNTR FROZEN)
3
2
UP
1
0 (CNTR FROZEN)
COMP
BW
FIGURE 9. RANGE LIMIT, NON-QUADRATURE (Shown with PR = 4)
7267-042713-12
1
2
8
WRITE
INPUT REG
(8)
FLAG
(8)
SBYTE0
8
SBYTE2
8
PR2
SBYTE1
8
(8)
PR1
8
8
(8)
PR0
(8)
SBYTE2
RLD
8
8
SBYTE1
BP
SBYTE0
CMR
IOR
IDR
24
PRO
8
CNTR
PSC
(24)
(8)
24
FCK
FCK PRESCALER
DIRECTION
FCKn
24
ERROR
COMPARATOR
(24)
COUNT CLOCK
BYTE 0
DIRECTION
BYTE 1
BYTE 2
8
OL2
SBYTE1
(8)
OL1
8
B
8
8
SBYTE2
A
CLOCK
GEN/FILTER
(8)
8
SBYTE0
OL0
(8)
8
8
INTERNAL BUS
8
READ/WRITE
I/O BUF
8
DATA-BUS
FIGURE 10. SINGLE-AXIS BLOCK DIAGRAM SHOWING MAJOR DATA PATHS
77267-042713-13
C Sample Routines for Interfacing with LS7266R1
#include<stdlib.h>
#include <stdio.h>
#include <conio.h>
#define XDATA(arg) (arg +0)
#define XCMD (arg) (arg + 1)
#define YDATA (arg) (arg +2)
#define YCMD (arg) (arg +3)
// RLD Reg.
#define RLD (arg) (arg | 0x80)
#define XRLD (arg) (arg | 0)
#define YRLD (arg) XRLD(arg)
#define Rst_BP 0x01
#define Rst_CNTR 0x02
#define Rst_FLAGS 0x04
#define Rst_E 0x06
#define Trf_PR_CNTR 0x08
#define Trf_CNTR_OL 0x10
#define Trf_PS0_PSC 0x18
//CMR Reg.
#define CMR(arg) (arg | 0xA0)
#define XCMR(arg) (arg | 0x20)
#define YCMR(arg) XCMR(arg)
#define BINCnt
0x00
#define BCDCnt 0x01
#define NrmCnt 0x00
#define RngLmt 0x02
#define NRcyc
0x04
#define ModN
0x06
#define NQDX 0x00
#define QDX1
0x08
#define QDX2
0x10
#define QDX4
0x18
//IOR Reg.
#define IOR(arg) (arg | 0xC0)
#define XIOR(arg) (arg | 0x40)
#define YIOR(arg) XIOR(arg)
#define DisAB 0x00
#define EnAB
0x01
void Init_7266(int Addr);
/* Initialize 7266 as follows (X + Y CNTR)
Modulo N count mode for N = 0x123456
Binary Counting
Index on LCNTR/LOL Input
CY and BW outputs
RCNTR/ABG controls Counters
A and B Enabled
*/
void Init_7266(int Addr)
{
/Setup IOR Reg.
outp(XCMD(Addr),IOR(DisAB + LOL + ABGate + CYBW));
#define LCNTR
#define LOL
#define RCNTR
#define ABGate
#define CYBW
#define CPBW
#define CB_UPDN
#define IDX_ERR
// IDR
#define IDR(arg) (arg | 0xE0)
#define XIDR(arg) (arg | 0x60)
#define YIDR(arg) XIDR(arg)
#define DisIDX 0x00
#define EnIDX 0x01
#define NIDX
0x00
#define PIDX 0x02
#define LIDX 0x00
#define RIDX
0x04
//Disable Counters and Set CY BW Mode
//Setup RLD Reg.
outp(XCMD(Addr),RLD(Rst_BP + Rst_FLAGS)); //Reset Byte Pointer(BP) And Flags
outp(XDATA(Addr),0x06);
//Load 6 to PR0 to setup Transfer to PS0
outp(YDATA(Addr),0x06);
//Load 6 to PR0 to setup Transfer to PS0
outp(XCMD(Addr),RLD(Rst_E + Trf_PS0_PSC)); //Reset E Flag and Transfer PR0 to PSC
outp(XCMD(Addr),RLD(Rst_BP + Rst_CNTR));
//Reset BP and Reset Counter
//Setup IDR Reg.
outp(XCMD(Addr),IDR(EnIDX + NIDX + LIDX)); //Enable Negative Index on LCNTR/LOL Input
//Setup CMR Reg.
outp(XCMD(Addr),CMR(BINCnt + ModN + QDX4)); //Set Binary Mondulo N Quadrature x4
7267-042713-14
0x00
0x02
0x00
0x04
0x00
0x08
0x10
0x18
//Setup PR Reg. for Modulo N Counter to 0x123456
outp(XDATA(Addr),0x56); //Least significant Byte first
outp(XDATA(Addr),0x34); //then middle byte
outp(XDATA(Addr),0x12); //then most significant byte
//Setup PR Reg. for Modulo N Counter to 0x123456
outp(YDATA(Addr),0x56); //Least significant Byte first
outp(YDATA(Addr),0x34); //then middle byte
outp(YDATA(Addr),0x12); //then most significant byte
//Enable Counters
outp(XCMD(Addr),IOR(EnAB));
}
/* Write_7266_PR
Input: Addr has Address of 7266 counter.
Data: has 24 bit data to be written to PR register
*/
void Write_7266_PR(int Addr,unsigned long Data);
void Write_7266_PR(int Addr,unsigned long Data)
{
outp(XCMD(Addr),RLD(Rst_BP));
//Reset Byte Pointer to Synchronize Byte Writing
outp(XDATA(Addr),(unsigned char)Data);
Data >>= 8;
outp (XDATA(Addr),(unsigned char)Data);
Data >>= 8;
outp(XDATA(Addr),(unsigned char)Data);
}
/* Read_7266_OL
Input: Addr has Address of 7266 counter.
Output: Data returns 24 bit OL register value.
*/
unsigned long Read_7266_OL(int Addr);
unsigned long Read_7266_OL(int Addr)
{ unsigned long Data=0;
outp(XCMD(Addr),(RLD(Rst_BP + Trf_Cntr_OL)); //Reset Byte Pointer to Synchronize Byte reading and
Transferring of data from counters to OL.
Data |=(unsigned long)inp(XDATA(Addr));
//read byte 0 from OL
lrotr(Data,8);
//Rotate for next Byte
Data |=(unsigned long)inp(XDATA(Addr));
//read byte 1 from OL
lrotr(Data,8);
//Rotate for next Byte
Data |=(unsigned long)inp(XDATA(Addr)); //read byte 2 from OL
lrotr(Data,16);
//Rotate for last Byte
return(Data);
}
/* Get_7266_Flags
Input: Addr has Address of 7266 counter.
returns Flags of counter
*/
unsigned char Get_7266_Flags(int Addr);
unsigned char Get_7266_Flags(int Addr)
{
return(inp(CMD(Addr)));
}
7267-042713-15