Sample & Buy Product Folder Support & Community Tools & Software Technical Documents LMC6482 SNOS674E – NOVEMBER 1997 – REVISED APRIL 2015 LMC6482 CMOS Dual Rail-to-Rail Input and Output Operational Amplifier 1 Features 3 Description • • The LMC6482 device provides a common-mode range that extends to both supply rails. This rail-to-rail performance combined with excellent accuracy, due to a high CMRR, makes it unique among rail-to-rail input amplifiers. The device is ideal for systems, such as data acquisition, that require a large input signal range. The LMC6482 is also an excellent upgrade for circuits using limited common-mode range amplifiers such as the TLC272 and TLC277. 1 • • • • • • • • Typical Unless Otherwise Noted Rail-to-Rail Input Common-Mode Voltage Range (Ensured Over Temperature) Rail-to-Rail Output Swing (Within 20-mV of Supply Rail, 100-kΩ Load) Ensured 3-V, 5-V, and 15-V Performance Excellent CMRR and PSRR: 82 dB Ultralow Input Current: 20 fA High Voltage Gain (R L = 500 k Ω): 130 dB Specified for 2-kΩ and 600-Ω Loads Power-Good Output Available in VSSOP Package 2 Applications • • • • • • Data Acquisition Systems Transducer Amplifiers Hand-held Analytic Instruments Medical Instrumentation Active Filter, Peak Detector, Sample and Hold, pH Meter, Current Source Improved Replacement for TLC272, TLC277 Maximum dynamic signal range is assured in low voltage and single supply systems by the rail-to-rail output swing of the LMC6482. The rail-to-rail output swing is ensured for loads down to 600 Ω of the device. Ensured low-voltage characteristics and lowpower dissipation make the LMC6482 especially wellsuited for battery-operated systems. LMC6482 is also available in a VSSOP package, which is almost half the size of a SOIC-8 device. See the LMC6484 data sheet for a quad CMOS operational amplifier with these same features. Device Information(1) PART NUMBER PACKAGE LMC6482 BODY SIZE (NOM) SOIC (8) 4.90 mm × 3.91 mm VSSOP (8) 3.00 mm × 3.00 mm PDIP (8) 9.81 mm × 6.35 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Rail-to-Rail Input A1 Rail-to-Rail Output ±0.18 V A2 3V ±0.18 V 3V 0V 0V 500mV 50s 500mV C001 50s C002 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LMC6482 SNOS674E – NOVEMBER 1997 – REVISED APRIL 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 3 6.1 6.2 6.3 6.4 6.5 6.6 6.7 3 4 4 4 4 7 9 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics for V+ = 5 V....................... Electrical Characteristics for V+ = 3 V....................... Typical Characteristics .............................................. Detailed Description ............................................ 18 7.1 Overview ................................................................. 18 7.2 Functional Block Diagram ....................................... 18 7.3 Feature Description................................................. 18 7.4 Device Functional Modes........................................ 19 8 Application and Implementation ........................ 20 8.1 Application Information............................................ 20 8.2 Typical Applications ............................................... 22 9 Power Supply Recommendations...................... 28 10 Layout................................................................... 28 10.1 Layout Guidelines ................................................. 28 10.2 Layout Example .................................................... 28 11 Device and Documentation Support ................. 30 11.1 Trademarks ........................................................... 30 11.2 Electrostatic Discharge Caution ............................ 30 11.3 Glossary ................................................................ 30 12 Mechanical, Packaging, and Orderable Information ........................................................... 30 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision D (March 2013) to Revision E • Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1 Changes from Revision C (March 2013) to Revision D • 2 Page Page Changed layout of National Data Sheet to TI format ........................................................................................................... 27 Submit Documentation Feedback Copyright © 1997–2015, Texas Instruments Incorporated Product Folder Links: LMC6482 LMC6482 www.ti.com SNOS674E – NOVEMBER 1997 – REVISED APRIL 2015 5 Pin Configuration and Functions D, DGK and P Packages 8-Pin SOIC, VSSOP and PDIP (Top View) Pin Functions PIN TYPE DESCRIPTION NO. NAME 1 OUTPUT A O Output for Amplifier A 2 INVERTING INPUT A I Inverting input for Amplifier A 3 NONINVERTING INPUT A I Noninverting input for Amplifier A 4 V– P Negative supply voltage input 5 NONINVERTING INPUT B I Noninverting input for Amplifier B 6 INVERTING INPUT B I Inverting input for Amplifier B 7 OUTPUT B O Output for Amplifier B 8 V+ P Positive supply voltage input 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) (2) MIN MAX Differential Input Voltage (V−) −0.3 Voltage at Input/Output Pin − + UNIT ±Supply Voltage Supply Voltage (V − V ) (V+) +0.3 V 16 V −5 5 mA −30 30 mA Current at Power Supply Pin 40 mA Lead Temperature 260 °C 150 °C 150 °C Current at Input Pin (3) Current at Output Pin (4) (5) (Soldering, 10 sec.) Junction Temperature (6) −65 Storage temperature, Tstg (1) (2) (3) (4) (5) (6) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications. Limiting input pin current is only necessary for input voltages that exceed absolute maximum input voltage ratings. Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature of 150°C. Output currents in excess of ±30 mA over long term may adversely affect reliability. Do not short circuit output to V+, when V+ is greater than 13 V or reliability will be adversely affected. The maximum power dissipation is a function of TJ(max), RθJA, and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(max) − TA)/θJA. All numbers apply for packages soldered directly into a PC board. Submit Documentation Feedback Copyright © 1997–2015, Texas Instruments Incorporated Product Folder Links: LMC6482 3 LMC6482 SNOS674E – NOVEMBER 1997 – REVISED APRIL 2015 www.ti.com 6.2 ESD Ratings V(ESD) (1) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) VALUE UNIT ±1500 V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) (1) MIN MAX 3 15.5 V LMC6482AM –55 125 °C LMC6482AI, LMC6482I –40 −85 °C Supply Voltage Junction Temperature Range (1) UNIT Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 6.4 Thermal Information THERMAL METRIC RθJA (1) (1) LMC6482 LMC6482 LMC6482 D (SOIC) DGK (VSSOP) P (PDIP) 8 PINS 8 PINS 8 PINS 155 194 90 Junction-to-ambient thermal resistance UNIT °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. 6.5 Electrical Characteristics for V+ = 5 V Unless otherwise specified, all limits specified for TJ = 25°C, V+ = 5 V, V− = 0 V, VCM = VO = V+/2 and RL > 1 M. PARAMETER At Temperature Extremes (1) TJ = 25°C TEST CONDITIONS MIN TYP (2) MAX (3) MIN TYP (2) UNIT MAX (3) DC Electrical Characteristics Input Offset Voltage VOS TCVOS IB IOS CIN RIN (1) (2) (3) (4) 4 LMC6482AI 0.11 0.75 1.35 LMC6482I 0.11 3 3.7 LMC6482M 0.11 3 3.8 Input Offset Voltage Average Drift Input Current Input Offset Current mV 1 μV/°C See See (4) (4) LMC6482AI 0.02 LMC6482I 0.02 4 LMC6482M 0.02 10 LMC6482AI 0.01 2 LMC6482I 0.01 2 LMC6482M 0.01 5 CommonMode Input Capacitance 4 pA pA 3 pF Input Resistance 10 TeraΩ See Recommended Operating Conditions for operating temperature ranges. Typical Values represent the most likely parametric norm. All limits are specified by testing or statistical analysis. Ensured limits are dictated by tester limitations and not device performance. Actual performance is reflected in the typical value. Submit Documentation Feedback Copyright © 1997–2015, Texas Instruments Incorporated Product Folder Links: LMC6482 LMC6482 www.ti.com SNOS674E – NOVEMBER 1997 – REVISED APRIL 2015 Electrical Characteristics for V+ = 5 V (continued) Unless otherwise specified, all limits specified for TJ = 25°C, V+ = 5 V, V− = 0 V, VCM = VO = V+/2 and RL > 1 M. PARAMETER MIN CMRR CommonMode Rejection Ratio Positive Power Supply +PSRR Rejection Ratio Negative Power Supply −PSRR Rejection Ratio VCM Input CommonMode Voltage Range 0 V ≤ VCM ≤ 15 V V+ = 15 V 0 V ≤ VCM ≤ 5 V V+ = 5 V + 5 V ≤ V ≤ 15 V, V− = 0 V VO = 2.5 V − −5 V ≤ V ≤ −15 V, V+ = 0 V VO = −2.5 V V = 5 V and 15 V For CMRR ≥ 50 dB MIN 70 82 67 65 82 62 LMC6482M 65 82 60 LMC6482AI 70 82 67 LMC6482I 65 82 62 LMC6482M 65 82 60 LMC6482AI 70 82 67 LMC6482I 65 82 62 LMC6482M 65 82 60 LMC6482AI 70 82 67 LMC6482I 65 82 62 LMC6482M 65 82 TYP (2) UNIT MAX (3) dB dB dB 60 LMC6482AI V− − 0.3 −0.25 0 LMC6482I V− − 0.3 −0.25 0 − V − 0.3 −0.25 V+ + 0.25 V+ + 0.3 V+ LMC6482I V+ + 0.25 V+ + 0.3 V+ Sinking Large Signal Voltage Gain Sinking V + V + 0.3 140 666 84 120 666 72 LMC6482M 120 666 60 LMC6482AI 35 75 20 LMC6482I 35 75 20 LMC6482M 35 75 18 LMC6482AI 80 300 48 Sourcing LMC6482I RL = 600 Ω (5) (4) + V + 0.25 LMC6482AI RL = 2 kΩ (5) (4) + V 0 LMC6482AI Sourcing LMC6482I (5) MAX (3) LMC6482I LMC6482M AV TYP (2) LMC6482AI LMC6482M + At Temperature Extremes (1) TJ = 25°C TEST CONDITIONS V 50 300 30 LMC6482M 50 300 25 LMC6482AI 20 35 13 LMC6482I 15 35 10 LMC6482M 15 35 8 V/mV V/mV V/mV V/mV V+ = 15 V, VCM = 7.5 V and RL connected to 7.5 V. For Sourcing tests, 7.5 V ≤ VO ≤ 11.5 V. For Sinking tests, 3.5 V ≤ VO ≤ 7.5 V. Submit Documentation Feedback Copyright © 1997–2015, Texas Instruments Incorporated Product Folder Links: LMC6482 5 LMC6482 SNOS674E – NOVEMBER 1997 – REVISED APRIL 2015 www.ti.com Electrical Characteristics for V+ = 5 V (continued) Unless otherwise specified, all limits specified for TJ = 25°C, V+ = 5 V, V− = 0 V, VCM = VO = V+/2 and RL > 1 M. PARAMETER MIN VO Output Swing V+ = 5 V RL = 2 kΩ to V+/2 TYP (2) V =5V RL = 600 Ω to V+/2 + V = 15 V RL = 2k Ω to V+/2 + V = 15 V RL = 600 Ω to V+/2 Sourcing, VO = 0 V ISC Output Short Circuit Current V+ = 5 V Sinking, VO = 5 V Sourcing, VO = 0 V ISC IS (6) 6 Output Short Circuit Current V+ = 15 V Supply Current Sinking, VO = 12 V (6) Both Amplifiers V+ = +5 V, VO = V+/2 Both Amplifiers V+ = 15 V, VO = V+/2 MAX (3) MIN LMC6482AI 4.8 4.9 4.7 LMC6482I 4.8 4.9 4.7 LMC6482M 4.8 4.9 TYP (2) UNIT MAX (3) V 4.7 LMC6482AI 0.1 0.18 0.24 LMC6482I 0.1 0.18 0.24 0.1 0.18 LMC6482M + At Temperature Extremes (1) TJ = 25°C TEST CONDITIONS V 0.24 LMC6482AI 4.5 4.7 4.24 LMC6482I 4.5 4.7 4.24 LMC6482M 4.5 4.7 4.24 LMC6482AI 0.3 0.5 0.65 LMC6482I 0.3 0.5 0.65 LMC6482M 0.3 0.5 0.65 LMC6482AI 14.4 14.7 14.2 LMC6482I 14.4 14.7 14.2 LMC6482M 14.4 14.7 14.2 LMC6482AI 0.16 0.32 0.45 LMC6482I 0.16 0.32 0.45 LMC6482M 0.16 0.32 0.45 LMC6482AI 13.4 14.1 13 LMC6482I 13.4 14.1 13 LMC6482M 13.4 14.1 13 0.5 1 1.3 LMC6482I 0.5 1 1.3 LMC6482M 0.5 1 1.3 16 20 12 LMC6482I 16 20 12 LMC6482M 16 20 10 LMC6482AI 11 15 9.5 LMC6482I 11 15 9.5 LMC6482M 11 15 8 LMC6482AI 28 30 22 LMC6482I 28 30 22 LMC6482M 28 30 20 LMC6482AI 30 30 24 LMC6482I 30 30 24 LMC6482M 30 30 V V LMC6482AI LMC6482AI V V mA mA mA mA 22 LMC6482AI 1 1.4 1.8 LMC6482I 1 1.4 1.8 LMC6482M 1 1.4 1.9 LMC6482AI 1.3 1.6 1.9 LMC6482I 1.3 1.6 1.9 LMC6482M 1.3 1.6 2 mA mA Do not short circuit output to V+, when V+ is greater than 13 V or reliability will be adversely affected. Submit Documentation Feedback Copyright © 1997–2015, Texas Instruments Incorporated Product Folder Links: LMC6482 LMC6482 www.ti.com SNOS674E – NOVEMBER 1997 – REVISED APRIL 2015 Electrical Characteristics for V+ = 5 V (continued) Unless otherwise specified, all limits specified for TJ = 25°C, V+ = 5 V, V− = 0 V, VCM = VO = V+/2 and RL > 1 M. PARAMETER At Temperature Extremes (1) TJ = 25°C TEST CONDITIONS MIN TYP (2) MAX (3) MIN TYP (2) UNIT MAX (3) AC Electrical Characteristics See SR Slew Rate GBW GainBandwidth Product φm Gm (7) LMC6482AI 1 1.3 0.7 LMC6482I 0.9 1.3 0.63 LMC6482M 0.9 1.3 0.54 V/μs V/μs V+ = 15 V 1.5 MHz Phase Margin 50 Deg Gain Margin 15 dB 150 dB Amp-to-Amp Isolation See (8) en Input-Referred F = 1 kHz Voltage Noise Vcm = 1 V 37 nV/√Hz In Input-Referred F = 1 kHz Current Noise 0.03 pA/√Hz T.H.D. (7) (8) Total Harmonic Distortion F = 10 kHz, AV = −2 RL = 10 kΩ, VO = 4.1 VPP 0.01% F = 10 kHz, AV = −2 RL = 10 kΩ, VO = 8.5 VPP V+ = 10 V 0.01% V + = 15V. Connected as Voltage Follower with 10V step input. Number specified is the slower of either the positive or negative slew rates. Input referred, V+ = 15 V and RL = 100 kΩ connected to 7.5 V. Each amp excited in turn with 1 kHz to produce VO = 12 VPP. 6.6 Electrical Characteristics for V+ = 3 V Unless otherwise specified, all limits specified for TJ = 25°C, V+ = 3V, V− = 0V, VCM = VO = V+/2 and RL > 1M. PARAMETER At Temperature Extremes (1) TJ = 25°C TEST CONDITIONS MAX (3) LMC6482AI 0.9 2 2.7 LMC6482I 0.9 3 3.7 LMC6482M 0.9 3 3.8 MIN TYP (2) UNIT TYP (2) MIN MAX (3) DC Electrical Characteristics Input Offset Voltage VOS TCVOS Input Offset Voltage Average Drift IB Input Bias Current 0.02 IOS Input Offset Current 0.01 CMRR Common Mode Rejection Ratio (1) (2) (3) μV/°C 2 0 V ≤ VCM ≤ 3 V LMC6482AI 64 74 LMC6482I 60 74 LMC6482M 60 74 mV pA pA dB See Recommended Operating Conditions for operating temperature ranges. Typical Values represent the most likely parametric norm. All limits are specified by testing or statistical analysis. Submit Documentation Feedback Copyright © 1997–2015, Texas Instruments Incorporated Product Folder Links: LMC6482 7 LMC6482 SNOS674E – NOVEMBER 1997 – REVISED APRIL 2015 www.ti.com Electrical Characteristics for V+ = 3 V (continued) Unless otherwise specified, all limits specified for TJ = 25°C, V+ = 3V, V− = 0V, VCM = VO = V+/2 and RL > 1M. PARAMETER PSRR Power Supply Rejection Ratio Input CommonMode Voltage Range VCM 3 V ≤ V+ ≤ 15 V, V− = 0 V For CMRR ≥ 50 dB MIN TYP (2) LMC6482AI 68 80 LMC6482I 60 80 LMC6482M 60 0 V− −0.25 0 − LMC6482M V −0.25 LMC6482AI V+ V+ + 0.25 LMC6482I V+ V+ + 0.25 V RL = 600 Ω to V+/2 IS Supply Current Both Amplifiers TYP (2) UNIT MAX (3) 80 LMC6482I + MIN dB V− −0.25 V 0 V + V + 0.25 RL = 2 kΩ to V+/2 Output Swing MAX (3) LMC6482AI LMC6482M VO At Temperature Extremes (1) TJ = 25°C TEST CONDITIONS 2.8 V 0.2 V LMC6482AI 2.5 2.7 LMC6482I 2.5 2.7 LMC6482M 2.5 2.7 V LMC6482AI 0.37 0.6 LMC6482I 0.37 0.6 LMC6482M 0.37 0.6 LMC6482AI 0.825 1.2 1.5 LMC6482I 0.825 1.2 1.5 LMC6482M 0.825 1.2 1.6 V mA AC Electrical Characteristics SR Slew Rate GBW GainBandwidth Product T.H.D. Total Harmonic Distortion (4) 8 See (4) F = 10 kHz, AV = −2 RL = 10 kΩ, VO = 2 VPP 0.9 V/μs 1 MHz 0.01% Connected as voltage Follower with 2-V step input. Number specified is the slower of either the positive or negative slew rates. Submit Documentation Feedback Copyright © 1997–2015, Texas Instruments Incorporated Product Folder Links: LMC6482 LMC6482 www.ti.com SNOS674E – NOVEMBER 1997 – REVISED APRIL 2015 6.7 Typical Characteristics VS = 15 V, Single Supply, TA = 25°C unless otherwise specified Figure 1. Supply Current vs. Supply Voltage Figure 2. Input Current vs. Temperature Figure 3. Sourcing Current vs. Output Voltage Figure 4. Sourcing Current vs. Output Voltage Figure 5. Sourcing Current vs. Output Voltage Figure 6. Sinking Current vs. Output Voltage Submit Documentation Feedback Copyright © 1997–2015, Texas Instruments Incorporated Product Folder Links: LMC6482 9 LMC6482 SNOS674E – NOVEMBER 1997 – REVISED APRIL 2015 www.ti.com Typical Characteristics (continued) VS = 15 V, Single Supply, TA = 25°C unless otherwise specified Figure 7. Sinking Current vs. Output Voltage Figure 9. Output Voltage Swing vs. Supply Voltage Figure 11. Input Voltage Noise vs. Input Voltage 10 Figure 8. Sinking Current vs. Output Voltage Figure 10. Input Voltage Noise vs. Frequency Figure 12. Input Voltage Noise vs. Input Voltage Submit Documentation Feedback Copyright © 1997–2015, Texas Instruments Incorporated Product Folder Links: LMC6482 LMC6482 www.ti.com SNOS674E – NOVEMBER 1997 – REVISED APRIL 2015 Typical Characteristics (continued) VS = 15 V, Single Supply, TA = 25°C unless otherwise specified Figure 13. Input Voltage Noise vs. Input Voltage Figure 14. Crosstalk Rejection vs. Frequency Figure 15. Crosstalk Rejection vs. Frequency Figure 16. Positive PSRR vs. Frequency Figure 17. Negative PSRR vs. Frequency Figure 18. CMRR vs. Frequency Submit Documentation Feedback Copyright © 1997–2015, Texas Instruments Incorporated Product Folder Links: LMC6482 11 LMC6482 SNOS674E – NOVEMBER 1997 – REVISED APRIL 2015 www.ti.com Typical Characteristics (continued) VS = 15 V, Single Supply, TA = 25°C unless otherwise specified 12 Figure 19. CMRR vs. Input Voltage Figure 20. CMRR vs. Input Voltage Figure 21. CMRR vs. Input Voltage Figure 22. ΔvOS vs. CMR Figure 23. ΔvOS vs. CMR Figure 24. Input Voltage vs. Output Voltage Submit Documentation Feedback Copyright © 1997–2015, Texas Instruments Incorporated Product Folder Links: LMC6482 LMC6482 www.ti.com SNOS674E – NOVEMBER 1997 – REVISED APRIL 2015 Typical Characteristics (continued) VS = 15 V, Single Supply, TA = 25°C unless otherwise specified Figure 25. Input Voltage vs. Output Voltage Figure 26. Open-Loop Frequency Response Figure 27. Open-Loop Frequency Response Figure 28. Open-Loop Frequency Response vs. Temperature Figure 29. Maximum Output Swing vs. Frequency Figure 30. Gain and Phase vs. Capacitive Load Submit Documentation Feedback Copyright © 1997–2015, Texas Instruments Incorporated Product Folder Links: LMC6482 13 LMC6482 SNOS674E – NOVEMBER 1997 – REVISED APRIL 2015 www.ti.com Typical Characteristics (continued) VS = 15 V, Single Supply, TA = 25°C unless otherwise specified 14 Figure 31. Gain and Phase vs. Capacitive Load Figure 32. Open-Loop Output Impedance vs. Frequency Figure 33. Open-Loop Output Impedance vs. Frequency Figure 34. Slew Rate vs. Supply Voltage Figure 35. Noninverting Large Signal Pulse Response Figure 36. Noninverting Large Signal Pulse Response Submit Documentation Feedback Copyright © 1997–2015, Texas Instruments Incorporated Product Folder Links: LMC6482 LMC6482 www.ti.com SNOS674E – NOVEMBER 1997 – REVISED APRIL 2015 Typical Characteristics (continued) VS = 15 V, Single Supply, TA = 25°C unless otherwise specified Figure 37. Noninverting Large Signal Pulse Response Figure 38. Noninverting Small Signal Pulse Response Figure 39. Noninverting Small Signal Pulse Response Figure 40. Noninverting Small Signal Pulse Response Figure 41. Inverting Large Signal Pulse Response Figure 42. Inverting Large Signal Pulse Response Submit Documentation Feedback Copyright © 1997–2015, Texas Instruments Incorporated Product Folder Links: LMC6482 15 LMC6482 SNOS674E – NOVEMBER 1997 – REVISED APRIL 2015 www.ti.com Typical Characteristics (continued) VS = 15 V, Single Supply, TA = 25°C unless otherwise specified 16 Figure 43. Inverting Large Signal Pulse Response Figure 44. Inverting Small Signal Pulse Response Figure 45. Inverting Small Signal Pulse Response Figure 46. Inverting Small Signal Pulse Response Figure 47. Stability vs. Capacitive Load Figure 48. Stability vs. Capacitive Load Submit Documentation Feedback Copyright © 1997–2015, Texas Instruments Incorporated Product Folder Links: LMC6482 LMC6482 www.ti.com SNOS674E – NOVEMBER 1997 – REVISED APRIL 2015 Typical Characteristics (continued) VS = 15 V, Single Supply, TA = 25°C unless otherwise specified Figure 49. Stability vs. Capacitive Load Figure 50. Stability vs. Capacitive Load Figure 51. Stability vs. Capacitive Load Figure 52. Stability vs. Capacitive Load Submit Documentation Feedback Copyright © 1997–2015, Texas Instruments Incorporated Product Folder Links: LMC6482 17 LMC6482 SNOS674E – NOVEMBER 1997 – REVISED APRIL 2015 www.ti.com 7 Detailed Description 7.1 Overview The LMC6482 is a dual CMOS operational amplifier that supports both rail-to-rail inputs and outputs. It may be operated in both dual supply mode and single supply mode. 7.2 Functional Block Diagram 7.3 Feature Description 7.3.1 Amplifier Topology The LMC6482 incorporates specially designed wide-compliance range current mirrors and the body effect to extend input common-mode range to each supply rail. Complementary paralleled differential input stages, like the type used in other CMOS and bipolar rail-to-rail input amplifiers, were not used because of their inherent accuracy problems due to CMRR, crossover distortion, and open-loop gain variation. The LMC6482s input stage design is complemented by an output stage capable of rail-to-rail output swing even when driving a large load. Rail-to-rail output swing is obtained by taking the output directly from the internal integrator instead of an output buffer stage. 7.3.2 Input Common-Mode Voltage Range Unlike Bi-FET amplifier designs, the LMC6482 does not exhibit phase inversion when an input voltage exceeds the negative supply voltage. Figure 53 shows an input voltage exceeding both supplies with no resulting phase inversion on the output. An input voltage signal exceeds the lMC6482 power supply voltages with no output phase inversion. Figure 53. Input Voltage The absolute maximum input voltage is 300 mV beyond either supply rail at room temperature. Voltages greatly exceeding this absolute maximum rating, as in Figure 54, can cause excessive current to flow in or out of the input pins possibly affecting reliability. 18 Submit Documentation Feedback Copyright © 1997–2015, Texas Instruments Incorporated Product Folder Links: LMC6482 LMC6482 www.ti.com SNOS674E – NOVEMBER 1997 – REVISED APRIL 2015 Feature Description (continued) A ±7.5-V input signal greatly exceeds the 3-V supply in Figure 55 causing no phase inversion due to RI. Figure 54. Input Signal Applications that exceed this rating must externally limit the maximum input current to ±5 mA with an input resistor (RI) as shown in Figure 55. RI input current protection for voltages exceeding the supply voltages. Figure 55. RI Input Current Protection for Voltages Exceeding the Supply Voltages 7.3.3 Rail-to-Rail Output The approximated output resistance of the LMC6482 is 180-Ω sourcing and 13-0Ω sinking at VS = 3 V and 110-Ω sourcing and 80-Ω sinking at Vs = 5 V. Using the calculated output resistance, maximum output voltage swing can be estimated as a function of load. 7.4 Device Functional Modes The LMC6482 may be used in applications where each amplifier channel is used independently, or in applications in which the channels are cascaded. See Typical Applications for more information. Submit Documentation Feedback Copyright © 1997–2015, Texas Instruments Incorporated Product Folder Links: LMC6482 19 LMC6482 SNOS674E – NOVEMBER 1997 – REVISED APRIL 2015 www.ti.com 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information 8.1.1 Upgrading Applications The LMC6484 quads and LMC6482 duals have industry-standard pin outs to retrofit existing applications. System performance can be greatly increased by the features of the LMC6482. The key benefit of designing in the LMC6482 is increased linear signal range. Most op-amps have limited input common-mode ranges. Signals that exceed this range generate a nonlinear output response that persists long after the input signal returns to the common-mode range. Linear signal range is vital in applications such as filters where signal peaking can exceed input common-mode ranges resulting in output phase inversion or severe distortion. 8.1.2 Data Acquisition Systems Low power, single supply data acquisition system solutions are provided by buffering the ADC12038 with the LMC6482 (Figure 56). Capable of using the full supply range, the LMC6482 does not require input signals to be scaled down to meet limited common-mode voltage ranges. The LMC4282 CMRR of 82 dB maintains integral linearity of a 12-bit data acquisition system to ±0.325 LSB. Other rail-to-rail input amplifiers with only 50 dB of CMRR will degrade the accuracy of the data acquisition system to only 8 bits. Operating from the same supply voltage, the LMC6482 buffers the ADC12038 maintaining excellent accuracy. Figure 56. Buffering the ADC12038 With the LMC6482 20 Submit Documentation Feedback Copyright © 1997–2015, Texas Instruments Incorporated Product Folder Links: LMC6482 LMC6482 www.ti.com SNOS674E – NOVEMBER 1997 – REVISED APRIL 2015 Application Information (continued) 8.1.3 Instrumentation Circuits The LMC6482 has the high input impedance, large common-mode range and high CMRR needed for designing instrumentation circuits. Instrumentation circuits designed with the LMC6482 can reject a larger range of common-mode signals than most in-amps. This makes instrumentation circuits designed with the LMC6482 an excellent choice of noisy or industrial environments. Other applications that benefit from these features include analytic medical instruments, magnetic field detectors, gas detectors, and silicon-based transducers. A small valued potentiometer is used in series with Rg to set the differential gain of the 3-op-amp instrumentation circuit in Figure 57. This combination is used instead of one large valued potentiometer to increase gain trim accuracy and reduce error due to vibration. Figure 57. Low Power 3-Op-Amp Instrumentation Amplifier A 2-op-amp instrumentation amplifier designed for a gain of 100 is shown in Figure 58. Low sensitivity trimming is made for offset voltage, CMRR, and gain. Low cost and low power consumption are the main advantages of this 2-op-amp circuit. Higher frequency and larger common-mode range applications are best facilitated by a 3-op-amp instrumentation amplifier. Figure 58. Low-Power Two-Op-Amp Instrumentation Amplifier 8.1.4 Spice Macromodel A • • • • • spice macromodel is available for the LMC6482. This model includes accurate simulation of the following: Input common-mode voltage range Frequency and transient response GBW dependence on loading conditions Quiescent and dynamic supply current Output swing dependence on loading conditions Many more characteristics are listed on the macromodel disk. Submit Documentation Feedback Copyright © 1997–2015, Texas Instruments Incorporated Product Folder Links: LMC6482 21 LMC6482 SNOS674E – NOVEMBER 1997 – REVISED APRIL 2015 www.ti.com Application Information (continued) Contact your local TI sales office to obtain an operational amplifier spice model library disk. 8.2 Typical Applications 8.2.1 3-V Single Supply Buffer Circuit Figure 59. 3-V Single Supply Buffer Circuit 8.2.1.1 Design Requirements For best performance, ensure that the input voltage swing is between V+ and V-. Ensure that the input does not exceed the common-mode input range. To reduce the risk of destabilizing the output, use resistive isolation on the output when driving capacitive loads (see the Detailed Design Procedure section). When large feedback resistors are used, it may be necessary to compensate for parasitic capacitance on the input. See the Detailed Design Procedure section. 8.2.1.2 Detailed Design Procedure 8.2.1.2.1 Capacitive Load Compensation Capacitive load compensation can be accomplished using resistive isolation as shown in Figure 60. This simple technique is useful for isolating the capacitive inputs of multiplexers and A/D converters. Figure 60. Resistive Isolation of a 330-pF Capacitive Load Figure 61. Pulse Response of the LMC6482 Circuit in Figure 60 22 Submit Documentation Feedback Copyright © 1997–2015, Texas Instruments Incorporated Product Folder Links: LMC6482 LMC6482 www.ti.com SNOS674E – NOVEMBER 1997 – REVISED APRIL 2015 Typical Applications (continued) 8.2.1.2.1.1 Capacitive Load Tolerance The LMC6482 can typically directly drive a 100-pF load with VS = 15 V at unity gain without oscillating. The unity gain follower is the most sensitive configuration. Direct capacitive loading reduces the phase margin of op-amps. The combination of the output impedance of the op-amp and the capacitive load induces phase lag. This results in either an underdamped pulse response or oscillation. Improved frequency response is achieved by indirectly driving capacitive loads, as shown in Figure 62. Compensated to handle a 330pF capacitive load. Figure 62. LMC6482 Noninverting Amplifier R1 and C1 serve to counteract the loss of phase margin by feeding forward the high-frequency component of the output signal back to the amplifiers inverting input, thereby preserving phase margin in the overall feedback loop. The values of R1 and C1 are experimentally determined for the desired pulse response. The resulting pulse response is shown in Figure 63. Figure 63. Pulse Response of Lmc6482 Circuit in Figure 62 8.2.1.2.1.2 Compensating For Input Capacitance It is quite common to use large values of feedback resistance with amplifiers that have ultralow input current, like the LMC6482. Large feedback resistors can react with small values of input capacitance due to transducers, photo diodes, and circuits board parasitics to reduce phase margins. Submit Documentation Feedback Copyright © 1997–2015, Texas Instruments Incorporated Product Folder Links: LMC6482 23 LMC6482 SNOS674E – NOVEMBER 1997 – REVISED APRIL 2015 www.ti.com Typical Applications (continued) Figure 64. Canceling the Effect of Input Capacitance The effect of input capacitance can be compensated for by adding a feedback capacitor. The feedback capacitor (as in Figure 64), Cf, is first estimated by: (1) or R1 CIN ≤ R2 Cf (2) which typically provides significant overcompensation. Printed-circuit-board stray capacitance may be larger or smaller than that of a bread-board, so the actual optimum value for Cf may be different. The values of Cf should be checked on the actual circuit. (Refer to the LMC660 quad CMOS amplifier data sheet for a more detailed discussion.) 8.2.1.2.1.3 Offset Voltage Adjustment Offset voltage adjustment circuits are illustrated in Figure 65 and Figure 66. Large value resistances and potentiometers are used to reduce power consumption while providing typically ±2.5 mV of adjustment range, referred to the input, for both configurations with VS = ±5 V. V+ R4 R3 500 k: 5V - VIN 1 LMC6482 2 1 M: VOUT + 1 k: -5V 499: 500 k: VOUT V- VIN =- R4 R3 V- Figure 65. Inverting Configuration Offset Voltage Adjustment Figure 66. Noninverting Configuration Offset Voltage Adjustment 24 Submit Documentation Feedback Copyright © 1997–2015, Texas Instruments Incorporated Product Folder Links: LMC6482 LMC6482 www.ti.com SNOS674E – NOVEMBER 1997 – REVISED APRIL 2015 Typical Applications (continued) 8.2.1.3 Application Curves Figure 68. Rail-To-Rail Output Figure 67. Rail-To-Rail Input 8.2.2 Typical Single-Supply Applications The circuit in Figure 69 uses a single supply to half-wave rectify a sinusoid centered about ground. RI limits current into the amplifier caused by the input voltage exceeding the supply voltage. Full-wave rectification is provided by the circuit in Figure 71. Figure 69. Half-Wave Rectifier With Input Current Protection (RI) Figure 70. Half-Wave Rectifier Waveform Submit Documentation Feedback Copyright © 1997–2015, Texas Instruments Incorporated Product Folder Links: LMC6482 25 LMC6482 SNOS674E – NOVEMBER 1997 – REVISED APRIL 2015 www.ti.com Typical Applications (continued) In Figure 75 dielectric absorption and leakage is minimized by using a polystyrene or polyethylene hold capacitor. The droop rate is primarily determined by the value of CH and diode leakage current. The ultralow input current of the LMC6482 has a negligible effect on droop. Figure 71. Full-Wave Rectifier With Input Current Protection (RI) Figure 72. Full-Wave Rectifier Waveform Figure 73. Large Compliance Range Current Source Figure 74. Positive Supply Current Sense Figure 75. Low-Voltage Peak Detector With Rail-To-Rail Peak Capture Range 26 Submit Documentation Feedback Copyright © 1997–2015, Texas Instruments Incorporated Product Folder Links: LMC6482 LMC6482 www.ti.com SNOS674E – NOVEMBER 1997 – REVISED APRIL 2015 Typical Applications (continued) The high CMRR (82 dB) of the LMC6482 allows excellent accuracy throughout the rail-to-rail dynamic capture range of the circuit. Figure 76. Rail-To-Rail Sample and Hold The low-pass filter circuit in Figure 77 can be used as an anti-aliasing filter with the same voltage supply as the A/D converter. Filter designs can also take advantage of the LMC6482 ultralow input current. The ultralow input current yields negligible offset error even when large value resistors are used. This in turn allows the use of smaller valued capacitors which take less board space and cost less. Figure 77. Rail-To-Rail Single Supply Low Pass Filter Submit Documentation Feedback Copyright © 1997–2015, Texas Instruments Incorporated Product Folder Links: LMC6482 27 LMC6482 SNOS674E – NOVEMBER 1997 – REVISED APRIL 2015 www.ti.com 9 Power Supply Recommendations The LMC6482 can be operated over a supply range of 3 V to 15 V. To achieve noise immunity as appropriate to the application, it is important to use good PCB layout practices for power supply rails and planes, as well as using bypass capacitors connected between the power supply pins and ground. 10 Layout 10.1 Layout Guidelines It is generally recognized that any circuit which must operate with less than 1000 pA of leakage current requires special layout of the PC board. When one wishes to take advantage of the ultralow input current of the LMC6482, typically less than 20 fA, it is essential to have an excellent layout. Fortunately, the techniques of obtaining low leakages are quite simple. First, the user must not ignore the surface leakage of the PCB, even through it may sometimes appear acceptably low, because under conditions of high humidity or dust or contamination, the surface leakage will be appreciable. To minimize the effect of any surface leakage, lay out a ring of foil completely surrounding the LM6482s inputs and the terminals of capacitors, diodes, conductors, resistors, relay terminals, and so forth connected to the inputs of the op-amp, as in Figure 78. To have a significant effect, guard rings should be placed on both the top and bottom of the PCB. This PC foil must then be connected to a voltage which is at the same voltage as the amplifier inputs, because no leakage current can flow between two points at the same potential. For example, a PCB trace-to-pad resistance of 1012 Ω, which is normally considered a very large resistance, could leak 5 pA if the trace were a 5-V bus adjacent to the pad of the input. This would cause a 250 times degradation from the actual performance of the LMC6482. However, if a guard ring is held within 5 mV of the inputs, then even a resistance of 1011 Ω would cause only 0.05 pA of leakage current. See Figure 79 through Figure 81 for typical connections of guard rings for standard op-amp configurations. The designer should be aware that when it is inappropriate to lay out a PCB for the sake of just a few circuits, another technique is even better than a guard ring on a PCB: Do not insert the input pin of the amplifier into the PCB at all, but bend it up in the air and use only air as an insulator. Air is an excellent insulator. In this case you may have to forego some of the advantages of PCB construction, but the advantages are sometimes well worth the effort of using point-to-point up-in-the-air wiring. See Figure 82. 10.2 Layout Example Figure 78. Example of Guard Ring in PCB Layout Typical Connections of Guard Rings 28 Submit Documentation Feedback Copyright © 1997–2015, Texas Instruments Incorporated Product Folder Links: LMC6482 LMC6482 www.ti.com SNOS674E – NOVEMBER 1997 – REVISED APRIL 2015 Layout Example (continued) Figure 79. Inverting Amplifier Typical Connections of Guard Rings Figure 80. Noninverting Amplifier Typical Connections of Guard Rings Figure 81. Follower Typical Connections of Guard Rings (Input pins are lifted out of PCB and soldered directly to components. All other pins connected to PCB.) Figure 82. Air Wiring Submit Documentation Feedback Copyright © 1997–2015, Texas Instruments Incorporated Product Folder Links: LMC6482 29 LMC6482 SNOS674E – NOVEMBER 1997 – REVISED APRIL 2015 www.ti.com 11 Device and Documentation Support 11.1 Trademarks All trademarks are the property of their respective owners. 11.2 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.3 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 30 Submit Documentation Feedback Copyright © 1997–2015, Texas Instruments Incorporated Product Folder Links: LMC6482 PACKAGE OPTION ADDENDUM www.ti.com 27-Jul-2016 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) LMC6482AI MDA ACTIVE DIESALE Y 0 324 Green (RoHS & no Sb/Br) Call TI Level-1-NA-UNLIM -40 to 85 LMC6482AIM NRND SOIC D 8 95 TBD Call TI Call TI -40 to 85 LMC64 82AIM LMC6482AIM/NOPB ACTIVE SOIC D 8 95 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LMC64 82AIM LMC6482AIMX NRND SOIC D 8 2500 TBD Call TI Call TI -40 to 85 LMC64 82AIM LMC6482AIMX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LMC64 82AIM LMC6482AIN/NOPB ACTIVE PDIP P 8 40 Green (RoHS & no Sb/Br) CU SN Level-1-NA-UNLIM -40 to 85 LMC64 82AIN LMC6482IM NRND SOIC D 8 95 TBD Call TI Call TI -40 to 85 LMC64 82IM LMC6482IM/NOPB ACTIVE SOIC D 8 95 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LMC64 82IM LMC6482IMM NRND VSSOP DGK 8 1000 TBD Call TI Call TI -40 to 85 A10 LMC6482IMM/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 A10 LMC6482IMMX NRND VSSOP DGK 8 3500 TBD Call TI Call TI -40 to 85 A10 LMC6482IMMX/NOPB ACTIVE VSSOP DGK 8 3500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 A10 LMC6482IMX NRND SOIC D 8 2500 TBD Call TI Call TI -40 to 85 LMC64 82IM LMC6482IMX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LMC64 82IM LMC6482IN/NOPB ACTIVE PDIP P 8 40 Green (RoHS & no Sb/Br) CU SN Level-1-NA-UNLIM -40 to 85 LMC6482IN (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 27-Jul-2016 (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 29-Oct-2014 TAPE AND REEL INFORMATION *All dimensions are nominal Device LMC6482AIMX Package Package Pins Type Drawing SOIC SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LMC6482AIMX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LMC6482IMM VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LMC6482IMM/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LMC6482IMMX VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LMC6482IMMX/NOPB VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LMC6482IMX SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LMC6482IMX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 29-Oct-2014 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMC6482AIMX SOIC D 8 2500 367.0 367.0 35.0 LMC6482AIMX/NOPB SOIC D 8 2500 367.0 367.0 35.0 LMC6482IMM VSSOP DGK 8 1000 210.0 185.0 35.0 LMC6482IMM/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 LMC6482IMMX VSSOP DGK 8 3500 367.0 367.0 35.0 LMC6482IMMX/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0 LMC6482IMX SOIC D 8 2500 367.0 367.0 35.0 LMC6482IMX/NOPB SOIC D 8 2500 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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