Product Folder Sample & Buy Support & Community Tools & Software Technical Documents LMV7235, LMV7239, LMV7239-Q1 SNOS532N – SEPTEMBER 2000 – REVISED APRIL 2015 LMV7235, LMV7239 and LMV7239-Q1 75-ns, Ultra Low Power, Low Voltage, Rail-to-Rail Input Comparator with Open-Drain and Push-Pull Output 1 Features 3 Description • The LMV7235, LMV7239 and LMV7239-Q1 are ultra low power, low voltage, 75-ns comparators. They are guaranteed to operate over the full supply voltage range of 2.7 V to 5.5 V. These devices achieve a 75 ns propagation delay while consuming only 65 µA of supply current at 5 V. 1 • • • • • • • VS = 5 V, TA = 25°C (Typical Values Unless Otherwise Specified) Propagation Delay 75 ns Low supply Current 65 µA Rail-to-Rail Input Open Drain and Push-pull Output Ideal for 2.7-V and 5-V Single Supply Applications Available in Space-saving Packages: – 5-pin SOT-23 – 5-pin SC70 LMV7239-Q1 is Qualified for Automotive Applications: – Device Temperature AEC-Q100 Grade 1: -40°C to 125°C Operating Range – Device HBM ESD Classification Level 1C The LMV7235 features an open drain output. By connecting an external resistor, the output of the comparator can be used as a level shifter. The LMV7239 and LMV7239-Q1 features a push-pull output stage. This feature allows operation without the need of an external pull-up resistor. The LMV7235, LMV7239 and LMV7239-Q1 are available in the 5-Pin SC70 and 5-Pin SOT-23 packages, which are ideal for systems where small size and low power is critical. 2 Applications • • • • • • The LMV7235, LMV7239 and LMV7239-Q1 have a greater than rail-to-rail common mode voltage range. The input common mode voltage range extends 200 mV below ground and 200 mV above supply, allowing both ground and supply sensing. Portable and Battery Powered Systems Set Top Boxes High Speed Differential Line Receiver Window Comparators Zero-crossing Detectors High Speed Sampling Circuits Device Information(1) PART NUMBER PACKAGES BODY SIZE (NOM) LMV7235, LMV7239 and LMV7239-Q1 SOT-23 (5) 2.90 mm x 1.60 mm SC70 (5) 2.00 mm x 1.25 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Supply Current vs. Supply Voltage 90 -40°C 25°C 85°C 125°C 100 PROPAGATION DELAY (ns) SUPPLY CURRENT (A) 120 Propagation Delay vs. Overdrive 80 60 40 20 0 VS= 5V CLOAD=15pF 85 Rising Edge 80 75 Falling Edge 70 0 1 2 3 4 SUPPLY VOLTAGE (V) 5 20 40 60 80 INPUT OVERDRIVE (mV) 100 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LMV7235, LMV7239, LMV7239-Q1 SNOS532N – SEPTEMBER 2000 – REVISED APRIL 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 6.7 4 4 4 4 4 5 6 Absolute Maximum Ratings ...................................... ESD Ratings, LMV7235 and LMV7239..................... ESD Ratings, LMV7239-Q1 ...................................... Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics, 2.7 V ............................... Electrical Characteristics, 5 V .................................. Typical Performance Characteristics .................. 7 Detailed Description ............................................ 10 8.1 Overview ................................................................. 10 8.2 Functional Block Diagram ....................................... 10 8.3 Feature Description................................................. 10 8.4 Device Functional Modes........................................ 11 9 Application and Implementation ........................ 15 9.1 Application Information............................................ 15 9.2 Typical Applications ................................................ 15 10 Power Supply Recommendations ..................... 18 11 Layout................................................................... 19 11.1 Layout Guidelines ................................................. 19 11.2 Layout Example .................................................... 19 12 Device and Documentation Support ................. 20 12.1 12.2 12.3 12.4 12.5 12.6 Device Support...................................................... Documentation Support ....................................... Related Links ........................................................ Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 20 20 20 20 20 20 13 Mechanical, Packaging, and Orderable Information ........................................................... 20 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision M (February 2013) to Revision N • Page Added, updated, or renamed the following sections: Device Information Table, Pin Configuration and Functions; Specifications. Detailed DescriptionLayout; Device and Documentation Support; Mechanical, Packaging, and Ordering Information............................................................................................................................................................... 1 Changes from Revision L (February 2013) to Revision M 2 Submit Documentation Feedback Page Copyright © 2000–2015, Texas Instruments Incorporated Product Folder Links: LMV7235 LMV7239 LMV7239-Q1 LMV7235, LMV7239, LMV7239-Q1 www.ti.com SNOS532N – SEPTEMBER 2000 – REVISED APRIL 2015 5 Pin Configuration and Functions 5-Pin SC70 and SOT-23 Packages DBV, DGK Top View 1 5 VOUT V- Non-Inverting Input 2 V+ SC70 SOT-23 3 4 Inverting Input Pin Functions PIN NO. NAME I/O DESCRIPTION 1 VOUT O Output 2 V- P Negative Supply 3 IN+ I Non-inverting Input 4 IN- I Inverting Input 5 V+ P Positive Supply Copyright © 2000–2015, Texas Instruments Incorporated Product Folder Links: LMV7235 LMV7239 LMV7239-Q1 Submit Documentation Feedback 3 LMV7235, LMV7239, LMV7239-Q1 SNOS532N – SEPTEMBER 2000 – REVISED APRIL 2015 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings (1) Over operating free-air temperature range (unless otherwise noted) MIN Differential Input Voltage Output Short Circuit Duration MAX UNIT ± Supply Voltage V See Supply Voltage (V+ - V−) (2) 6 V SOLDERING INFORMATION Infrared or Convection (20 sec) 235 °C Wave Soldering (10 sec) 260 (lead temp) °C Voltage at Input/Output Pins (V+) +0.3, (V−) −0.3 V ±10 mA 150 °C 150 °C Current at Input Pin (3) Storage Temperature, Tstg -65 Junction Temperature,TJ (1) (2) (3) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature of 150°C. Output currents in excess of ±30mA over long term may adversely affect reliability. Limiting input pin current is only necessary for input voltages that exceed absolute maximum input voltage ratings. 6.2 ESD Ratings, LMV7235 and LMV7239 VALUE V(ESD) (1) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±1000 Machine model (MM) ±100 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 500-V HBM is possible with the necessary precautions. 6.3 ESD Ratings, LMV7239-Q1 VALUE Human-body model (HBM), per AEC Q100-002 (1) V(ESD) Electrostatic discharge Machine model (MM) Charged-device model (CDM), per AEC Q100-011 (1) UNIT ±1000 ±100 (1) DBV package only V ±750 JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 250-V CDM is possible with the necessary precautions. 6.4 Recommended Operating Conditions MIN + − Supply Voltages (V - V ) Temperature Range (1) (1) MAX UNIT 2.7 5.5 V LMV7235/LMV7239 −40 85 °C LMV7239Q −40 125 °C The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) – TA) / θJA. All numbers apply for packages soldered directly onto a PC Board. 6.5 Thermal Information THERMAL METRIC (1) RθJA (1) 4 Junction-to-ambient thermal resistance SC70 SOT-23 5 PINS 5 PINS 478 265 UNIT °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2000–2015, Texas Instruments Incorporated Product Folder Links: LMV7235 LMV7239 LMV7239-Q1 LMV7235, LMV7239, LMV7239-Q1 www.ti.com SNOS532N – SEPTEMBER 2000 – REVISED APRIL 2015 6.6 Electrical Characteristics, 2.7 V Unless otherwise specified, all limits guaranteed for TA = 25°C, VCM = V+/2, V+ = 2.7 V, V− = 0 V−. LMV7239 in table below also applies to LMV7239-Q1 unless noted. MIN (1) TEST CONDITIONS VOS Input Offset Voltage Input Bias Current IOS Input Offset Current CMRR Common Mode Rejection Ratio 0 V < VCM < 2.7 V (3) PSRR Power Supply Rejection Ratio V+ = 2.7 V to 5 V VCM Input Common-Mode Voltage Range tr Propagation Delay Skew (LMV7239 only) Output Rise Time tf Output Fall Time ILEAKAGE Output Leakage Current (LMV7235 only) (1) (2) (3) (4) (5) (6) CMRR > 50 dB IL = 4 mA, VID = 500 mV 600 200 400 52 62 65 85 V− −0.1 −0.2 to 2.9 V− At temp extremes V+ −0.35 IL = 0.4 mA, VID = 500 mV mV nA nA dB dB V+ +0.1 V+ V V+ −0.26 V V+ −0.02 V 230 At temp extremes Output Short Circuit Current tSKEW 400 At temp extremes Output Swing Low Propagation Delay 30 UNIT 8 IL = −4 mA, VID = −500 mV tPD 6 5 VO Supply Current 0.8 At temp extremes Output Swing High (LMV7239 only) IS MAX (1) At temp extremes IB ISC TYP (2) 350 mV 450 IL = −0.4 mA, VID = −500 mV 15 mV Sourcing, VO = 0 V (LMV7239 only) (4) 15 mA Sinking, VO = 2.7 V (LMV7235, RL = 10 k) (4) 20 mA No load 52 At temp extremes 85 100 µA Overdrive = 20 mV CLOAD = 15 pF (5) 96 ns Overdrive = 50 mV CLOAD = 15 pF (5) 87 ns Overdrive = 100 mV CLOAD = 15 pF (5) 85 ns Overdrive = 20 mV (6) 2 ns LMV7239/LMV7239Q 10% to 90% 1.7 ns LMV7235 10% to 90% (5) 112 ns 90% to 10% 1.7 ns 3 nA All limits are guaranteed by testing or statistical analysis. Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not guaranteed on shipped production material. CMRR is not linear over the common mode range. Limits are guaranteed over the worst case from 0 to VCC/2 or VCC/2 to VCC. Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature of 150°C. Output currents in excess of ±30mA over long term may adversely affect reliability. A 10k pull-up resistor was used when measuring the LMV7235. The rise time of the LMV7235 is a function of the R-C time constant. Propagation Delay Skew is defined as the absolute value of the difference between tPDLH and tPDHL. Copyright © 2000–2015, Texas Instruments Incorporated Product Folder Links: LMV7235 LMV7239 LMV7239-Q1 Submit Documentation Feedback 5 LMV7235, LMV7239, LMV7239-Q1 SNOS532N – SEPTEMBER 2000 – REVISED APRIL 2015 www.ti.com 6.7 Electrical Characteristics, 5 V Unless otherwise specified, all limits guaranteed for TA = 25°C, VCM = V+/2, V+ = 5V, V− = 0V. LMV7239 in table below also applies to LMV7239-Q1 unless noted. MIN (1) TEST CONDITIONS Input Offset Voltage IB Input Bias Current IOS Input Offset Current CMRR Common Mode Rejection Ratio 0 V < VCM < 5 V PSRR Power Supply Rejection Ratio V+ = 2.7 V to 5 V 8 30 600 5 400 52 85 V −0.1 −0.2 to 5.2 CMRR > 50dB V− At temp extremes IL = 4 mA, VID = 500 mV V+ −0.25 IL = 0.4 mA, VID = 500 mV Output Swing Low Sourcing, VO = 0 V (LMV7239 only) (3) Output Short Circuit Current Propagation Delay Propagation Delay Skew (LMV7239 only) tSKEW tr Output Rise Time tf Output Fall Time ILEAKAGE Output Leakage Current (LMV7235 only) (1) (2) (3) (4) (5) 6 Sinking, VO = 5 V (LMV7235, RL = 10k) (3) No load dB V +0.1 V+ −0.01 V 350 55 mA 60 mA 20 65 At temp extremes mV mV 15 30 V V 10 At temp extremes nA + 450 25 nA V+ −0.15 230 At temp extremes mV V+ At temp extremes IL = −0.4 mA, VID = −500 mV UNIT dB 67 65 − IL = −4 mA, VID = −500 mV tPD 200 At temp extremes VO Supply Current 400 At temp extremes Output Swing High (LMV7239 only) IS 6 At temp extremes Input Common-Mode Voltage Range ISC MAX (1) 1 VOS VCM TYP (2) 95 110 µA Overdrive = 20 mV CLOAD = 15 pF (4) 89 ns Overdrive = 50 mV CLOAD = 15 pF (4) 82 ns Overdrive = 100 mV CLOAD = 15 pF (4) 75 ns Overdrive = 20 mV (5) 1 ns LMV7239 10% to 90% 1.2 ns LMV7235 10% to 90% (4) 100 ns 90% to 10% 1.2 ns 3 nA All limits are guaranteed by testing or statistical analysis. Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not guaranteed on shipped production material. Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature of 150°C. Output currents in excess of ±30mA over long term may adversely affect reliability. A 10k pull-up resistor was used when measuring the LMV7235. The rise time of the LMV7235 is a function of the R-C time constant. Propagation Delay Skew is defined as the absolute value of the difference between tPDLH and tPDHL. Submit Documentation Feedback Copyright © 2000–2015, Texas Instruments Incorporated Product Folder Links: LMV7235 LMV7239 LMV7239-Q1 LMV7235, LMV7239, LMV7239-Q1 www.ti.com SNOS532N – SEPTEMBER 2000 – REVISED APRIL 2015 7 Typical Performance Characteristics (Unless otherwise specified, VS = 5V, CL = 10pF, TA = 25°C). 100 -40°C 25°C 85°C 125°C 100 VS = 5V 80 10 ISOURCE (mA) SUPPLY CURRENT (A) 120 60 40 1 20 0 0 1 2 3 4 SUPPLY VOLTAGE (V) .1 .01 5 Figure 1. Supply Current vs. Supply Voltage 10 1 Figure 2. Sourcing Current vs. Output Voltage 100 100 VS = 5V VS = 2.7V 10 ISINK (mA) 10 ISOURCE (mA) .1 OUTPUT VOLTAGE REFERENCED TO V+ (V) 1 1 .1 .01 .1 1 .1 .01 10 OUTPUT VOLTAGE REFERENCED TO V+ (V) Figure 3. Sourcing Current vs. Output Voltage .1 1 10 OUTPUT VOLTAGE REFERENCED TO GND (V) Figure 4. Sinking Current vs. Output Voltage 50 100 40 INPUT BIAS CURRENT (nA) VS = 2.7V ISINK (mA) 10 1 VS = 5V 30 IBIAS+ 20 10 0 -10 IBIAS- -20 -30 -40 .1 .01 .1 1 10 -50 -0.2 OUTPUT VOLTAGE REFERENCED TO GND (V) Figure 5. Sinking Current vs. Output Voltage 1 2 3 4 5 VIN (V) Figure 6. Input Bias Current vs. Input Voltage Copyright © 2000–2015, Texas Instruments Incorporated Product Folder Links: LMV7235 LMV7239 LMV7239-Q1 Submit Documentation Feedback 7 LMV7235, LMV7239, LMV7239-Q1 SNOS532N – SEPTEMBER 2000 – REVISED APRIL 2015 www.ti.com Typical Performance Characteristics (continued) (Unless otherwise specified, VS = 5V, CL = 10pF, TA = 25°C). 160 VS = 2.7V 50 40 30 PROPAGATION DELAY (ns) INPUT BIAS CURRENT (nA) 70 60 IBIAS+ 20 10 0 -10 -20 -30 -40 IBIAS- -50 -60 140 130 Falling Edge 120 110 100 90 Rising Edge 80 0 2 1 2.7 -40 -20 0 20 40 60 80 100 120 140 TEMPERATURE (°C) VIN (V) Figure 7. Input Bias Current vs. Input Voltage Figure 8. Propagation Delay vs. Temperature 140 106 VS=5V VOD=20mV CLOAD=15pF 130 PROPAGATION DELAY (ns) PROPAGATION DELAY (ns) VS=2.7V VOD=20mV CLOAD=15pF 150 120 Falling Edge 110 100 90 VS= 2.7V VOD=20mV 104 102 Falling Edge 100 98 96 Rising Edge Rising Edge 80 94 -40 -20 0 20 40 60 80 100 120 140 TEMPERATURE (°C) Figure 9. Propagation Delay vs. Temperature 0 100 VS= 5V VOD=20mV PROPAGATION DELAY (ns) PROPAGATION DELAY (ns) 100 Figure 10. Propagation Delay vs. Capacitive Load 96 94 Falling Edge 92 90 VS= 2.7V CLOAD=15pF 95 Rising Edge 90 85 Rising Edge Falling Edge 88 80 0 20 40 60 80 CAPACITANCE (pF) 100 Figure 11. Propagation Delay vs. Capacitive Load 8 20 40 60 80 CAPACITANCE (pF) Submit Documentation Feedback 20 30 40 50 60 70 80 90 100 INPUT OVERDRIVE (mV) Figure 12. Propagation Delay vs. Input Overdrive Copyright © 2000–2015, Texas Instruments Incorporated Product Folder Links: LMV7235 LMV7239 LMV7239-Q1 LMV7235, LMV7239, LMV7239-Q1 www.ti.com SNOS532N – SEPTEMBER 2000 – REVISED APRIL 2015 Typical Performance Characteristics (continued) (Unless otherwise specified, VS = 5V, CL = 10pF, TA = 25°C). 120 VS= 5V CLOAD=15pF PROPAGATION DELAY (ns) PROPAGATION DELAY (ns) 90 85 Rising Edge 80 75 Falling Edge VS= 2.7V VOD=20mV CLOAD=15pF 115 110 105 100 70 95 90 85 Rising Edge Falling Edge 80 20 40 60 80 INPUT OVERDRIVE (mV) 100 0.0 0.5 1.0 1.5 2.0 2.5 3.0 INPUT COMMON MODE VOLTAGE (V) Figure 13. Propagation Delay vs. Input Overdrive Figure 14. Propagation Delay vs. Common Mode Voltage PROPAGATION DELAY (ns) 110 VS= 5V VOD=20mV CLOAD=15pF 100 Falling Edge Rising Edge 90 80 0 1 2 3 4 5 INPUT COMMON MODE VOLTAGE (V) Figure 15. Propagation Delay vs. Common Mode Voltage Copyright © 2000–2015, Texas Instruments Incorporated Product Folder Links: LMV7235 LMV7239 LMV7239-Q1 Submit Documentation Feedback 9 LMV7235, LMV7239, LMV7239-Q1 SNOS532N – SEPTEMBER 2000 – REVISED APRIL 2015 www.ti.com 8 Detailed Description 8.1 Overview The LMV7235, LMV7239 and LMV7239-Q1 are ultra low power, low voltage, 75-ns comparators. They are guaranteed to operate over the full supply voltage range of 2.7 V to 5.5 V. These devices achieve a 75-ns propagation delay while consuming only 65 µA of supply current at 5 V. The LMV7235, LMV7239 and LMV7239-Q1 have a greater than rail-to-rail common mode voltage range. The input common mode voltage range extends 200 mV below ground and 200 mV above supply, allowing both ground and supply sensing. 8.2 Functional Block Diagram Simplified Schematic of LMV7239 8.3 Feature Description 8.3.1 Input Stage The LMV7235, LMV7239 and LMV7239-Q1 are rail-to-rail input and output. The typical input common mode voltage range of −0.2 V below the ground to 0.2 V above the supply. The LMV7235, LMV7239 and LMV7239-Q1 use a complimentary PNP and NPN input stage in which the PNP stage senses common mode voltage near V− and the NPN stage senses common mode voltage near V+. If either of the input signals falls below the negative common mode limit, the parasitic PN junction formed by the substrate and the base of the PNP will turn on resulting in an increase of input bias current. If one of the inputs goes above the positive common mode limit, the output will still maintain the correct logic level as long as the other input stays within the common mode range. However, the propagation delay will increase. When both inputs are outside the common mode voltage range, current saturation occurs in the input stage, and the output becomes unpredictable. The propagation delay does not increase significantly with large differential input voltages. However, large differential voltages greater than the supply voltage should be avoided to prevent damage to the input stage. 8.3.2 Output Stage, LMV7239 and LMV7239-Q1 The LMV7239 has a push-pull output. When the output switches, there is a low resistance path between VCC and ground, causing high output sinking or sourcing current during the transition. 10 Submit Documentation Feedback Copyright © 2000–2015, Texas Instruments Incorporated Product Folder Links: LMV7235 LMV7239 LMV7239-Q1 LMV7235, LMV7239, LMV7239-Q1 www.ti.com SNOS532N – SEPTEMBER 2000 – REVISED APRIL 2015 Feature Description (continued) Figure 16. LMV7239 Push-Pull Output Stage 8.3.3 Output Stage, LMV7235 The LMV7235 has an open drain that requires a pull-up resistor to a positive supply voltage for the output to switch properly. The internal circuitry is identical to the LMV7239 except that the upper P channel output device M4 is absent in the Functional Block Diagram above. When the internal output transistor is off, the output voltage will be pulled up to the external positive voltage by the external pull-up resistor. This allows the output to be OR'ed with other open drain outputs on the same bus. The output pull-up resistor can be connected to any voltage level between V- and V+ for level shifting applications. Figure 17. LMV7235 Open Drain Output 8.4 Device Functional Modes 8.4.1 Capacitive and Resistive Loads The propagation delay is not affected by capacitive loads at the output of the LPV7239 or LMV7239-Q1. However, resistive loads slightly effect the propagation delay on the falling edge depending on the load resistance value. The propagation delay on the rising edge of the LMV7235 depends on the load resistance and capacitance values. 8.4.2 Noise Most comparators have rather low gain. This allows the output to spend time between high and low when the input signal changes slowly. The result is the output may oscillate between high and low when the differential input is near zero. The high gain of this comparator eliminates this problem. Less than 1 μV of change on the input will drive the output from one rail to the other rail. If the input signal is noisy, the output cannot ignore the noise unless some hysteresis is provided by positive feedback. (See Hysteresis.) Copyright © 2000–2015, Texas Instruments Incorporated Product Folder Links: LMV7235 LMV7239 LMV7239-Q1 Submit Documentation Feedback 11 LMV7235, LMV7239, LMV7239-Q1 SNOS532N – SEPTEMBER 2000 – REVISED APRIL 2015 www.ti.com Device Functional Modes (continued) 8.4.3 Hysteresis In order to improve propagation delay when low overdrive is needed hysteresis can be added. 8.4.3.1 Inverting Comparator with Hysteresis The inverting comparator with hysteresis requires a three resistor network that is referenced to the supply voltage V+ of the comparator as shown in Figure 18. When VIN at the inverting input is less than VA, the voltage at the non-inverting node of the comparator (VIN < VA), the output voltage is high (for simplicity assume VO switches as high as V+). The three network resistors can be represented as R1//R3 in series with R2. Figure 18. Inverting Comparator with Hysteresis The lower input trip voltage VA1 is defined as: VA1 = VCCR2 / [(R1 // R3) + R2)]. (1) When VIN is greater than VA, the output voltage is low or very close to ground. In this case the three network resistors can be presented as R2 // R3 in series with R1. The upper trip voltage VA2 is defined as: VA2 = VCC (R2 // R3) / [(R1 ) + (R2 // R3)] (2) The total hysteresis provided by the network is defined as ΔVA = VA1 - VA2. VCCR1R2 'VA R1R2 R1R3 R2R3 (3) 8.4.3.2 Non-Inverting Comparator with Hysteresis A non-inverting comparator with hysteresis requires a two resistor network, and a voltage reference (VREF) at the inverting input. When VIN is low, the output is also low. For the output to switch from low to high, VIN must rise up to VIN1 where VIN1 is calculated by: 12 Submit Documentation Feedback Copyright © 2000–2015, Texas Instruments Incorporated Product Folder Links: LMV7235 LMV7239 LMV7239-Q1 LMV7235, LMV7239, LMV7239-Q1 www.ti.com SNOS532N – SEPTEMBER 2000 – REVISED APRIL 2015 Device Functional Modes (continued) 'VIN1 VREF (R1 R2 ) R2 (4) As soon as VO switches to VCC, VA steps to a value greater than VREF which is given by: (V VIN1 )R1 VA VIN CC R1 R2 (5) To make the comparator switch back to its low state, VIN must equal VREF before VA will again equal VREF. VIN2 can be calculated by: VREF (R1 R2 ) VCC R1 VIN2 R2 (6) The hysteresis of this circuit is the difference between VIN1 and VIN2. ΔVIN = VCCR1 / R2 (7) VCC - VREF VA VIN VO + R1 RL R2 Figure 19. Non-Inverting Comparator with Hysteresis Figure 20. Non-Inverting Comparator Thresholds 8.4.4 Zero Crossing Detector In a zero crossing detector circuit, the inverting input is connected to ground and the non-inverting input is connected to a 100 mVPP AC signal. As the signal at the non-inverting input crosses 0V, the comparator’s output changes state. Figure 21. Simple Zero Crossing Detector 8.4.4.1 Zero Crossing Detector with Hysteresis To improve switching times and centering the input threshold to ground a small amount of positive feedback is added to the circuit. Voltage divider R4 and R5 establishes a reference voltage, V1, at the positive input. By making the series resistance, R1 plus R2 equal to R5, the switching condition, V1 = V2, will be satisfied when VIN = 0. Copyright © 2000–2015, Texas Instruments Incorporated Product Folder Links: LMV7235 LMV7239 LMV7239-Q1 Submit Documentation Feedback 13 LMV7235, LMV7239, LMV7239-Q1 SNOS532N – SEPTEMBER 2000 – REVISED APRIL 2015 www.ti.com Device Functional Modes (continued) The positive feedback resistor, R6, is made very large with respect to R5 || R6 = 2000 R5). The resultant hysteresis established by this network is very small (ΔV1 < 10 mV) but it is sufficient to insure rapid output voltage transitions. Diode D1 is used to insure that the inverting input terminal of the comparator never goes below approximately −100 mV. As the input terminal goes negative, D1 will forward bias, clamping the node between R1 and R2 to approximately −700 mV. This sets up a voltage divider with R2 and R3 preventing V2 from going below ground. The maximum negative input overdrive is limited by the current handling ability of D1. VCC R3 R1 R4 R2 - VIN V2 D1 VO V1 + R6 R5 Figure 22. Zero Crossing Detector with Hysteresis 8.4.5 Threshold Detector Instead of tying the inverting input to 0V, the inverting input can be tied to a reference voltage. As the input on the non-inverting input passes the VREF threshold, the comparator’s output changes state. It is important to use a stable reference voltage to ensure a consistent switching point. Figure 23. Threshold Detector 14 Submit Documentation Feedback Copyright © 2000–2015, Texas Instruments Incorporated Product Folder Links: LMV7235 LMV7239 LMV7239-Q1 LMV7235, LMV7239, LMV7239-Q1 www.ti.com SNOS532N – SEPTEMBER 2000 – REVISED APRIL 2015 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information The LMV7235, LMV7239 and LMV7239-Q1 are single supply comparators with 75 ns of propagation delay and only 65 µA of supply current. 9.2 Typical Applications 9.2.1 Square Wave Oscillator R4 C1 VC VO + R1 + VA R3 V + R2 V 0 Figure 24. Square Wave Oscillator 9.2.1.1 Design Requirements A typical application for a comparator is as a square wave oscillator. The circuit in Figure 24 generates a square wave whose period is set by the RC time constant of the capacitor C1 and resistor R4. 9.2.1.2 Detailed Design Procedure The maximum frequency is limited by the large signal propagation delay of the comparator and by the capacitive loading at the output, which limits the output slew rate. Figure 25. Square Wave Oscillator Timing Thresholds Consider the output of Figure 24 to be high to analyze the circuit. That implies that the inverted input (VC) is lower than the non-inverting input (VA). This causes the C1 to be charged through R4, and the voltage VC increases until it is equal to the non-inverting input. The value of VA at this point is: VCC R2 VA1 R2 R1 R R3 (8) If R1 = R2 = R3, then V A1 = 2 Vcc/3 Copyright © 2000–2015, Texas Instruments Incorporated Product Folder Links: LMV7235 LMV7239 LMV7239-Q1 Submit Documentation Feedback 15 LMV7235, LMV7239, LMV7239-Q1 SNOS532N – SEPTEMBER 2000 – REVISED APRIL 2015 www.ti.com Typical Applications (continued) At this point the comparator switches pulling down the output to the negative rail. The value of VA at this point is: VCC (R2 R R3 ) VA2 R1 (R2 R R3 ) (9) If R1 = R2 = R3, then VA2 = VCC/3. The capacitor C1 now discharges through R4, and the voltage VC decreases until it is equal to VA2, at which point the comparator switches again, bringing it back to the initial stage. The time period is equal to twice the time it takes to discharge C1 from 2VCC/3 to VCC/3, which is given by R4C1·ln2. Hence the formula for the frequency is: F = 1/(2·R4·C1·ln2) (10) The LMV7239 should be used for a symmetrical output. The LMV7235 will require a pull-up resistor on the output to function, and will have a slightly asymmetrical output due to the reduced sourcing current. 9.2.1.3 Application Curves Figure Figure 26 shows the simulated results of an oscillator using the following values: 1. 2. 3. 4. R1 = R2 = R3 = R4 = 100kΩ C1 = 100pF, CL = 20pF V+ = 5V, V- = GND CSTRAY (not shown) from Va to GND = 10pF 6 VOUT 5 Va VOUT (V) 4 3 2 1 Vc 0 -1 0 10 20 30 40 TIME (µs) 50 C001 Figure 26. Square Wave Oscillator Output Waveform 9.2.2 Crystal Oscillator A simple crystal oscillator using the LMV7235, LMV7239 and LMV7239-Q1 is shown in Figure 27. Resistors R1 and R2 set the bias point at the comparator’s non-inverting input. Resistors, R3 and R4 and capacitor C1 set the inverting input node at an appropriate DC average level based on the output. The crystal’s path provides resonant positive feedback and stable oscillation occurs. The output duty cycle for this circuit is roughly 50%, but it is affected by resistor tolerances and to a lesser extent by the comparator 16 Submit Documentation Feedback Copyright © 2000–2015, Texas Instruments Incorporated Product Folder Links: LMV7235 LMV7239 LMV7239-Q1 LMV7235, LMV7239, LMV7239-Q1 www.ti.com SNOS532N – SEPTEMBER 2000 – REVISED APRIL 2015 Typical Applications (continued) VCC 100K Crystal 100K VOUT 100K 0.1uF Figure 27. Crystal Oscillator 9.2.3 Infrared (IR) Receiver The LMV7235, LMV7239 and LMV7239-Q1 can also be used as an infrared receiver. The infrared photo diode creates a current relative to the amount of infrared light present. The current creates a voltage across RD. When this voltage level cross the voltage applied by the voltage divider to the inverting input, the output transitions. Figure 28. IR Receiver 9.2.4 Window Detector V + R1 + VREF2 A OUTPUT A B OUTPUT B R2 VIN + - VREF1 R3 Figure 29. Window Detector A window detector monitors the input signal to determine if it falls between two voltage levels. Both outputs are true (high) when VREF1 < VIN < VREF2 Copyright © 2000–2015, Texas Instruments Incorporated Product Folder Links: LMV7235 LMV7239 LMV7239-Q1 Submit Documentation Feedback 17 LMV7235, LMV7239, LMV7239-Q1 SNOS532N – SEPTEMBER 2000 – REVISED APRIL 2015 www.ti.com Typical Applications (continued) VIN V OUTPUT B + VREF2 VREF1 OUTPUT A BOTH OUTPUTS ARE HIGH Figure 30. Window Detector Output Signal The comparator outputs A and B are high only when VREF1 < VIN < VREF2, or "within the window", where these are defined as: VREF1 = R3/R1+R2+R3) * V+ (11) VREF2 = R2+R3)/R1+R2+R3) * V+ (12) To determine if the input signal falls outside of the two voltage levels, both inputs on each comparators can be reversed to invert the logic. The LMV7235 with an open drain output should be used if the outputs are to be tied together for a common logic output. Other names for window detectors are: threshold detector, level detector, and amplitude trigger or detector. 10 Power Supply Recommendations To minimize supply noise, power supplies should be decoupled by a 0.01 μF ceramic capacitor in parallel with a 10 μF capacitor. Due to the nanosecond edges on the output transition, peak supply currents will be drawn during the time the output is transitioning. Peak current depends on the capacitive loading on the output. The output transition can cause transients on poorly bypassed power supplies. These transients can cause a poorly bypassed power supply to "ring" due to trace inductance and low self-resonance frequency of high ESR bypass capacitors. Treat the LMV7235, LMV7239 and LMV7239-Q1 as a high-speed device. Keep the ground paths short and place small (low ESR ceramic) bypass capacitors directly between the V+ and V- pins. Output capacitive loading and output toggle rate will cause the average supply current to rise over the quiescent current. 18 Submit Documentation Feedback Copyright © 2000–2015, Texas Instruments Incorporated Product Folder Links: LMV7235 LMV7239 LMV7239-Q1 LMV7235, LMV7239, LMV7239-Q1 www.ti.com SNOS532N – SEPTEMBER 2000 – REVISED APRIL 2015 11 Layout 11.1 Layout Guidelines Proper grounding and the use of a ground plane will help to ensure the specified performance of the LMV7235, LMV7239 and LMV7239-Q1. Minimizing trace lengths, reducing unwanted parasitic capacitance and using surface-mount components will also help. Comparators are very sensitive to input noise. The LMV7235, LMV7239 and LMV7239-Q1 require high speed layout. Follow these layout guidelines: 1. Use printed circuit board with a good, unbroken low-inductance ground plane. 2. Place a decoupling capacitor (0.1µF ceramic surface mount capacitor) as close as possible to VCC pin. 3. On the inputs and the output, keep lead lengths as short as possible to avoid unwanted parasitic feedback around the comparator. Keep inputs away from output. 4. Solder the device directly to the printed circuit board rather than using a socket. 5. For slow moving input signals, take care to prevent parasitic feedback. A small capacitor (1000 pF or less) placed between the inputs can help eliminate oscillations in the transition region. This capacitor causes some degradation to tPD when the source impedance is low. 6. The topside ground plane runs between the output and inputs. 7. Ground trace from the ground pin runs under the device up to the bypass capacitor, shielding the inputs from the outputs. 11.2 Layout Example Figure 31. SOT-23 Board Layout Example Copyright © 2000–2015, Texas Instruments Incorporated Product Folder Links: LMV7235 LMV7239 LMV7239-Q1 Submit Documentation Feedback 19 LMV7235, LMV7239, LMV7239-Q1 SNOS532N – SEPTEMBER 2000 – REVISED APRIL 2015 www.ti.com 12 Device and Documentation Support 12.1 Device Support 12.1.1 Development Support LMV7239 TINA SPICE Model, SNOM392 TINA-TI SPICE-Based Analog Simulation Program, http://www.ti.com/tool/tina-ti DIP Adapter Evaluation Module, http://www.ti.com/tool/dip-adapter-evm TI Universal Operational Amplifier Evaluation Module, http://www.ti.com/tool/opampevm 12.2 Documentation Support 12.2.1 Related Documentation AN-74 - A Quad of Independently Functioning Comparators, SNOA654 12.3 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 1. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY LMV7235 Click here Click here Click here Click here Click here LMV7239 Click here Click here Click here Click here Click here LMV7239-Q1 Click here Click here Click here Click here Click here 12.4 Trademarks All trademarks are the property of their respective owners. 12.5 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 12.6 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 20 Submit Documentation Feedback Copyright © 2000–2015, Texas Instruments Incorporated Product Folder Links: LMV7235 LMV7239 LMV7239-Q1 PACKAGE OPTION ADDENDUM www.ti.com 27-Jul-2016 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) LMV7235M5 NRND SOT-23 DBV 5 1000 TBD Call TI Call TI -40 to 85 C21A LMV7235M5/NOPB ACTIVE SOT-23 DBV 5 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 C21A LMV7235M5X NRND SOT-23 DBV 5 3000 TBD Call TI Call TI -40 to 85 C21A LMV7235M5X/NOPB ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 C21A LMV7235M7 NRND SC70 DCK 5 1000 TBD Call TI Call TI -40 to 85 C21 LMV7235M7/NOPB ACTIVE SC70 DCK 5 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 C21 LMV7235M7X/NOPB ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 C21 LMV7239 MWC ACTIVE WAFERSALE YS 0 1 Green (RoHS & no Sb/Br) Call TI Level-1-NA-UNLIM -40 to 85 LMV7239M5 NRND SOT-23 DBV 5 1000 TBD Call TI Call TI -40 to 85 C20A LMV7239M5/NOPB ACTIVE SOT-23 DBV 5 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 C20A LMV7239M5X NRND SOT-23 DBV 5 3000 TBD Call TI Call TI -40 to 85 C20A LMV7239M5X/NOPB ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 C20A LMV7239M7 NRND SC70 DCK 5 1000 TBD Call TI Call TI -40 to 85 C20 LMV7239M7/NOPB ACTIVE SC70 DCK 5 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 C20 LMV7239M7X NRND SC70 DCK 5 3000 TBD Call TI Call TI -40 to 85 C20 LMV7239M7X/NOPB ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 C20 LMV7239QDBVRQ1 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 ZBMX LMV7239QM7/NOPB ACTIVE SC70 DCK 5 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 C42 LMV7239QM7X/NOPB ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 C42 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 27-Jul-2016 LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF LMV7239, LMV7239-Q1 : • Catalog: LMV7239 • Automotive: LMV7239-Q1 NOTE: Qualified Version Definitions: Addendum-Page 2 PACKAGE OPTION ADDENDUM www.ti.com 27-Jul-2016 • Catalog - TI's standard catalog product • Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 3 PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2015 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) LMV7235M5 SOT-23 DBV 5 1000 178.0 8.4 LMV7235M5/NOPB SOT-23 DBV 5 1000 178.0 LMV7235M5X SOT-23 DBV 5 3000 178.0 LMV7235M5X/NOPB SOT-23 DBV 5 3000 LMV7235M7 SC70 DCK 5 W Pin1 (mm) Quadrant 3.2 3.2 1.4 4.0 8.0 Q3 8.4 3.2 3.2 1.4 4.0 8.0 Q3 8.4 3.2 3.2 1.4 4.0 8.0 Q3 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 1000 178.0 8.4 2.25 2.45 1.2 4.0 8.0 Q3 LMV7235M7/NOPB SC70 DCK 5 1000 178.0 8.4 2.25 2.45 1.2 4.0 8.0 Q3 LMV7235M7X/NOPB SC70 DCK 5 3000 178.0 8.4 2.25 2.45 1.2 4.0 8.0 Q3 LMV7239M5 SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LMV7239M5/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LMV7239M5X SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LMV7239M5X/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LMV7239M7 SC70 DCK 5 1000 178.0 8.4 2.25 2.45 1.2 4.0 8.0 Q3 LMV7239M7/NOPB SC70 DCK 5 1000 178.0 8.4 2.25 2.45 1.2 4.0 8.0 Q3 LMV7239M7X SC70 DCK 5 3000 178.0 8.4 2.25 2.45 1.2 4.0 8.0 Q3 LMV7239M7X/NOPB SC70 DCK 5 3000 178.0 8.4 2.25 2.45 1.2 4.0 8.0 Q3 LMV7239QDBVRQ1 SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LMV7239QM7/NOPB SC70 DCK 5 1000 178.0 8.4 2.25 2.45 1.2 4.0 8.0 Q3 LMV7239QM7X/NOPB SC70 DCK 5 3000 178.0 8.4 2.25 2.45 1.2 4.0 8.0 Q3 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2015 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMV7235M5 SOT-23 DBV 5 1000 210.0 185.0 35.0 LMV7235M5/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0 LMV7235M5X SOT-23 DBV 5 3000 210.0 185.0 35.0 LMV7235M5X/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0 LMV7235M7 SC70 DCK 5 1000 210.0 185.0 35.0 LMV7235M7/NOPB SC70 DCK 5 1000 210.0 185.0 35.0 LMV7235M7X/NOPB SC70 DCK 5 3000 210.0 185.0 35.0 LMV7239M5 SOT-23 DBV 5 1000 210.0 185.0 35.0 LMV7239M5/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0 LMV7239M5X SOT-23 DBV 5 3000 210.0 185.0 35.0 LMV7239M5X/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0 LMV7239M7 SC70 DCK 5 1000 210.0 185.0 35.0 LMV7239M7/NOPB SC70 DCK 5 1000 210.0 185.0 35.0 LMV7239M7X SC70 DCK 5 3000 210.0 185.0 35.0 LMV7239M7X/NOPB SC70 DCK 5 3000 210.0 185.0 35.0 LMV7239QDBVRQ1 SOT-23 DBV 5 3000 210.0 185.0 35.0 LMV7239QM7/NOPB SC70 DCK 5 1000 210.0 185.0 35.0 LMV7239QM7X/NOPB SC70 DCK 5 3000 210.0 185.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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