Product Folder Sample & Buy Support & Community Tools & Software Technical Documents LMH6642, LMH6643, LMH6644 SNOS966Q – MAY 2001 – REVISED SEPTEMBER 2014 LMH664x Low Power, 130 MHz, 75 mA Rail-to-Rail Output Amplifiers 1 Features (VS = ±5 V, TA = 25°C, RL = 2 kΩ, AV = +1. Typical Values Unless Specified). 1 • • • • • • • • • • • • • • • • −3 dB BW (AV = +1) 130 MHz Supply Voltage Range 2.7 V to 12.8 V Slew Rate, (AV = −1) 130V/µs(1) Supply Current (no load) 2.7 mA/amp Output Short Circuit Current +115 mA to 145 mA Linear Output Current ±75 mA Input Common Mode Volt. 0.5 V Beyond V−, 1 V from V+ Output Voltage Swing 40 mV from Rails Input Voltage Noise (100 kHz) 17nV/√Hz Input Current Noise (100 kHz) 0.9pA/√Hz THD (5MHz, RL = 2kΩ, VO = 2VPP, AV = +2) −62 dBc Settling Time 68 ns Fully Characterized for 3 V, 5 V, and ±5 V Overdrive Recovery 100 ns Output Short Circuit Protected(2) No Output Phase Reversal with CMVR Exceeded 3 Description The LMH664X family true single supply voltage feedback amplifiers offer high speed (130 MHz), low distortion (−62 dBc), and exceptionally high output current (approximately 75 mA) at low cost and with reduced power consumption when compared against existing devices with similar performance. Input common mode voltage range extends to 0.5 V below V− and 1 V from V+. Output voltage range extends to within 40 mV of either supply rail, allowing wide dynamic range especially desirable in low voltage applications. The output stage is capable of approximately 75 mA in order to drive heavy loads. Fast output Slew Rate (130 V/µs) ensures large peak-to-peak output swings can be maintained even at higher speeds, resulting in exceptional full power bandwidth of 40 MHz with a 3 V supply. These characteristics, along with low cost, are ideal features for a multitude of industrial and commercial applications. Device Information(1) PART NUMBER LMH6642 Slew rate is the average of the rising and falling slew rates LMH6643 Output short circuit duration is infinite for VS < 6 V at room temperature and below. For VS > 6 V, allowable short circuit duration is 1.5 ms. LMH6644 (1) SOIC (8) 4.90 mm × 3.91 mm 3.00 mm × 3.00 mm VSSOP (8) SOIC (14) 8.64 mm × 3.91 mm TSSOP (14) 5.00 mm × 4.40 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. Closed Loop Gain vs. Frequency for Various Supplies Active Filters CD/DVD ROM ADC Buffer Amp Portable Video Current Sense Buffer 8.0 ±1.5V 6.0 4.0 ±5 2.0 GAIN (dB) • • • • • BODY SIZE (NOM) 2.90 mm × 1.60 mm SOIC (8) (2) 2 Applications PACKAGE SOT-23 (5) 0.0 ±2.5V VO = 0.2VPP AV = +2 RF = RL = 2k 100k 1M 10M 200M FREQUENCY (Hz) 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LMH6642, LMH6643, LMH6644 SNOS966Q – MAY 2001 – REVISED SEPTEMBER 2014 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Description (continued)......................................... Pin Configuration and Functions ......................... Specifications......................................................... 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 8 1 1 1 2 3 4 5 Absolute Maximum Ratings ...................................... 5 Handling Ratings....................................................... 5 Recommended Operating Conditions....................... 5 Thermal Information .................................................. 5 3V Electrical Characteristics .................................... 6 5V Electrical Characteristics .................................... 8 ±5V Electrical Characteristics ................................ 10 Typical Performance Characteristics ...................... 12 Detailed Description ............................................ 21 8.1 Overview ................................................................. 21 8.2 Functional Block Diagram ....................................... 21 8.3 Feature Description................................................. 21 8.4 Device Functional Modes........................................ 21 9 Application and Implementation ........................ 22 9.1 Application Information............................................ 22 9.2 Typical Application .................................................. 22 10 Power Supply Recommendations ..................... 24 11 Layout................................................................... 25 11.1 Layout Guidelines ................................................. 25 11.2 Layout Example .................................................... 25 12 Device and Documentation Support ................. 26 12.1 12.2 12.3 12.4 Related Links ........................................................ Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 26 26 26 26 13 Mechanical, Packaging, and Orderable Information ........................................................... 26 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision P (March 2013) to Revision Q Page • Added, revised, or updated the following sections: Device Information Table, Application and Implementation; Power Supply Recommendations; Device and Documentation Support; Mechanical, Packaging, and Ordering Information ........ 1 • Changed "Junction Temperature Range" to "Operating Temperature Range" ...................................................................... 5 • Deleted TJ = 25°C for Electrical Characteristics tables. ......................................................................................................... 6 • Changed from "RL " to "Rf" ..................................................................................................................................................... 6 • Deleted TJ = 25°C for Typical Performance Characteristics ................................................................................................ 12 Changes from Revision O (March 2013) to Revision P • 2 Page Changed layout of National Data Sheet to TI format ............................................................................................................. 1 Submit Documentation Feedback Copyright © 2001–2014, Texas Instruments Incorporated Product Folder Links: LMH6642 LMH6643 LMH6644 LMH6642, LMH6643, LMH6644 www.ti.com SNOS966Q – MAY 2001 – REVISED SEPTEMBER 2014 5 Description (continued) Careful attention has been paid to ensure device stability under all operating voltages and modes. The result is a very well behaved frequency response characteristic (0.1dB gain flatness up the 12 MHz under 150 Ω load and AV = +2) with minimal peaking (typically 2dB maximum) for any gain setting and under both heavy and light loads. This along with fast settling time (68ns) and low distortion allows the device to operate well in an ADC buffer as well as high frequency filter applications. This device family offers professional quality video performance with low DG (0.01%) and DP (0.01°) characteristics. Differential Gain and Differential Phase characteristics are also well maintained under heavy loads (150 Ω) and throughout the output voltage range. The LMH664X family is offered in single (LMH6642), dual (LMH6643), and quad (LMH6644) options. Copyright © 2001–2014, Texas Instruments Incorporated Product Folder Links: LMH6642 LMH6643 LMH6644 Submit Documentation Feedback 3 LMH6642, LMH6643, LMH6644 SNOS966Q – MAY 2001 – REVISED SEPTEMBER 2014 www.ti.com 6 Pin Configuration and Functions 5-Pin SOT-23 (LMH6642) Package DBV05A Top View 8-Pin SOIC (LMH6642) Package D08A Top View 5 1 V OUTPUT 1 + -IN V - 2 7 - N/C + V 2 +IN - + 4 3 +IN 8 N/C -IN - 3 6 + 4 5 N/C V 8-Pin SOIC and VSSOP (LMH6643) Package DGK08A Top View 1 8 14-Pin SOIC and 14-Pin TSSOP (LMH6644) Package D14A, PW14A Top View + 2 14 2 13 OUT D A ±IN A A - 1 OUT A V OUT A + 7 -IN A OUTPUT ± + D ±IN D + ± 3 12 4 11 5 10 +IN D +IN A OUT B V± V+ 6 -IN B B + +IN C +IN B - 6 ±IN B V - 4 5 + ± +IN A B ± + 3 ±IN C C 7 +IN B 9 8 OUT C OUT B Pin Functions PIN LMH6642 NAME LMH6643 LMH6644 DGK08A D14A and PW14A I/O DESCRIPTION DBV05A D08A -IN 4 2 I Inverting Input +IN 3 3 I Non-inverting Input -IN A 2 2 I ChA Inverting Input +IN A 3 3 I ChA Non-inverting Input -IN B 6 6 I ChB Inverting Input +IN B 5 5 I ChB Non-inverting Input -IN C 9 I ChC Inverting Input +IN C 10 I ChC Non-inverting Input -IN D 13 I ChD Inverting Input +IN D 12 I ChD Non-inverting Input N/C –– No connection OUT A 1,5,8 1 1 O ChA Output OUT B 7 7 O ChB Output 8 O ChC Output 14 O ChD Output O Output OUT C OUT D OUTPUT 1 6 V- 2 4 4 11 I Negative Supply + 5 7 8 4 I Positive Supply V 4 Submit Documentation Feedback Copyright © 2001–2014, Texas Instruments Incorporated Product Folder Links: LMH6642 LMH6643 LMH6644 LMH6642, LMH6643, LMH6644 www.ti.com SNOS966Q – MAY 2001 – REVISED SEPTEMBER 2014 7 Specifications 7.1 Absolute Maximum Ratings (1) (2) over operating free-air temperature range (unless otherwise noted) MIN MAX VIN Differential UNIT ±2.5 Output Short Circuit Duration See Supply Voltage (V+ - V−) (3) and V (4) 13.5 V V+ +0.8 V− −0.8 V Input Current ±10 mA Junction Temperature (5) +150 °C Infrared or Convection Reflow (20 sec) 235 °C Wave Soldering Lead Temp.(10 sec) 260 °C Voltage at Input/Output pins Soldering Information (1) (2) (3) (4) (5) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test conditions, see the Electrical Characteristics. If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications. Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature of 150°C. Output short circuit duration is infinite for VS < 6V at room temperature and below. For VS > 6V, allowable short circuit duration is 1.5ms. The maximum power dissipation is a function of TJ(MAX), RθJA, and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) - TA)/ RθJA . All numbers apply for packages soldered directly onto a PC board. 7.2 Handling Ratings Tstg Storage temperature range MIN MAX UNIT −65 +150 °C Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (2) V(ESD) (1) (2) (3) (4) Electrostatic discharge (1) 2000 Machine model (MM) (3) 200 Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (4) 1000 V Human body model, 1.5 kΩ in series with 100 pF. Machine Model, 0 Ω in series with 200 pF. JEDEC document JEP155 states that 2000-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 200-V MM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 1000-V CDM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Conditions (1) over operating free-air temperature range (unless otherwise noted) MIN MAX Supply Voltage (V – V ) 2.7 12.8 V Operating Temperature Range (2) −40 +85 °C + (1) (2) − UNIT Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test conditions, see the Electrical Characteristics. The maximum power dissipation is a function of TJ(MAX), RθJA, and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) - TA)/ RθJA. All numbers apply for packages soldered directly onto a PC board. 7.4 Thermal Information LMH6642 THERMAL METRIC (1) RθJA (1) (2) Junction-to-ambient Thermal Resistance (2) LMH6643 LMH6644 DBV05A D08A DGK08A D14A PW14A 5 PINS 8 PINS 8 PINS 14 PINS 14 PINS 265 190 235 145 155 UNIT °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. The maximum power dissipation is a function of TJ(MAX), RθJA, and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) - TA)/ RθJA. All numbers apply for packages soldered directly onto a PC board. Copyright © 2001–2014, Texas Instruments Incorporated Product Folder Links: LMH6642 LMH6643 LMH6644 Submit Documentation Feedback 5 LMH6642, LMH6643, LMH6644 SNOS966Q – MAY 2001 – REVISED SEPTEMBER 2014 7.5 www.ti.com 3V Electrical Characteristics Unless otherwise specified, all limits ensured for V+ = 3V, V− = 0V, VCM = VO = V+/2, VID (input differential voltage) as noted (where applicable) and RL = 2kΩ to V+/2. PARAMETER TEST CONDITIONS MIN −3dB BW BW V+ = 3V, V− = 0V, VCM = VO = V+/2, VID RL = 2 kΩ to V+/2 AT TEMPERATURE EXTREMES TYP MAX AV = +1, VOUT = 200mVPP MIN (1) TYP (2) 80 115 AV = +2, −1, VOUT = 200mVPP 46 BW0.1dB 0.1dB Gain Flatness AV = +2, RL = 150Ω to V+/2, Rf = 402Ω, VOUT = 200mVPP 19 PBW Full Power Bandwidth AV = +1, −1dB, VOUT = 1VPP 40 en Input-Referred Voltage Noise f = 100kHz 17 f = 1kHz 48 Input-Referred Current Noise f = 100kHz THD Total Harmonic Distortion f = 5MHz, VO = 2VPP, AV = −1, RL = 100Ω to V+/2 DG Differential Gain VCM = 1V, NTSC, AV = +2 RL =150Ω to V+/2 in f = 1kHz MHz MHz MHz nV/√Hz pA/√Hz 3.3 −48 dBc 0.17% RL =1kΩ to V /2 Differential Phase MAX (1) 0.90 + DP UNIT 0.03% VCM = 1V, NTSC, AV = +2 RL =150Ω to V+/2 0.05 RL =1kΩ to V+/2 0.03 deg CT Rej. Cross-Talk Rejection f = 5MHz, Receiver: Rf = Rg = 510Ω, AV = +2 47 TS Settling Time VO = 2VPP, ±0.1%, 8pF Load, VS = 5V 68 SR Slew Rate VOS Input Offset Voltage For LMH6642 and LMH6644 ±7 ±1 ±5 For LMH6643 ±7 ±1 ±3.4 TC VOS Input Offset Average Drift See (4) IB Input Bias Current See (5) IOS Input Offset Current RIN Common Mode Input Resistance (1) (2) (3) (4) (5) 6 (3) AV = −1, VI = 2VPP 90 dB ns 120 V/µs mV µV/°C ±5 −3.25 −1.50 −2.60 µA 1000 20 800 nA 3 MΩ All limits are ensured by testing or statistical analysis. Typical values represent the most likely parametric norm. Slew rate is the average of the rising and falling slew rates. Offset voltage average drift determined by dividing the change in VOS at temperature extremes by the total temperature change. Positive current corresponds to current flowing into the device. Submit Documentation Feedback Copyright © 2001–2014, Texas Instruments Incorporated Product Folder Links: LMH6642 LMH6643 LMH6644 LMH6642, LMH6643, LMH6644 www.ti.com SNOS966Q – MAY 2001 – REVISED SEPTEMBER 2014 3V Electrical Characteristics (continued) Unless otherwise specified, all limits ensured for V+ = 3V, V− = 0V, VCM = VO = V+/2, VID (input differential voltage) as noted (where applicable) and RL = 2kΩ to V+/2. PARAMETER TEST CONDITIONS MIN CIN V+ = 3V, V− = 0V, VCM = VO = V+/2, VID RL = 2 kΩ to V+/2 AT TEMPERATURE EXTREMES TYP MIN (1) MAX Common Mode Input Capacitance pF CMRR ≥ 50dB CMRR Common Mode Rejection Ratio VCM Stepped from 0V to 1.5V AVOL Large Signal Voltage Gain VO = 0.5V to 2.5V RL = 2kΩ to V+/2 VO = 0.5V to 2.5V RL = 150Ω to V+/2 VO ISC MAX (1) 2 Input CommonMode Voltage Range CMVR TYP (2) UNIT −0.1 1.6 −0.5 1.8 2.0 72 95 75 80 96 70 74 82 −0.2 V dB dB Output Swing High RL = 2kΩ to V+/2, VID = 200mV 2.90 2.98 + 2.80 2.93 Output Swing Low RL = 2kΩ to V+/2, VID = −200mV 25 75 RL = 150Ω to V+/2, VID = −200mV 75 150 Output Short Circuit Current Sourcing to V+/2 VID = 200mV (6) RL = 150Ω to V /2, VID = 200mV 35 50 95 40 55 110 V mA + Sinking to V /2 VID = −200mV (6) IOUT Output Current VOUT = 0.5V from either supply +PSRR Positive Power Supply Rejection Ratio V+ = 3.0V to 3.5V, VCM = 1.5V Supply Current (per channel) No Load IS (6) mV ±65 mA dB 75 4.50 85 2.70 4.00 mA Short circuit test is a momentary test. See Note 7 under 5 V Electrical Characteristics. Copyright © 2001–2014, Texas Instruments Incorporated Product Folder Links: LMH6642 LMH6643 LMH6644 Submit Documentation Feedback 7 LMH6642, LMH6643, LMH6644 SNOS966Q – MAY 2001 – REVISED SEPTEMBER 2014 7.6 www.ti.com 5V Electrical Characteristics Unless otherwise specified, all limits ensured for V+ = 5V, V− = 0V, VCM = VO = V+/2, VID (input differential voltage) as noted (where applicable) and RL = 2kΩ to V+/2. PARAMETER TEST CONDITIONS AT TEMPERATURE EXTREMES MIN −3dB BW BW TYP MAX AV = +1, VOUT = 200mVPP V+ = 5V, V− = 0V, VCM = VO = V+/2, VID RL = 2kΩ to V+/2 MIN (1) TYP (2) 90 120 AV = +2, −1, VOUT = 200mVPP 46 BW0.1dB 0.1dB Gain Flatness AV = +2, RL = 150Ω to V+/2, Rf = 402Ω, VOUT = 200mVPP 15 PBW Full Power Bandwidth AV = +1, −1dB, VOUT = 2VPP 22 en Input-Referred Voltage Noise f = 100kHz 17 f = 1kHz 48 Input-Referred Current Noise f = 100kHz THD Total Harmonic Distortion f = 5MHz, VO = 2VPP, AV = +2 DG Differential Gain NTSC, AV = +2 RL =150Ω to V+/2 in f = 1kHz MHz MHz MHz nV/√Hz pA/√Hz 3.3 dBc −60 0.16% RL = 1kΩ to V /2 Differential Phase MAX (1) 0.90 + DP UNIT 0.05% NTSC, AV = +2 RL = 150Ω to V+/2 0.05 RL = 1kΩ to V+/2 0.01 CT Rej. Cross-Talk Rejection TS Settling Time SR Slew Rate VOS Input Offset Voltage For LMH6642 and LMH6644 ±7 ±1 ±5 For LMH6643 ±7 ±1 ±3.4 TC VOS Input Offset Average Drift See (4) IB Input Bias Current See (5) IOS Input Offset Current RIN Common Mode Input Resistance 3 Common Mode Input Capacitance 2 CIN f = 5MHz, Receiver: Rf = Rg = 510Ω, AV = +2 deg (3) VO = 2VPP, ±0.1%, 8pF Load AV = −1, VI = 2VPP ns V/µs mV µV/°C −3.25 −1.70 −2.60 µA 1000 20 800 nA pF CMRR Common Mode Rejection Ratio VCM Stepped from 0V to 3.5V AVOL Large Signal Voltage Gain VO = 0.5V to 4.50V RL = 2kΩ to V+/2 VO = 0.5V to 4.25V RL = 150Ω to V+/2 8 68 125 MΩ CMRR ≥ 50dB (1) (2) (3) (4) (5) 95 dB ±5 Input CommonMode Voltage Range CMVR 47 −0.1 3.6 −0.5 3.8 4.0 72 95 82 86 98 72 76 82 −0.2 V dB dB All limits are ensured by testing or statistical analysis. Typical values represent the most likely parametric norm. Slew rate is the average of the rising and falling slew rates. Offset voltage average drift determined by dividing the change in VOS at temperature extremes by the total temperature change. Positive current corresponds to current flowing into the device. Submit Documentation Feedback Copyright © 2001–2014, Texas Instruments Incorporated Product Folder Links: LMH6642 LMH6643 LMH6644 LMH6642, LMH6643, LMH6644 www.ti.com SNOS966Q – MAY 2001 – REVISED SEPTEMBER 2014 5V Electrical Characteristics (continued) Unless otherwise specified, all limits ensured for V+ = 5V, V− = 0V, VCM = VO = V+/2, VID (input differential voltage) as noted (where applicable) and RL = 2kΩ to V+/2. PARAMETER TEST CONDITIONS AT TEMPERATURE EXTREMES MIN VO ISC IOUT IS (6) (7) MAX MIN (1) TYP (2) Output Swing High RL = 2kΩ to V /2, VID = 200mV 4.90 4.98 RL = 150Ω to V+/2, VID = 200mV 4.65 4.90 Output Swing Low RL = 2kΩ to V+/2, VID = −200mV Output Short Circuit Current Sourcing to V+/2 VID = 200mV (6) (7) 40 55 115 Sinking to V+/2 VID = −200mV (6) (7) 55 70 140 Output Current +PSRR TYP + V+ = 5V, V− = 0V, VCM = VO = V+/2, VID RL = 2kΩ to V+/2 RL = 150Ω to V+/2, VID = −200mV UNIT MAX (1) V 25 100 100 150 mA VO = 0.5V from either supply ±70 mA + Positive Power Supply Rejection Ratio V = 4.0V to 6V Supply Current (per channel) No Load mV dB 79 5.00 90 2.70 4.25 mA Short circuit test is a momentary test. See Note 7. Output short circuit duration is infinite for VS < 6V at room temperature and below. For VS > 6V, allowable short circuit duration is 1.5ms. Copyright © 2001–2014, Texas Instruments Incorporated Product Folder Links: LMH6642 LMH6643 LMH6644 Submit Documentation Feedback 9 LMH6642, LMH6643, LMH6644 SNOS966Q – MAY 2001 – REVISED SEPTEMBER 2014 7.7 www.ti.com ±5V Electrical Characteristics Unless otherwise specified, all limits ensured for V+ = 5V, V− = −5V, VCM = VO = 0V, VID (input differential voltage) as noted (where applicable) and RL = 2kΩ to ground. PARAMETER TEST CONDITIONS MIN −3dB BW BW V+ = 5V, V− = −5V, VCM = VO = 0V, VID AT TEMPERATURE EXTREMES TYP MAX AV = +1, VOUT = 200mVPP MIN (1) TYP (2) 95 130 AV = +2, −1, VOUT = 200mVPP 46 BW0.1dB 0.1dB Gain Flatness AV = +2, RL = 150Ω to V+/2, Rf = 806Ω, VOUT = 200mVPP 12 PBW Full Power Bandwidth AV = +1, −1dB, VOUT = 2VPP 24 en Input-Referred Voltage Noise f = 100kHz 17 f = 1kHz 48 Input-Referred Current Noise f = 100kHz THD Total Harmonic Distortion f = 5MHz, VO = 2VPP, AV = +2 DG Differential Gain NTSC, AV = +2 RL = 150Ω to V+/2 0.15% RL = 1kΩ to V+/2 0.01% in DP Differential Phase UNIT MAX (1) MHz MHz MHz nV/√Hz 0.90 f = 1kHz pA/√Hz 3.3 dBc −62 NTSC, AV = +2 RL = 150Ω to V+/2 0.04 RL = 1kΩ to V+/2 0.01 deg CT Rej. Cross-Talk Rejection f = 5MHz, Receiver: Rf = Rg = 510Ω, AV = +2 47 TS Settling Time VO = 2VPP, ±0.1%, 8pF Load, VS = 5V 68 SR Slew Rate VOS Input Offset Voltage For LMH6642 and LMH6644 ±7 ±1 ±5 For LMH6643 ±7 ±1 ±3.4 TC VOS Input Offset Average Drift See (4) IB Input Bias Current See (5) IOS Input Offset Current RIN Common Mode Input Resistance 3 Common Mode Input Capacitance 2 CIN CMVR CMRR (1) (2) (3) (4) (5) 10 (3) AV = −1, VI = 2VPP 100 dB ns 135 V/µs mV µV/°C ±5 −3.25 −1.60 −2.60 µA 1000 20 800 nA MΩ pF Input CommonMode Voltage Range CMRR ≥ 50dB Common Mode Rejection Ratio VCM Stepped from −5V to 3.5V −5.1 3.6 −5.5 3.8 4.0 74 95 −5.2 V dB All limits are ensured by testing or statistical analysis. Typical values represent the most likely parametric norm. Slew rate is the average of the rising and falling slew rates. Offset voltage average drift determined by dividing the change in VOS at temperature extremes by the total temperature change. Positive current corresponds to current flowing into the device. Submit Documentation Feedback Copyright © 2001–2014, Texas Instruments Incorporated Product Folder Links: LMH6642 LMH6643 LMH6644 LMH6642, LMH6643, LMH6644 www.ti.com SNOS966Q – MAY 2001 – REVISED SEPTEMBER 2014 ±5V Electrical Characteristics (continued) Unless otherwise specified, all limits ensured for V+ = 5V, V− = −5V, VCM = VO = 0V, VID (input differential voltage) as noted (where applicable) and RL = 2kΩ to ground. PARAMETER TEST CONDITIONS AT TEMPERATURE EXTREMES MIN AVOL VO ISC IOUT Large Signal Voltage Gain MAX MIN (1) TYP (2) VO = −4.5V to 4.5V, RL = 2kΩ 84 88 96 VO = −4.0V to 4.0V, RL = 150Ω 74 78 82 UNIT MAX (1) dB Output Swing High RL = 2kΩ, VID = 200mV 4.90 4.96 RL = 150Ω, VID = 200mV 4.65 4.80 Output Swing Low RL = 2kΩ, VID = −200mV −4.96 −4.90 RL = 150Ω, VID = −200mV −4.80 −4.65 Output Short Circuit Current Sourcing to Ground VID = 200mV (6) (7) 35 60 115 Sinking to Ground VID = −200mV (6) (7) 65 85 145 Output Current + V ±75 mA − Power Supply Rejection Ratio (V , V ) = (4.5V, −4.5V) to (5.5V, −5.5V) IS Supply Current (per channel) No Load V mA VO = 0.5V from either supply PSRR (6) (7) TYP V+ = 5V, V− = −5V, VCM = VO = 0V, VID 78 5.50 dB 90 2.70 4.50 mA Short circuit test is a momentary test. See (7). Output short circuit duration is infinite for VS < 6V at room temperature and below. For VS > 6V, allowable short circuit duration is 1.5ms. Copyright © 2001–2014, Texas Instruments Incorporated Product Folder Links: LMH6642 LMH6643 LMH6644 Submit Documentation Feedback 11 LMH6642, LMH6643, LMH6644 SNOS966Q – MAY 2001 – REVISED SEPTEMBER 2014 www.ti.com 7.8 Typical Performance Characteristics V+ = +5, V− = −5V, RF = RL = 2 kΩ. Unless otherwise specified. +3 VS = ±1.5V VS = ±5V +2 VS = ±2.5V -1 GAIN (dB) NORMALIZED GAIN (dB) 0 VS = ±5V -2 -3 VS = ±1.5V VS = ±2.5V VS = ±5V AV = +1 RL = 2k RL = 2k +1 VOUT = 0.2VPP 0 -1 AV = +10 -2 -3 AV = +5 AV = +2 AV = +1 VOUT = 0.2VPP 100k 1M 10M 200M 10k 100k 1M FREQUENCY (Hz) Figure 1. Closed Loop Frequency Response for Various Supplies +3 0 -40°C -2 VOUT = 0.2VPP 25°C -4 0 -1 -2 -6 GAIN (dB) NORMALIZED GAIN (dB) AV = +1 AV = +10 -3 VS = ±1.5V AV = +5 RL = 2k AV = +1 AV = +2 10k 100k 1M VO = 0.2VPP 10M 100M 500M 10k 100k FREQUENCY (Hz) 1M 10M Figure 4. Closed Loop Frequency Response for Various Temperature ±1.5V 7.0 85°C 0 ±2.5V 6.5 -2 25°C 6.0 -4 ±5V 5.5 GAIN (dB) GAIN (dB) 100M 500M FREQUENCY (Hz) Figure 3. Closed Loop Gain vs. Frequency for Various Gain 5.0 AV = +2 VS = ±5V RF = 2k AV = +1 VO = 0.2VPP 100k -40°C RL = 2k RL = 150 1M VOUT = 0.2VPP 10M 200M 10k 100k FREQUENCY (Hz) Figure 5. Closed Loop Gain vs. Frequency for Various Supplies 12 500 M Figure 2. Closed Loop Gain vs. Frequency for Various Gain RL = 2k +1 100M 85°C VS = ±1.5V +2 10M FREQUENCY (Hz) Submit Documentation Feedback 1M 10M 100M 500M FREQUENCY (Hz) Figure 6. Closed Loop Frequency Response for Various Temperature Copyright © 2001–2014, Texas Instruments Incorporated Product Folder Links: LMH6642 LMH6643 LMH6644 LMH6642, LMH6643, LMH6644 www.ti.com SNOS966Q – MAY 2001 – REVISED SEPTEMBER 2014 Typical Performance Characteristics (continued) V+ = +5, V− = −5V, RF = RL = 2 kΩ. Unless otherwise specified. 8.0 8.0 ±2.5V 6.0 4.0 4VPP 2.0 ±5 2.0 0.0 0.0 GAIN (dB) GAIN (dB) 2VPP ±5V 4.0 ±1.5V 6.0 ±2.5V AV = +2 VO = 0.2VPP RF = RL = 2k AV = +2 RF = RL = 2k 100k 1M 10M 200M 1M 100k FREQUENCY (Hz) 10M 200M FREQUENCY (Hz) Figure 7. Large Signal Frequency Response Figure 8. Closed Loop Small Signal Frequency Response for Various Supplies ±5V 6 ±1.5V 4 ±1.5V +0.3 2 +0.2 GAIN (dB) GAIN (dB) ±2.5V 0 0 +25 -0.1 AV = +2 RF = 806: -65 AV = +2 -110 ±2.5V RL = 150: 10M 200M 100K FREQUENCY (Hz) -20 VO = 0.4VPP RF = 806: RL 150: 1M ±5V PHASE VO = 0.4VPP 100K ±5V GAIN +0.1 PHASE (deg) ±2.5V -155 ±1.5V 1M 10M 200M FREQUENCY (Hz) Figure 9. Closed Loop Frequency Response for Various Supplies Figure 10. ±0.1dB Gain Flatness for Various Supplies 5 3 RL = 2k 4 RL = 100: VOUT (VPP) VOUT (VPP) 2 3 2 1 VS = 5V 1 VS = 3V AV = -1 0 100k 1M 10M 100M AV = -1 Rf = 2k RL = 2K to VS/2 0 100K 1M FREQUENCY (Hz) Figure 11. VOUT (VPP) for THD < 0.5% 10M 100M FREQUENCY (Hz) Figure 12. VOUT (VPP) for THD < 0.5% Copyright © 2001–2014, Texas Instruments Incorporated Product Folder Links: LMH6642 LMH6643 LMH6644 Submit Documentation Feedback 13 LMH6642, LMH6643, LMH6644 SNOS966Q – MAY 2001 – REVISED SEPTEMBER 2014 www.ti.com Typical Performance Characteristics (continued) V+ = +5, V− = −5V, RF = RL = 2 kΩ. Unless otherwise specified. 80 10 85°C 9 RL = 2K 8 60 GAIN (dB) VOUT (VPP) 6 5 4 PHASE (Deg) PHASE 7 40 60 GAIN 20 40 -40°C 20 3 RL = 100: 2 0 VS = ±5V 1 AV = -1 0 100k 1M 10M 100M 0 VS = ±1.5V RL= 2k -20 10k 100k 25°C 1M 10M 150M FREQUENCY (Hz) FREQUENCY (Hz) Figure 14. Open Loop Gain/Phase for Various Temperature Figure 13. VOUT (VPP) for THD < 0.5% 80 -80 85°C -75 GAIN 60 -70 40 60 20 40 25°C -65 HD2 (dBc) PHASE (Deg) GAIN (dB) PHASE 20 0 RL = 2k -20 10k 100k -50 10MHz VS = 5V -40 -40°C 1M -55 -45 0 VS = ±5V 5MHz -60 AV = -1 -35 R = 2k to V /2 L S 10M -30 150M 0 FREQUENCY (Hz) 1 2 3 4 5 VOUT (VPP) Figure 16. HD2 (dBc) vs. Output Swing Figure 15. Open Loop Gain/Phase for Various Temperature -90 -80 100:,1MHz -75 -80 -70 100:5MHz -70 -65 2k:, 5MHz HD2 (dBc) HD3 (dBc) 5MHz -60 -55 -50 -45 -60 -50 2k:, 10MHz -40 VS = 5V -40 10MHz AV = -1 -35 RL = 2k to VS/2 -30 0 1 2 3 4 5 100:, 10MHz -30 VS = 5V, AV = +2 RL = 2k: & 100: to VS/2 -20 0.0 1.0 2.0 3.0 VOUT (VPP) Figure 17. HD3 (dBc) vs. Output Swing 14 Submit Documentation Feedback 4.0 5.0 VOUT (VPP) Figure 18. HD2 vs. Output Swing Copyright © 2001–2014, Texas Instruments Incorporated Product Folder Links: LMH6642 LMH6643 LMH6644 LMH6642, LMH6643, LMH6644 www.ti.com SNOS966Q – MAY 2001 – REVISED SEPTEMBER 2014 Typical Performance Characteristics (continued) V+ = +5, V− = −5V, RF = RL = 2 kΩ. Unless otherwise specified. -90 -80 100:,1MHz VS = 5V -70 -70 AV = -1 -65 THD (dBc) HD3 (dBc) RL = 2k TO VS/2 -75 -80 2k:,5MHz -60 2k:,10MHz -50 -60 5MHz -55 -50 -45 100:, 5MHz -40 -40 -30 VS = 5V, AV = +2 RL = 2k: &100: to VS/2 100:, 10MHz -20 0.0 1.0 2.0 3.0 4.0 5.0 10MHz -35 -30 0 1 2 VOUT (VPP) 3 4 5 VOUT (VPP) Figure 19. HD3 vs. Output Swing Figure 20. THD (dBc) vs. Output Swing 1k 80 100 60 40 30 10 VOLTAGE CURRENT 1 10 VS = 5V 20 AV = -1 Rf = RL = 2k CL = 8pF 0 1 1.5 0.5 INPUT STEP AMPLITUDE (VPP) 1 10 2 100 0.1 1M 10 10 VS=±1.5V VOUT FROM V (V) VS = ±1.5V 1 1 - + 1K 10K 100K FREQUENCY (Hz) Figure 22. Input Noise vs. Frequency Figure 21. Settling Time vs. Input Step Amplitude (Output Slew and Settle Time) VOUT FROM V (V) in (pA/ Hz) 10 100 50 en (nV/ Hz) ±0.1% SETTLING TIME 70 85°C 0.1 85°C 0.1 -40°C -40°C 25°C 25°C 0.01 0.01 1 10 100 1k 1 10 100 1K ISOURCE (mA) ISINK (mA) Figure 23. VOUT from V+ vs. ISOURCE Figure 24. VOUT from V− vs. ISINK Copyright © 2001–2014, Texas Instruments Incorporated Product Folder Links: LMH6642 LMH6643 LMH6644 Submit Documentation Feedback 15 LMH6642, LMH6643, LMH6644 SNOS966Q – MAY 2001 – REVISED SEPTEMBER 2014 www.ti.com Typical Performance Characteristics (continued) V+ = +5, V− = −5V, RF = RL = 2 kΩ. Unless otherwise specified. 10 10 VS = ±5V VS = ±5V 85°C -40°C VOUT FROM V (V) 1 - + VOUT FROM V (V) 25°C 1 85° C 0.1 -40°C 85°C 0.1 -40°C 25°C 0.01 0.01 1 10 100 1 1k 100 1k ISINK (mA) Figure 25. VOUT from V+ vs. ISOURCE Figure 26. VOUT from V− vs. ISINK 180 160 RL = 150: 85°C, Sink 85°C, Sourcing -40°C, Sink 160 140 25°C, Sink 25°C, Sourcing 140 120 120 -40°C, Sourcing ISC (mA) VOUT FROM SUPPLY (mV) 10 ISOURCE (mA) 100 80 100 25°C, Source 80 60 60 85°C, Sinking 40 -40°C, Source 25°C, Sinking 40 85°C, Source 20 -40°C, Sinking 0 20 2 3 4 5 6 7 VS (V) 8 9 2 10 4 5 6 Figure 27. Swing vs. VS 8 9 10 Figure 28. Short Circuit Current (to VS/2) vs. VS 1 VS = ±2.5 0.9 VS = ±2.5V 0.9 0.8 0.8 VOUT FROM V (V) 85°C + 0.7 0.6 0.5 25°C 0.4 0.3 0.2 25°C 0.7 0.6 85°C 0.5 0.4 0.3 0.2 -40°C 0.1 0.1 0 0 0 20 40 60 80 100 120 -40°C 0 20 ISINK(mA) Submit Documentation Feedback 40 60 80 100 120 ISOURCING (mA) Figure 29. Output Sinking Saturation Voltage vs. IOUT 16 7 VS (V) 1 VOUT FROM V- (V) 3 Figure 30. Output Sourcing Saturation Voltage vs. IOUT Copyright © 2001–2014, Texas Instruments Incorporated Product Folder Links: LMH6642 LMH6643 LMH6644 LMH6642, LMH6643, LMH6644 www.ti.com SNOS966Q – MAY 2001 – REVISED SEPTEMBER 2014 Typical Performance Characteristics (continued) V+ = +5, V− = −5V, RF = RL = 2 kΩ. Unless otherwise specified. 1000 90 AV = +1 VS = 5V 80 100 AV = +10 70 + PSRR PSRR (dB) ZOUT (:) 60 10 1 50 40 - PSRR 30 20 0.1 10 0.01 1k 0 10k 100k 10M 1M 100M 10k 100k FREQUENCY (Hz) 10M 100M Figure 32. PSRR vs. Frequency 100 100 90 90 80 80 CT (rej) (dB) CMRR (dB) Figure 31. Closed Loop Output Impedance vs. Frequency AV = +1 70 60 50 70 60 50 VS = 5V 40 40 AV = +6 30 100 1k Receive CH.: AV = +2, Rf = Rg = 510 30 10k 100k 1M 10M 1k 10k 100k 1M 10M FREQUENCY (Hz) FREQUENCY (Hz) Figure 33. CMRR vs. Frequency Figure 34. Crosstalk Rejection vs. Frequency (Output to Output) 2 1 VS = 10V VS = 5V 0.8 1.5 RL = 150: to V+/2 0.6 1.0 0.4 85°C 0.2 VOS (mV) VOS (mV) 1M FREQUENCY (Hz) 85°C 0 -0.2 -0.4 0.5 0 25°C -0.5 25°C -1 -40°C -0.6 -1.5 -0.8 -40°C -1 -2 -2 VOUT (V) 4 VCM (V) Figure 35. VOS vs. VOUT (Typical Unit) Figure 36. VOS vs. VCM (Typical Unit) 0 1 2 3 4 5 Copyright © 2001–2014, Texas Instruments Incorporated Product Folder Links: LMH6642 LMH6643 LMH6644 0 2 6 8 10 Submit Documentation Feedback 17 LMH6642, LMH6643, LMH6644 SNOS966Q – MAY 2001 – REVISED SEPTEMBER 2014 www.ti.com Typical Performance Characteristics (continued) V+ = +5, V− = −5V, RF = RL = 2 kΩ. Unless otherwise specified. 1 1 -40°C 0.8 0.8 Unit #1 0.6 0.4 0.4 0.2 0.2 VOS (mV) VOS (mV) Unit #1 0.6 0 -0.2 25°C 0 Unit #2 -0.2 Unit #2 -0.4 -0.4 Unit #3 -0.6 -0.6 Unit #3 -0.8 -0.8 -1 -1 2 4 6 8 10 12 2 3 4 5 8 7 9 10 11 VS (V) Figure 37. VOS vs. VS (for 3 Representative Units) Figure 38. VOS vs. VS (for 3 Representative Units) 1 -1000 0.8 -1100 Unit #1 0.6 -1200 0.4 -1300 0.2 IB (nA) VOS (mV) 85°C 0 Unit #2 -0.2 -40°C -1400 25°C -1500 -1600 -0.4 85°C -1700 -0.6 Unit #3 -1800 -0.8 -1900 -1 2 3 4 5 6 8 7 9 10 2 12 4 6 10 12 Figure 40. IB vs. VS Figure 39. VOS vs. VS (for 3 Representative Units) 50 4 45 3.5 VS = 10V 85°C IS (mA) (PER CHANNEL) 40 35 IOS (nA) 8 VS (V) VS (V) 30 25 -40°C 20 15 25°C 10 5 2 4 3 2.5 25°C 2 -40°C 1.5 1 0.5 0 85°C 0 18 6 VS (V) 6 8 10 12 -0.5 -2 VS (V) 4 VCM (V) Figure 41. IOS vs. VS Figure 42. IS vs. VCM Submit Documentation Feedback 0 2 6 8 10 Copyright © 2001–2014, Texas Instruments Incorporated Product Folder Links: LMH6642 LMH6643 LMH6644 LMH6642, LMH6643, LMH6644 www.ti.com SNOS966Q – MAY 2001 – REVISED SEPTEMBER 2014 Typical Performance Characteristics (continued) V+ = +5, V− = −5V, RF = RL = 2 kΩ. Unless otherwise specified. 4 VS = 3V VO = 100mVPP IS (mA) (PER CHANNEL) 85°C RL = 2k to VS/2 AV = -1 3 25°C 2 -40°C 1 2 4 6 8 10 12 20 ns/DIV 40 mV/DIV VS (V) Figure 43. IS vs. VS Figure 44. Small Signal Step Response AV = +2 VS = ±5V VO = 8VPP AV = +1 RL= 2k VS=±1.5V VO=2VPP AV= -1 RL=2k 4 /DIV 200.0 ns/DIV Figure 45. Large Signal Step Response 400 mV/DIV Figure 46. Large Signal Step Response VS = 3V VS = ±5V VO = 100mVPP VO = 100mVPP RL = 2k to VS/2 AV = +1, RL = 2k AV = +1 40 mV/DIV 40.0 nS/DIV 10 ns/DIV Figure 47. Small Signal Step Response 40 mV/DIV 10.0 ns/DIV Figure 48. Small Signal Step Response Copyright © 2001–2014, Texas Instruments Incorporated Product Folder Links: LMH6642 LMH6643 LMH6644 Submit Documentation Feedback 19 LMH6642, LMH6643, LMH6644 SNOS966Q – MAY 2001 – REVISED SEPTEMBER 2014 www.ti.com Typical Performance Characteristics (continued) V+ = +5, V− = −5V, RF = RL = 2 kΩ. Unless otherwise specified. VS = ±5V VS = ±5V VO = 200mVPP AV = +2, RL = 2k VO = 100mVPP RL = 2k AV = -1 40 mV/DIV 20 ns/DIV 40 mV/DIV Figure 49. Small Signal Step Response Figure 50. Small Signal Step Response VS = ±5V VS = ±5V VO = 8VPP VO = 2VPP AV = +2 RL = 2k RL = 2k AV = -1 2 V/DIV 400 mV/DIV 40.0 ns/DIV 20 ns/DIV Figure 52. Large Signal Step Response Figure 51. Large Signal Step Response AV = -1 VS = ±5V VOUT = 8VPP RL = 2K: 2 V/DIV 20.0 ns/DIV 100 ns/DIV Figure 53. Large Signal Step Response 20 Submit Documentation Feedback Copyright © 2001–2014, Texas Instruments Incorporated Product Folder Links: LMH6642 LMH6643 LMH6644 LMH6642, LMH6643, LMH6644 www.ti.com SNOS966Q – MAY 2001 – REVISED SEPTEMBER 2014 8 Detailed Description 8.1 Overview The LMH664X family is based on proprietary VIP10 dielectrically isolated bipolar process. This device family architecture features the following: • Complimentary bipolar devices with exceptionally high ft (∼8 GHz) even under low supply voltage (2.7 V) and low bias current. • A class A-B “turn-around” stage with improved noise, offset, and reduced power dissipation compared to similar speed devices (patent pending). • Common Emitter push-push output stage capable of 75 mA output current (at 0.5 V from the supply rails) while consuming only 2.7 mA of total supply current per channel. This architecture allows output to reach within mV of either supply rail. • Consistent performance over the entire operating supply voltage range with little variation for the most important specifications (for example, BW, SR, IOUT, and so forth) • Significant power saving (∼40%) compared to competitive devices on the market with similar performance. 8.2 Functional Block Diagram V+ V+ V+ R R IN- IN+ V- V- Figure 54. Input Equivalent Circuit 8.3 Feature Description The LMH664X family is a drop-in replacement for the AD805X family of high speed Op Amps in most applications. In addition, the LMH664X will typically save about 40% on power dissipation, due to lower supply current, when compared to competition. All AD805X family’s specified parameters are included in the list of LMH664X ensured specifications in order to ensure equal or better level of performance. However, as in most high performance parts, due to subtleties of applications, it is strongly recommended that the performance of the part to be evaluated is tested under actual operating conditions to ensure full compliance to all specifications. 8.4 Device Functional Modes With 3-V supplies and a common mode input voltage range that extends 0.5 V below V−, the LMH664X find applications in low voltage/low power applications. Even with 3-V supplies, the −3dB BW (@ AV = +1) is typically 115 MHz with a tested limit of 80 MHz. Production testing guarantees that process variations will not compromise speed. High frequency response is exceptionally stable, confining the typical −3dB BW over the industrial temperature range to ±2.5%. As seen in Typical Performance Characteristics, the LMH664X output current capability (∼75 mA) is enhanced compared to AD805X. This enhancement increases the output load range, adding to the LMH664X’s versatility. Since LMH664X is capable of high output current, device junction temperature should not to exceed the Absolute Maximum Ratings. Copyright © 2001–2014, Texas Instruments Incorporated Product Folder Links: LMH6642 LMH6643 LMH6644 Submit Documentation Feedback 21 LMH6642, LMH6643, LMH6644 SNOS966Q – MAY 2001 – REVISED SEPTEMBER 2014 www.ti.com 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information This device family was designed to avoid output phase reversal. With input overdrive, the output is kept near supply rail (or as closed to it as mandated by the closed loop gain setting and the input voltage). See Figure 56. However, if the input voltage range of −0.5 V to 1 V from V+ is exceeded by more than a diode drop, the internal ESD protection diodes will start to conduct. The current in the diodes should be kept at or below 10 mA. Output overdrive recovery time is less than 100 ns as can be seen in Figure 57. 9.2 Typical Application Cf 5pF Photodiode Equivalent Circuit Vbias Rbias Rf 1k: C1 100nF Q1 2N3904 VCC = +5V -1mAPP - Cd Photodiode Rd 10 200pF Id ×100k: R5 510: R2 1.8k: x Vout + D1 1N4148 R11 910 : R10 1k: R3 1k: +5V Figure 55. Single Supply Photodiode I-V Converter 9.2.1 Design Requirements The circuit shown in Figure 55 is used to amplify the current from a photodiode into a voltage output. In this circuit, the emphasis is on achieving high bandwidth and the transimpedance gain setting is kept relatively low. Because of its high slew rate limit and high speed, the LMH664X family lends itself well to such an application. This circuit achieves approximately 1V/mA of transimpedance gain and capable of handling up to 1mApp from the photodiode. Q1, in a common base configuration, isolates the high capacitance of the photodiode (Cd) from the Op Amp input in order to maximize speed. Input is AC coupled through C1 to ease biasing and allow single supply operation. With 5-V single supply, the device input/output is shifted to near half supply using a voltage divider from VCC. Note that Q1 collector does not have any voltage swing and the Miller effect is minimized. D1, tied to Q1 base, is for temperature compensation of Q1’s bias point. Q1 collector current was set to be large enough to handle the peak-to-peak photodiode excitation and not too large to shift the U1 output too far from mid-supply. 22 Submit Documentation Feedback Copyright © 2001–2014, Texas Instruments Incorporated Product Folder Links: LMH6642 LMH6643 LMH6644 LMH6642, LMH6643, LMH6644 www.ti.com SNOS966Q – MAY 2001 – REVISED SEPTEMBER 2014 Typical Application (continued) 9.2.1.1 Input and Output Topology All input / output pins are protected against excessive voltages by ESD diodes connected to V+ and V- rails (see Figure 54). These diodes start conducting when the input / output pin voltage approaches 1Vbe beyond V+ or Vto protect against over voltage. These diodes are normally reverse biased. Further protection of the inputs is provided by the two resistors (R in Figure 54), in conjunction with the string of anti-parallel diodes connected between both bases of the input stage. The combination of these resistors and diodes reduces excessive differential input voltages approaching 2Vbe. This occurs most commonly when the device is used as a comparator (or with little or no feedback) and the device inputs no longer follow each other. In such a case, the diodes may conduct. As a consequence, input current increases and the differential input voltage is clamped. It is important to make sure that the subsequent current flow through the device input pins does not violate the Absolute Maximum Ratings of the device. To limit the current through this protection circuit, extra series resistors can be placed. Together with the built-in series resistors of several hundred ohms, these external resistors can limit the input current to a safe number (that is, less than 10mA). Be aware that these input series resistors may impact the switching speed of the device and could slow down the device. 9.2.1.2 Single Supply, Low Power Photodiode Amplifier The circuit shown in Figure 55 is used to amplify the current from a photodiode into a voltage output. In this circuit, the emphasis is on achieving high bandwidth and the transimpedance gain setting is kept relatively low. Because of its high slew rate limit and high speed, the LMH664X family lends itself well to such an application. This circuit achieves approximately 1V/mA of transimpedance gain and capable of handling up to 1mApp from the photodiode. Q1, in a common base configuration, isolates the high capacitance of the photodiode (Cd) from the Op Amp input in order to maximize speed. Input is AC coupled through C1 to ease biasing and allow single supply operation. With 5V single supply, the device input/output is shifted to near half supply using a voltage divider from VCC. Note that Q1 collector does not have any voltage swing and the Miller effect is minimized. D1, tied to Q1 base, is for temperature compensation of Q1’s bias point. Q1 collector current was set to be large enough to handle the peak-to-peak photodiode excitation and not too large to shift the U1 output too far from mid-supply. No matter how low an Rf is selected, there is a need for Cf in order to stabilize the circuit. The reason for this is that the Op Amp input capacitance and Q1 equivalent collector capacitance together (CIN) will cause additional phase shift to the signal fed back to the inverting node. Cf will function as a zero in the feedback path counteracting the effect of the CIN and acting to stabilized the circuit. By proper selection of Cf such that the Op Amp open loop gain is equal to the inverse of the feedback factor at that frequency, the response is optimized with a theoretical 45° phase margin. CF = SQRT (CIN)/(2SGBWP RF) where • GBWP is the Gain Bandwidth Product of the Op Amp (1) Optimized as such, the I-V converter will have a theoretical pole, fp, at: fP = SQRT GBWP/(2SRF CIN) (2) With Op Amp input capacitance of 3pF and an estimate for Q1 output capacitance of about 3pF as well, CIN = 6 pF. From the typical performance plots, LMH6642/6643 family GBWP is approximately 57 MHz. Therefore, with Rf = 1k, from Equation 1 and Equation 2: Cf = ∼4.1 pF and fp = 39 MHz (3) For this example, optimum Cf was empirically determined to be around 5 pF. This time domain response is shown in Figure 58 below showing about 9 ns rise/fall times, corresponding to about 39 MHz for fp. The overall supply current from the +5 V supply is around 5 mA with no load. Copyright © 2001–2014, Texas Instruments Incorporated Product Folder Links: LMH6642 LMH6643 LMH6644 Submit Documentation Feedback 23 LMH6642, LMH6643, LMH6644 SNOS966Q – MAY 2001 – REVISED SEPTEMBER 2014 www.ti.com Typical Application (continued) 9.2.2 Detailed Design Procedure No matter how low an Rf is selected, there is a need for Cf in order to stabilize the circuit. The reason for this is that the Op Amp input capacitance and Q1 equivalent collector capacitance together (CIN) will cause additional phase shift to the signal fed back to the inverting node. Cf will function as a zero in the feedback path counteracting the effect of the CIN and acting to stabilized the circuit. By proper selection of Cf such that the Op Amp open loop gain is equal to the inverse of the feedback factor at that frequency, the response is optimized with a theoretical 45° phase margin where GBWP is the Gain Bandwidth Product of the Op Amp, Optimized as such, the I-V converter will have a theoretical pole, fp, at: (2) With Op Amp input capacitance of 3pF and an estimate for Q1 output capacitance of about 3pF as well, CIN = 6 pF. From the typical performance plots, LMH6642/6643 family GBWP is approximately 57 MHz. Therefore, with Rf = 1k, from Equation 2 and Equation 3 : Cf = ∼4.1 pF and fp = 39 MHz. Single Supply Photodiode I-V Converter For this example, optimum Cf was empirically determined to be around 5 pF. This time domain response is shown in Figure 58 showing about 9 ns rise/fall times, corresponding to about 39 MHz for fp. The overall supply current from the +5 V supply is around 5 mA with no load. 9.2.3 Application Curves VIN (1 V/DIV) Output V + VOUT (VPP) Input V VS = ±2.5V - VS=±5V, VIN=5VPP AV = +1 1V/DIV AV=+5, RF=RL=2k 200 ns/DIV 2 V/DIV Figure 56. Input and Output Shown with CMVR Exceeded 200 mV/DIV VOUT (2 V/DIV) 100 ns/DIV Figure 57. Overload Recovery Waveform 20 ns/DIV Figure 58. Converter Step Response (1VPP, 20 ns/DIV) 10 Power Supply Recommendations The LMH664x device family can operate off a single supply or with dual supplies. The input CM capability of the parts (CMVR) extends all the way down to the V- rail to simplify single supply applications. Supplies should be decoupled with low inductance, often ceramic, capacitors to ground less than 0.5 inches from the device pins. The use of ground plane is recommended, and as in most high speed devices, it is advisable to remove ground plane close to device sensitive pins such as the inputs. 24 Submit Documentation Feedback Copyright © 2001–2014, Texas Instruments Incorporated Product Folder Links: LMH6642 LMH6643 LMH6644 LMH6642, LMH6643, LMH6644 www.ti.com SNOS966Q – MAY 2001 – REVISED SEPTEMBER 2014 11 Layout 11.1 Layout Guidelines Generally, a good high frequency layout will keep power supply and ground traces away from the inverting input and output pins. Parasitic capacitances on these nodes to ground will cause frequency response peaking and possible circuit oscillations (see Application Note OA-15, "Frequent Faux Pas in Applying Wideband Current Feedback Amplifiers", SNOA367, for more information). Texas Instruments suggests the following evaluation boards as a guide for high frequency layout and as an aid in device testing and characterization: Table 1. Printed Circuit Board Layout And Component Values DEVICE PACKAGE EVALUATION BOARD PN LMH6642MF 5-Pin SOT-23 LMH730216 LMH6642MA 8-Pin SOIC LMH730227 LMH6643MA 8-Pin SOIC LMH730036 LMH6643MM 8-Pin VSSOP LMH730123 LMH6644MA 14-Pin SOIC LMH730231 LMH6644MT 14-Pin TSSOP LMH730131 Another important parameter in working with high speed/high performance amplifiers, is the component values selection. Choosing external resistors that are large in value will effect the closed loop behavior of the stage because of the interaction of these resistors with parasitic capacitances. These capacitors could be inherent to the device or a by-product of the board layout and component placement. Either way, keeping the resistor values lower, will diminish this interaction to a large extent. On the other hand, choosing very low value resistors could load down nodes and will contribute to higher overall power dissipation. 11.2 Layout Example Figure 59. LMH6642/LMH6643/LMH6644 Layer 1 Figure 60. LMH6642/LMH6643/LMH6644 Layer 2 Copyright © 2001–2014, Texas Instruments Incorporated Product Folder Links: LMH6642 LMH6643 LMH6644 Submit Documentation Feedback 25 LMH6642, LMH6643, LMH6644 SNOS966Q – MAY 2001 – REVISED SEPTEMBER 2014 www.ti.com 12 Device and Documentation Support 12.1 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 2. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY LMH6642 Click here Click here Click here Click here Click here LMH6643 Click here Click here Click here Click here Click here LMH6644 Click here Click here Click here Click here Click here 12.2 Trademarks All trademarks are the property of their respective owners. 12.3 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 12.4 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 26 Submit Documentation Feedback Copyright © 2001–2014, Texas Instruments Incorporated Product Folder Links: LMH6642 LMH6643 LMH6644 PACKAGE OPTION ADDENDUM www.ti.com 27-Jul-2016 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) LMH6642MA/NOPB ACTIVE SOIC D 8 95 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LMH66 42MA LMH6642MAX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LMH66 42MA LMH6642MF NRND SOT-23 DBV 5 1000 TBD Call TI Call TI -40 to 85 A64A LMH6642MF/NOPB ACTIVE SOT-23 DBV 5 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 A64A LMH6642MFX/NOPB ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 A64A LMH6643MA NRND SOIC D 8 95 TBD Call TI Call TI -40 to 85 LMH6643MA/NOPB ACTIVE SOIC D 8 95 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LMH6643MAX NRND SOIC D 8 2500 TBD Call TI Call TI -40 to 85 LMH6643MAX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LMH6643MM NRND VSSOP DGK 8 1000 TBD Call TI Call TI -40 to 85 LMH6643MM/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 A65A LMH6643MMX/NOPB ACTIVE VSSOP DGK 8 3500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 A65A LMH6644 MDC ACTIVE DIESALE Y 0 100 Green (RoHS & no Sb/Br) Call TI Level-1-NA-UNLIM -40 to 85 LMH6644MA/NOPB ACTIVE SOIC D 14 55 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LMH6644MA LMH6644MAX/NOPB ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LMH6644MA LMH6644MT/NOPB ACTIVE TSSOP PW 14 94 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 85 LMH66 44MT LMH6644MTX/NOPB ACTIVE TSSOP PW 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 85 LMH66 44MT (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. Addendum-Page 1 LMH66 43MA LMH66 43MA Samples PACKAGE OPTION ADDENDUM www.ti.com 27-Jul-2016 NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 21-Jun-2016 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LMH6642MAX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LMH6642MF SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LMH6642MF/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LMH6642MFX/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LMH6643MAX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LMH6643MM/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LMH6643MMX/NOPB VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LMH6644MAX/NOPB SOIC D 14 2500 330.0 16.4 6.5 9.35 2.3 8.0 16.0 Q1 LMH6644MTX/NOPB TSSOP PW 14 2500 330.0 12.4 6.95 5.6 1.6 8.0 12.0 Q1 LMH6644MTX/NOPB TSSOP PW 14 2500 330.0 12.4 6.95 5.6 1.6 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 21-Jun-2016 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMH6642MAX/NOPB SOIC D 8 2500 367.0 367.0 35.0 LMH6642MF SOT-23 DBV 5 1000 210.0 185.0 35.0 LMH6642MF/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0 LMH6642MFX/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0 LMH6643MAX/NOPB SOIC D 8 2500 367.0 367.0 35.0 LMH6643MM/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 LMH6643MMX/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0 LMH6644MAX/NOPB SOIC D 14 2500 367.0 367.0 35.0 LMH6644MTX/NOPB TSSOP PW 14 2500 367.0 367.0 35.0 LMH6644MTX/NOPB TSSOP PW 14 2500 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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