ON MTP2955VG Power mosfet Datasheet

MTP2955V
Preferred Device
Power MOSFET
12 Amps, 60 Volts
P−Channel TO−220
This Power MOSFET is designed to withstand high energy in the
avalanche and commutation modes. Designed for low voltage, high
speed switching applications in power supplies, converters and power
motor controls, these devices are particularly well suited for bridge
circuits where diode speed and commutating safe operating areas are
critical and offer additional safety margin against unexpected voltage
transients.
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12 AMPERES, 60 VOLTS
RDS(on) = 230 mW
P−Channel
D
Features
• Avalanche Energy Specified
• IDSS and VDS(on) Specified at Elevated Temperature
• Pb−Free Package is Available*
G
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
S
Symbol
Value
Unit
Drain−to−Source Voltage
VDSS
60
Vdc
Drain−to−Gate Voltage (RGS = 1.0 M)
VDGR
60
Vdc
Gate−to−Source Voltage
− Continuous
− Non−Repetitive (tp ≤ 10 s)
VGS
VGSM
± 15
± 25
Vdc
Vpk
ID
ID
12
8.0
42
Adc
PD
60
0.40
W
W/°C
TJ, Tstg
−55 to 175
°C
EAS
216
mJ
Drain Current − Continuous
Drain Current − Continuous @ 100°C
Drain Current − Single Pulse (tp ≤ 10 s)
Total Power Dissipation
Derate above 25°C
Operating and Storage Temperature Range
Single Pulse Drain−to−Source Avalanche
Energy − Starting TJ = 25°C
(VDD = 25 Vdc, VGS = 10 Vdc, Peak
IL = 12 Apk, L = 3.0 mH, RG = 25)
Thermal Resistance
− Junction−to−Case
− Junction−to−Ambient
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from case for 10 seconds
IDM
RJC
RJA
2.5
62.5
TL
260
TO−220AB
CASE 221A
STYLE 5
Apk
°C/W
°C
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
August, 2006 − Rev. 7
4
Drain
4
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
© Semiconductor Components Industries, LLC, 2006
MARKING DIAGRAM
AND PIN ASSIGNMENT
1
1
2
MTP2955VG
AYWW
3
1
Gate
MTP2955V
A
Y
WW
G
2
Drain
3
Source
= Device Code
= Location Code
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
Device
Package
Shipping
MTP2955V
TO−220AB
50 Units/Rail
MTP2955VG
TO−220AB
(Pb−Free)
50 Units/Rail
Preferred devices are recommended choices for future use
and best overall value.
Publication Order Number:
MTP2955V/D
MTP2955V
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Symbol
Characteristic
Min
Typ
Max
Unit
60
−
−
58
−
−
Vdc
mV/°C
−
−
−
−
10
100
−
−
100
nAdc
2.0
−
2.8
5.0
4.0
−
Vdc
mV/°C
−
0.185
0.230
−
−
−
−
2.9
2.5
gFS
3.0
5.0
−
mhos
Ciss
−
550
700
pF
Coss
−
200
280
Crss
−
50
100
td(on)
−
15
30
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
(VGS = 0 Vdc, ID = 0.25 mAdc)
Temperature Coefficient (Positive)
(Cpk ≥ 2.0) (Note 3)
V(BR)DSS
Zero Gate Voltage Drain Current
(VDS = 60 Vdc, VGS = 0 Vdc)
(VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150°C)
IDSS
Gate−Body Leakage Current (VGS = ± 15 Vdc, VDS = 0 Vdc)
IGSS
Adc
ON CHARACTERISTICS (Note 1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Threshold Temperature Coefficient (Negative)
(Cpk ≥ 2.0) (Note 3)
VGS(th)
Static Drain−to−Source On−Resistance
(VGS = 10 Vdc, ID = 6.0 Adc)
(Cpk ≥ 1.5) (Note 3)
RDS(on)
Drain−to−Source On−Voltage
(VGS = 10 Vdc, ID = 12 Adc)
(VGS = 10 Vdc, ID = 6.0 Adc, TJ = 150°C)
VDS(on)
Forward Transconductance (VDS = 10 Vdc, ID = 6.0 Adc)
Vdc
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
(VDS = 25 Vdc, VGS = 0 Vdc, f = 1.0 MHz)
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS (Note 2)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
(VDD = 30 Vdc, ID = 12 Adc,
VGS = 10 Vdc, RG = 9.1 )
Fall Time
Gate Charge
(VDS = 48 Vdc, ID = 12 Adc, VGS = 10 Vdc)
tr
−
50
100
td(off)
−
24
50
tf
−
39
80
QT
−
19
30
Q1
−
4.0
−
Q2
−
9.0
−
Q3
−
7.0
−
−
−
1.8
1.5
3.0
−
trr
−
115
−
ta
−
90
−
tb
−
25
−
QRR
−
0.53
−
−
4.5
−
−
7.5
−
ns
nC
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage (Note 1)
(IS = 12 Adc, VGS = 0 Vdc)
(IS = 12 Adc, VGS = 0 Vdc, TJ = 150°C)
Reverse Recovery Time
(IS = 12 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge
VSD
Vdc
ns
C
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from the drain lead 0.25″ from package to center of die)
LD
Internal Source Inductance
(Measured from the source lead 0.25″ from package to source bond pad)
LS
1. Pulse Test: Pulse Width ≤ 300 s, Duty Cycle ≤ 2%.
2. Switching characteristics are independent of operating junction temperature.
Max limit − Typ
3. Reflects typical values.
Cpk =
3 x SIGMA
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2
nH
nH
MTP2955V
TYPICAL ELECTRICAL CHARACTERISTICS
24
VGS = 10 V
9V
8V
7V
15
10
6V
5
1
2
3
4
5
6
7
8
9
100°C
25°C
15
12
9
6
3
0
10
4
5
6
7
8
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
R DS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS)
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
9
10
21
24
0.250
VGS = 10 V
0.35
TJ = 25°C
0.225
0.30
VGS = 10 V
0.200
TJ = 100°C
0.25
0.175
25°C
0.20
0.15
15 V
0.150
0.125
−55°C
0.100
0.10
0.05
0.075
0
3
6
9
18
15
12
ID, DRAIN CURRENT (AMPS)
0.050
24
21
0
Figure 3. On−Resistance versus Drain Current
and Temperature
1000
2.0
1.8
1.6
6
3
9
18
12
15
ID, DRAIN CURRENT (AMPS)
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
VGS = 0 V
VGS = 10 V
ID = 6 A
1.4
I DSS , LEAKAGE (nA)
RDS(on) , DRAIN−TO−SOURCE RESISTANCE
(NORMALIZED)
3
2
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
0.40
0
TJ = −55°C
18
5V
0
VDS ≥ 10 V
21
20
0
R DS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS)
TJ = 25°C
I D , DRAIN CURRENT (AMPS)
I D , DRAIN CURRENT (AMPS)
25
1.2
1.0
0.8
0.6
TJ = 125°C
100°C
100
0.4
0.2
0
−50
−25
0
25
50
75
100 125
TJ, JUNCTION TEMPERATURE (°C)
150
10
175
0
Figure 5. On−Resistance Variation with
Temperature
10
20
30
40
50
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 6. Drain−To−Source Leakage
Current versus Voltage
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3
60
MTP2955V
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (t)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (IG(AV)) can be made from a
rudimentary analysis of the drive circuit so that
t = Q/IG(AV)
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the off−state condition when
calculating td(on) and is read at a voltage corresponding to the
on−state when calculating td(off).
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
During the rise and fall time interval when switching a
resistive load, VGS remains virtually constant at a level
known as the plateau voltage, VSGP. Therefore, rise and fall
times may be approximated by the following:
tr = Q2 x RG/(VGG − VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG − VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
1800
C, CAPACITANCE (pF)
1600
VDS = 0 V
VGS = 0 V
TJ = 25°C
Ciss
1400
1200
Crss
1000
800
Ciss
600
400
Coss
200
Crss
0
10
5
0
VGS
5
10
15
20
25
VDS
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
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4
30
QT
9
8
Q1
27
24
Q2
7
21
VGS
6
18
5
15
4
12
3
ID = 12 A 9
TJ = 25°C 6
2
Q3
1
0
0
2
VDS
4
6
8
10
12
14
16
18
3
0
20
1000
t, TIME (ns)
10
VDS , DRAIN−TO−SOURCE VOLTAGE (VOLTS)
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
MTP2955V
VDD = 30 V
ID = 12 A
VGS = 10 V
TJ = 25°C
100
tr
tf
td(off)
td(on)
10
1
1
10
QT, TOTAL CHARGE (nC)
RG, GATE RESISTANCE (OHMS)
Figure 8. Gate−To−Source and Drain−To−Source
Voltage versus Total Charge
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
100
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
I S , SOURCE CURRENT (AMPS)
12
11
VGS = 0 V
TJ = 25°C
10
9
8
7
6
5
4
3
2
1
0
0.5
0.7
0.9
1.1
1.3
1.5
1.7
1.9
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
a constant. The energy rating decreases non−linearly with an
increase of peak current in avalanche and peak junction
temperature.
Although many E−FETs can withstand the stress of
drain−to−source avalanche at currents up to rated pulsed
current (IDM), the energy rating is specified at rated
continuous current (ID), in accordance with industry
custom. The energy rating must be derated for temperature
as shown in the accompanying graph (Figure 13). Maximum
energy at currents below rated continuous ID can safely be
assumed to equal the values indicated.
The Forward Biased Safe Operating Area curves define the
maximum simultaneous drain−to−source voltage and drain
current that a transistor can handle safely when it is forward
biased. Curves are based upon maximum peak junction
temperature and a case temperature (TC) of 25°C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance−General
Data and Its Use.”
Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
(IDM) nor rated voltage (VDSS) is exceeded and the
transition time (tr,tf) do not exceed 10 s. In addition the total
power averaged over a complete switching cycle must not
exceed (TJ(MAX) − TC)/(RJC).
A Power MOSFET designated E−FET can be safely used
in switching circuits with unclamped inductive loads. For
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5
MTP2955V
SAFE OPERATING AREA
225
VGS = 15 V
SINGLE PULSE
TC = 25°C
EAS, SINGLE PULSE DRAIN−TO−SOURCE
AVALANCHE ENERGY (mJ)
I D , DRAIN CURRENT (AMPS)
100
10
100 s
1 ms
10 ms
1.0
dc
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.1
0.1
10
1.0
ID = 12 A
200
175
150
125
100
75
50
25
0
100
25
50
75
100
125
175
150
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
TJ, STARTING JUNCTION TEMPERATURE (°C)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. Maximum Avalanche Energy versus
Starting Junction Temperature
r(t), NORMALIZED EFFECTIVE
TRANSIENT THERMAL RESISTANCE
1.0
D = 0.5
0.2
0.1
0.1
0.05
P(pk)
0.02
0.01
SINGLE PULSE
t1
t2
DUTY CYCLE, D = t1/t2
0.01
1.0E−05
1.0E−04
1.0E−03
1.0E−02
t, TIME (s)
1.0E−01
Figure 13. Thermal Response
di/dt
IS
trr
ta
tb
TIME
0.25 IS
tp
IS
Figure 14. Diode Reverse Recovery Waveform
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RJC(t) = r(t) RJC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) − TC = P(pk) RJC(t)
1.0E+00
1.0E+01
MTP2955V
PACKAGE DIMENSIONS
TO−220
CASE 221A−09
ISSUE AB
−T−
B
F
SEATING
PLANE
C
T
S
4
A
Q
1 2 3
DIM
A
B
C
D
F
G
H
J
K
L
N
Q
R
S
T
U
V
Z
U
H
K
Z
L
R
V
J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION Z DEFINES A ZONE WHERE ALL
BODY AND LEAD IRREGULARITIES ARE
ALLOWED.
G
D
N
INCHES
MIN
MAX
0.570
0.620
0.380
0.405
0.160
0.190
0.025
0.035
0.142
0.147
0.095
0.105
0.110
0.155
0.018
0.025
0.500
0.562
0.045
0.060
0.190
0.210
0.100
0.120
0.080
0.110
0.020
0.055
0.235
0.255
0.000
0.050
0.045
−−−
−−−
0.080
STYLE 5:
PIN 1.
2.
3.
4.
MILLIMETERS
MIN
MAX
14.48
15.75
9.66
10.28
4.07
4.82
0.64
0.88
3.61
3.73
2.42
2.66
2.80
3.93
0.46
0.64
12.70
14.27
1.15
1.52
4.83
5.33
2.54
3.04
2.04
2.79
0.508
1.39
5.97
6.47
0.00
1.27
1.15
−−−
−−−
2.04
GATE
DRAIN
SOURCE
DRAIN
E−FET is a trademark of Semiconductor Components Industries, LLC (SCILLC).
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are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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