ON LC703200AW-8C99-H Speech processing ic Datasheet

Ordering number : EN*A2234
LC703200AW
Advance Information
http://onsemi.com
CMOS LSI
Speech Processing IC
Overview
LC703200AW is a Speech Processing LSI which equips original DSP, ADC/DAC, PCM Interface, I2C
Interface and Flash memory. The LSI realizes speech processing functions such as Noise Canceller, Voice
Speed Control, S-LIVE (Original Low Boost), Center Enhancement and Stereo Enhancement. And the LSI
Realize small standalone system by supporting Timer and many I/O functions.
Features
1) DSP Block
32bit DSP : Max Frequency = 68MHz, Power Save Mode Support
2) I2C Interface : Master/Slave : 1ch
3) 24bit ADC/DAC : 2ch, Fs = 8kHz / 11.025kHz / 12kHz / 16kHz / 22.05kHz / 24kHz / 32kHz / 44.1kHz
/ 48kHz
4) PCM Interface : Master mode 2ch, I2S, Left/Right Justified, Long frame Sync., Short Frame Sync.
Fs = 8kHz / 11.025kHz / 12kHz / 16kHz / 22.05kHz / 24kHz / 32kHz / 44.1kHz / 48kHz
Note : Slave mode only support PCM Interface, it doesn’t support ADC/DAC.
5) TIMER/PWM (MTM) : 6ch(resolution 16bit)
TIMER (PTM) : 1ch(resolution 16bit)
6) WDT : 1ch (Max period 32.7S at 8.192MHz oscillation)
7) SIO : 2ch (8bit/16bit mode)
8) External interrupt request input : 8ch
9) GPIO : 21port (Including CPU I/F, SIO, PCM I/F, PWM/TIMER, INT2B - INT7B)
10) MIC AMP : 2ch, Gain : 30dB / 27dB / 24dB / 21dB / 18dB / 15dB / 12dB / 0dB
Including MIC bias circuit
11) Oscillation frequency : 8.192MHz / 11.2896MHz / 12.288MHz
12) Supply Voltage : from 3.0V to 3.6V (IO, OSC, PLL), 1.5V±10% (Internal Logic)
Package
SQFP64(10mm  10mm)
SPQFP64 10x10 / SQFP64
Figure 1
This document contains information on a new product. Specifications and information
herein are subject to change without notice.
ORDERING INFORMATION
See detailed ordering and shipping information on page 20 of this data sheet.
Semiconductor Components Industries, LLC, 2013
December, 2013
D0413HK No.A2234-1/20
LC703200AW
Block Diagram
MICBIAS
AVDD
MIC Bias
AVSS
VREF
MIC0IN
MIC0COM
MIC1IN
MIC1COM
VREF
AMP
ADC
DAC
DAOUT0
AMP
ADC
DAC
DAOUT1
TEST
MODE
(TEST)
controller
MODE0
MODE1
SCL
I2C
SDA/SIO0_BUSY
PCM0 IF
GPIO0/LRCK0/SIO1_BUSY
RESETB
PDNB
SYSRDY
GPIO1/BCK0/SIO1_SCK
PCM1 IF
System
standby
controller
GPIO2/SI0/SIO1_SI
GPIO3/SO0/SIO1_SO
GPIO
GPIO4/ACLK
WDT
DVDD15
SIO1
DVSS
Flash IF
MTM0
SELECTOR
DVDD33
GPIO5/SI1/TMAIO5/PWM5
SIO0
PTM
XIN
XOUT
OSC
MTM2
PLL
MTM3
PDO
XVDD
XVSS
GPIO7/TMAIO0/PWM0
GPIO8/TMBIO0/INTB2
GPIO9/TMAIO1/PWM1
GPIO10/TMBIO1/INTB3
GPIO11/TMAIO2/PWM2
GPIO12/TMBIO2/INTB4
MTM1
Flash
memory
(2Mbit)
GPIO6/SO1/TMBIO5
GPIO13/TMAIO3/PWM3
GPIO14/TMBIO3/INTB5
GPIO15/TMAIO4/PWM4
GPIO16/TMBIO4/INTB6
GPIO17/TCLKA
Clock
controller
PLLAVDD
SYSTEM clock
GPIO18/SIO0_SCK
MTM4
Data
memory A
(8192Wx32bit)
GPIO19/SIO0_SI
GPIO20/SIO0_SO
MTM5
Data
memory B
(8192Wx32bit)
INT
INT0
INTB1
Boot ROM
(1024Wx40bit)
Memory IF
Program
memory
(12288Wx40bit)
JTAG_TMS
DSP
(32bit Core)
JTAG
controller
JTAG_TCK
JTAG_TDI
JTAG_TDO
Figure 2
No.A2234-2/20
LC703200AW
Pin Assignment
GPIO2/SI0/SIO1_SI
GPIO1/BCK0/SIO1_SCK
GPIO0/LRCK0/SIO1_BUSY
GPIO20/SIO0_SO
GPIO19/SIO0_SI
GPIO18/SIO0_SCK
SYSRDY
PDNB
RESETB
57
56
55
54
53
52
51
50
49
60
58
DVDD15
61
59
DVSS
62
GPIO4/ACLK
DVDD33
63
GPIO3/SO0/SIO1_SO
PLLAVDD
48
INTB1
XIN
2
47
INT0
XOUT
3
46
DVDD33
XVDD
4
45
DVSS
JTAG_TMS
5
44
DVDD15
JTAG_TDO
6
43
SDA/SIO0_BUSY
MODE1
7
42
SCL
MODE0
8
41
JTAG_TCK
DVDD15
9
40
JTAG_TDI
39
AVSS
LC703200AW
(SQFP64)
10
64
1
DVSS
PDO
XVSS
DVDD33
11
38
AVDD
GPIO17/TCLKA
12
37
DAOUT1
GPIO7/TMAIO0/PWM0
13
36
DAOUT0
GPIO8/TMBIO0/INTB2
14
35
VREF
GPIO9/TMAIO1/PWM1
15
34
AVDD
GPIO10/TMBIO1/INTB3
16
33
AVSS
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
GPIO11/TMAIO2/PWM2
GPIO12/TMBIO2/INTB4
GPIO13/TMAIO3/PWM3
GPIO14/TMBIO3/INTB5
GPIO15/TMAIO4/PWM4
GPIO16/TMBIO4/INTB6
GPIO5/SI1/TMAIO5/PWM5
GPIO6/SO1/TMBIO5
TEST
AVSS
AVDD
MIC0IN
MIC0COM
MIC1COM
MIC1IN
MICBIAS
Figure 3 Pin layout
No.A2234-3/20
LC703200AW
Table.1A Pin Assignment
Pin
Pin Name
No.
1
XVSS
2
XIN
3
XOUT
4
XVDD
5
JTAG_TMS
6
JTAG_TDO
7
MODE1
8
MODE0
9
DVDD15
10 DVSS
11 DVDD33
12 GPIO17/TCLKA
13 GPIO7/TMAIO0/PWM0
14 GPIO8/TMBIO0/INTB2
15 GPIO9/TMAIO1/PWM1
16 GPIO10/TMBIO1/INTB3
17 GPIO11/TMAIO2/PWM2
18 GPIO12/TMBIO2/INTB4
19 GPIO13/TMAIO3/PWM3
20 GPIO14/TMBIO3/INTB5
21 GPIO15/TMAIO4/PWM4
22 GPIO16/TMBIO4/INTB6
23 GPIO5/SI1/TMAIO5/PWM5
24 GPIO6/SO1/TMBIO5
25 TEST
26 AVSS
27 AVDD
28 MIC0IN
29 MIC0COM
30 MIC1COM
31 MIC1IN
32 MICBIAS
33 AVSS
34 AVDD
35 VREF
36 DAOUT0
37 DAOUT1
38 AVDD
39 AVSS
40 JTAG_TDI
41 JTAG_TCK
42 SCL
43 SDA/SIO0_BUSY
44 DVDD15
45 DVSS
46 DVDD33
47 INT0
48 INTB1
49 RESETB
50 PDNB
51 SYSRDY
52 GPIO18/SIO0_SCK
53 GPIO19/SIO0_SI
54 GPIO20/SIO0_SO
55 GPIO0/LRCK0/SIO1_BUSY
56 GPIO1/BCK0/SIO1_SCK
57 GPIO2/SI0/SIO1_SI
58 GPIO3/SO0/SIO1_SO
59 GPIO4/ACLK
60 DVDD15
61 DVSS
62 DVDD33
63 PLLAVDD
64 PDO
*) = means hold previous status.
*) TEST pins should be set to L level.
IO
PS
DI
DO
PS
DI
DO
DI
DI
PS
PS
PS
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DI
PS
PS
AI
AI
AI
AI
AO
PS
PS
AO
AO
AO
PS
PS
DI
DI
DB
DB
PS
PS
PS
DI
DI
DI
DI
DO
DB
DB
DB
DB
DB
DB
DB
DB
PS
PS
PS
PS
AO
Reset
Period
-
Standby
Period
-
Power
Supply
GND
-
-
3.3V
DI
DI
DI
DI
DI
DI
DI
DI
DI
DI
DI
DI
DI
L
-
=
=
=
=
=
=
=
=
=
=
=
=
=
L
-
1.5V
GND
3.3V
GND
3.3V
-
-
GND
3.3V
-
-
3.3V
GND
DI
DI
-
=
=
-
1.5V
GND
3.3V
L
L
DI
DI
DI
DI
DI
DI
DI
DI
-
H
L
L
=
=
=
=
=
=
=
=
-
1.5V
GND
3.3V
1.5V
Function
Oscillation circuit GND
Oscillation circuit input
Oscillation circuit output
Oscillation circuit 3.3V power supply
JTAG test mode select
JTAG test mode output
Mode setting pin 1
Mode setting pin 0
Digital 1.5V power supply
Digital GND
I/O 3.3V power supply
GPIO17, Timer clock input
GPIO7, Timer 0A I/O, PWM0 output
GPIO8, Timer 0B I/O, Interrupt 2
GPIO9, Timer 1A I/O, PWM1output
GPIO10, Timer 1B I/O, Interrupt 3
GPIO11, Timer 2A I/O, PWM2 output
GPIO12, Timer 2B I/O, Interrupt 4
GPIO13, Timer 3A I/O, PWM3 output
GPIO14, Timer 3B I/O, Interrupt 5
GPIO15, Timer 4A I/O, PWM4 output
GPIO16, Timer 4B I/O, Interrupt 6
GPIO5, PCMIF1 SI, Timer5A I/O, PWM4 output
GPIO6, PCMIF1 SO, Timer 5B I/O
TEST pin (normally tied to low)
Analog GND
Analog 3.3V power supply
MIC input 0 (Lch)
MIC common input 0 (Lch)
MIC common input 1 (Rch)
MIC input 1 (Rch)
MIC BIAS output
Analog GND
Analog 3.3V power supply
Analog reference voltage output
DAC output 0 (Lch)
DAC output 1 (Rch)
Analog 3.3V power supply
Analog GND
JTAG test data input
JTAG test clock
I2C SCL clock
I2C SDA data, SIO BUSY output
Digital 1.5V power supply
Digital GND
I/O pin 3.3V power supply
Interrupt 0
Interrupt 1
Reset input
Standby control input
System ready output
GPIO18, SIO0 clock
GPIO19/SIO0 serial input
GPIO20/SIO0 serial output
GPIO0, PCMIF LRCK, SIO1 Busy output
GPIO1, PCMIF bit clock, SIO1 clock
GPIO2, PCMIF0 serial input, SIO1 serial input
GPIO3, PCMIF0 serial output, SIO1 serial output
GPIO4, PCMIF master clock
Digital 1.5V power supply
Digital GND
I/O 3.3V power supply
PLL 1.5V power supply
PLL filter output
No.A2234-4/20
LC703200AW
Table.1B I/O Functions
I/O Symbol
DI
DO
DB
AI
AO
PS
Function
Digital Input
Digital Output
Digital Input/output
Analog Input
Analog Output
Power Supply, GND
No.A2234-5/20
LC703200AW
Electrical Characteristics
(1) Absolute Maximum Ratings
Table.2 Absolute Maximum Ratings
VSS = AVSS = XVSS = 0V
Parameter
Maximum Supply Voltage
Input Voltage
Output Voltage
Allowable power dissipation
Operating Ambient Temperature
Storage Ambient Temperature
Symbol
VDD33max
VDD15max
XVDD33max
AVDD33max
AVDD15max
VI
VIA
VO
VOA1
VOA2
Pdmax
Topr
Tstg
Conditions
DVDD33
DVDD15
XVDD
AVDD
PLLAVDD
3.3V Digital I/O
3.3V Analog input
3.3V Digital I/O
3.3V Analog output
1.5V Analog output
SQFP64 (10x10) Ta = 30°C to +70°C
Ratings
0.3 to +3.96
0.3 to +1.8
0.3 to +3.96
0.3 to +3.96
0.3 to +1.8
0.3 to DVDD33+0.3
0.3 to AVDD33+0.3
0.3 to DVDD33+0.3
0.3 to AVDD+0.3
0.3 to PLLAVDD+0.3
260
30 to +70
55 to +125
Unit
V
mW
°C
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating
Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
(2) Allowable Operating Range
Table.3 Allowable Operating Range
Ta = 30°C to +70°C, VSS = AVSS = XVSS = 0V
Parameter
Symbol
Pins
Supply Voltage
VDD33
DVDD33
VDD15
DVDD15
XVDD33
XVDD
AVDD33
AVDD
AVDD15
PLLAVDD
Input Voltage
VI33
TEST,MODE0-1,
RESETB,PDNB,INT0,INTB1,
GPIO0-20,
SCL,SDA,
JTAG_TCK,JTAG_TSM,JTAG_TDI
VIA33
MIC0IN,MIC1IN,
MIC0COM,MIC1COM
VIX33
XIN
Oscillation
Fopr
XIN,XOUT
Frequency
Conditions
Min
3.0
1.35
3.0
3.0
1.35
0
Typ
3.3
1.5
3.3
3.3
1.5
-
Max
3.6
1.65
3.6
3.6
1.65
VDD33
0
-
AVDD33
0
8.192
11.2896
12.288
XVDD33
Unit
V
MHz
*) The following relations must be satisfied during power on and power off sequence.
AVDD33  XVDD33  VDD33  AVDD15  VDD15
No.A2234-6/20
LC703200AW
(3) DC Characteristics
Table.4 DC Characteristics(Digital Block)
Ta = 30°C to +70°C, VDD33 = XVDD33 = 3.0V to 3.6V, VDD15 = 1.35V to 1.65V, DVSS = XVSS = 0V
Parameter
Symbol
Pins
Conditions
Min
Input “H” level voltage
VIH
TEST, MODE0-1, RESETB,
0.7VDD33
PDNB, INT0, INTB1, GPIO0-20,
Input “L” level voltage
VIL
SCL, SDA, JTAG_TCK,
Input “H” level current
IIH
VI=VDD33
10
JTAG_TSM, JTAG_TDI
Input “L” level current
IIL
VI=VSS
10
Output“H” level voltage
VOH2
SYSRDY, JTAG_TDO
IOH=-2mA
VDD330.4
GPIO0-3, GPIO5-20
Output “L” level voltage
VOL2
IOL=2mA
Output “H” level voltage
VOH4
SCL, SDA, GPIO4
IOH=-4mA
VDD330.4
Output “L” level voltage
VOL4
IOL=4mA
Output leakage current
IOZ
GPIO0-20,SCL, SDA
VO=Hi_z
-10
Typ
-
Max
0.3VDD33
+10
+10
0.4
0.4
+10
Unit
V
μA
V
μA
Table.5 DC Characteristics (Analog Block)
Ta = 25°C, AVDD33 = 3.3V, AVSS = 0V
MIC amp circuit (Analog input)
Parameter
Symbol
Input resistance
MIC_Rin
Input voltage
MIC_Vin
MIC amp gain
MIC_gain
MIC bias circuit
Parameter
MIC bias output voltage
MIC bias output current
Symbol
MIC_Vbias
MIC_Ibias
Pins
MIC0IN,
MIC1IN,
MIC0COM,
MIC1COM
Pin Name
MICBIAS
Conditions
Gain = 0dB
Gain = 27dB
Gain = 0dB
Single end input
Gain = 0dB
Differential input
MIC_GAIN=111b
MIC_GAIN=110b
MIC_GAIN=101b
MIC_GAIN=100b
MIC_GAIN=011b
MIC_GAIN=010b
MIC_GAIN=001b
MIC_GAIN=000b
Min
Conditions
AVDD = 3.3V
@RL = 5KΩ
Min
Typ
52.8
5.34
Symbol
DAC_RES
DAC_SNR
DAC_DR
DAC_THD+N
DAC_ISO
DAC_VO
DAC_RL
DAC_CL
Pins
Analog Block Reference Voltage Generator Circuit
Parameter
Symbol
Pins
Reference voltage
VREF
VREF
Startup time (*)
ST
Condition
A-weighted
A-weighted
f=1KHz
Condition
C=10μF
0.85AVDD33
Unit
KΩ
KΩ
Vp-p
0.425AVDD33
Vp-p
30
27
24
21
18
15
12
0
Typ
2.31
ADC Block (MIC0IN / MIC1IN / MIC0COM / MIC1COM → MICAMP → ADC → SO0 / SO1(PCM-I/F))
Parameter
Symbol
Pins
Conditions
Min
Typ
Resolution
ADC_RES
24
S/N
ADC_SNR
MIC_GAIN=0dB
85
90
A-weighted
MIC_GAIN=27dB
75
80
A-weighted
Dynamic Range
ADC_DR
MIC_GAIN=0dB
85
90
A-weighted
MIC_GAIN=27dB
75
80
A-weighted
THD+N
ADC_THD+N
MIC_GAIN=0dB
86
MIC_GAIN=27dB
76
Inter channel Isolation
ADC_ISO
MIC_GAIN=0dB
100
MIC_GAIN=27dB
90
DAC Block
Parameter
Resolution
S/N
Dynamic Range
THD+N
Inter channel isolation
Output Voltage
Output load resistance
Output load capacity
Max
dB
dB
dB
dB
dB
dB
dB
dB
Max
20
Unit
V
mA
Max
-
Unit
bit
dB
-
dB
-
dB
-
dB
75
72
90
80
dB
dB
dB
dB
Min
85
85
10
-
Typ
24
90
90
86
90
-
Max
75
85
0.85AVDD33
30
Unit
bit
dB
dB
dB
dB
Vp-p
KΩ
pF
Min
-
Typ
1.65
80
Max
-
Unit
V
ms
(*) The definition of Startup time is the time VREF output reach 98% of reference voltage (= 0.98AVDD33/2)
from power down release.
No.A2234-7/20
LC703200AW
(4) Current Consumption
Table.6
Current consumption
Ta= 30°C to +70°C,VDD33 = XDD33 = AVDD33 = 3.0V to 3.6V, VDD15 = 1.35V to 1.65V, VSS = XVSS = AVSS = 0V
Parameter
Symbol
Conditions
Min
Typ
Max
Standby current (*)
IDDS
Sum of VDD33, XVDD33,
10
VDD15, AVDD33, PLLAVDD
(**)
Current consumption
IDD15D
Digital 1.5V for Logic
24
IDD15A
Analog 1.5V for PLL
1
IDD33D
Digital 3.3V for IO, XVDD
1
IDD33A
Analog 3.3V
14
IDD
Total
40
Unit
μA
mA
mA
mA
mA
mA
(*) Both oscillation and PLL halt
(**) The value is example that the LSI executes noise cancel processing at 50MHz system clock.
No.A2234-8/20
LC703200AW
AC characteristics
(1) PCM Interface
I2S Format
Parameter
LRCK period
LRCK setup time
LRCK hold time
BCK period
st
BCK period(1 half)
nd
BCK period(2 half)
SI setup time
SI hold time
SO delay
Symbol
Tlrckcy
Tlrs
Tlrh
Tbckcy
Tbckf
Tbckb
Tsis
tsih
Tsodl
Min
3Tsys+2
Tsys+2
3Tsys
3Tsys
15
2Tsys+5
2Tsys+29
Typ
1/Fs
1/32Fs or 1/64Fs
-
Max
-
Unit
nS
nS
nS
nS
nS
nS
nS
nS
nS
*) Tsys is system clock frequency.
*) Fs is sampling frequency.
Tlrckcy
Tlbh
Tlbh
LRCK
Tlbs
Tlbs
BCK
SI
SO
Tbckcy
Tbckb
Tbckf
BCK
Tsis
Tsih
VALID
SI
Tsodl
SO
VALID
No.A2234-9/20
LC703200AW
PCM format
Parameter
LRCK period
LRCK setup time
LRCK hold time
BCK period
st
BCK period(1 half)
nd
BCK period(2 half)
SI setup time
SI hold time
SO delay
Symbol
Tlrckcy
Tlrs
Tlrh
Tbckcy
Tbckf
Tbckb
Tsis
tsih
Tsodl
Min
3Tsys+2
Tsys+2
3Tsys
3Tsys
15
2Tsys+5
2Tsys+29
Typ
1/Fs
1/(32Fs) or 1/(64Fs)
-
Max
-
Unit
nS
nS
nS
nS
nS
nS
nS
nS
nS
*) Tsys is system clock frequency.
*) Fs is sampling frequency.
Tlrckcy
Tlrh
Tlrh
LRCK
Tlrs
Tlrs
BCK
SI
SO
Tbckcy
Tbckb
Tbckf
BCK
Tsis
Tsih
VALID
SI
Tsodl
SO
VALID
No.A2234-10/20
LC703200AW
Long flame synchronous format
Parameter
LRCK period
LRCK setup time
LRCK hold time
BCK period
st
BCK period (1 half)
nd
BCK period (2 half)
SI setup time
SI hold time
SO delay
Symbol
Tlrckcy
Tlrs
Tlrh
Tbckcy
Tbckf
Tbckb
Tsis
tsih
Tsodl
Min
3Tsys+2
Tsys+2
3Tsys
3Tsys
15
2Tsys+5
2Tsys+29
Typ
1/Fs
1/(32Fs) or 1/(64Fs)
-
Max
-
Unit
nS
nS
nS
nS
nS
nS
nS
nS
nS
*) Tsys is system clock frequency.
*) Fs is sampling frequency.
Tlrckcy
Tlbs
LRCK
Tlbh
BCK
SI
SO
Tbckcy
Tbckb
Tbckf
BCK
Tsis
Tsih
VALID
SI
Tsodl
SO
VALID
No.A2234-11/20
LC703200AW
Short frame synchronous format
Parameter
LRCK period
LRCK setup time
LRCK hold time
BCK period
st
BCK period (1 half)
nd
BCK period (2 half)
SI setup time
SI hold time
SO delay
Symbol
Tlrckcy
Tlrs
Tlrh
Tbckcy
Tbckf
Tbckb
Tsis
tsih
Tsodl
Min
3Tsys+2
Tsys+2
3Tsys
3Tsys
15
2Tsys+5
2Tsys+29
Typ
1/Fs
1/(32Fs) or 1/(64Fs)
-
Max
-
Unit
nS
nS
nS
nS
nS
nS
nS
nS
nS
*) Tsys is system clock frequency.
*) Fs is sampling frequency.
Tlrckcy
Tlbs
LRCK
Tlbh
BCK
SI
SO
Tbckcy
Tbckb
Tbckf
BCK
Tsis
Tsih
VALID
SI
Tsodl
SO
VALID
No.A2234-12/20
LC703200AW
(2) I2C Interface
Parameter
Symbol
SCL frequency
Hold time (repeated) START condition
Low period of SCL clock
High period of SCL clock
Setup time for a repeated Start condition
Data hold time
Data setup time
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
Setup time for STOP condition
Bus free time between a STOP and START condition
fSCL
tHD;STA
tLOW
tHIGH
tSU;STA
tHD;DAT
tSU;DAT
Tr
Tf
tSU;STO
tBUF
Standard mode
Min
Max
0
100
4.0
4.7
4.0
4.7
0
3.45
250
1000
300
4.0
4.7
-
Fast mode
Min
Max
0
400
0.6
1.3
0.6
0.6
0
0.9
100
300
300
0.6
1.3
-
Unit
kHz
μS
μS
μS
μS
μS
nS
nS
nS
μS
μS
SDA
Tf
tLOW
tSU:DAT
Tr
Tf
tHD:STA
Tr
tBUF
SCL
tSU:STA
tHD:STA
tHD:DAT
tSU:STO
tHIGH
No.A2234-13/20
LC703200AW
(3) SIO Interface
Parameter
SCLK period
st
SCLK period (1 half)
nd
SCLK period (2 half)
SI setup time
SI hold time
SO delay
BUSY-SCLK hold time
BUSY output delay
Symbol
Tsckcy
Tsckf
Tsckb
Tsins
Tsinh
Tsoutdl
Tbsyh
Tbsydl
Min
8Tsys
3Tsys
3Tsys
0
2Tsys+5
0
-
Typ
-
Max
2Tsys+27
2Tsys+27
Unit
nS
nS
nS
nS
nS
nS
nS
nS
*) Tsys is system clock period.
SCLK
SI
SO
Tbsydl
Tbsyh
BUSY
Tsckcy
Tsckf
Tsckb
SCLK
Tsins
Tsinh
VALID
SI
Tsoutdl
SO
VALID
No.A2234-14/20
LC703200AW
(4) Timer (MTM)
Parameter
Timer resolution
Timer period
Symbol
Ttmres
Tleng
Min
3Tmtm
Ttmres
Typ
-
Max
65536Tmtm
65536Ttmres
Unit
nS
nS
*) Tmtm is MTM clock period and selectable between OSC clock and PLL clock.
(5) PWM (MTM)
Parameter
PWM resolution
PWM period
Symbol
Tpwres
Tpwcy
Min
3Tmtm
Tpwres
Typ
-
Max
65536Tmtm
65536Tpwres
Unit
nS
nS
*) Tmtm is MTM clock period and selectable between OSC clock and PLL clock.
Tpwcy
Tpwres
PWM
(6) Timer (PTM)
Parameter
Timer resolution
Timer period
Symbol
Tptres
Tptcy
Min
Tosc
Tptres
Typ
-
Max
8Tosc
65536Tptres
Unit
nS
nS
Max
268435456Tosc
Unit
nS
*) Tosc is OSC clock period.
(7) WDT
Parameter
WDT period
Symbol
Twdcy
Min
131072Tosc
Typ
-
*) Tosc is OSC clock period.
(8) System clock/Reset
Table.7
System clock
VDD = XVDD = 3.0V to 3.6V, VSS = XVSS = 0V, Ta = -30°C to +70°C
Parameter
Symbols
Condition
Min
Oscillation frequency
fop
-
Typ
8.192
11.2896
12.288
Max
-
Unit
MHz
*) Recommended Oscillator
Murata Manufacturing Co., Ltd.
CERALOCK© : CSTCE8M19G55-R0 (8.192MHz)
CSTCE11M2896G55-R0 (11.2896MHz)
CSTCE12M288G55-R0 (12.288MHz)
Table.8 System clock and sampling frequency
Relationship between system clock and sampling frequency
System clock (MHz)
Sampling frequency (KHz)
8.192
32
16
11.2896
44.1
22.05
12.288
48
24
comment
8
11.025
12
No.A2234-15/20
LC703200AW
Table.9 Reset
VDD = XVDD = 3.0V to 3.6V, VSS = XVSS = 0V, Ta = 30°C to 70°C
Parameter
Symbol
Min
Typ
Hold time of Reset
tres
500
Rising time of Reset
trsrise
1
Max
-
Unit
μs
mS
0.9VDD
0.1VDD
tres
trsrise
No.A2234-16/20
LC703200AW
Power Supply
LC703200AW has a power supply of two kinds of voltage of 3.3V and 1.5V, and it is necessary to maintain the
following power requirement to power on / off.
Power requirement
•The power supply to belong to same voltage system start supply at the same time.
3.3V power supply: AVDD33, XVDD33, VDD33
1.5V power supply: AVDD15, VDD15
•The voltage of the power supply of the 3.3V preventing you from being less than the voltage of the power
supply of the 1.5V under any circumstance.
Specialy, when the power supply on / off, be careful the period of the voltage rise / fall.
•Reducing time difference as much as possible when I make time difference between voltage system and
perform power supply on / off.
Listing not to intend may affect the external circuit without the state (input /"L" listing /"H" listing) of a
terminal (GPIO, SCL, SDA) having an input and output function being settled because 1.5V system is a
state of non-supply after a setup in 3.3V system, and a system reset signal does not arrive at it inside.
No.A2234-17/20
LC703200AW
Startup sequence
LC703200AW starts a program stored away by built-in flash memory after download in program memory.
Each terminal pin state sequence at the time of the start is a street of the chart belows.
3.3V power on
1.5V power on
Oscillation stabilizes
Program download starts
Boot ends
Oscillation
RESETB
PDNB
Uncertainty state
SYSRDY
GPIO
Input mode (Hi-Z)
SCL
Input mode (Hi-Z)
SDA
Input mode (Hi-Z)
Pull-up from outside
Program load period (Tload)
After this point, input or output
is defined by the program.
Shorten it as much as possible
during this period until a 1.5V
power supply is supplied
because an input and
output state becomes
unsettled.
*) It is as follows during the period required for a program road.
Tload =
2384 + word * 706
OSC * 1000
Tload : Program load period [mS]
word : Program size [word length]
OSC : Osccilation frequency [MHz]
(1word length = 40bit)
No.A2234-18/20
LC703200AW
Package Dimensions
unit : mm
SPQFP64 10x10 / SQFP64
CASE 131AK
ISSUE A
0.5±0.2
12.0±0.2
64
10.0±0.1
12.0±0.2
10.0±0.1
1 2
+0.08
0.5
0.18 −0.03
1.7 MAX
(1.5)
(1.25)
0.15±0.05
0.10
0.1±0.1
0~10°
0.10
GENERIC MARKING DIAGRAM*
SOLDERING FOOTPRINT*
11.40
XXXXXXXX
YDD
XXXXXXXX
YMDDD
11.40
(Unit: mm)
XXXXX = Specific Device Code
Y = Year
DD = Additional Traceability Data
XXXXX = Specific Device Code
Y = Year
M = Month
DDD = Additional Traceability Data
0.50
0.28
1.00
*This information is generic. Please refer to
device data sheet for actual part marking.
NOTE: The measurements are not to guarantee but for reference only.
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
No.A2234-19/20
LC703200AW
ORDERING INFORMATION
Device
LC703200AW-8C99-H
Package
SPQFP64 10x10 / SQFP64
(Pb-Free / Halogen Free)
Shipping (Qty / Packing)
500 / Tray Foam
ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number
of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at
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performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical
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PS No.A2234-20/20
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