OPA658 OPA 658 OPA 658 SBOS045A – MARCH 1994 – REVISED JUNE 2003 Wideband, Low-Power, Current-Feedback Operational Amplifier FEATURES DESCRIPTION ● UNITY-GAIN STABLE BANDWIDTH: 900MHz ● LOW POWER: 50mW ● LOW DIFFERENTIAL GAIN/PHASE ERRORS: 0.025%/0.02° ● HIGH SLEW RATE: 1700V/µs ● GAIN FLATNESS: 0.1dB to 135MHz ● HIGH OUTPUT CURRENT (80mA) The OPA658 is an ultra-wideband, low power current feedback video operational amplifier featuring high slew rate and low differential gain/phase error. The current feedback design allows for superior large signal bandwidth, even at high gains. The low differential gain/phase errors, wide bandwidth and low quiescent current make the OPA658 a perfect choice for numerous video, imaging and communications applications. The OPA658 is optimized for low gain operation and is also available in dual (OPA2658) configurations. APPLICATIONS ● ● ● ● ● ● ● ● MEDICAL IMAGING HIGH-RESOLUTION VIDEO HIGH-SPEED SIGNAL PROCESSING COMMUNICATIONS PULSE AMPLIFIERS ADC/DAC GAIN AMPLIFIER MONITOR PREAMPLIFIER CCD IMAGING AMPLIFIER +VS Current Mirror IBIAS In+ In– Buffer VOUT CCOMP IBIAS Current Mirror –VS Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. Copyright © 1994-2003, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. www.ti.com ELECTROSTATIC DISCHARGE SENSITIVITY ABSOLUTE MAXIMUM RATINGS(1) Supply ............................................................................................... ±5.5V Internal Power Dissipation ........................... See Thermal Characteristics Differential Input Voltage .................................................................. ±1.2V Input Voltage Range ............................................................................ ±VS Storage Temperature Range: P, U, UB, N .................... –40°C to +125°C Lead Temperature (soldering, 10s) ............................................... +300°C (soldering, SO 3s) .......................................... +260°C Junction Temperature (TJ) ............................................................ +150°C This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. PACKAGE/ORDERING INFORMATION PRODUCT OPA658 PACKAGE-LEAD PACKAGE DESIGNATOR(1) SPECIFIED TEMPERATURE RANGE PACKAGE MARKING ORDERING NUMBER TRANSPORT MEDIA, QUANTITY SO-8 Surface-Mount D –40°C to +85°C OPA658U " " " " OPA658U OPA658U/2K5 Rails, 100 Tape and Reel, 2500 SO-8 Surface-Mount D –40°C to +85°C OPA658UB OPA658UB Rails, 100 " " " " SOT23-5 DBV –40°C to +85°C A58 " " " " DIP-8 P –40°C to +85°C OPA658P OPA658UB/2K5 OPA658N/250 OPA658N/3K OPA658P Tape and Reel, 2500 Tape and Reel, 250 Tape and Reel, 3000 Rails, 50 " OPA658 " OPA658 " OPA658 NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com. PIN CONFIGURATION Top View DIP, SO NC 1 8 NC –Input 2 7 +VS +Input 3 6 Output –VS 4 5 NC Top View SOT23 Output 1 –VS 2 +Input 3 5 +VS 4 –Input NC = No Connection 2 OPA658 www.ti.com SBOS045A ELECTRICAL CHARACTERISTICS At TA = +25°C, VS = ±5V, RL = 100Ω, and RFB = 402Ω, unless otherwise noted. OPA658P, U, N PARAMETER FREQUENCY RESPONSE Closed-Loop Bandwidth(1) Slew Rate(4) At Minimum Specified Temperature Settling Time: 0.01% 0.1% 1% Spurious-Free Dynamic Range 3rd-Order Intercept Point Differential Gain Differential Phase Bandwidth for 0.1dB Flatness OFFSET VOLTAGE Input Offset Voltage Over Temperature Range Power-Supply Rejection Ratio INPUT BIAS CURRENT Noninverting Over Temperature Range Inverting Over Temperature Range CONDITION MIN G = +1(2) G = +2 G = +5 G = +10 G = +2, 2V Step VCM = 0V 55 VCM = 0V VCM = 0V NOISE Input Voltage Noise Density f = 100Hz f = 2kHz f = 10kHz f = 1MHz fB = 100Hz to 200MHz Input Bias Current Noise Density Inverting: f = 1MHz Noninverting: f = 1MHz INPUT VOLTAGE RANGE Common-Mode Input Range Over Temperature Range Common-Mode Rejection INPUT IMPEDANCE Noninverting Inverting OPEN-LOOP TRANSRESISTANCE Open-Loop Transresistance Over Temperature Range OUTPUT Voltage Output Over Temperature Range Voltage Output Over Temperature Range Voltage Output Over Temperature Range Output Current, Sourcing Over Temperature Output Current, Sinking Over Temperature Short Circuit Current Output Resistance POWER SUPPLY Specified Operating Voltage Operating Voltage Range Quiescent Current Over Temperature Range ±2.5 45 VCM = ±1V MAX 900 680 370 200 1700 1500 15 11.5 6 68 56 40 0.025 0.02 135(5) G = +2, 2V Step G = +2, 2V Step G = +2, 2V Step f = 5MHz, G = +2, VO = 2VPP f = 20MHz, G= +2, VO = 2VPP f = 10MHz, 4dBm Each Tone G = +2, NTSC, VO = 1.4VPP, RL = 150Ω G = +2, NTSC, VO = 1.4VPP, RL = 150Ω G = +2 VS = ±4.7 to ±5.5V TYP OPA658UB MIN 400 1000 900 ±3 ±5 64 ±5.5 ±8 ±5.7 ±10 ±1.1 ±30 ±30 ±80 ±35 ±75 58 TYP MAX ✻(3) ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ UNITS MHz MHz MHz MHz V/µs V/µs ns ns ns dBc dBc dBm % degrees MHz ±2 ±4 67 ±4.5 ±7 mV mV dB ✻ ✻ ✻ ✻ ±18 ±35 ✻ ✻ µA µA µA µA 16 4.9 3.2 3.2 45.3 ✻ ✻ ✻ ✻ ✻ nV/√Hz nV/√Hz nV/√Hz nV/√Hz µVrms 32 11.9 ✻ ✻ pA/√Hz pA/√Hz ✻ ✻ V dB ✻ ✻ kΩ || pF Ω ±2.9 50 ✻ ✻ 500 || 1 50 VO = ±2V, RL = 100Ω VO = ±2V, RL = 100Ω 150 100 190 200 150 250 kΩ kΩ No Load ±2.7 ±2.5 ±2.7 ±2.5 ±2.2 ±2.0 80 70 60 35 ±2.9 ±2.75 ±2.9 ±2.7 ±2.8 ±2.5 120 ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ V V V V V V mA mA mA mA mA Ω RL = 250Ω RL = 100Ω ±4.5 TEMPERATURE RANGE Specification: P, U, N, UB Thermal Resistance, θJA P DIP-8 U SO-8 N SOT23-5 –40 100 125 150 ±5 ±5 ±5.5 ✻ ✻ ✻ 150 0.02 0.1MHz, G = +2 VS = ±5V 80 ✻ ±5.5 ±7.75 ±8.5 ✻ +85 ✻ ±4.5 ±4.7 ✻ ✻ ✻ ✻ ±5.75 ±6.5 V V mA mA ✻ °C °C/W °C/W °C/W (1) Frequency response can be strongly influenced by PC board parasitics. The demonstration boards show low parasitic layouts for this part. Refer to the demonstration board layout for details. (2) At G = +1, RFB = 560Ω for DIP and 402Ω for SO-8. (3) An asterisk (✻) specifies the same value as the grade to the left. (4) Slew rate is rate of change from 10% to 90% of output voltage step. (5) This specification is PC board layout dependent. OPA658 SBOS045A www.ti.com 3 TYPICAL CHARACTERISTICS At TA = +25°C, VS = ±5V, RL = 100Ω, and RFB = 402Ω, unless otherwise noted. POWER-SUPPLY REJECTION RATIO AND COMMON-MODE REJECTION vs TEMPERATURE COMMON-MODE REJECTION vs INPUT COMMON-MODE VOLTAGE 55 PSRR , CMR (dB) 70 Common-Mode Rejection (dB) 75 PSRR 65 60 PSR+ 55 PSR– 50 CMR 45 –75 50 45 40 35 30 25 –50 –25 0 25 50 75 100 –4 125 –3 –2 –1 0 1 2 3 4 100 125 Common-Mode Voltage (V) Temperature (°C) SUPPLY CURRENT vs TEMPERATURE OUTPUT CURRENT vs TEMPERATURE 5.5 120 5.0 Output Current (±mA) Supply Current (±mA) IO+ 4.5 4.0 110 100 90 80 I O– 3.5 70 –75 –50 –25 0 25 50 75 100 Noninverting Input Bias Current IB+ (µA) Output Swing (V) 0 25 50 75 NONINVERTING INPUT BIAS CURRENT vs TEMPERATURE RL = 250Ω 3.00 +VO –VO 2.90 2.80 2.70 –VO 2.60 +VO RL = 100Ω 2.50 2.40 2.30 –20 0 20 40 60 80 100 10 9 8 7 6 5 4 3 2 –75 Temperature (°C) 4 –25 OUTPUT SWING vs TEMPERATURE 3.10 –40 –50 Ambient Temperature (°C) 3.20 –60 –75 125 Ambient Temperature (°C) –50 –25 0 25 50 75 100 125 Ambient Temperature (°C) OPA658 www.ti.com SBOS045A TYPICAL CHARACTERISTICS (Cont.) At TA = +25°C, VS = ±5V, RL = 100Ω, and RFB = 402Ω, unless otherwise noted. OPEN-LOOP TRANSIMPEDANCE AND PHASE vs FREQUENCY INVERTING INPUT BIAS CURRENT vs TEMPERATURE 106 45 Transimpedance 105 1.6 1.4 1.2 1.0 0.8 0.6 0 104 –45 Phase 103 –90 102 –135 101 –180 0.4 –225 1 –75 –50 –25 0 25 50 75 100 1k 125 Temperature (°C) OPEN-LOOP GAIN AND PHASE vs FREQUENCY 45 1G SO-8 Bandwidth = 881MHz, RFB = 402Ω 0 20 –45 Phase 0 –90 Gain (dB) 3 Open-Loop Phase (°) Open-Loop Gain (dB) 100M G = +1 Gain 0 –3 –20 –135 –40 –180 –6 –225 –9 –60 100k 100k 1M 10M Frequency (Hz) 6 40 10k 10k CLOSED-LOOP BANDWIDTH 60 1k Open-Loop Phase (°) 1.8 Transimpedance (Ω) Inverting Input Bias Current IB– (µA) 2.0 1M 10M 100M DIP Bandwidth = 949MHz, RFB = 560Ω 1G 1M 10M Frequency (Hz) 100M 1G Frequency (Hz) CLOSED-LOOP BANDWIDTH CLOSED-LOOP BANDWIDTH 20 9 G = +5 G = +2 17 6 SO-8/DIP Bandwidth= 372MHz 14 Gain (dB) Gain (dB) DIP Bandwidth = 682MHz 3 0 11 8 SO-8 Bandwidth = 680MHz –3 5 2 –6 1M 10M 100M 1M 1G OPA658 SBOS045A 10M 100M 1G Frequency (Hz) Frequency (Hz) www.ti.com 5 TYPICAL CHARACTERISTICS (Cont.) At TA = +25°C, VS = ±5V, RL = 100Ω, and RFB = 402Ω, unless otherwise noted. SMALL-SIGNAL TRANSIENT RESPONSE CLOSED-LOOP BANDWIDTH 26 160 G = +2 G = +10 120 Output Voltage (mV) 23 SO-8/DIP Bandwidth = 200MHz Gain (dB) 20 17 14 11 80 40 0 –40 –80 –120 8 –160 1M 10M 100M 1G Time (5ns/div) Frequency (Hz) RECOMMENDED ISOLATION RESISTANCE vs CAPACITIVE LOAD 40 LARGE-SIGNAL TRANSIENT RESPONSE 1.6 G = +2 G = +2 1.2 Output Voltage (V) Isolation Resistance 35 30 25 RISO OPA658 20 CL 402Ω 15 0.8 0.4 0 –0.4 –0.8 1kΩ 402Ω –1.2 10 –1.6 10 20 30 40 50 60 70 80 90 100 Capacitive Load (pF) Time (5ns/div) 5MHz HARMONIC DISTORTION vs OUTPUT SWING –60 –55 –65 Harmonic Distortion (dBc) Harmonic Distortion (dBc) HARMONIC DISTORTION vs FREQUENCY –50 –60 –65 –70 –75 –80 2fO –85 –90 3fO 2fO –75 –80 –85 –90 –100 1M 10M 100M 0 1 2 3 4 Output Swing (VPP) Frequency (Hz) 6 3fO –70 –95 –95 –100 100k G = +2 OPA658 www.ti.com SBOS045A TYPICAL CHARACTERISTICS (Cont.) At TA = +25°C, VS = ±5V, RL = 100Ω, and RFB = 402Ω, unless otherwise noted. HARMONIC DISTORTION vs TEMPERATURE 10MHz HARMONIC DISTORTION vs OUTPUT SWING –60 Harmonic Distortion (dBc) Harmonic Distortion (dBc) –60 –70 2fO –80 3fO –90 VO = 2VPP G = +2 –65 3fO –70 2fO –75 –80 –85 –100 0.01 1 0.1 4V –75 10 –50 –25 0 50 75 100 Output Swing (VPP) HARMONIC DISTORTION vs GAIN INPUT VOLTAGE AND CURRENT NOISE vs FREQUENCY 125 100 –50 fO = 5MHz VO = 2VPP –55 Voltage Noise (nV/√Hz) Current Noise (pA/√Hz) Harmonic Distortion (dBc) 25 Temperature (°C) –60 –65 3fO –70 Inverting Current Noise Noninverting Noise 10 Voltage Noise 2fO 1 –75 0 1 2 3 4 5 6 7 8 9 102 10 104 105 106 107 Frequency (Hz) Noninverting Gain (V/V) OPA658 SBOS045A 103 www.ti.com 7 APPLICATIONS INFORMATION THEORY OF OPERATION Conventional op amps depend on feedback to drive their inputs to the same potential, however the current-feedback op amp’s inverting and noninverting inputs are connected by a unity-gain buffer, thus enabling the inverting input to automatically assume the same potential as the noninverting input. This results in very low impedance at the inverting input to sense the feedback as an error current signal. For noninverting operation, the input signal is applied to the noninverting (high impedance buffer) input. The output (buffer) error current (IE) is generated at the low impedance inverting input. The signal generated at the output is fed back to the inverting input such that the overall gain is (1 + RFB/RFF). Where a voltage-feedback amplifier has two symmetrical high impedance inputs, a current-feedback amplifier has a low inverting (buffer output) impedance and a high noninverting (buffer input) impedance. The closed-loop gain for the OPA658 can be calculated using Equations 1 and 2. DISCUSSION OF PERFORMANCE R − FB RFF Inverting Gain = 1 1+ Loop Gain The OPA658 is a low-power, unity-gain stable, currentfeedback operational amplifier which operates on ±5V power supply. The current-feedback architecture offers the following important advantages over voltage-feedback architectures: (1) the high slew rate allows the large-signal performance to approach the small-signal performance, and (2) there is very little bandwidth degradation at higher gain settings. RFB 1 + RFF Noninverting Gain = 1 1+ Loop Gain The current-feedback architecture of the OPA658 provides the traditional strength of excellent large-signal response plus wide bandwidth, making it a good choice for use in highresolution video, medical imaging and Digital-to-Analog Converter (DAC) I/V Conversion. The low-power requirements make it an excellent choice for numerous portable applications. DC GAIN TRANSFER CHARACTERISTICS The circuit in Figure 1 shows the equivalent circuit for calculating the DC gain. When operating the device in the inverting mode, the input signal error current (IE) is amplified by the open loop transimpedance gain (TO). The output signal generated is equal to TO x IE. Negative feedback is applied through RFB such that the device operates at a gain equal to –RFB/RFF. (1) TO where Loop Gain = R FB RFB + 1 + R FF RS (2) At higher gains, the small value inverting input impedance causes an apparent loss in bandwidth. This can be seen from Equation 3. f ACTUALBW ≈ [f ( A V = + 2)BW ] × (1.25) RS RFB 1 + × 1 + R R FB FF (3) This loss in bandwidth at high gains can be corrected without affecting stability by lowering the value of the feedback resistor from the specified value of 402Ω. OFFSET VOLTAGE AND NOISE The output offset is the algebraic sum of the input offset voltage and bias current errors. The output offset for the model of Figure 2 is calculated by Equation 4. IE RFF RS LS TO – VN Output Offset Voltage = CC + R R ±IbN × RN 1 + FB ± VIO 1 + FB ± IbN × RFB RFF RFF VO (50Ω) VI (4) C1 RFB RFF RFB IbN RN FIGURE 1. Equivalent Circuit. 8 IbI VIO FIGURE 2. Output Offset Voltage Equivalent Circuit. OPA658 www.ti.com SBOS045A If all terms are divided by the gain (1 + RFB/RFF) it can be observed that input referred offsets improve as gain increases. The effective noise at the output can be determined by taking the root sum of the squares of Equation 4 and applying the spectral noise values found in the Typical Characteristics section. This applies to noise from the op amp only. Note that both the noise figure (NF) and the equivalent input offset voltages improve as the closed-loop gain increases (by keeping RFB fixed and reducing RFF with RN = 0Ω). The feedback resistor value acts as the frequency response compensation element for a current-feedback type amplifier. The 402Ω used in setting the specification achieves a nominal maximally-flat butterworth response while assuming a 2pF output pin parasitic. Increasing the feedback resistor will overcompensate the amplifier, rolling off the frequency response, while decreasing it will decrease phase margin, peaking up the frequency response. Note that a noninverting, unity-gain buffer application still requires a feedback resistor for stability (560Ω for SO-8, 402Ω for DIP, and 324Ω for SOT23). INCREASING BANDWIDTH AT HIGH GAINS d) Connections to other wideband devices on the board may be made with short direct traces or through onboard transmission lines. For short connections, consider the trace and the input to the next device as a lumped capacitive load. Relatively wide traces (50 mils to 100 mils) should be used, preferably with ground and power planes opened up around them. Estimate the total capacitive load and set RISO from the plot of recommended RISO vs capacitive load. Low parasitic loads may not need an RISO since the OPA658 is nominally compensated to operate with a 2pF parasitic load. The closed-loop bandwidth can be extended at high gains by reducing the value of the feedback resistor RFB. This bandwidth reduction is caused by the feedback current being split between RS and RFF (refer to Figure 1). As the gain increases (for a fixed RFB), more feedback current is shunted through RFF, which reduces closed-loop bandwidth. CIRCUIT LAYOUT AND BASIC OPERATION Achieving optimum performance with a high-frequency amplifier such as the OPA658 requires careful attention to layout parasitics and selection of external components. Recommendations for PC board layout and component selection include: a) Minimize parasitic capacitance to any ac ground for all of the signal I/O pins. Parasitic capacitance on the output and inverting input pins can cause instability; on the noninverting input it can react with the source impedance to cause unintentional bandlimiting. To reduce unwanted capacitance, a window around the signal I/O pins should be opened in all of the ground and power planes. Otherwise, ground and power planes should be unbroken elsewhere on the board. b) Minimize the distance (< 0.25") from the two power pins to high-frequency 0.1µF decoupling capacitors. At the pins, the ground and power-plane layout should not be in close proximity to the signal I/O pins. Avoid narrow power and ground traces to minimize inductance between the pins and the decoupling capacitors. Larger (2.2µF to 6.8µF) decoupling capacitors, effective at lower frequencies, should also be used. These may be placed somewhat farther from the device and may be shared among several devices in the same area of the PC board. c) Careful selection and placement of external components will preserve the high-frequency performance of the OPA658. Resistors should be a very low reactance type. Surface-mount resistors work best and allow a tighter overall layout. Metal film or carbon composition axially-leaded resistors can also provide good high-frequency performance. Again, keep their leads as short as possible. Never use wirewound type resistors in a high-frequency application. Since the output pin and the inverting input pin are most sensitive to parasitic capacitance, always position the feedback and series output resistor, if any, as close as possible to the package pins. Other network components, such as noninverting input termination resistors, should also be placed close to the package. If a long trace is required and the 6dB signal loss intrinsic to doubly-terminated transmission lines is acceptable, implement a matched impedance transmission line using microstrip or stripline techniques (consult an ECL design handbook for microstrip and stripline layout techniques). A 50Ω environment is not necessary onboard, and in fact a higher impedance environment will improve distortion as shown in the distortion vs load plot. With a characteristic impedance defined based on board material and desired trace dimensions, a matching series resistor into the trace from the output of the amplifier is used as well as a terminating shunt resistor at the input of the destination device. Remember also that the terminating impedance will be the parallel combination of the shunt resistor and the input impedance of the destination device; the total effective impedance should match the trace impedance. Multiple destination devices are best handled as separate transmission lines, each with their own series and shunt terminations. If the 6dB attenuation loss of a doubly-terminated line is unacceptable, a long trace can be series-terminated at the source end only. This will help isolate the line capacitance from the op amp output, but will not preserve signal integrity as well as a doubly-terminated line. If the shunt impedance at the destination end is finite, there will be some signal attenuation due to the voltage divider formed by the series and shunt impedances. e) Socketing a high-speed part like the OPA658 is not recommended. The additional lead length and pin-to-pin capacitance introduced by the socket creates an extremely troublesome parasitic network which can make it almost impossible to achieve a smooth, stable response. Best results are obtained by soldering the part onto the board. If socketing for the DIP package is desired, high-frequency, flush-mount pins (for instance, McKenzie Technology #710C) can give good results. OPA658 SBOS045A www.ti.com 9 100 Output Impedance (Ω) The OPA658 is nominally specified for operation using ±5V power supplies. A 10% tolerance on the supplies, or an ECL –5.2V for the negative supply, is within the maximum specified total supply voltage of 11V. Higher supply voltages can break down internal junctions possibly leading to catastrophic failure. Single-supply operation is possible as long as common-mode voltage constraints are observed. The common-mode input and output voltage specifications can be interpreted as a required headroom to the supply voltage. Observing this input and output headroom requirement will allow non-standard or single-supply operation. Figure 3 shows one approach to single-supply operation. 10 1 0.1 G = +2 0.01 0.001 10k 100k 1M 10M 100M Frequency (Hz) +VS +VS VS 2 FIGURE 4. Closed-Loop Output Impedance vs Frequency. VOUT = VS + AV VAC 2 THERMAL CONSIDERATIONS The OPA658 will not require heatsinking under most operating conditions. Maximum desired junction temperature will set a maximum allowed internal power dissipation as described below. In no case should the maximum junction temperature be allowed to exceed 175°C. ROUT VAC OPA658 RL Operating junction temperature (TJ) is given by TA + PD × θJA. The total internal power dissipation (PD) is the sum of quiescent power (PDQ) and additional power dissipated in the output stage (PDL) to deliver load power. Quiescent power is simply the specified no-load supply current times the total supply voltage across the part. PDL will depend on the required output signal and load but would, for a grounded resistive load, be at a maximum when the output is fixed at a voltage equal to 1/2 either supply voltage (for equal bipolar supplies). Under this condition PDL = VS2/(4 × RL) where RL includes feedback network loading. 402Ω 402Ω AV = +2 FIGURE 3. Single-Supply Operation. ESD PROTECTION ESD static damage has been well recognized for MOSFET devices, but any semiconductor device deserves protection from this potentially damaging source. This is particularly true for very high-speed, fine geometry processes. ESD static damage can cause subtle changes in amplifier input characteristics without necessarily destroying the device. In precision operational amplifiers, this may cause a noticeable degradation of offset voltage and drift. Therefore, static protection is strongly recommended when handling the OPA658. OUTPUT DRIVE CAPABILITY The OPA658 has been optimized to drive 75Ω and 100Ω resistive loads. The device can drive 2VPP into a 75Ω load. This high-output drive capability makes the OPA658 an ideal choice for a wide range of RF, IF, and video applications. In many cases, additional buffer amplifiers are unneeded. Many demanding high-speed applications such as Analog-toDigital Converter (ADC)/DAC buffers require op amps with low wideband output impedance. For example, low output impedance is essential when driving the signal-dependent capacitances at the inputs of flash ADCs. As shown in Figure 4, the OPA658 maintains very low closed-loop output impedance over frequency. Closed-loop output impedance increases with frequency since loop gain is decreasing with frequency. 10 Note that it is the power in the output stage and not into the load that determines internal power dissipation. As an example, compute the maximum TJ for an OPA658N at AV = +2, RL = 100Ω, RFB = 402Ω, ±VS = ±5V, and the specified maximum TA = +85°C. PD = 10V × 8.5mA + 52/[4 × (100Ω || 804Ω)] = 155mW Maximum TJ = 85°C + 0.155W × 150°C/W = 108°C DRIVING CAPACITIVE LOADS The OPA658’s output stage has been optimized to drive low resistive loads. Capacitive loads, however, will decrease the amplifier’s phase margin which may cause high-frequency peaking or oscillations. Capacitive loads greater than 5pF should be buffered by connecting a small resistance, usually 10Ω to 35Ω, in series with the output as illustrated in Figure 5. This is particularly important when driving high capacitance loads such as flash ADCs. In general, capacitive loads should be minimized for optimum high-frequency performance. Coaxial lines can be driven if the cable is properly terminated. The capacitance of coaxial cable (29pF/foot for RG-58) will not load the amplifier when the coaxial cable or transmission line is terminated with its characteristic impedance. OPA658 www.ti.com SBOS045A 402Ω 402Ω appear at fO ± 3 × Df. The 2-tone, 3rd-order spurious plot shown in Figure 7 indicates how far below these two equal power, closely-spaced tones the intermodulation spurious will be. The single-tone power is at a matched 50Ω load. The unique design of the OPA658 provides much greater spurious free range than what a 2-tone, 3rd-order intermodulation intercept specification would predict. This can be seen in Figure 7 as the spurious-free range actually increases at the higher output power levels. 10Ω to 35Ω RISO OPA658 RL 50Ω CL FIGURE 5. Driving Capacitive Loads. 2-TONE, 3RD-ORDER SPURIOUS LEVELS –65 3rd-Order Spurious Level (dBc) COMPENSATION The OPA658 is internally compensated and is stable in unity gain with a phase margin of approximately 62°, and approximately 64° in a gain of +2V/V when used with the recommended feedback resistor value. Frequency response for other gains are shown in the Typical Characteristics. The high-frequency response of the OPA658 in a good layout is very flat with frequency. DISTORTION 5MHz HARMONIC DISTORTION vs LOAD RESISTANCE (G = +2) Harmonic Distortion (dBc) G = +2 VO = 2VPP fO = 5MHz –60 –65 –70 3fO 2fO –75 –80 –85 10 10MHz –75 5MHz –80 –85 –90 The OPA658’s Harmonic Distortion characteristics into a 100Ω load are shown versus frequency and power output in the Typical Characteristics. Distortion can be further improved by increasing the load resistance as illustrated in Figure 6. Remember to include the contribution of the feedback resistance when calculating the effective load resistance seen by the amplifier. –55 20MHz –70 100 1k Load Resistance (Ω) –18 –16 –14 –12 –10 –8 –6 –4 –2 0 2 4 Single-Tone Power (dBm) FIGURE 7. 3rd-Order Spurious Level vs Frequency. DIFFERENTIAL GAIN AND PHASE Differential Gain (dG) and Differential Phase (dP) are among the more important specifications for video applications. dG is defined as the percent change in closed-loop gain over a specified change in output voltage level. dP is defined as the change in degrees of the closed-loop phase over the same output voltage change. Both dG and dP are specified at the NTSC sub-carrier frequency of 3.58MHz and the PAL subcarrier of 4.43MHz. All NTSC measurements were performed using a Tektronix model VM700A Video Measurement Set. dG/dP of the OPA658 were measured with the amplifier in a gain of +2V/V with 75Ω input impedance and the output back-terminated in 75Ω. The input signal selected from the generator was a 0V to 1.4V modulated ramp with sync pulse. With these conditions the test circuit shown in Figure 8 delivered a 100IRE modulated ramp to the 75Ω input of the videoanalyzer. The signal averaging feature of the analyzer was used to establish a reference against which the perfor- FIGURE 6. 5MHz Harmonic Distortion vs Load Resistance. 75Ω 75Ω Narrowband communication channel requirements will benefit from the OPA658’s wide bandwidth and low intermodulation distortion on low quiescent power. If output signal power at two closely spaced frequencies is required, 3rd-order nonlinearities in any amplifier will cause spurious power at frequencies very near the two fundamental frequencies. If the two test frequencies, f1 and f2, are specified in terms of average and delta frequency, fO = (f1 + f2)/2 and Df = Ωf2 – f1Ω, the two, 3rd-order, close-in spurious tones will OPA658 75Ω 402Ω 75Ω 402Ω TEK TSG 130A TEK VM700A FIGURE 8. Configuration for Testing Differential Gain/Phase. OPA658 SBOS045A www.ti.com 11 mance of the amplifier was measured. Signal averaging was also used to measure the dg and dp of the test signal in order to eliminate the generator’s contribution to measured amplifier performance. Typical performance of the OPA658 is 0.025% differential gain and 0.02° differential phase to both NTSC and PAL standards. PACKAGE BOARD PART NUMBER LITERATURE REQUEST NUMBER OPA658U SO-8 DEM-OPA68xU SBOU009 OPA658N SOT23-5 DEM-OPA6xxN SBOU010 OPA658P DIP-8 DEM-OPA68xP SBOU008 PRODUCT TABLE I. Demo Board Part/Ordering Numbers. DESIGN-IN TOOLS To request any of these boards, check the Texas Instruments web site at www.ti.com. DEMONSTRATION BOARDS Several PC boards are available to assist in the initial evaluation of circuit performance using the OPA658 in its three package styles. All of these are available free as an unpopulated PC board delivered with descriptive documentation. The summary information for these boards is shown in Table I. 12 OPA658 www.ti.com SBOS045A PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) (3) OPA658N/250 OBSOLETE SOT-23 DBV 5 TBD Call TI Call TI OPA658N/3K OBSOLETE SOT-23 DBV 5 TBD Call TI Call TI OPA658NB/250 OBSOLETE SOT-23 DBV 5 TBD Call TI Call TI OPA658NB/3K OBSOLETE SOT-23 DBV 5 TBD Call TI Call TI OPA658P OBSOLETE PDIP P 8 TBD Call TI Call TI OPA658U OBSOLETE SOIC D 8 TBD Call TI Call TI OPA658U-1 OBSOLETE SOIC D 8 TBD Call TI Call TI OPA658U/2K5 OBSOLETE SOIC D 8 TBD Call TI Call TI OPA658UB OBSOLETE SOIC D 8 TBD Call TI Call TI OPA658UB/2K5 OBSOLETE SOIC D 8 TBD Call TI Call TI Top-Side Markings (4) 0 to 70 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. 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