L6747A High current MOSFET driver Features ■ Dual MOSFET driver for synchronous rectified converters ■ High driving current for fast external MOSFET switching ■ Integrated bootstrap diode ■ High frequency operation ■ Enable pin ■ Adaptive dead-time management ■ Flexible gate-drive: 5 V to 12 V compatible ■ High-impedance (HiZ) management for output stage shutdown ■ Preliminary overvoltage (OV) protection ■ VFDFPN8 3x3 mm package VFDFPN8 3x3 mm regulator solutions for modern high-current CPUs and for DC-DC conversion in general. Applications ■ High current VRM / VRD for desktop / server / workstation CPUs ■ High current and high efficiency DC-DC converters The L6747A embeds high-current drivers for both high-side and low-side MOSFETS. The device accepts a flexible power supply of 5 V to 12 V. This allows optimization of the high-side and lowside gate-drive voltage to maximize system efficiency. The embedded bootstrap diode eliminates the need for external diodes. Anti shoot-through management prevents the high-side and low-side MOSFETs from conducting simultaneously and, combined with adaptive dead-time control, minimizes the LS body diode conduction time. The L6747A features preliminary OV protection to protect the load from dangerous overvoltage due to MOSFET failures at startup. Description The L6747A is a flexible, high-frequency dualdriver specifically designed to drive N-channel MOSFETs connected in synchronous-rectified buck topology. The L6747A device is available in a VFDFPN8 3x3 mm package. Combined with ST PWM controllers, the driver allows the implementation of complete voltage Table 1. March 2010 Device summary Order code Package Packing L6747A VFDFPN8 Tube L6747ATR VFDFPN8 Tape and reel Doc ID 17126 Rev 1 1/15 www.st.com 15 Contents L6747A Contents 1 Typical application circuit and block diagram . . . . . . . . . . . . . . . . . . . . 3 2 Pin information and thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 4 2.1 Pin information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Device description and operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.1 High-impedance (HiZ) management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.2 Preliminary OV protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.3 BOOT capacitance design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.4 Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.5 Layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2/15 Doc ID 17126 Rev 1 L6747A Typical application circuit and block diagram Figure 1. L6747A typical application circuit VCC = 5V to 12V CDEC VIN = 5V to 12V VCC BOOT CBULK CHF PWM Input PWM EN Input EN GND L6747A HS UGATE Vout L PHASE COUT LS LGATE L6747A Reference Schematic Figure 2. L6747A block diagram VCC BOOT EN L6747A CONTROL LOGIC & PROTECTIONS PWM PWM 7k UGATE HS 10k ADAPTIVE ANTI CROSS CONDUCTION 70k PHASE VCC LGATE LS 10k 1 Typical application circuit and block diagram GND Doc ID 17126 Rev 1 3/15 Pin information and thermal data L6747A 2 Pin information and thermal data 2.1 Pin information Pin connection diagram (top view) BOOT PWM EN VCC Table 2. Pin # 1 2 2 3 4 8 7 6 5 UGATE PHASE GND LGATE Pin descriptions Name Function BOOT High-side driver supply. This pin supplies the high-side floating driver. Connect through a RBOOT CBOOT (2.2Ω - 220nF typ.) network to the PHASE pin. Internally connected to the cathode of the integrated bootstrap diode. See Section 4.3 for guidance in selecting the capacitor value. PWM Control input for the driver; 5V compatible, internally clamp to 3.3V. This pin controls the state of the driver and which external MOSFET must be turned ON according to EN status. It manages the high-impedance (HiZ) state which sets all the MOSFETs to OFF if externally set in the HiZ window (see Table 5). See Section 4.1 for details of HiZ. Enable input for the driver; 5V compatible, internally clamp to 3.3V. Pull high to enable the driver based on the PWM status. Pull low to enter HiZ state with all MOSFETs OFF, regardless of the PWM status. See Section 4.1 for details of HiZ. 3 EN 4 VCC 5 LGATE Low-side driver output. Connect directly to the low-side MOSFET gate. A small series resistor may be used to reduce dissipated power, especially in high frequency applications. 6 GND All internal references, logic and drivers are referenced to this pin. Connect to the PCB ground plane. 7 4/15 1 L6747A Figure 3. PHASE Device and LS driver power supply. Connect to any voltage between 5V and 12V. Bypass with low-ESR MLCC capacitor to GND (1µF typ). High-side driver return path. Connect to the high-side MOSFET source. This pin is also monitored for adaptive dead-time management and pre-OV protection. Internal clamp circuitry prevents leakage from this pin in disable conditions. Doc ID 17126 Rev 1 L6747A Pin information and thermal data Table 2. 2.2 Pin descriptions (continued) Pin # Name Function 8 UGATE High-side driver output. Connect to high-side MOSFET gate. A small series resistor may be used to control the PHASE pin negative spike. - TH. PAD Thermal pad connects the silicon substrate and makes good thermal contact with the PCB. Connect to the PGND plane. Thermal data Table 3. Symbol Thermal data Parameter Value Unit RTHJA Thermal resistance junction-to-ambient (device soldered on 2s2p, 67mm x 69mm board) 45 °C/W RTHJC Thermal resistance junction-to-case 5 °C/W TMAX Maximum junction temperature 150 °C TSTG Storage temperature range 0 to 150 °C TJ Junction temperature range 0 to 125 °C 2.25 W PTOT Maximum power dissipation at 25°C (device soldered on 2s2p,67mm x 69mm board) Doc ID 17126 Rev 1 5/15 Electrical specifications L6747A 3 Electrical specifications 3.1 Absolute maximum ratings Table 4. Absolute maximum ratings Symbol Value Unit VCC to GND -0.3 to 18 V VBOOT to GND to GND, t < 200 ns to PHASE -0.3 to 41 -0.3 to 44 -0.3 to 15 V PHASE -0.3 to BOOT +0.3 PHASE -1 to BOOT +0.3 V -8 to 26 -8 to 30 V -0.3 to VCC + 0.3 -1.5 to VCC + 0.3 V -0.3 to 7 V VUGATE 3.2 Parameter t < 200 ns VPHASE to GND to GND; t < 200 ns, VCC = 12V VLGATE to GND to GND, t < 200 ns VPWM, VEN to GND Electrical characteristics VCC = 12 V±15%, TJ = 0 °C to 70 °C unless otherwise specified. Table 5. Symbol Electrical characteristics Parameter Test conditions Min. Typ. Max. Unit UGATE = LGATE = OPEN; BOOT = 12V; EN = 1; PWM = 1 1.5 2.0 mA UGATE = LGATE = OPEN; BOOT = 12V; EN = 1; PWM = 0 2.7 3.5 mA UGATE = LGATE = OPEN; BOOT = 12V; EN = 0 1.0 1.5 mA UGATE = OPEN; PHASE = GND; BOOT = 12V; EN = 1; PWM = 1 2.3 3.3 mA UGATE = OPEN; PHASE = GND; BOOT = 12V; EN = 1; PWM = 0 2.0 3.0 mA UGATE = OPEN; PHASE = GND; BOOT = 12V; EN = 0 1.3 2.3 mA 4.1 V Supply current and power-on ICC IBOOT UVLOVCC 6/15 VCC supply current BOOT supply current VCC turn-ON VCC rising VCC turn-OFF VCC falling Doc ID 17126 Rev 1 3.5 V L6747A Table 5. Electrical specifications Electrical characteristics (continued) Symbol Parameter Test conditions Min. Typ. Max. Unit PWM and EN input PWM tHiZ tprop_L Input high - VPWM_IH PWM rising Input low - VPWM_IL PWM falling Input leakage PWM = GND HiZ hold-off time See Figure 4 Propagation delays See Figure 4 2 V -5 0.8 V 5 μA 120 tprop_H ns 25 35 ns 30 45 ns Input high - VEN_IH EN rising Input low - VEN_IH EN falling RHIHS HS source resistance BOOT - PHASE = 12V; 100mA 1.4 IUGATE HS source current (1) BOOT - PHASE = 12V; CUGATE to PHASE = 3.3nF 3.5 RLOHS HS sink resistance BOOT - PHASE = 12V; 100mA 1.0 1.5 Ω RHILS LS source resistance 100mA 1.4 2.0 Ω CLGATE to GND = 5.6nF 3.5 1.0 EN 2 V 0.8 V 2.0 Ω Gate drivers (1) ILGATE LS source current RLOLS LS sink resistance 100mA Pre-OV threshold PHASE rising A A 1.5 Ω Protections VPRE_OV 1.7 1.8 V 1. Parameter(s) guaranteed by design, not fully tested in production Doc ID 17126 Rev 1 7/15 Device description and operation 4 L6747A Device description and operation The L6747A provides high-current driving control for both high-side and low-side N-channel MOSFETs, connected as step-down DC-DC converters and driven by an external PWM signal. The integrated high-current drivers allow the use of different types of power MOSFETs (also multiple MOS to reduce the equivalent RDS(on)), maintaining fast switching transition. The driver for the high-side MOSFET uses the BOOT pin for supply and the PHASE pin for return. The driver for the low-side MOSFET uses the VCC pin for supply and the PGND pin for return. The driver includes anti-shoot-through and adaptive dead-time control to minimize low-side body diode conduction time, maintaining good efficiency and eliminating the need for Schottky diodes. When the high-side MOSFET turns off, the voltage on its source begins to fall; when the voltage falls below the proper threshold, the low-side MOSFET gate drive voltage is suddenly applied. When the low-side MOSFET turns off, the voltage at the LGATE pin is sensed. When it drops below the proper threshold, the high-side MOSFET gate drive voltage is suddenly applied. If the current flowing in the inductor is negative, the source of the high-side MOSFET never drops. To allow the low-side MOSFET to turn on even in this case, a watchdog controller is enabled. If the source of the high-side MOSFET does not drop, the low-side MOSFET is switched on, allowing the negative current of the inductor to recirculate. This mechanism allows the system to regulate even if the current is negative. Before VCC goes above the UVLO threshold, the L6747A keeps both the high-side and lowside MOSFETS firmly OFF. Then, after the UVLO has been crossed, the EN and PWM inputs take control over the driver’s operations. The EN pin enables the driver. If low, it keeps all MOSFETs OFF (HiZ) regardless of the status of PWM. When EN is high, the PWM input takes control. If externally set within the HiZ window, the driver enters an HiZ state and both MOSFETS are kept in an OFF state until PWM exits the HiZ window (see Figure 4). After the UVLO threshold has been crossed and while in HiZ, the preliminary OV protection is activated. If the voltage sensed through the PHASE pin goes above about 1.8 V, the lowside MOSFET is latched ON in order to protect the load from dangerous overvoltage. The driver status is reset from a PWM transition. Driver power supply, as well as power conversion input, are flexible: 5 V and 12 V can be chosen for high-side and low-side MOSFET voltage drive. Figure 4. Timing diagram (EN = high) VPWM_IH HiZ Window HiZ Window VPWM_IL PWM HiZ HiZ HS Gate 8/15 Doc ID 17126 Rev 1 thold-off tprop_ H thold-off tprop_ L tdead_HL tprop_H tdead_LH tprop_L LS Gate L6747A 4.1 Device description and operation High-impedance (HiZ) management The driver is capable of managing a high-impedance conditions by keeping all MOSFETs in an OFF state. This is achieved in two different ways: ● If the EN signal is pulled low, the device keeps all MOSFETs OFF regardless of the PWM status. ● When EN is asserted, if the PWM signal is externally set within the HiZ window for a time greater than the hold-off time, the device detects the HiZ condition and turns off all the MOSFETs. The HiZ window is defined as the PWM voltage range between VPWM_HIZ_H = 1.6 V and VPWM_HIZ_L = 1.3 V. The device exits from the HiZ state after any PWM transition. See Figure 4 for details about HiZ timing. The implementation of the high-impedance state allows the controller connected to the driver to manage the high-impedance state of its output, preventing the generation of negative undershoot on the regulated voltage during the shutdown stage. Also, different power management states may be managed, such as pre-bias startup. 4.2 Preliminary OV protection When VCC exceeds its UVLO threshold while the device is in HiZ, theL6747A activates the preliminary OV protection. The intent of this protection feature is to protect the load during system startup, especially from high-side MOSFET failures. In fact, VRM, and more generally PWM, controllers, have a 12 V bus-compatible turn-on threshold and are non-operative if VCC is below the turn-on thresholds (which is in the range of about 10 V). In cases of high-side MOSFET failure, the controller does not recognize the overvoltage until VCC = ~10 V (unless other special features are implemented). However, in this case the output voltage is already at the same voltage (~10 V) and the load (a CPU in most cases) is already burnt. The L6747A bypasses the PWM controller by latching on the low-side MOSFET if the PHASE pin voltage exceeds 1.8 V during the HiZ state. When the PWM input exits from the HiZ window, the protection is reset and the control of the output voltage is transferred to the controller connected to the PWM input. Since the driver has its own UVLO threshold, a simple way to provide protection to the output in all conditions when the device is OFF is to supply the controller through the 5 VSB bus. 5 VSB is always present before any other voltage and, in case of high-side short, the lowside MOSFET is driven with 5 V. This ensures reliable protection of the load. Preliminary OV is active after UVLO and while the driver is in an HiZ state, and it is disabled after the first PWM transition. The controller must manage its output voltage from that moment on. 4.3 BOOT capacitance design The L6747A embeds a bootstrap diode to supply the high-side driver, removing the necessity for an external component. Simply connecting an external capacitor between BOOT and PHASE completes the high-side supply connections. Doc ID 17126 Rev 1 9/15 Device description and operation L6747A The bootstrap capacitor value should be selected to obtain a negligible discharge due to the turning on of the high-side MOSFET. It must provide a stable voltage supply to the high-side driver during the MOSFET turn-on, and minimize the power dissipated by the embedded boot diode. Figure 5 illustrates some guidelines on how to select the capacitance value for the bootstrap according to the desired discharge, and the selected MOSFET. To prevent the bootstrap capacitor from overcharging as a consequence of large negative spikes, an external series RBOOT resistor (in the range of few ohms) may be required in series with the BOOT pin. Figure 5. 4.4 Bootstrap capacitance design Power dissipation The L6747A embeds high current drivers for both high-side and low-side MOSFETs. It is therefore important to consider the power that the device is going to dissipate in driving them in order to avoid exceeding the maximum junction operating temperature. Two main factors contribute to device power dissipation: bias power and driver power. ● Device power (PDC) depends on the static consumption of the device through the supply pins and is easily quantifiable as follows: P DC = V CC ⋅ I CC + V PVCC ⋅ I PVCC ● Driver power is the power needed by the driver to continuously switch the external MOSFETs ON and OFF. It is a function of the switching frequency and total gate charge of the selected MOSFETs. It can be quantified considering that the total power PSW dissipated to switch the MOSFETs is influenced by three main factors: external gate resistance (when present), intrinsic MOSFET resistance, and intrinsic driver resistance. This last factor is the important one to be determined to calculate the device power dissipation. The total power dissipated to switch the MOSFETs is: P SW = F SW ⋅ ( Q GHS ⋅ PVCC + Q GLS ⋅ VCC ) When designing an application based on the L6747A, it is recommended to take into consideration the effect of external gate resistors on the power dissipated by the driver. External gate resistors help the device to dissipate the switching power since the same power PSW is shared between the internal driver impedance and the external resistor, resulting in a general cooling of the device. 10/15 Doc ID 17126 Rev 1 L6747A Device description and operation Referring to Figure 6, a classic MOSFET driver can be represented by a push-pull output stage with two different MOSFETs: a P-MOSFET to drive the external gate high, and an NMOSFET to drive the external gate low (with their own RDS(on): Rhi_HS, Rlo_HS, Rhi_LS, Rlo_LS). The external power MOSFET can be represented in this case as a capacitance (CG_HS, CG_LS) that stores the gate-charge (QG_HS, QG_LS) required by the external power MOSFET to reach the driving voltage (PVCC for HS and VCC for LS). This capacitor is charged and discharged at the driver switching frequency FSW. The total power PSW is dissipated among the resistive components distributed along the driving path. According to the external gate resistance and the power MOSFET intrinsic gate resistance, the driver dissipates only a portion of PSW as follows: R loHS R hiHS 1 2 - + ---------------------------------------------------------------⎞ P SW – HS = --- ⋅ C GHS ⋅ PVCC ⋅ Fsw ⋅ ⎛⎝ --------------------------------------------------------------2 R hiHS + R GateHS + R iHS R loHS + R GateHS + R iHS⎠ R loLS R hiLS 1 2 P SW – LS = --- ⋅ C GLS ⋅ VCC ⋅ Fsw ⋅ ⎛⎝ ------------------------------------------------------------- + -------------------------------------------------------------⎞ 2 R hiLS + R GateLS + R iLS R loLS + R GateLS + R iLS⎠ The total power dissipated from the driver can then be determined as follows: P = P DC + P SW – HS + P SW – LS Figure 6. Equivalent circuit for a MOSFET driver VCC RhiHS RGATELS RILS LGATE GND LS DRIVER 4.5 BOOT CGLS LS MOSFET RloHS RloLS RhiLS VCC RGATEHS RIHS HGATE PHASE HS DRIVER CGHS HS MOSFET Layout guidelines The L6747A provides driving capability to implement high-current step-down DC-DC converters. The first priority when placing components for these applications should be given to the power section, minimizing the length of each connection and loop as much as possible. To minimize noise and voltage spikes (as well as EMI and losses) power connections must be part of a power plane, and in any case constructed with wide and thick copper traces. The loop must be minimized. The critical components, such as the power MOSFETs, must be close to each other. However, some space between the power MOSFETs is required to assure good thermal cooling and airflow. Doc ID 17126 Rev 1 11/15 Device description and operation L6747A Traces between the driver and the MOSFETS should be short and wide to minimize the inductance of the trace, which in turn minimizes ringing in the driving signals. Moreover, the VIA count should be minimized to reduce the related parasitic effect. The use of a multi-layer printed circuit board is recommended. Small signal components and connections to critical nodes of the application, as well as bypass capacitors for the device supply, are also important. Place the bypass capacitor (VCC, PVCC and BOOT capacitors) close to the device with the shortest possible loop, using wide copper traces to minimize parasitic inductance. Systems that do not use Schottky diodes in parallel with the low-side MOSFET might show large negative spikes on the PHASE pin. This spike can be limited, as can the positive spike, but has an additional consequence: it causes the bootstrap capacitor to be overcharged. This extra charge can cause, in the worst case condition of maximum input voltage and during particular transients, that boot-to-phase voltage exceeds the absolute maximum ratings causing device failures. It is therefore suggested in this cases to limit this extra charge by adding a small RBOOT resistor in series with the boot capacitor. The use of RBOOT also contributes in the limitation of the spike present on the BOOT pin. For heat dissipation, place the copper area under the IC. This copper area may be connected by internal copper layers through several VIAs to improve thermal conductivity. The combination of copper pad, copper plane and VIAs under the driver allows the device to achieve its best thermal performance. Figure 7. Driver turn-on and turn-off paths VCC VCC BOOT CGD RBOOT RGATE RINT RGATE LGATE CBOOT LS DRIVER Figure 8. GND RINT HGATE CGS CDS CBOOT LS MOSFET HS DRIVER PHASE External component placement example BOOT PWM EN VCC 1 2 3 4 Cboot L6747A Rboot C 12/15 CGD RBOOT Doc ID 17126 Rev 1 8 7 6 5 UGATE PHASE GND LGATE CGS HS MOSFET CDS L6747A 5 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 9. VFDFPN8 mechanical data and package dimensions DIMENSIONS REF. A mm TYP. MAX. 0.80 35.43 39.37 0.787 1.968 25.59 31.49 A1 A2 mils MIN. TYP. MAX. MIN. 0.55 A3 0.90 1.00 0.02 0.05 0.65 0.80 31.49 21.65 0.20 0.18 0.25 0.30 7.086 9.842 11.81 D 2.85 3.00 3.15 112.2 118.1 124.0 D2 2.20 2.70 86.61 E 2.85 3.15 112.2 E2 1.40 1.75 55.11 e L ddd 0.50 0.30 0.40 Very thin Fine pitch Dual Flat Package no Lead 7.874 b 3.00 PACKAGE AND PACKING INFORMATION Weight: not available 106.3 118.1 124.0 68.89 19.68 0.50 0.08 11.81 15.74 19.68 3.149 Doc ID 17126 Rev 1 VFDFPN8 (3x3) 13/15 Revision history 6 L6747A Revision history Table 6. 14/15 Document revision history Date Revision 24-Mar-2010 1 Changes Initial release. Doc ID 17126 Rev 1 L6747A Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein. UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY, DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK. Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST. ST and the ST logo are trademarks or registered trademarks of ST in various countries. Information in this document supersedes and replaces all information previously supplied. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. © 2010 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com Doc ID 17126 Rev 1 15/15