Product Folder Sample & Buy Support & Community Tools & Software Technical Documents LP8754 SNVS861A – FEBRUARY 2014 – REVISED AUGUST 2014 LP8754 Multi-Phase Six-Core Step-Down Converter 1 Features 3 Description • The LP8754 is designed to meet the power management requirements of the latest applications processors in mobile phones and similar portable applications. The device contains six step-down DC/DC converter cores, which are bundled together in a 6-phase buck converter. The device is fully controlled by a Dynamic Voltage Scaling (DVS) interface or an I2C-compatible serial interface. 1 • • • • • • • Six High-Efficiency Step-Down DC/DC Converter Cores: – Max Output Current 10 A – Cores Bundled to a 6-Phase Converter – Load Current Reporting – Programmable Overcurrent Protection (OCP) – Auto PWM/PFM and Forced-PWM Operations and Automatic Low Power-Mode Setting – Automatic Phase Adding/Shedding – Remote Differential Feedback Voltage Sensing – Output Voltage Ramp Control – VOUT Range = 0.6 V to 1.67 V I2C-Compatible Interface which Supports Standard (100 kHz), Fast (400 kHz), and High-Speed (3.4 MHz) Modes Four Selectable I2C Addresses Interrupt Function with Programmable Masking Output Short-Circuit and Input Overvoltage Protection (OVP) Spread Spectrum and Phase Control for EMI Reduction Overtemperature Protection (OTP) Undervoltage Lock-out (UVLO) 2 Applications • • • Smart Phones, eBooks and Tablets GSM, GPRS, EDGE, LTE, CDMA and WCDMA Handsets Gaming Devices The automatic PWM/PFM operation together with the automatic phase adding/shedding maximizes efficiency over a wide output current range. The LP8754 supports remote differential voltage sensing to compensate IR drop between the regulator output and the point-of-load thus improving the accuracy of the output voltage. The protection features include short-circuit protection, current limits, input OVP, UVLO, temperature warning, and shutdown functions. Several error flags are provided for status information of the IC. In addition, I2C read-back includes total load current and load current for each buck core: The LP8754 has the ability to sense current being delivered to the load without the addition of current sense resistors. During start-up, the device controls the output voltage slew rate to minimize overshoot and the inrush current. Device Information(1) PART NUMBER LP8754 PACKAGE DSBGA (49) BODY SIZE (MAX) 3.022 mm x 2.882 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. Efficiency vs. Load Current 100 Low-Power PFM Mode PFM Mode PWM Mode EFFICIENCY (%) 90 80 70 60 VIN = 3.7 V, VOUT = 1.1 V 50 1 10 100 1000 OUTPUT CURRENT (mA) 10000 C027 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LP8754 SNVS861A – FEBRUARY 2014 – REVISED AUGUST 2014 www.ti.com Table of Contents 1 2 3 4 5 6 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 7 7.2 7.3 7.4 7.5 7.6 1 1 1 2 3 5 8 Functional Block Diagram ....................................... Features Descriptions ............................................. Device Functional Modes........................................ Programming .......................................................... Register Maps ......................................................... 16 16 24 26 28 Application and Implementation ........................ 37 8.1 Application Information............................................ 37 8.2 Typical Application .................................................. 37 Absolute Maximum Ratings ..................................... 5 Handling Ratings ...................................................... 5 Recommended Operating Conditions (2) .................. 5 Thermal Information .................................................. 6 General Electrical Characteristics............................. 6 6-Phase Buck Electrical Characteristics ................... 7 6-Phase Buck System Characteristics...................... 8 Protection Features Characteristics........................ 10 I2C Serial Bus Timing Parameters .......................... 11 Typical Characteristics .......................................... 13 9 Power Supply Recommendations...................... 45 10 Layout................................................................... 45 10.1 Layout Guidelines ................................................. 45 10.2 Layout Example .................................................... 46 11 Device and Documentation Support ................. 47 11.1 11.2 11.3 11.4 Detailed Description ............................................ 15 Device Support...................................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 47 47 47 47 12 Mechanical, Packaging, and Orderable Information ........................................................... 47 7.1 Overview ................................................................. 15 4 Revision History 2 DATE REVISION NOTES August 2014 Rev. A Initial release to Web Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LP8754 LP8754 www.ti.com SNVS861A – FEBRUARY 2014 – REVISED AUGUST 2014 5 Pin Configuration and Functions DSBGA (YFQ) 49 Top View 7 GND B0 GND B0 VLDO GNDA VIO SYS GND B3 GND B3 6 SW B0 SW B0 NSLP FB B0+/B0 INT SW B3 SW B3 5 VIN B0/B1 VIN B0/B1 VIN B0/B1 FB B0-/B1 VIN B3/B4 VIN B3/B4 VIN B3/B4 4 SW B1 SW B1 ADDR FB B2 NRST SW B4 SW B4 3 GND B1/B2 GND B1/B2 GND B1/B2 FB B3+/B3 GND B4/B5 GND B4/B5 GND B4/B5 2 SW B2 SW B2 SCL SYS FB B3-/B4 SCL SR SW B5 SW B5 1 VIN B2 VIN B2 SDA SYS FB B5 SDA SR VDDA 5V VIN B5 A B C BUCK0 BUCK1 BUCK3 BUCK2 BUCK4 BUCK5 D E F G Pin Functions PIN TYPE DESCRIPTION NUMBER NAME A1, B1 VINB2 P Input for Buck 2. The separate power pins VINBXX are not connected together internally VINBXX pins must be connected together in the application and be locally bypassed. A2, B2 SWB2 A Buck 2 switch node A3, B3, C3 GNDB1/B2 G Power Ground for Buck 1 and Buck 2 A4, B4 SWB1 A Buck 1 switch node A5, B5, C5 VINB0/B1 P Input for Buck 0 and Buck 1. The separate power pins VINBXX are not connected together internally - VINBXX pins must be connected together in the application and be locally bypassed. A6, B6 SWB0 A Buck 0 switch node A7, B7 GNDB0 G Power Ground for Buck 0 C1 SDASYS D/I/O C2 SCLSYS D/I Serial interface clock input for system access. Connect a pull-up resistor. C4 ADDR D/I Serial bus address selection. Connect to GND (addr = 60h), VIOSYS (addr = 61h), SDASYS (addr = 62h) or SCLSYS (addr = 63h). C6 NSLP D/I Full Power to Low Power state transition control signal (By default active LOW for Low-Power PFM mode) C7 VLDO A Internal supply voltage capacitor pin. A ceramic low ESR 1-µF capacitor should be connected from this pin to GNDA. The LDO voltage is generated internally, do NOT supply or load this pin externally. D1 FBB5 A Not used for six-phase converter. Connect to GND. D2 FBB3−/B4 A Not used for six-phase converter. Connect to GND. D3 FBB3+/B3 A Not used for six-phase converter. Connect to GND. D4 FBB2 A Not used for six-phase converter. Connect to GND. Serial interface data input and output for system access. Connect a pull-up resistor. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LP8754 3 LP8754 SNVS861A – FEBRUARY 2014 – REVISED AUGUST 2014 www.ti.com Pin Functions (continued) PIN TYPE DESCRIPTION NUMBER NAME D5 FBB0−/B1 A Remote sensing (negative). Connect to the respective sense pin of the processor or to the negative power supply trace of the processor as close as possible to the processor. D6 FBB0+/B0 A Remote sensing (positive). Connect to the respective sense pin of the processor or to the positive power supply trace of the processor as close as possible to the processor. D7 GNDA G Ground E1 SDASR D/I/O Serial Interface data input and output for Dynamic Voltage Scaling (DVS). Connect a pull-up resistor / connect to GND if not used. E2 SCLSR D/I Serial Interface clock input for Dynamic Voltage Scaling (DVS). Connect a pull-up resistor / connect to GND if not used. E3, F3, G3 GNDB4/B5 G Power Ground for Buck 4 and Buck 5 E4 NRST A Voltage reference input for Dynamic Voltage Scaling (DVS) interface. Setting NRST input HIGH triggers start-up sequence. E5, F5, G5 VINB3/B4 P Input for Buck 3 and Buck 4.The separate power pins VINBXX are not connected together internally - VINBXX pins must be connected together in the application and be locally bypassed. E6 INT D/O E7 VIOSYS A This pin shall be tied to the system I/O-voltage. Bias supply voltage for the device. Enables the I/O interface: All registers are accessible via serial bus interface when this pin is pulled high. An internal power-on reset (POR) occurs when VIOSYS is toggled low/high. The I2C host should allow at least 500 µs before sending data to the LP8754 after the rising edge of the VIOSYS line. Open-drain interrupt output. Active LOW. Connect a pull-up resistor to I/O supply. F1 VDDA5V P Input for Analog blocks F2, G2 SWB5 A Buck 5 switch node F4, G4 SWB4 A Buck 4 switch node F6, G6 SWB3 A Buck 3 switch node F7, G7 GNDB3 G Power Ground for Buck 3 G1 VINB5 P Input for Buck 5. The separate power pins VINBXX are not connected together internally VINBXX pins must be connected together in the application and be locally bypassed. A: Analog Pin, D: Digital Pin, G: Ground Pin, P: Power Pin, I: Input Pin, O: Output Pin 4 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LP8754 LP8754 www.ti.com SNVS861A – FEBRUARY 2014 – REVISED AUGUST 2014 6 Specifications 6.1 Absolute Maximum Ratings (1) (2) over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT Voltage on Power Connections (VIOSYS, VDDA5V, VINBXX) −0.3 6 Voltage on Logic pins (Input or Output pins) (SCLSYS, SDASYS, NRST, NSLP, ADDR, INT, SCLSR, SDASR) −0.3 6 V Buck switch nodes (SWBXX) −0.3 (VVINBXX + 0.2 V) with 6 V max V VLDO, FBB0+/B0, FBB0−/B1, FBB2, FBB3+/B3, FBB3−/B4, FBB5 −0.3 2 All other analog pins −0.3 6 INPUT VOLTAGE V TEMPERATURE Junction Temperature (TJ-MAX) 150 Maximum Lead Temperature (Soldering, 10 s) (3) 260 (1) (2) (3) °C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to network ground pin. For detailed soldering specifications and information, please refer to Application Note 1112: DSBGA Wafer-Level Chip-Scale Package (AN-1112). 6.2 Handling Ratings Tstg V(ESD) (All pins) (1) (1) (2) (3) MIN MAX UNIT −65 150 °C Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (2) –1000 1000 Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (3) –250 250 Storage temperature range Electrostatic discharge V Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic discharges in to the device. JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions (1) over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT Voltage on power connections (VDDA5V, VINBXX) 2.5 5 V Voltage on VIOSYS 1.8 smaller of 3.3 V or VVINBXX V INPUT VOLTAGE SCLSYS, SDASYS, ADDR 0 VVIOSYS V SCLSR, SDASR, NSLP, INT 0 VNRST V NRST 0 1.8 V Junction temperature (TJ) −40 125 Ambient temperature (TA) −40 85 TEMPERATURE (1) °C All voltage values are with respect to network ground pin. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LP8754 5 LP8754 SNVS861A – FEBRUARY 2014 – REVISED AUGUST 2014 www.ti.com 6.4 Thermal Information LP8754 THERMAL METRIC (1) YFQ UNIT 49 PINS RθJA Junction-to-ambient thermal resistance 49.2 RθJCtop Junction-to-case (top) thermal resistance 0.2 RθJB Junction-to-board thermal resistance 6.6 ψJT Junction-to-top characterization parameter 2.9 ψJB Junction-to-board characterization parameter 6.5 RθJCbot Junction-to-case (bottom) thermal resistance n/a (1) °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. 6.5 General Electrical Characteristics (1) (2) Limits apply over the full ambient temperature range -40°C ≤ TA ≤ 85°C, VVDDA5V = VVINBXX = 3.7 V, VVIOSYS = VNRST = 1.8 V, VOUT = 1.1 V, (unless otherwise noted). SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX 0.1 2 UNIT CURRENTS ISHDN Shutdown supply current. Total current into power connections VDDA5V and VINBXX VVIOSYS = 0 V, VNRST = 0 V ISTBY Standby mode supply current. Total current into power connections VDDA5V and VINBXX VVIOSYS = 1.8 V, VNRST = 0 V IActive Active mode current consumption. Total current into power connections VDDA5V and VINBXX µA 50 Low-power PFM Mode, no load, one core active 130 µA PFM Mode, no load, one core active 400 µA Forced PWM Mode, no load, one core active 14.5 mA LOGIC AND CONTROL INPUTS SCLSYS, SDASYS, ADDR VIL Input low level VVIOSYS = 1.8 V to 3.3 V VIH Input high level VVIOSYS = 1.8 V to 3.3 V Vhys Hysteresis of Schmitt trigger inputs (SCLSYS, SDASYS) Ci Capacitance of pins (1) (2) (3) 6 0.3 x VVIOSYS 0.7 x VVIOSYS V 0.1 x VVIOSYS See (3) 4 pF All voltage values are with respect to network ground pin. Minimum (Min) and Maximum (Max) limits are specified by design, test, or statistical analysis. Typical (Typ.) numbers are not ensured, but do represent the most likely norm. Maximum capacitance of SCLSYS or SDASYS line is 8 pF, if ADDR pin is connected to line for serial bus address selection. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LP8754 LP8754 www.ti.com SNVS861A – FEBRUARY 2014 – REVISED AUGUST 2014 General Electrical Characteristics(1)(2) (continued) Limits apply over the full ambient temperature range -40°C ≤ TA ≤ 85°C, VVDDA5V = VVINBXX = 3.7 V, VVIOSYS = VNRST = 1.8 V, VOUT = 1.1 V, (unless otherwise noted). SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNIT LOGIC AND CONTROL INPUTS SCLSR, SDASR, NSLP, NRST VIL Input low level VNRST = 1.8 V VIH Input high level VNRST = 1.8 V Vhys Hysteresis of Schmitt trigger inputs (SCLSR, SDASR) Ci Capacitance of SCLSR and SDASR pins RIN Input resistance VIL_NRST Input low level NRST VIH_NRST Input high level NRST 0.3 x VNRST 0.7 x VNRST V 0.1 x VNRST 4 NRST pulldown resistor to GND 1200 pF kΩ 0.54 1.3 V LOGIC AND CONTROL OUTPUTS Voltage on INT pin, ISINK = 3 mA, VNRST = VVIOSYS = 1.8 V VOL Output low level V Voltage on SDASYS, SDASR, ISINK = 3 mA, VNRST = VVIOSYS = 1.8 V External pull-up resistor for INT RP 0.4 0.36 To I/O Supply 10 kΩ ALL LOGIC AND CONTROL INPUTS ILEAK All Logic Inputs over pin voltage range. Note that NRST pin does have an 1.2-MΩ internal pulldown resistor and current through this resistor is not included into ILEAK rating. TA = 25°C Input current −1 1 µA 6.6 6-Phase Buck Electrical Characteristics Limits apply over the full ambient temperature range -40°C ≤ TA ≤ 85°C, VVDDA5V = VVINBXX = 3.7 V, VVIOSYS = VNRST = 1.8 V, VOUT = 1.1 V, (unless otherwise noted). SYMBOL VFB PARAMETER TEST CONDITIONS Differential feedback voltage PWM Mode, VOUTSET = 0.6 V to 1.67 V, (1) IOUT ≤ 10 A (2) VFB0+/B0 - VFB0-/B1 PFM Mode, VOUTSET = 0.6 V to 1.67 V, IOUT ≤ 375 mA Low-Power PFM Mode, VOUTSET = 0.6 V to 1.67 V, IOUT ≤ 30 mA (1) (2) MIN min (VOUTSET 2.5%, VOUTSET - 25 mV) min (VOUTSET 2.5%, VOUTSET - 25 mV) min (VOUTSET 3%, VOUTSET 30 mV) TYP MAX VOUTSET max (VOUTSET + 2.5%, VOUTSET + 25 mV) VOUTSET max (VOUTSET + 2.5%, VOUTSET + 25 mV) VOUTSET max (VOUTSET + 3%, VOUTSET + 30 mV) UNIT V Due to the nature of the converter operating in PFM mode/Low-Power Mode, the Feedback Voltage accuracy specification is for the lower point of the ripple. Thus the converter will position the average output voltage typically slightly above the nominal PWM-mode output voltage. The power switches in the LP8754 are designed to operate continuously with currents up to the switch current limit thresholds. However, when continuously operating at high current levels there will be significant heat generated within the IC and thus sustained total DC current which the device can support is typically limited by thermal constraints. Thermal issues will become extremely important when designing PCB and the thermal environment of the LP8754. PCB with high thermal efficiency is required to ensure the junction temperature is kept below 125°C. Completing thermal analyses in early stages of the product design process is highly recommended to predict thermal performance at board level. Under high current load conditions the serial bus master device must monitor the temperature of the converter using the Thermal warning feature, see Protection Features Characteristics. If the 2nd thermal warning is triggered at 120°C, the application must quickly decrease the load current to keep the converter within its recommended operating temperature. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LP8754 7 LP8754 SNVS861A – FEBRUARY 2014 – REVISED AUGUST 2014 www.ti.com 6-Phase Buck Electrical Characteristics (continued) Limits apply over the full ambient temperature range -40°C ≤ TA ≤ 85°C, VVDDA5V = VVINBXX = 3.7 V, VVIOSYS = VNRST = 1.8 V, VOUT = 1.1 V, (unless otherwise noted). SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX 2050 2600 3300 Reverse current 650 900 1050 Range, Programmable by register setting 0.6 1.0 1.67 ILIMITP High side switch current limit 2.5 A register setting ILIMITN Low side switch current limit VOUT Output voltage Step fSW Switching frequency 10 2.5 V ≤ VVINBXX ≤ 5 V 2.7 120 3.4 RDSON_P Pin-pin resistance for PFET Test Current = 200 mA; Full FET 60 RDSON_N Pin-pin resistance for NFET IOUT = –200 mA 50 ILK_HS High-side leakage current VSW = 0 V, Per Buck Core 2 ILK_LS Low-side leakage current VSW = 3.7 V = VVINBXX, Per Buck Core 2 RPD Pull-down resistor Enabled via control register, Active only when converter disabled, Per Buck Core RIN_FB Differential feedback Input resistance (3) TA = 25°C (3) V MHz mΩ µA Ω 250 200 mA mV 3.0 Test Current = 200 mA; Split FET UNIT 300 400 kΩ Datasheet min/max specification limits are specified by design. 6.7 6-Phase Buck System Characteristics Limits apply over the full ambient temperature range -40°C ≤ TA ≤ 85°C, VVDDA5V = VVINBXX = 3.7 V, VVIOSYS = VNRST = 1.8 V, VOUT = 1.1 V, (unless otherwise noted). SYMBOL PARAMETER TEST CONDITIONS Programmable via control register MIN RAMP_B0[2:0] = 000 KRAMP Ramp timer TYP MAX UNIT (1) 30 RAMP_B0[2:0] = 001 15 RAMP_B0[2:0] = 010 7.5 RAMP_B0[2:0] = 011 3.8 RAMP_B0[2:0] = 100 1.9 RAMP_B0[2:0] = 101 0.94 RAMP_B0[2:0] = 110 0.47 RAMP_B0[2:0] = 111 0.23 mV/µs TSTART Start-up time Time from NRST-HIGH to start of switching 25 µs TRAMP VOUT rise time Time to ramp from 5% to 95% of VOUT 20 µs Average output current, programmable via control register, VOUT = 1.1 V (2) IPFM–PWM (1) (2) 8 PFM_EXIT_B0[2:0] = 011 PFM-to-PWM switch–over current PFM_EXIT_B0[2:0] = 100 threshold PFM_EXIT_B0[2:0] = 101 175 PFM_EXIT_B0[2:0] = 110 325 PFM_EXIT_B0[2:0] = 111 375 225 mA 275 In the real application, achievable output voltage ramp profiles are influenced by a number of factors, including the amount of output capacitance, the load current level, the load characteristic (either resistive or constant-current), and the voltage ramp amplitude. Typical values are measured with typical conditions. The final PFM-to-PWM and PWM-to-PFM switchover current varies slightly and is dependant on the output voltage, input voltage, and the inductor current level. Typical values are measured with typical conditions. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LP8754 LP8754 www.ti.com SNVS861A – FEBRUARY 2014 – REVISED AUGUST 2014 6-Phase Buck System Characteristics (continued) Limits apply over the full ambient temperature range -40°C ≤ TA ≤ 85°C, VVDDA5V = VVINBXX = 3.7 V, VVIOSYS = VNRST = 1.8 V, VOUT = 1.1 V, (unless otherwise noted). SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Average output current, Programmable via control register, VOUT = 1.1 V (2) IPWM–PFM IADD PWM-to-PFM switchover current threshold Phase adding level ISHED 125 PFM_ENTRY_B0[2:0] = 010 150 PFM_ENTRY_B0[2:0] = 011 175 PFM_ENTRY_B0[2:0] = 100 225 ADD_PH_B0[2:0] = 010 500 ADD_PH_B0[2:0] = 011 600 ADD_PH_B0[2:0] = 100 700 ADD_PH_B0[2:0] = 101 800 ADD_PH_B0[2:0] = 110 900 ADD_PH_B0[2:0] = 111 1000 mA mA 300 SHED_PH_B0[2:0] = 001 400 SHED_PH_B0[2:0] = 010 500 SHED_PH_B0[2:0] = 011 600 SHED_PH_B0[2:0] = 100 700 SHED_PH_B0[2:0] = 101 800 Line Regulation 2.5 V ≤ VVINBXX ≤ 5 V ILOAD = 1 A, forced PWM 0.05 %/V Load regulation in PWM mode of operation 100 mA ≤ ILOAD ≤ 10 A, Differential sensing enabled 0.2 %/A AUTO (no Low-Power PFM) mode, IOUT 0.5 mA → 500 mA → 0.5 mA, 100 ns load step ±30 mV PWM mode, IOUT 0.6 A → 2 A → 0.6 A, 400-ns load step ±20 mV PWM mode, IOUT 1 A → 8 A → 1 A, 400-ns load step ±60 mV VVINBXX stepping 3.3 V <—> 3.8 V, tr = tf = 10 µs, IOUT = 2000 mA DC ±15 mV Phase shedding level Transient load step response Transient line response IOUT Output current COUT Output capacitance (4) (4) 100 PFM_ENTRY_B0[2:0] = 001 SHED_PH_B0[2:0] = 000 ΔVOUT (3) PFM_ENTRY_B0[2:0] = 000 DC load each phase Six phases combined mA 1670 (3) Effective capacitance during operation, VOUT = 0.6 V to 1.67 V, Min value over TA –40°C to 85°C 10000 30 50 mA µF The power switches in the LP8754 are designed to operate continuously with currents up to the switch current limit thresholds. However, when continuously operating at high current levels there will be significant heat generated within the IC and thus sustained total DC current which the device can support is typically limited by thermal constraints. Thermal issues will become extremely important when designing PCB and the thermal environment of the LP8754. PCB with high thermal efficiency is required to ensure the junction temperature is kept below 125°C. Completing thermal analyses in early stages of the product design process is highly recommended to predict thermal performance at board level. Under high current load conditions the serial bus master device must monitor the temperature of the converter using the Thermal warning feature, see Protection Features Characteristics. If the 2nd thermal warning is triggered at 120°C, the application must quickly decrease the load current to keep the converter within its recommended operating temperature. Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics. The performance of the LP8754 device depends greatly on the care taken in designing the Printed Circuit Board (PCB). The use of low inductance and low serial resistance ceramic capacitors is strongly recommended, while proper grounding is crucial. Attention should be given to decoupling the power supplies. Decoupling capacitors must be connected close to the IC and between the power and ground pins to support high peak currents being drawn from System Power Rail during turn-on of the switching MOSFETs. Keep input and output traces as short as possible, because trace inductance, resistance and capacitance can easily become the performance limiting items. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LP8754 9 LP8754 SNVS861A – FEBRUARY 2014 – REVISED AUGUST 2014 www.ti.com 6-Phase Buck System Characteristics (continued) Limits apply over the full ambient temperature range -40°C ≤ TA ≤ 85°C, VVDDA5V = VVINBXX = 3.7 V, VVIOSYS = VNRST = 1.8 V, VOUT = 1.1 V, (unless otherwise noted). SYMBOL PARAMETER TEST CONDITIONS CIN Input capacitance on each input voltage rail (5) (4) Effective capacitance during operation, 2.5 V ≤ VVINBXX ≤ 5 V, Min value over TA –40°C to 85°C L Output inductance Effective inductance during operation IBALANCE Current balancing accuracy IOUT ≥ 1000 mA MIN TYP 2.5 10 0.25 COUT ESR = 10 mΩ PFM mode IOUT = 100 µA C ESR = 10 mΩ VRIPPLE_L Output Voltage Ripple Low-Power OUT Low-power PFM mode (6) PFM mode P IOUT = 100 µA (5) UNIT µF 0.47 1 µH < 10% COUT ESR = 10 mΩ VRIPPLE_P Output voltage ripple PWM mode, PWM mode, IOUT = 200 mA One phase active (6) WM Switching frequency = 3 MHz VRIPPLE_P Output voltage ripple PFM mode (6) FM MAX 7 mVPP 8 mVPP 8 mVPP In addition to these capacitors, at least one higher value capacitor (for example 22 µF) should be placed close to the power pins. Note that cores B0-B1 and B3-B4 do have combined power input pins. Ripple voltage should be measured at COUT electrode on a well-designed PCB, using suggested inductors and capacitors and with a high-quality scope probe. (6) 6.8 Protection Features Characteristics Limits apply over the full ambient temperature range -40°C ≤ TA ≤ 85°C, VVDDA5V = VVINBXX = 3.7 V, VVIOSYS = VNRST = 1.8 V, VOUT = 1.1 V, (unless otherwise noted). SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOLTAGE MONITORING VPG Power good threshold voltage Power good threshold for voltage decreasing, % of setting, VOUT = 1.1 V VOVP Input overvoltage protection trigger point (1) (2) VIN rising. Voltage monitored on VDDA5V pin 5.15 5.30 5.45 VUVLO Input undervoltage lockout (UVLO) turn-on threshold (1) VIN falling. Voltage monitored on VDDA5V pin 2.15 2.25 2.35 VSCP Output short-circuit fault threshold Detected by sensing the voltage on converter output with respect to GND. 400 mV tMASKSCP SCP masking time Triggered by converter start-up, specified by design 400 µs Triggered by converter start-up, specified by design 400 µs 90% V Triggered by VSET transition, specified by design Slew Rate setting mV/µs tMASKPG (1) (2) 10 Power Good masking time 30 50 15 100 7.5 200 3.8 400 1.9 800 0.94 1600 0.47 3200 0.23 6400 µs Undervoltage lock-out (UVLO) and overvoltage protection (OVP) circuits shut down the LP8754 when the system input voltage is outside the desired operating range. Limits for OVP trigger points apply when VVIOSYS is high. False OVP alarm may occur, if the input voltage rises close to 5 V while VVIOSYS is low. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LP8754 LP8754 www.ti.com SNVS861A – FEBRUARY 2014 – REVISED AUGUST 2014 Protection Features Characteristics (continued) Limits apply over the full ambient temperature range -40°C ≤ TA ≤ 85°C, VVDDA5V = VVINBXX = 3.7 V, VVIOSYS = VNRST = 1.8 V, VOUT = 1.1 V, (unless otherwise noted). SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNIT THERMAL SHUTDOWN AND MONITORING TSHUT TWARN Thermal shutdown (TSD) Threshold, Temperature rising Thermal warning 150 Hysteresis 25 Temperature rising, 1st warning, Interrupt only 85 Hysteresis 10 Temperature rising, 2nd warning, Interrupt and flag set Thermal warning prior to TSD °C 120 Hysteresis 10 6.9 I2C Serial Bus Timing Parameters Serial bus address is selected by the ADDR pin. Connect the pin to GND (addr = 60h), VIOSYS (addr = 61h), SDASYS (addr = 62h), or SCLSYS (addr = 63h). Both of the serial buses share the same address; that is, if addr = 60h is selected for the System bus, the Dynamic Voltage Scaling bus will respond to the same address. Start conditions are used to secure the I2C slave address. During the I2C bus start condition, it is detected whether the ADDR is connected to SDASYS, SCLSYS, GND, or VIOSYS. The I2C host should allow at least 500 µs before sending data to the LP8754 after the rising edge of the VIOSYS line. These specifications are ensured by design. Limits apply over the full ambient temperature range -40°C ≤ TA ≤ 85°C, VVDDA5V = VVINBXX = 3.7 V, VVIOSYS = VNRST = 1.8 V, VOUT = 1.1 V, (unless otherwise noted). SYMBOL PARAMETER (See Figure 1) TEST CONDITIONS MAX UNIT Standard mode 100 kHz Fast mode 400 kHz High-speed mode, Cb = 100 pF (max) 3.4 MHz High-speed mode, Cb = 400 pF (max) (4) 1.7 MHz DIGITAL TIMING SPECIFICATIONS (SCL, SDA) fCLK Serial clock frequency tLOW tHIGH tSU;DAT SCL low time SCL high time Data setup time Standard mode 4.7 Fast mode 1.3 High-speed mode, Cb = 100 pF (max) 160 High-speed mode, Cb = 400 pF (max) (4) 320 Standard mode 4.0 Fast mode 0.6 High-speed mode, Cb = 100 pF (max) (1) (2) (3) (4) Data hold time TYP µs ns µs 60 High-speed mode, Cb = 400 pF (max) (4) 120 Standard mode 250 Fast mode 100 High-speed mode tHD;DAT MIN (1) (2) (3) ns ns 10 Standard mode 0 3.45 Fast mode 0 0.9 High-speed mode, Cb = 100 pF (max) 0 70 High-speed mode, Cb = 400 pF (max) (4) 0 150 µs ns Unless otherwise stated, 'SDA' in this paragraph refers to both of the SDASR and SDASYS signals, and respectively 'SCL' refers to SCLSR and SCLSYS signals. Cb refers to the capacitance of one bus line. Cb is expressed in pF units. The specification table provided applies to both of the interfaces; DVS and System interface. The power-on default setting for the system bus and the DVS bus is High-speed-enabled, there is no handshaking required to initiate High speed. For bus line loads Cb between 100 pF and 400 pF the timing parameters must be linearly interpolated. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LP8754 11 LP8754 SNVS861A – FEBRUARY 2014 – REVISED AUGUST 2014 www.ti.com I2C Serial Bus Timing Parameters (continued) Serial bus address is selected by the ADDR pin. Connect the pin to GND (addr = 60h), VIOSYS (addr = 61h), SDASYS (addr = 62h), or SCLSYS (addr = 63h). Both of the serial buses share the same address; that is, if addr = 60h is selected for the System bus, the Dynamic Voltage Scaling bus will respond to the same address. Start conditions are used to secure the I2C slave address. During the I2C bus start condition, it is detected whether the ADDR is connected to SDASYS, SCLSYS, GND, or VIOSYS. The I2C host should allow at least 500 µs before sending data to the LP8754 after the rising edge of the VIOSYS line. These specifications are ensured by design. Limits apply over the full ambient temperature range -40°C ≤ TA ≤ 85°C, VVDDA5V = VVINBXX = 3.7 V, VVIOSYS = VNRST = 1.8 V, VOUT = 1.1 V, (unless otherwise noted). SYMBOL tSU;STA tHD;STA PARAMETER (See Figure 1) Set-up time for a repeated start condition Hold time for a start or a repeated start condition tBUF Bus free time between a stop and start condition tSU;STO Set-up time for a stop condition TEST CONDITIONS MIN Standard mode 4.7 Fast mode 0.6 High-speed mode 160 Standard mode 4.0 Fast mode 0.6 High-speed mode 160 Standard mode 4.7 Fast mode 1.3 Standard mode 4.0 Fast mode 0.6 High-speed mode 160 Standard mode trDA Rise time of SDA signal Fall time of SDA signal Rise time of SCL signal trCL1 Rise time of SCL signal after a repeated start condition and after anacknowledge bit Fall time of a SCL signal Cb Capacitive load for each bus line (SCL and SDA) tSP Pulse width of spike suppressed (6) (5) (6) 12 µs ns µs ns µs µs ns 1000 ns 300 ns High-speed mode, Cb = 100 pF (max) 10 80 ns High-speed mode, Cb = 400 pF (max) (4) 20 160 ns 300 ns Fast Mode 6.5 300 ns High-speed mode, Cb = 100 pF (max) 10 80 ns High-speed mode, Cb = 400 pF (max) (4) 20 160 ns 1000 ns Fast mode 20 300 ns High-speed mode, Cb = 100 pF (max) 10 40 ns High-speed mode, Cb = 400 pF (max) (5) 20 80 ns High-speed mode, Cb = 100 pF (max) 10 80 ns 20 160 ns High-speed mode, Cb = 400 pF (max) (5) Standard mode tfCL UNIT 20 Standard mode trCL MAX Fast mode Standard mode tfDA TYP 300 ns Fast mode 6.5 300 ns High-speed mode, Cb = 100 pF (max) 10 40 ns High-speed mode, Cb = 400 pF (max) (5) 20 80 ns 400 pF Fast mode 50 High-speed mode 10 ns For bus line loads Cb between 100 pF and 400 pF the timing parameters must be linearly interpolated. Spike suppression filtering on SCLSYS, SCLSR, SDASYS and SDASR will suppress spikes that are less than the indicated width. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LP8754 LP8754 www.ti.com SNVS861A – FEBRUARY 2014 – REVISED AUGUST 2014 tBUF SDA tfDA tHD;STA trCL tLOW trDA tfCL tSP SCL tHD;STA tSU;STA tHIGH tSU;STO tHD;DAT tSU;DAT START STOP REPEATED START START Figure 1. I2C Timing 6.10 Typical Characteristics 7 7 6 6 5 5 PHASES PHASES Unless otherwise specified: VVDDA5V = VVINBXX = 3.7 V, VOUT = 1.1 V, TA = 25°C 4 500 mA 3 600 mA 700 mA 2 4 300 mA 3 400 mA 500 mA 2 600 mA 800 mA 1 1 900 mA 1000 mA 0 800 mA 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 LOAD CURRENT (A) LOAD CURRENT (A) C017 Figure 2. Phase Adding vs Load Current with Different Level Settings C018 Figure 3. Phase Shedding vs Load Current with Different Level Settings 55.0 140 54.0 138 136 CURRENT (µA) 53.0 CURRENT (µA) 700 mA 52.0 51.0 50.0 49.0 134 132 130 128 126 124 48.0 122 47.0 120 2.5 3.0 3.5 4.0 INPUT VOLTAGE (V) VVIOSYS = 1.8 V 4.5 5.0 2.5 VNRST = 0 V Low-Power Mode Figure 4. Standby Mode Current Consumption vs VIN 3.0 3.5 4.0 4.5 INPUT VOLTAGE (V) C010 No load 5.0 C001 One core active Figure 5. Low-Power PFM Mode Current Consumption vs VIN Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LP8754 13 LP8754 SNVS861A – FEBRUARY 2014 – REVISED AUGUST 2014 www.ti.com Typical Characteristics (continued) 388.0 16.0 387.5 15.5 CURRENT (mA) CURRENT (µA) Unless otherwise specified: VVDDA5V = VVINBXX = 3.7 V, VOUT = 1.1 V, TA = 25°C 387.0 386.5 386.0 385.5 14.5 14.0 13.5 385.0 13.0 2.5 3.0 3.5 4.0 INPUT VOLTAGE (V) PFM Mode No load 4.5 5.0 2.5 One core active 3.0 3.5 4.0 INPUT VOLTAGE (V) C002 Figure 6. PFM Mode Current Consumption vs VIN 14 15.0 PWM Mode No load 4.5 5.0 C003 One core active Figure 7. PWM Mode Current Consumption vs VIN Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LP8754 LP8754 www.ti.com SNVS861A – FEBRUARY 2014 – REVISED AUGUST 2014 7 Detailed Description 7.1 Overview The LP8754 is a high-efficiency, high-performance power supply IC with six step-down DC-DC converter cores. It delivers 0.6 V to 1.67 V regulated voltage rail from either a single Li-Ion or three cell NiMH/NiCd batteries to portable devices such as cell phones and PDAs. There are three modes of operation for the 6-phase converter, depending on the output current required: PWM (Pulse Width Modulation), PFM (Pulse-Frequency Modulation), and Low-Power PFM. Converter operates in PWM mode at high load currents of approximately 250 mA or higher, depending on register setting. Lighter output current loads will cause the converter to automatically switch into PFM or Low-Power PFM mode for reduced current consumption and a longer battery life. Forced PWM is also available for highest transient performance. Under no-load conditions the device can be set to Standby or Shutdown. Shutdown mode turns off the device, offering the lowest current consumption (ISHDN = 0.1 µA typ.). Additional features include soft-start, undervoltage lockout, input overvoltage protection, current overload protection, thermal warning, and thermal shutdown. The modes and features can be programmed via control registers. All the registers can be accessed with both I2C serial interfaces: System serial interface and Dynamic voltage scaling (DVS) interface. Using DVS interface for dynamic voltage scaling prevents latencies if System serial interface is busy. Using DVS interface is optional; System serial interface can also be used for dynamic voltage scaling. 7.1.1 Buck Information The LP8754 has six integrated high-efficiency buck converter cores. The cores are designed for flexibility; most of the functions are programmable, thus allowing optimization of the SMPS operation for each application. The cores are bundled together to establish a multi-phase converter This is shown in Figure 24. Operating Modes: • OFF: Output is isolated from the input voltage rail in this mode. Output has an optional pull-down resistor which can be enabled with BUCK0_CTRL.RDIS_B0 bit. • PWM: Converter operates in buck configuration. Average switching frequency is constant. • PFM: Converter switches only when output voltage decreases below programmed threshold. Inductor current is discontinuous. • Low-Power PFM: This mode is similar to PFM mode, but used with lower load conditions. In this mode some of the internal blocks are turned off between the PFM pulses. Load transient response is compromised due to the wake-up time. Features: • DVS support • Automatic mode control based on the loading • Synchronous rectification • Current mode loop with PI compensator • Soft start • Power good flag with maskable interrupt • Overvoltage comparator • Phase control and spread spectrum techniques for reducing EMI • Average output current sensing (for PFM/PWM entry/exit, phase adding/shedding, and load current reporting) • Current balancing between the phases of the converter • Differential voltage sensing • Dynamic phase adding/shedding, each output being phase shifted Programmability (The following parameters can be programmed via registers): • Output voltage • Forced PWM operation • Switch current limits for high side FET • PWM/PFM mode entry and exit (based on average output current) Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LP8754 15 LP8754 SNVS861A – FEBRUARY 2014 – REVISED AUGUST 2014 www.ti.com Overview (continued) • • Phase adding and shedding levels Output voltage slew rate 7.2 Functional Block Diagram LP8754 INTERNAL LDO VLDO 1 F FBB0+ / B0 FBB0- / B1 SYSTEM POWER POWER INPUTS Configurable Feedback Amplifiers Logic Control VIOSYS FBB2 FBB3+ / B3 FBB3- / B4 FBB5 (chip EN) SCLSYS SDASYS ADDR SYS IO Domain EPROM Buck 0 / Master 0 Buck 1 Reference Voltage SCLSR SDASR INT NSLP Buck 2 SWB0 SWB1 SWB2 Oscillator SR IO Domain NRST Internal Pull-down 1.1 M Thermal Monitoring Voltage Monitoring Buck 3 / Master 1 Buck 4 Buck 5 SWB3 SWB4 SWB5 POWER GROUNDS AGND 7.3 Features Descriptions 7.3.1 Multi-Phase DC/DC Converters A multi-phase synchronous buck converter offers several advantages over a single power-stage converter. For application processor power delivery, lower ripple on the input and output currents and faster transient response to load steps are the most significant advantages. Also, since the load current is evenly shared among multiple channels, the heat generated is greatly reduced for each channel due to the fact that power loss is proportional to square of current. Physical size of the output inductor shrinks significantly for the similar reason. 16 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LP8754 LP8754 www.ti.com SNVS861A – FEBRUARY 2014 – REVISED AUGUST 2014 Features Descriptions (continued) + - SLAVE PHASE CONTROL RAMP GENERATOR VOUT - GATE CONTROL ERROR AMP + VOLTAGE SETTING VDAC SLEW RATE CONTROL PROGRAMMABLE PARAMETERS + - VIN POS CURRENT LIMIT + - FBP FBN PMOS CURRENT SENSE DIFFERENTIAL TO SINGLE-ENDED LOOP COMP POWER GOOD CONTROL BLOCK MASTER INTERFACE SW NEG CURRENT LIMIT NMOS CURRENT SENSE SLAVE INTERFACE ZERO CROSS DETECT IADC GND Figure 8. Detailed Block Diagram Showing One Buck Core 7.3.1.1 Multi-Phase Operation and Phase-Shedding Under heavy load conditions, the switching phase of the bucks are interleaved. As a result, the 6-phase converter has higher effective switching frequency than the switching frequency of any one phase. The parallel operation decreases the efficiency at low load conditions. In order to overcome this operational inefficiency, the LP8754 automatically changes the number of active phases to maximize the efficiency. This is called phase-shedding and the concept is illustrated in Figure 9. 6-PHASE OPERATION 5-PHASE OPERATION 4-PHASE OPERATION 3-PHASE OPERATION 2-PHASE OPERATION 1-PHASE OPERATION BEST EFFICIENCY OBTAINED WITH EFFICIENCY N=1 N=2 N=3 N=6 N=4 N=5 LOAD CURRENT Figure 9. Multi-phase Buck Converter Efficiency vs Number of Phases; All Converters in PWM Mode (1) (1) Graph is not to scale and is for illustrative purposes only. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LP8754 17 LP8754 SNVS861A – FEBRUARY 2014 – REVISED AUGUST 2014 www.ti.com Features Descriptions (continued) 7.3.1.2 Transitions Between Low-Power PFM, PFM, and PWM Modes Normal PWM-mode operation with phase-shedding can optimize efficiency at mid-to-full load, but this is usually at the expense of light-load efficiency. The LP8754 converter operates in PWM mode at a load current of 100 to 375 mA or higher; this mode transition trip-point is set by register. Lighter load current causes the device to automatically switch into PFM mode for reduced current consumption. By combining PFM and PWM modes in the same regulator and providing automatic switching, high efficiency can be achieved over a wide output load current range. Efficiency is further enhanced when the converter enters Low-Power PFM mode. The LP8754 includes LowPower mode function for low-current consumption. In this mode most of the internal blocks are disabled between the inductor current ramp up and ramp down phases to reduce the operating current. However, as a result, the transient performance of the converter is compromised. The Low-Power mode can be enabled by control register setting. Also, the application processor or the PMIC may provide an HW signal (NSLP) to the LP8754 input to indicate when the processor has entered a low-power state. When the signal is asserted, the LP8754 Low-Power PFM function will be enabled, and the LP8754 will run with a reduced input current. The right timing of the NSLP signal from the system is important for best load-transient performance. The NSLP signal should be asserted only when load current is stable and below 30 mA. Before the load current increases above 30 mA, the NSLP signal should be de-asserted 100 µs (minimum) prior to a load step to prepare the converter for the higher load current. 7.3.1.3 Buck Converter Load Current The buck load current can be monitored via I2C registers. Current of different buck converter cores or the total load current of the master can be selected from register 0x21 (see SEL_I_LOAD). A write to this selection register starts a current measurement sequence. The measurement sequence is a minimum of 50 µs long. When a measurement sequence starts, the FLAGS_1.I_LOAD_READY bit in register 0x0E is set to '0'. After the measurement sequence is finished, the FLAGS_1.I_LOAD_READY bit is set to '1'. (Note that by default this bit is '0'.) The measurement result can be read from registers 0x22 (LOAD_CURR.BUCK_LOAD_CURR[7:0]) and 0x21 (SEL_I_LOAD.BUCK_LOAD_CURR[10:8]). The measurement result [10:0] LSB is 10 mA, and the maximum value of the measurement is 20 A. The LP8754 can be configured to give out an interrupt after the load current measurement sequence is finished. Load current measurement interrupt can be masked with INT_MASKS_2.MASK_I_LOAD_READY bit. 7.3.1.4 Spread Spectrum Mode Systems with periodic switching signals may generate a large amount of switching noise in a set of narrowband frequencies (the switching frequency and its harmonics). The usual solution to reduce noise coupling is to add EMI-filters and shields to the boards. The LP8754's register-selectable spread spectrum mode minimizes the need for output filters, ferrite beads, or chokes. In spread spectrum mode, the switching frequency varies randomly around the center frequency, reducing the EMI emissions radiated by the converter, associated passive components, and PCB traces. See Figure 10. 18 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LP8754 LP8754 www.ti.com SNVS861A – FEBRUARY 2014 – REVISED AUGUST 2014 POWER SPECTRUM IS SPREAD AND LOWERED RADIADED ENERGY Features Descriptions (continued) FREQUENCY Where a fixed-frequency converter exhibits large amounts of spectral energy at the switching frequency, the spread spectrum architecture of the LP8754 spreads that energy over a large bandwidth. Figure 10. Spread Spectrum Modulation 7.3.2 Power-Up and Output Voltage Sequencing The power-up sequence for the LP8754 is as follows: • VVINBXX and VVDDA5V reach min recommended levels. • VVIOSYS set high. Enables the system I/O interface. For power-on-reset (POR), the I2C host should allow at least 500 µs before sending data to the LP8754 after the rising edge of the VIOSYS line. • VLDO voltage is raising. The LDO voltage is generated internally. The internal POR signal is activated. • Internal POR deasserted, OTP read. • Device enters standby mode. • DC/DC enable, output voltage, voltage slew rate programmed over I2C as needed by the application. • NRST set high. The DC/DC converter can be enabled and disabled by VSET_B0.EN_DIS_B0 bit or using the NRST signal. VVDDA5V VVIOSYS LDO (internal) t0 t1 t2 NRST tI2CT LP8754 receiving/sending data across the system I2C bus. Figure 11. Timing Diagram for the Power-Up Sequence Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LP8754 19 LP8754 SNVS861A – FEBRUARY 2014 – REVISED AUGUST 2014 www.ti.com Features Descriptions (continued) Table 1. Power-Up Sequence (1) CONDITION (1) SYMBOL PARAMETER t0 VVDDA5V to VVIOSYS assertion t1 LDOON Delay Time MIN t2 LDOON to NRST HIGH Device ready for I2C data transfer MAX <100 150 UNIT µs CLDO = 1 µF tI2CT TYP 0 µs 0 µs 500 µs These specification table entries are specified by design. The power input lines VVINBXX, VVDDA5V and VVIOSYS must be stable before the NRST line goes High. Also, the VLDO line must be stable 1.8 V before the NRST line goes High. 7.3.3 Device Reset Scenarios There are three reset methods implemented on the LP8754: • Software reset • Hardware reset • Power-on reset (POR) An SW-reset occurs when the RESET.SW_RESET bit is written first with 1, followed by 0 right after that. This event resets the control registers shown in Table 2 to the default values. The temperature, power good, and other faults are persistent over the SW reset to allow for the system to identify to cause of the failure. An internal power-on reset (POR) occurs when the supply voltage (VVDDA5V) transitions above the POR threshold or VVIOSYS is toggled low/high. Each of the registers contain a factory-defined value upon POR, and this data remains there until any of the following occurs: • Device sets a Flag bit, causing the Status register to be updated. The other registers remain untouched. • A different data word is written to a writable register. The internal registers will lose their contents if the supply voltage (VVDDA5V) goes below 1 V (typ.). A hardware reset is accomplished by NRST low. This event resets the control registers shown in Table 2 to the default values. Under OVP, UVLO, TSD, or VVIOSYS low (while NRST still high) conditions, a Fast Power-Down is launched. Normal Power-Down Sequence Follows This Event (Marked as '1') VVDDA5V VVDDA5V VVIOSYS 2 VVIOSYS 1 NRST NRST Figure 12. The External Power Control System Deasserts NRST 20 Fast Power-Down Follows This Event Figure 13. NRST Stays HIGH While VVIOSYS Transition from HIGH to LOW Happens (Marked as '2') Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LP8754 LP8754 www.ti.com SNVS861A – FEBRUARY 2014 – REVISED AUGUST 2014 Inductor Current Dropping to Zero in ~2 µs (All Converters, All Phases) IInductor tRST1 tRST2 HW RST by NRST OTP_MEM_READ tRST2 SW RST by I2C OTP_MEM_READ 0 Time ~2 Ps Figure 14. Fast Power-Down Figure 15. Reset Timings SYMBOL PARAMETER LIMIT tRST1 NRST active low pulse width 1 µs min + value on DELAY_BUCK0 register. tRST2 NRST inactive or I2C reset event to MEMORY READ end 25 µs max Table 2. Hardware Reset, Power-On Reset (POR) and Software Reset: Registers After Reset HEX ADDRESS REGISTER SOFTWARE RESET I2C RESET HARDWARE RESET NRST LOW (1) POWER-ON RESET VVIOSYS LOW 0x00 VSET_B0 All bits retained All bits retained All bits cleared 0x06 FPWM All bits cleared All bits cleared All bits cleared 0x07 to 0x0C BUCK0_CTRL to BUCK5_CTRL All bits cleared All bits cleared All bits cleared 0x0D FLAGS_0 All bits retained All bits retained All bits cleared 0x0E FLAGS_1 All bits retained All bits retained All bits cleared 0x0F INT_MASK0 All bits cleared All bits cleared All bits cleared 0x10 GENERAL All bits cleared All bits cleared All bits cleared 0x11 RESET N/A All bits cleared All bits cleared 0x12 DELAY_BUCK0 All bits cleared All bits cleared All bits cleared 0x18 CHIP_ID 0x19 PFM_LEV_B0 0x1F PHASE_LEV_B0 0x21 SEL_I_LOAD 0x22 LOAD_CURR 0x2E INT_MASK_2 (1) Read Only All bits cleared All bits cleared All bits cleared All bits cleared All bits cleared All bits cleared All bits retained All bits retained All bits cleared Read Only All bits cleared All bits cleared All bits cleared Reset will take effect upon complete of the power-down sequence. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LP8754 21 LP8754 SNVS861A – FEBRUARY 2014 – REVISED AUGUST 2014 www.ti.com 7.3.4 Diagnosis and Protection Features The LP8754 is capable of providing two levels of protection features: warnings for diagnosis and faults which are causing the converters to shut down. When the device detects warning or fault conditions, the LP8754 sets the flag bits indicating which fault or warning conditions have occurred; the INT pin will be pulled low. INT will be released again after a clear of flags is complete. The flag bits are persistent over reset to allow for the system to identify what was causing the interrupt and/or converter shutdown. Also, the LP8754 has a soft-start circuit that limits in-rush current during start-up. The output voltage increase rate is 30 mV/µs (default) during soft-start. Table 3. Summary of Exceptions and Interrupt Signals EVENT REGISTER.BIT INTERRUPT SIGNAL PRODUCED? INT MASK AVAILABLE? SCP triggered FLAGS_1.SCP Yes Yes Not PowerGood FLAGS_0.nPG_B0 Yes Yes TEMP status change FLAGS_0.TEMP[1:0] On any temperature change except for the case when TEMP[1:0] = 0b11 Yes Yes Thermal warning FLAGS_1.T_WARNING Yes Thermal shutdown FLAGS_1.THSD Yes No OVP triggered FLAGS_1.OVP Yes Yes Load current measurement ready FLAGS_1.I_LOAD_READY Yes Yes UVLO triggered FLAGS_1.UVLO Yes Yes 7.3.4.1 Warnings for Diagnosis (No Power Down) 7.3.4.1.1 Short-Circuit Protection (SCP) A short-circuit protection feature allows the LP8754 to protect itself and external components during overload conditions. The output short-circuit fault threshold is 400 mV (typ.) . 7.3.4.1.2 Power Good Monitoring When the converter's feedback-pin voltage falls lower than 90% (typ.) of the set voltage, the FLAGS_0.nPG_B0 flag is set. To prevent a false alarm, the power good circuit is masked during converter start-up and voltage transitions. The duration of the power good mask is set to 400 µs for converter start-up. For voltage ramps the masking time is extended by an internal logic circuit up to 6.4 ms. (See Protection Features Characteristics.) tMASK, RAMP Voltage tMASK, START VOUT Time Masking time for start-up is constant 400 µs (typ.). Masking time for voltage transitions depends on the selected ramp rates. Figure 16. Power Good Masking Principle 7.3.4.1.3 Thermal Warnings Prior to the thermal shutdown, thermal warnings are set. The first warning is set at 85°C (INT pin low), and the second at 120°C (INT pin pulled low and FLAGS_1.T_WARNING flag set). If the chip temperature crosses any of the thresholds of 85°C, 120°C, or 150°C (see FLAGS_0 register) the INT pin will be triggered. INT will be cleared upon read of FLAGS_0.TEMP[1:0] bits except if FLAGS_0.TEMP [1:0] = 0b11, which is a thermal fault event. 22 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LP8754 LP8754 www.ti.com SNVS861A – FEBRUARY 2014 – REVISED AUGUST 2014 7.3.4.2 Faults (Fault State and Fast Power Down) 7.3.4.2.1 Undervoltage Lock-out (UVLO) When the input voltage falls below VUVLO (typ. 2.25 V) at the VDDA5V pin, the LP8754 indicates a fault by activating the FLAGS_1.UVLO flag. The buck converter shut down without a power-down sequence (Fast PowerDown). The flag will remain active until the input voltage is raised above the UVLO threshold. If the flag is cleared while the fault persists, the flag is immediately re-asserted, and interrupt remains active. 7.3.4.2.2 Overvoltage Protection (OVP) When an input voltage greater than VOVP (typ. 5.3 V) is detected at the VDDA5V pin, the LP8754 indicates a fault by activating the FLAGS_1.OVP flag. The buck converter is shut down immediately (Fast Power-Down). The flag will remain active until the input voltage is below the OVP threshold. If the flag is cleared while the fault persists, the flag is immediately re-asserted and interrupt remains active. 7.3.4.2.3 Thermal Shutdown (THSD) The LP8754 has a thermal overload protection function that operates to protect itself from short-term misuse and overload conditions. When the junction temperature exceeds around 150°C, the device enters shutdown via faultstate. INT will be cleared upon write of the FLAGS_1.THSD flag even when thermal shutdown is active. This allows automatic recovery when temperature decreases below thermal shutdown level. See Figure 17 for LP8754 thermal diagnosis and protection features. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LP8754 23 LP8754 SNVS861A – FEBRUARY 2014 – REVISED AUGUST 2014 www.ti.com Read FLAGS_0 Clear THSD E\ZULWLQJ¶0' INT Released THSD De-asserted Yes INT Requested THSD Asserted TEMP[1:0] = 0b11 Power Outputs Disabled No Tj < 125°C Tj > 150°C Read FLAGS_0 Clear T_WARNING E\ZULWLQJ¶0' No INT by change in TEMP released Yes INT Requested If THSD low then enable power outputs INT by T_WARNING released TEMP[1:0] = 0b10 Yes INT Requested T_WARNING Asserted No Tj < 110°C Tj > 120°C Read FLAGS_0 No INT Released Yes INT Requested TEMP[1:0] = 0b01 Yes INT Requested No Tj < 75°C Tj > 85°C Read FLAGS_0 Yes INT Requested No INT Released TEMP[1:0] = 0b00 Note that INT is asserted whenever any of the thermal thresholds is crossed, if unmasked. Note also the 10°C Hysteresis on the TJ Thresholds. Figure 17. Thermal Warnings and Thermal Shutdown Flow 7.4 Device Functional Modes SHUTDOWN: All switch, reference, control and bias circuitry of the LP8754 are turned off. The main battery supply voltage is high enough to start the buck power-up sequence but VVIOSYS and NRST are LOW. STANDBY: Setting VVIOSYS HIGH enables standby-operation. All registers can be read or written by the system master via the system serial interface. Recovery from UVLO, TSD, or OVP event also leads to standby. ACTIVE: Regulated DC/DC converters are on or can be enabled with full current capability. In this mode, all features and control registers are available via the system serial bus and via DVS interface. LOW-POWER: At light loads (less than ~30 mA), and when the load does not require highest level of transient performance, the device enters automatically Low-Power mode. In this mode the part operates at low Iq. Conditions entering and exiting Low-Power mode are shown in Figure 18. 24 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LP8754 LP8754 www.ti.com SNVS861A – FEBRUARY 2014 – REVISED AUGUST 2014 Device Functional Modes (continued) FROM ANY STATE VVIOSYS LOW SHUTDOWN VVIOSYS HIGH READ OTP REG RESET *** THERMAL SHUTDOWN or UVLO/OVP RELEASED and FLAG(s) CLEARED STANDBY NRST LOW 2 or I C RESET 2 I C RESET NRST HIGH ACTIVE FAULT CONDITION DETECTED ** * FROM ANY STATE EXCEPT SHUTDOWN ACTIVE LOW POWER *) HIGH LOAD CURRENT OR ANY OF THE FOLLOWING CONDITIONS: NSLP (pin) LP_B0 (bit) LP_EN (bit) FPWM_B0 (bit) **) LOW LOAD CURRENT AND ALL THE FOLLOWING CONDITIONS NSLP (pin) LP_B0 (bit) LP_EN (bit) FPWM_B0 (bit) HIGH µ0¶ µ0¶ µ1¶ LOW µ1¶ µ1¶ µ0¶ ***) 6((´5(6(76&(1$5,26´)25 DETAILS Figure 18. Device Operation Modes Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LP8754 25 LP8754 SNVS861A – FEBRUARY 2014 – REVISED AUGUST 2014 www.ti.com 7.5 Programming 7.5.1 I2C-Compatible Interface The I2C-compatible synchronous serial interface provides access to the programmable functions and registers on the device. This protocol uses a two-wire interface for bidirectional communications between the IC's connected to the bus. The two interface lines are the Serial Data Line (SDA), and the Serial Clock Line (SCL). Every device on the bus is assigned a unique address and acts as either a Master or a Slave depending on whether it generates or receives the serial clock SCL. The SCL and SDA lines should each have a pull-up resistor placed somewhere on the line and remain HIGH even when the bus is idle. Note: CLK pin is not used for serial bus data transfer. There are two buses implemented: the System I2C bus and the DVS bus. In the following paragraphs, SCL refers to both SCLSYS and SCLSR, and SDA refers to SDASYS and SDASR. The LP8754 supports standard mode (100 kHz), fast mode (400 kHz) and high-speed mode (3.4 MHz). 7.5.1.1 Data Validity The data on SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, state of the data line can only be changed when clock signal is LOW. SCL SDA data change allowed data valid data change allowed data valid data change allowed Figure 19. Data Validity Diagram 7.5.1.2 Start and Stop Conditions The LP8754 is controlled via an I2C-compatible interface. START and STOP conditions classify the beginning and end of the I2C session. A START condition is defined as SDA transitions from HIGH to LOW while SCL is HIGH. A STOP condition is defined as SDA transition from LOW to HIGH while SCL is HIGH. The I2C master always generates the START and STOP conditions. SDA SCL S P Start Condition Stop Condition Figure 20. Start and Stop Sequences The I2C bus is considered busy after a START condition and free after a STOP condition. During data transmission the I2C master can generate repeated START conditions. A START and a repeated START condition are equivalent function-wise. The data on SDA must be stable during the HIGH period of the clock signal (SCL). In other words, the state of SDA can only be changed when SCL is LOW. Figure 1 shows the SDA and SCL signal timing for the I2C-Compatible Bus. See the I2C Serial Bus Timing Parameters for timing values. 7.5.1.3 Transferring Data Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first. Each byte of data has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated by the master. The master releases the SDA line (HIGH) during the acknowledge clock pulse. The LP8754 pulls down the SDA line during the 9th clock pulse, signifying an acknowledge. The LP8754 generates an acknowledge after each byte has been received. 26 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LP8754 LP8754 www.ti.com SNVS861A – FEBRUARY 2014 – REVISED AUGUST 2014 Programming (continued) There is one exception to the “acknowledge after every byte” rule. When the master is the receiver, it must indicate to the transmitter an end of data by not-acknowledging (“negative acknowledge”) the last byte clocked out of the slave. This “negative acknowledge” still includes the acknowledge clock pulse (generated by the master), but the SDA line is not pulled down. After the START condition, the bus master sends a chip address. This address is seven bits long followed by an eighth bit which is a data direction bit (READ or WRITE). For the eighth bit, a “0” indicates a WRITE and a “1” indicates a READ. The second byte selects the register to which the data will be written. The third byte contains data to write to the selected register. ack from slave ack from slave ack from slave start MSB Chip Addr LSB w ack MSB Register Addr LSB ack MSB Data LSB ack stop start id = 60h w ack addr = 40h ack address 40h data ack stop SCL SDA Figure 21. Write Cycle (w = write; SDA = '0'), id = device address = 60Hex for LP8754. ack from slave start MSB Chip Addr LSB w ack from slave MSB Register Addr LSB repeated start ack from slave data from slave nack from master rs MSB Chip Address LSB rs id = 60h r MSB Data LSB stop address 3Fh data nack stop SCL SDA start id =60h w ack address = 3Fh ack r ack When READ function is to be accomplished, a WRITE function must precede the READ function as shown above. Figure 22. Read Cycle ( r = read; SDA = '1'), id = device address = 60Hex for LP8754. 7.5.1.4 I2C-Compatible Chip Address The device address for the LP8754 is 0x60 (ADDR pin tied to the GND). After the START condition, the I2C master sends the 7-bit address followed by an eighth bit, read or write (R/W). R/W = 0 indicates a WRITE and R/W = 1 indicates a READ. The second byte following the device address selects the register address to which the data will be written. The third byte contains the data for the selected register. MSB 1 Bit 7 LSB 1 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 R/W Bit 0 2 I C Slave Address (chip address) Here device address is 1100000Bin = 60 Hex. Figure 23. Device Address Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LP8754 27 LP8754 SNVS861A – FEBRUARY 2014 – REVISED AUGUST 2014 www.ti.com Programming (continued) 7.5.1.5 Auto-Increment Feature The auto-increment feature allows writing several consecutive registers within one transmission. Every time an 8bit word is sent to the LP8754, the internal address index counter will be incremented by one, and the next register will be written. Table 4 below shows writing sequence to two consecutive registers. Note: the autoincrement feature does not work for read. Table 4. Auto-Increment Example Master Action Start Device Address = 60H Write Register Address LP8754 Action Data ACK ACK Data Stop ACK ACK 7.6 Register Maps 7.6.1 Register Descriptions The LP8754 is controlled by a set of registers through the system serial interface port or through the Dynamic Voltage Scaling interface. Table 5 below lists device registers, their addresses and their abbreviations. A more detailed description is given in the sections VSET_B0 to INT_MASK_2. Many registers contain bits, that are reserved for future use. When writing to a register, any reserved bits should not be changed. Table 5. 28 Addr Register Read / Write D7 0x00 VSET_B0 R/W EN_DIS_B 0 0x06 FPWM R/W 0x07 BUCK0_CTRL R/W OC_LEV_B0[1:0] 0x08 BUCK1_CTRL R/W OC_LEV_B1[1:0] Reserved 0x09 BUCK2_CTRL R/W OC_LEV_B2[1:0] Reserved 0x0A BUCK3_CTRL R/W OC_LEV_B3[1:0] Reserved 0x0B BUCK4_CTRL R/W OC_LEV_B4[1:0] Reserved 0x0C BUCK5_CTRL R/W OC_LEV_B5[1:0] 0x0D FLAGS_0 R/W Reserved I_LOAD_REA DY 0x0E FLAGS_1 R/W 0x0F INT_MASK_0 R/W 0x10 GENERAL R/W 0x11 RESET R/W 0x12 DELAY_BUCK0 R/W D6 D5 D4 D3 D2 D1 D0 VSET_B0[6:0] Reserved Reserved LP_B0 RDIS_B0 FPWM_B0 Reserved Reserved nPG_B0 UVLO T_WARNIN G Reserved Reserved RAMP_B0[2:0] EN_SS Reserved DIS_DIF_B0 Reserved TEMP[1:0] THSD OVP SCP MASK_nPG _B0 MASK_OVP MASK_SCP Reserved SLP_POL LP_EN SW_RESET DELAY_B0[7:0] 0x18 CHIP_ID R DEVICE 0x19 PFM_LEV_B0 R/W Reserved 0x1F PHASE_LEV_B0 R/W 0x21 SEL_I_LOAD R/W 0x22 LOAD_CURR R 0x2E INT_MASK_2 R/W OTP_REV[4:0] DIE_REV[1:0] PFM_ENTRY_B0[2:0] Reserved PFM_EXIT_B0[2:0] Reserved ADD_PH_B0[2:0] Reserved SHED_PH_B0[2:0] Reserved BUCK_LOAD_CURR[10:8] Reserved LOAD_CURRENT_SOURCE[2:0] BUCK_LOAD_CURR[7:0] Reserved Submit Documentation Feedback MASK_ILO AD_READY MASK_UVL MASK_TWA MASK_TEM O RNING P Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LP8754 LP8754 www.ti.com SNVS861A – FEBRUARY 2014 – REVISED AUGUST 2014 7.6.2 VSET_B0 Address: 0x00 D7 EN_DIS_B0 D6 D5 D4 D3 VSET_B0[6:0] D2 D1 D0 Bits Field Type Default Description 7 EN_DIS_B0 R/W 1 DC/DC converter Buck0 Enable/Disable. The Enable of the master Buck0 controls the operation of the slave bucks. 0 = Converter disabled 1 = Converter enabled Note: When a disable request is received the converter is disabled immediately. 6:0 VSET_B0[6:0] R/W 011 1100 Sets the output voltage. Defined by: VOUT = 0.5 V + 10 mV * VSET_B0 VOUT range = 0.6 V to 1.67 V NOTE: Do not use VSET_B0 values < 0001010 (10 dec) = 0.6 V. NOTE: Register settings starting from 1110110 up to 1111111 are clamped to 1.67 V. 7.6.3 FPWM Address: 0x06 D7 D6 D5 D4 Reserved Bits Field Type Default 7:1 Reserved R/W 001 1111 0 FPWM_B0 R/W 1 D3 D2 D1 D0 FPWM_B0 Description Forced PWM mode of operation, Buck regulator 0 (Master). The setting of the master controls the operation of the slave bucks. 0 = PWM, PFM or Low-Power PFM operation mode. 1 = This will force the master converter and the slaves to operate always in the PWM mode. 7.6.4 BUCK0_CTRL Address: 0x07 D7 D6 OC_LEV_B0[1:0] D5 LP_B0 D4 RDIS_B0 D3 Reserved D2 D1 RAMP_B0[2:0] D0 Bits Field Type Default 7:6 OC_LEV_B0[1:0] R/W 10 Inductor positive current limit on Buck 0. Note that OC_LEV_B0...B5 should have the same value. 00 = 1.5 A 01 = 2.0 A 10 = 2.5 A 11 = 3.0 A Description 5 LP_B0 R/W 0 Allows converter to enter into Low-Power PFM mode. 1 = Entering to Low-Power PFM mode is allowed. 0 = Entering to Low-Power PFM more is not allowed. 4 RDIS_B0 R/W 1 Enables the output discharge resistors when the VOUT supply has been disabled. 1 = Enable pull-down 0 = Disable pull-down 3 Reserved R/W 0 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LP8754 29 LP8754 SNVS861A – FEBRUARY 2014 – REVISED AUGUST 2014 Bits Field Type Default 2:0 RAMP_B0[2:0] R/W 001 www.ti.com Description This set the output voltage change ramp as follows: 000 = 30 mV/µs 001 = 15 mV/µs 010 = 7.5 mV/µs 011 = 3.8 mV/µs 100 = 1.9 mV/µs 101 = 0.94 mV/µs 110 = 0.47 mV/µs 111 = 0.23 mV/µs 7.6.5 BUCK1_CTRL Address: 0x08 D7 D6 OC_LEV_B1[1:0] D5 D4 D3 D2 D1 D0 Reserved Bits Field Type Default 7:6 OC_LEV_B1[1:0] R/W 10 5:0 Reserved R/W 01 0001 Description Inductor positive current limit on Buck 1. Note that OC_LEV_B0...B5 should have the same value. 00 = 1.5 A 01 = 2.0 A 10 = 2.5 A 11 = 3.0 A 7.6.6 BUCK2_CTRL Address: 0x09 D7 D6 OC_LEV_B2[1:0] D5 D4 D3 D2 D1 D0 Reserved Bits Field Type Default 7:6 OC_LEV_B2[1:0] R/W 10 5:0 Reserved R/W 01 0001 Description Inductor positive current limit on Buck 2. Note that OC_LEV_B0...B5 should have the same value. 00 = 1.5 A 01 = 2.0 A 10 = 2.5 A 11 = 3.0 A 7.6.7 BUCK3_CTRL Address: 0x0A D7 D6 OC_LEV_B3[1:0] D5 D3 D2 D1 D0 Reserved Bits Field Type Default 7:6 OC_LEV_B3[1:0] R/W 10 5:0 Reserved R/W 01 0001 30 D4 Description Inductor positive current limit on Buck 3. Note that OC_LEV_B0...B5 should have the same value. 00 = 1.5 A 01 = 2.0 A 10 = 2.5 A 11 = 3.0 A Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LP8754 LP8754 www.ti.com SNVS861A – FEBRUARY 2014 – REVISED AUGUST 2014 7.6.8 BUCK4_CTRL Address: 0x0B D7 D6 OC_LEV_B4[1:0] D5 D4 D3 D2 D1 D0 Reserved Bits Field Type Default 7:6 OC_LEV_B4[1:0] R/W 10 5:0 Reserved R/W 01 0001 Description Inductor positive current limit on Buck 4. Note that OC_LEV_B0...B5 should have the same value. 00 = 1.5 A 01 = 2.0 A 10 = 2.5 A 11 = 3.0 A 7.6.9 BUCK5_CTRL Address: 0x0C D7 D6 OC_LEV_B5[1:0] D5 D4 D3 D2 D1 D0 Reserved Bits Field Type Default 7:6 OC_LEV_B5[1:0] R/W 10 5:0 Reserved R/W 01 0001 Description Inductor positive current limit on Buck 5. Note that OC_LEV_B0...B5 should have the same value. 00 = 1.5 A 01 = 2.0 A 10 = 2.5 A 11 = 3.0 A 7.6.10 FLAGS_0 Address: 0x0D D7 D6 D5 Reserved D4 D3 D2 nPG_B0 Bits Field Type Default 7:3 Reserved R/W X XXXX 2 nPG_B0 R/W 0 Flag Bit (1) Power good fault flag for VOUT rail 1 = Power fault detected 0 = Power good 1:0 TEMP[1:0] R 00 indicates the die temperature as follows: 00: die temperature lower than 85ºC 01: 85ºC ≤ die temperature < 120ºC 10: 120ºC ≤ die temperature < 150ºC 11: die temperature 150ºC or higher (1) D1 D0 TEMP[1:0] Description The flag bit can be cleared only by writing a zero to the associated register bit or power cycling the device (VVIOSYS to LOW). Reading or RESET does not clear the flag bits. After clearing, the nPG_B0 fault flag will be raised again '1' if the fault condition persists. Any unmasked flag bit High will cause the interrupt to be asserted on the INT pin. The INT pin will be pulled Low until all the unmasked flags are clear again. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LP8754 31 LP8754 SNVS861A – FEBRUARY 2014 – REVISED AUGUST 2014 www.ti.com 7.6.11 FLAGS_1 Address: 0x0E D7 D6 D5 I_LOAD_READ Y Reserved Bits D4 UVLO D3 T_WARNING D2 THSD D1 OVP D0 SCP Field Type Default 7:6 Reserved R/W 00 5 I_LOAD_READY R/W 0 Flag Bit (1) 1 = Buck load current measurement data ready 0 = Buck load current measurement data not ready 4 UVLO R/W 0 Flag Bit (1) 1= Input undervoltage lockout (UVLO): Input voltage sagged below UVLO threshold. 0 = No UVLO 3 T_WARNING R/W 0 Flag Bit (1) 1= Thermal warning: The IC temperature exceeds 120°C, in advance of the thermal shutdown protection. 0 = No thermal warning 2 THSD R/W 0 Flag Bit (1) 1 = Thermal shutdown event detected 0 = No thermal shutdown 1 OVP R/W 0 Flag Bit (1) 1= Indicates overvoltage protection (OVP) circuit activation. 0 = No OVP event. The OVP circuitry monitors VDDA5V power input. 0 SCP R/W 0 Flag Bit (1) 1= Indicates short-circuit protection (SCP) circuit activation. The bit is activated when a short-circuit condition is detectedon output rail. 0 = No SCP event (1) Description The flag bit(s) can be cleared only by writing a zero to the associated register bit(s) or power cycling the device (VVIOSYS to LOW). Reading or RESET does not clear the flag bits. After clearing, the OVP, SCP fault flag(s) will be raised again '1' if the fault condition persists. The THSD flag will remain '0' after clear, even though the fault condition persists. Any unmasked flag bit High will cause the interrupt to be asserted on the INT pin. The INT pin will be pulled Low until all the unmasked flags are clear again. 7.6.12 INT_MASK_0 Address: 0x0F D7 D6 D5 Reserved D4 D3 D2 MASK_nPG_B 0 D1 MASK_OVP Bits Field Type Default 7:3 Reserved R/W 1 1111 2 MASK_nPG_B0 R/W 0 Interrupt mask for power good fault flag 1 = nPG_B0 does not set interrupt. 0 = nPG_B0 sets interrupt, when triggered. 1 MASK_OVP R/W 0 Interrupt mask for Overvoltage Protection (OVP) fault flag 1 = OVP does not set interrupt. 0 = OVP sets interrupt, when triggered. 0 MASK_SCP R/W 0 Interrupt mask for short-circuit protection SCP fault flag 1 = SCP does not set interrupt. 0 = SCP sets interrupt, when triggered. D0 MASK_SCP Description 7.6.13 GENERAL Address: 0x10 32 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LP8754 LP8754 www.ti.com SNVS861A – FEBRUARY 2014 – REVISED AUGUST 2014 D7 D6 D5 EN_SS Reserved D4 Reserved D3 DIS_DIF_B0 D2 Reserved D1 SLP_POL D0 LP_EN Bits Field Type Default 7:6 Reserved R/W 00 Description 5 EN_SS R/W 0 4 Reserved R/W 0 3 DIS_DIF_B0 R/W 0 2 Reserved R/W 0 1 SLP_POL R/W 0 Sets the polarity of the NSLP pin 1 = NSLP is active high 0 = NSLP is active low 0 LP_EN R/W 1 1 = allows Low-Power PFM mode. In order to reduce power consumption under low load conditions, the unit will automatically switch off unused internal blocks. 0 = Low-Power mode not allowed Spread Spectrum 1 = Spread Spectrum enabled 0 = Spread Spectrum disabled Disable Differential-to-single-ended amplifier 1 = Differential amplifier disabled 0 = Differential amplifier enabled 7.6.14 RESET Address: 0x11 D7 D6 D5 D4 Reserved Bits Field Type Default 7:1 Reserved R/W 000 0000 0 SW_RESET R/W 0 D3 D2 D1 D0 SW_RESET Description Writing this bit with '1' and '0', in this order, will reset the registers to the default values. If NRST is still kept HIGH, the converter output(s) will be regulated to the programmed register values. If a full POR reset is required VVIOSYS must be pulled low. The fault flags are persistent over SW-reset. 7.6.15 DELAY_BUCK0 Address: 0x12 D7 D6 D5 D4 D3 D2 D1 D0 DELAY_B0 Bits Field Type 7:0 DELAY_B0 R/W (1) Default Description 0000 0000 Master delay Sets the delay time from when NRST is asserted to when the VOUT rail is enabled. Sets the delay time from when NRST is de-asserted to when the VOUT rail is disabled. DELAY = DELAY_B0 * 100 µs If DELAY_B0 = FFh, supply is never enabled. (1) If this register is set to FFh when the converter is already started, it will cause an immediate power down of the converter. 7.6.16 CHIP_ID Address: 0x18 D7 DEVICE D6 D5 D4 OTP_REV D3 D2 D1 D0 DIE_REV Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LP8754 33 LP8754 SNVS861A – FEBRUARY 2014 – REVISED AUGUST 2014 Bits Field Type Default 7 DEVICE R 1 6:2 OTP_REV R 0 0001 1:0 DIE_REV R 00 www.ti.com Description DEVICE Contains Device ID OTP_REV Contains OTP Version ID DIE_REV Contains Revision ID 7.6.17 PFM_LEV_B0 Address: 0x19 D7 Reserved Bits D6 D5 PFM_ENTRY_B0[2:0] Field Type 7 Reserved R/W 0 6:4 PFM_ENTRY_B0 R/W 011 3 Reserved R/W 0 2:0 PFM_EXIT_B0 R/W 110 (1) D4 D3 Reserved Default D2 D1 PFM_EXIT_B0[2:0] D0 Description PFM_ENTRY_B0 (1) Sets the target PFM entry level for Buck 0. The final PWM-to-PFM switchover current varies slightly and is dependant on the output voltage, input voltage and the inductor current level. 000 = 100 mA 001 = 125 mA 010 = 150 mA 011 = 175 mA 100 = 225 mA 101 = Reserved 110 = Reserved 111 = Reserved PFM_EXIT_B0 (1) Sets the target PFM exit level for Buck 0. The final PFM-to-PWM switchover current varies slightly and is dependant on the output voltage, input voltage and the inductor current level. 000 = Reserved 001 = Reserved 010 = Reserved 011 = 175 mA 100 = 225 mA 101 = 275 mA 110 = 325 mA 111 = 375 mA For proper operation, the PFM exit current level should be at least 150 mA higher than the PFM entry current level. 7.6.18 PHASE_LEV_B0 Address: 0x1F D7 Reserved 34 D6 D5 ADD_PH_B0[2:0] D4 D3 Reserved Submit Documentation Feedback D2 D1 SHED_PH_B0[2:0] D0 Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LP8754 LP8754 www.ti.com SNVS861A – FEBRUARY 2014 – REVISED AUGUST 2014 Bits Field Type Default 7 Reserved R/W 0 6:4 ADD_PH_B0 R/W 100 3 Reserved R/W 0 2:0 SHED_PH_B0 R/W 010 (1) Description ADD_PH_B0 (1) Sets the level on which a phase is added. 000 = Reserved 001 = Reserved 010 = 0.5 A * No. of Active Phases 011 = 0.6 A * No. of Active Phases 100 = 0.7 A * No. of Active Phases 101 = 0.8 A * No. of Active Phases 110 = 0.9 A * No. of Active Phases 111 = 1.0 A * No. of Active Phases SHED_PH_B0 (1) Sets the level of phase shedding. 000 = 0.3 A * No. of Active Phases 001 = 0.4 A * No. of Active Phases 010 = 0.5 A * No. of Active Phases 011 = 0.6 A * No. of Active Phases 100 = 0.7 A * No. of Active Phases 101 = 0.8 A * No. of Active Phases 110 = Reserved 111 = Reserved ADD_PH_B0 and SHED_PH_B0 values must be chosen so that the resulting hysteresis is a minimum of 100 mA and ADD_PH_B0 > SHED_PH_B0. 7.6.19 SEL_I_LOAD Address: 0x21 D7 Reserved D6 D5 BUCK_LOAD_CURR[10:8] Bits Field Type Default 7 Reserved R/W 0 6:4 BUCK_LOAD_ CURR[10:8] R 000 3 Reserved R/W 0 2:0 LOAD_CURRENT_ SOURCE[2:0] R/W 000 D4 D3 Reserved D2 D1 D0 LOAD_CURRENT_SOURCE[2:0] Description BUCK_LOAD_CURR This register reports 3 MSB bits of the magnitude of the average load current of the selected Buck Converter. See LOAD_CURR register. LOAD_CURRENT_SOURCE These bits are used for choosing the Buck Converter whose load current will be measured. 000 = Converter 0 load current will be measured. 001 = Converter 1 load current will be measured. 010 = Converter 2 load current will be measured. 011 = Converter 3 load current will be measured. 100 = Converter 4 load current will be measured. 101 = Converter 5 load current will be measured. 110 = Master total load current will be measured. 111 = Reserved 7.6.20 LOAD_CURR Address: 0x22 D7 D6 D5 D4 D3 BUCK_LOAD_CURR[7:0] D2 D1 D0 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LP8754 35 LP8754 SNVS861A – FEBRUARY 2014 – REVISED AUGUST 2014 Bits Field Type 7:0 BUCK_LOAD_ CURR[7:0] R www.ti.com Default Description 0000 0000 BUCK_LOAD_CURR This register reports 8 LSB bits of the magnitude of the average load current of the selected Buck Converter. The value is reported with a resolution of 10 mA per LSB and 20A max current. Three MSB bits are reported by SEL_I_LOAD.BUCK_LOAD_CURR[10:8] bits, see SEL_I_LOAD. The current reported is an average over the last 5 milliseconds. The host system has read-only access to this register. This register is cleared to 0 on all resets. 000 0000 0000 Load current lower than 10 mA 000 0000 0001 10 mA ≤ Load current < 20 mA ... 111 1111 1110 20460 mA ≤ Load current < 20470 mA 111 1111 1111 Load current 20470 mA or higher. Note: Not production tested. Typical values for reference only. 7.6.21 INT_MASK_2 Address: 0x2E D7 D6 D5 D4 Reserved D3 MASK_ILOAD_ READY D2 MASK_UVLO D1 MASK_TWARN ING Bits Field Type Default 7:4 Reserved R/W 0000 3 MASK_ILOAD_ READY R/W 1 Interrupt mask for load current measurement flag 1 = FLAGS_1.I_LOAD_READY does not set interrupt. 0 = FLAGS_1.I_LOAD_READY sets interrupt. 2 MASK_UVLO R/W 0 Interrupt mask for undervoltage lock-out flag 1 = FLAGS_1.UVLO does not set interrupt. 0 = FLAGS_1.UVLO sets interrupt, when triggered. 1 MASK_ TWARNING R/W 1 Interrupt mask for thermal warning flag 1 = FLAGS_1.T_WARNING does not set interrupt. 0 = FLAGS_1.T_WARNING sets interrupt, when triggered. 0 MASK_TEMP R/W 1 Interrupt mask for die temperature flag bits 1 = FLAGS_0.TEMP[1:0] value change does not set interrupt. 0 = FLAGS_0.TEMP[1:0] value change sets interrupt. 36 D0 MASK_TEMP Description Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LP8754 LP8754 www.ti.com SNVS861A – FEBRUARY 2014 – REVISED AUGUST 2014 8 Application and Implementation 8.1 Application Information The LP8754 is a multi-phase step-down converter with 6 switcher cores bundled together. 8.2 Typical Application SYSTEM VOLTAGE LP8754: 6-PHASE CONFIGURATION 2.5 V - 5.0 V OUTPUT VOLTAGE L0 0.47 PH SWB0 VINB0/B1 CIN0 10 PF APPLICATIONS PROCESSOR L1 0.47 PH VINB2 SWB1 CIN1 10 PF L2 0.47 PH SWB2 VINB3/B4 CIN2 10 PF COUT6PH 4 x 22 PF CPU LOAD 10A MAX L3 0.47 PH SWB3 VINB5 CIN3 10 PF L4 0.47 PH SWB4 VDDA5V 1 PF L5 0.47 PH VIOSYS SWB5 CVIOSYS CPU SENSE CVDD VIO1V8 1 PF SDASR FBB0+/B0 SCLSR FBB0-/B1 CLDO 1 PF OPTIONAL NSLP VLDO VIO1V8 FBB2 RP1 SDASYS FBB3+/B3 RP2 SCLSYS FBB3-/B4 RP3 ADDR GNDs FBB5 INT NRST CPU POWER REQUEST Figure 24. 6-Phase Configuration Schematic Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LP8754 37 LP8754 SNVS861A – FEBRUARY 2014 – REVISED AUGUST 2014 www.ti.com Typical Application (continued) 8.2.1 Design Requirements Table 6 shows requirements for 6-phase configuration. Table 6. Design Parameters DESIGN PARAMETER EXAMPLE VALUE Input voltage range 2.5 V to 5 V Output voltage 1.1 V Converter operation mode Forced PWM Maximum load current 10 A Inductor current limit 2.5 A 8.2.2 Detailed Design Procedure The performance of the LP8754 device depends greatly on the care taken in designing the Printed Circuit Board (PCB). The use of low inductance and low serial resistance ceramic capacitors is strongly recommended, while proper grounding is crucial. Attention should be given to decoupling the power supplies. Decoupling capacitors must be connected close to the IC and between the power and ground pins to support high peak currents being drawn from System Power Rail during turn-on of the switching MOSFETs. Keep input and output traces as short as possible, because trace inductance, resistance and capacitance can easily become the performance limiting items. The separate power pins VINBXX are not connected together internally. The VINBXX power connections shall be connected together outside the package using power plane construction. 8.2.2.1 Inductor Selection The DC bias current characteristics of inductors must be considered. Different manufacturers follow different saturation current rating specifications, so attention must be given to details. (Please request DC bias curves from the manufacturer as part of the inductor selection process.) Minimum effective value of inductance to ensure good performance is 0.25 µH at 2.5 A (Default ILIMITP typ.) bias current over the inductor's operating temperature range. The inductor’s DC resistance should be less than 0.05 Ω for good efficiency at high-current condition. The inductor AC loss (resistance) also affects conversion efficiency. Higher Q factor at switching frequency usually gives better efficiency at light load to middle load. Table 7 below lists suggested inductors and suppliers. Shielded inductors radiate less noise and are preferable. Table 7. Suggested Inductors ITEM MODEL VENDOR L0 to L5; Step-down converter inductor 0.47 µH LQM21PNR47MGH DFE252012 R47 DFE201612C R47N Murata TOKO TOKO DIMENSIONS LxWxH (mm) D.C.R (mΩ) MAX 2.0 x 1.2 x 1.0 2.5 x 2 x 1.2 2.0 x 1.6 x 1.2 40 (typ) 39 50 8.2.2.2 Input Capacitor Selection A ceramic input capacitor of 10 µF, 10 V is sufficient for most applications. Place the input capacitor as close as possible to the VINBXX pin and GND pin of the device. A larger value or higher voltage rating may be used to improve input voltage filtering. Use X7R or X5R types, do not use Y5V. DC bias characteristics of ceramic capacitors must be considered when selecting case sizes like 0402. Minimum effective input capacitance to ensure good performance is 2.5 µF at maximum input voltage DC bias including tolerances and over ambient temp range, assuming that there is at least 22 µF of additional capacitance common for all the power input pins on the system power rail. The input filter capacitor supplies current to the PFET (high-side) switch in the first half of each cycle and reduces voltage ripple imposed on the input power source. A ceramic capacitor's low ESR provides the best noise filtering of the input voltage spikes due to this rapidly changing current. Select an input filter capacitor with sufficient ripple current rating. For additional noise immunity, adding a high-frequency decoupling capacitor of 100 nF to 1 µF between VDDA5V pin and GND is recommended. 38 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LP8754 LP8754 www.ti.com SNVS861A – FEBRUARY 2014 – REVISED AUGUST 2014 Table 8. Suggested Input/Output Capacitors (X5R Dielectric) MANUFACTURER PART NUMBER VALUE CASE SIZE VOLTAGE RATING Murata GRM188R60J106ME84 10 µF (20%) 0603 6.3 V TDK C1608X5R1A106KT 10 µF (10%) 0603 10 V Taiyo Yuden LMK107BJ106MALTD 10 µF (20%) 0603 10 V Samsung CL10A226MP8NUNE 22 µF (20%) 0603 10 V Samsung CL03A105MQ3CSNH 1 µF (20%) 0201 6.3 V 8.2.2.3 Output Capacitor Selection Use ceramic capacitor, X7R or X5R types; do not use Y5V. DC bias voltage characteristics of ceramic capacitors must be considered. DC bias characteristics vary from manufacturer to manufacturer, and DC bias curves should be requested from them as part of the capacitor selection process. The output filter capacitor smooths out current flow from the inductor to the load, helps maintain a steady output voltage during transient load changes and reduces output voltage ripple. These capacitors must be selected with sufficient capacitance and sufficiently low ESR to perform these functions. Minimum effective output capacitance to ensure good performance in 6-phase configuration is 30 µF at the output voltage DC bias including tolerances and over ambient temp range. The output voltage ripple is caused by the charging and discharging of the output capacitor and also due to its RESR. The RESR is frequency dependent (as well as temperature dependent); make sure the value used for selection process is at the switching frequency of the part. See suggested capacitors in Table 8. A higher output capacitance improves the load step behavior and reduces the output voltage ripple as well as decreasing the PFM switching frequency. For most 6-phase applications 4 x 22 µF 0603 capacitors for COUT is suitable. Although the converter's loop compensation can be programmed to adapt to virtually several hundreds of microfarads COUT, an effective COUT less than 120 µF is preferred -- there is not necessarily any benefit to having a COUT higher than 120 µF. Note that the output capacitor may be the limiting factor in the output voltage ramp, especially for very large (> 100 µF) output capacitors. For large output capacitors, the output voltage might be slower than the programmed ramp rate at voltage transitions, because of the higher energy stored on the output capacitance. Also at start-up, the time required to charge the output capacitor to target value might be longer. At shutdown, if the output capacitor is discharged by the internal discharge resistor, more time is required to settle VOUT down as a consequence of the increased time constant. 8.2.2.4 LDO Capacitor Selection A ceramic low ESR 1.0-μF capacitor should be connected between the VLDO and GNDA pins 8.2.2.5 VIOSYS Capacitor Selection Adding a ceramic low ESR 1.0-μF capacitor between the VIOSYS pin and GND is recommended. If VVIOSYS signal is low noisy the capacitor is not required. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LP8754 39 LP8754 SNVS861A – FEBRUARY 2014 – REVISED AUGUST 2014 www.ti.com 8.2.3 Application Performance Plots 100 100 90 90 EFFICIENCY (%) EFFICIENCY (%) Unless otherwise specified: VVDDA5V = VVINBXX = 3.7 V, VOUT = 1.1 V, TA = 25°C 80 70 1500 mV 1300 mV 1100 mV 60 80 70 1500 mV 1300 mV 1100 mV 60 900 mV 900 mV 700 mV 50 0 2000 4000 6000 8000 10000 OUTPUT CURRENT (mA) VIN = 3.7 V 700 mV 50 0 2000 4000 6000 Inductor: Murata LQM21PNR47MGH VIN = 2.7 V Figure 25. Efficiency vs Load Current in Forced PWM Mode 1500 mV 1300 mV 1100 mV 900 mV 700 mV 1300 mV LP PFM 1100 mV LP PFM 900 mV LP PFM 1300 mV PFM 1100 mV PFM 900 mV PFM 1300 mV PWM 1100 mV PWM 900 mV PWM 50 40 30 1 10 100 1000 EFFICIENCY (%) EFFICIENCY (%) 90 60 4500 5000 C030 Figure 28. Efficiency vs Input Voltage in PWM Mode 1500 mV 1300 mV 1100 mV 900 mV 700 mV 95 EFFICIENCY (%) EFFICIENCY (%) 4000 100 85 80 75 90 85 80 75 70 2500 3000 3500 4000 INPUT VOLTAGE (mV) IOUT = 3 A 4500 5000 70 2500 3000 Inductor: Murata LQM21PNR47MGH 3500 4000 INPUT VOLTAGE (mV) C031 Figure 29. Efficiency vs Input Voltage in PWM Mode 40 3500 IOUT = 1 A Inductor: Murata LQM21PNR47MGH 1500 mV 1300 mV 1100 mV 900 mV 700 mV 90 3000 INPUT VOLTAGE (mV) Figure 27. Efficiency vs Load Current in Low-Power PFM Mode, PFM Mode, and Forced PWM Mode 95 80 C033 VOUTSET = 900, 1100 and 1300 mV Inductor: Murata LQM21PNR47MGH 100 90 70 2500 10000 OUTPUT CURRENT (mA) C029 Inductor: Murata LQM21PNR47MGH 100 70 10000 Figure 26. Efficiency vs Load Current in Forced PWM Mode 100 80 8000 OUTPUT CURRENT (mA) C028 IOUT = 6 A 4500 5000 C032 Inductor: Murata LQM21PNR47MGH Figure 30. Efficiency vs Input Voltage in PWM Mode Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LP8754 LP8754 www.ti.com SNVS861A – FEBRUARY 2014 – REVISED AUGUST 2014 1105 1110 VIN = 2.5 V 1104 1103 VIN = 5 V 1104 VOUT (mV) VOUT (mV) VIN = 3.7 V 1106 VIN = 5 V 1102 VIN = 2.5 V 1108 VIN = 3.7 V 1101 1100 1099 1102 1100 1098 1098 1096 1097 1094 1096 1092 1095 1090 0 1 2 3 4 5 6 7 8 9 10 LOAD CURRENT (A) 0 100 200 300 400 500 LOAD CURRENT (mA) C019 VOUTSET = 1.1 V C026 VOUTSET = 1.1 V Figure 31. Output Voltage vs Load Current in Forced PWM Mode Figure 32. Output Voltage vs Load Current in PFM/PWM Mode 1100.0 1110 1108 1106 1099.5 VOUT (mV) 1102 1100 1098 1096 1099.0 1098.5 1094 PWM, ILOAD = 3 A 1092 PFM, ILOAD = 100 mA 1098.0 2500 1090 ±40 ±20 0 20 40 60 80 100 120 TEMPERATURE (C) 3000 VOUTSET = 1.1 V ILOAD = 1.0 A Figure 33. Output Voltage vs Temperature 1400 1200 8.0 6.0 1000 800 4.0 600 400 4500 5000 C037 VOUTSET = 1.1 V 2.0 10.0 Buck 0 Iout (mA) Buck 1 Iout (mA) Buck 2 Iout (mA) Accuracy 1800 PHASE CURRENT (mA) PHASE CURRENT (mA) 1600 2000 10.0 Buck 0 Iout (mA) Buck 1 Iout (mA) Buck 2 Iout (mA) Buck 3 Iout (mA) Buck 4 Iout (mA) Buck 5 Iout (mA) Accuracy 1800 4000 Figure 34. Line Regulation ACCURACY (%) 2000 3500 INPUT VOLTAGE (mV) C042 1600 8.0 1400 1200 6.0 1000 800 4.0 600 400 ACCURACY (%) VOUT (mV) 1104 2.0 200 200 0 0 2000 4000 6000 8000 0.0 10000 TOTAL IOUT (mA) 0 0 2000 3000 4000 0.0 5000 TOTAL IOUT (mA) C038 Figure 35. Phase Currents and Current Balancing Accuracy, 6 Phases Active (Currents measured by LP8754) 1000 C040 Figure 36. Phase Currents and Current Balancing Accuracy, 3 Phases Active (Currents measured by LP8754) Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LP8754 41 LP8754 SNVS861A – FEBRUARY 2014 – REVISED AUGUST 2014 4500 8000 16.0 4000 16.0 7000 14.0 3500 14.0 6000 12.0 3000 12.0 5000 10.0 2500 10.0 4000 8.0 2000 8.0 3000 6.0 1500 6.0 2000 4.0 1000 4.0 1000 2.0 500 2.0 0 0.0 10000 0 0 2000 4000 6000 8000 REAL IOUT (mA) 0 1000 18.0 2000 3000 0.0 5000 C041 Figure 38. Load Current Measured by LP8754 vs Real Load Current, 3 Phases Active VOUT AC COUPLED 20 mV/DIV VOUT AC COUPLED 20 mV/DIV ILOAD 4 A/DIV ILOAD 1 A/DIV TIME 20 Ps/DIV TIME 20 Ps/DIV IOUT 1 A → 8 A → 1 A 4000 REAL IOUT (mA) C039 Figure 37. Load Current Measured by LP8754 vs Real Load Current, 6 Phases Active 20.0 IOUT Accuracy ACCURACY (%) TOTAL IOUT (mA) 5000 18.0 IOUT Accuracy 9000 ACCURACY (%) 20.0 10000 TOTAL IOUT (mA) www.ti.com tr = tf = 400 ns Figure 39. Transient Load Step Response, PWM Mode IOUT 0.6 A → 2 A → 0.6 A tr = tf = 400 ns Figure 40. Transient Load Step Response, PWM Mode VOUT AC COUPLED 20 mV/DIV VIN 500 mV/DIV VOUT AC COUPLED 10 mV/DIV ILOAD 200 mA/DIV TIME 40 Ps/DIV TIME 20 Ps/DIV VIN 3.3 V → 3.8 V → 3.3 V IOUT = 2000 mA DC IOUT 0.5 mA → 0.5 A → 0.5 mA tr = tf = 100 ns Figure 41. Transient Load Step Response, AUTO Mode 42 Submit Documentation Feedback tr = tf = 10 µs Figure 42. Transient Line Response Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LP8754 LP8754 www.ti.com SNVS861A – FEBRUARY 2014 – REVISED AUGUST 2014 VOUT AC COUPLED 10 mV/DIV VOUT AC COUPLED 10 mV/DIV SW 1 V/DIV SW 1 V/DIV TIME 400 µs/DIV TIME 200 ns/DIV IOUT = 100 µA IOUT = 200 mA Figure 43. Output Voltage Ripple, PFM Mode Figure 44. Output Voltage Ripple, PWM Mode, One Phase Active NRST 2 V/DIV NRST 2 V/DIV VOUT 200 mV/DIV VOUT 200 mV/DIV LOAD 1 A/DIV SW 5 V/DIV SW 5 V/DIV TIME 20 Ps/DIV TIME 20 Ps/DIV No Load 3-A Load Figure 45. Start-up with NRST, Forced PWM Figure 46. Start-up with NRST, Forced PWM NRST 2 V/DIV VOUT 200 mV/DIV VOUT 200 mV/DIV SW 5 V/DIV TIME 10 ms/DIV TIME 400 µs/DIV No Load Figure 47. Shutdown with NRST, Forced PWM Figure 48. VOUT Transition from 0.6 V to 1.4 V with Different Ramp Settings Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LP8754 43 LP8754 SNVS861A – FEBRUARY 2014 – REVISED AUGUST 2014 www.ti.com VOUT AC COUPLED 10 mV/DIV IL_B0 200 mV/DIV VOUT AC COUPLED 10 mV/DIV LOAD 1 A/DIV TIME 100 ms/DIV VSW 2 V/DIV TIME 2 µs/DIV IOUT 0 A → 5 A → 0 A Figure 49. Load Ramp Figure 50. Transient from PFM to PWM Mode INT 500 mV/DIV VOUT AC COUPLED 10 mV/DIV VOUT 200 mV/DIV LOAD 5 A/DIV VSW 2 V/DIV TIME 400 Ps/DIV TIME 2 µs/DIV Figure 51. Transient from PWM to PFM Mode Figure 52. Interrupt Line Going Low with Not Power Good Activation SW 2 V/DIV VOUT 200 mV/DIV INT 500 mV/DIV TIME 10 Ps/DIV Figure 53. Metallic Short Applied at VOUT 44 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LP8754 LP8754 www.ti.com SNVS861A – FEBRUARY 2014 – REVISED AUGUST 2014 9 Power Supply Recommendations The device is designed to operate from an input voltage supply range between 2.5 V and 5 V. This input supply should be well regulated and able to withstand maximum input current and maintain stable voltage without voltage drop even at load transition condition. The resistance of the input supply rail should be low enough that the input current transient does not cause too high drop in the LP8754 supply voltage that can cause false UVLO fault triggering. If the input supply is located more than a few inches from the LP8754 additional bulk capacitance may be required in addition to the ceramic bypass capacitors. 10 Layout 10.1 Layout Guidelines The high frequency and large switching currents of the LP8754 make the choice of layout important. Good power supply results will only occur when care is given to proper design and layout. Bad layout will affect noise pickup and generation and can cause a good design to perform with less-than-expected results. With a range of output currents from milliamps to 10 A, good power-supply layout is more challenging than for most general PCB design. The following steps should be used as a reference to ensure the device is stable and maintains proper voltage and current regulation across its intended operating voltage and current range: 1. Place CIN as close as possible to the VINBXX pin and the GND pin. Route the VIN trace wide and thick to avoid IR drops. The trace between the input capacitor's positive node and LP8754’s VINBXX pin(s) as well as the trace between the input capacitor's negative node and power GND pin(s) must be kept as short as possible. The input capacitance provides a low-impedance voltage source for the switching converter. The parasitic inductance on these traces must be kept as tiny as possible for proper device operation. 2. The output filter for each buck, consisting of COUT and L, converts the switching signal at SW to the noiseless output voltage. For optimal EMI behavior, it should be placed as close as possible to the device, keeping the switch node small. Route the traces between the LP8754's output capacitors and the load's input capacitors direct and wide to avoid losses due to the IR drop. 3. Input for analog blocks (VDDA5V and GNDA) should be isolated from noisy signals. Connect VDDA5V directly to a quiet system voltage node and GNDA to a quiet ground point where no IR drop occurs. For additional noise immunity, adding a high-frequency decoupling capacitor of 100 nF to 1 µF is recommended. Place the decoupling capacitor as close to the VDDA5V pin as possible. VDDA5V trace is low current, so the trace width does not need to be optimized. 4. If the processor load supports voltage remote sensing, connect the LP8754’s feedback pins FBBXX to the respective sense pins on the processor. The sense lines are susceptible to noise. They must be kept away from noisy signals such as GNDBXX, VIN, and SW, as well as high bandwidth signals such as the I2C. Avoid both capacitive as well as inductive coupling by keeping the sense lines short, direct, and close to each other. Run the lines in a quiet layer. Isolate them from noisy signals by a voltage or ground plane if possible. Running the signal as a differential pair is recommended. 5. GNDBXX, VIN, and SW should be routed on thick layers. They must not surround inner signal layers which are not able to withstand interference from noisy GNDBXX, VIN, and SW. This can create noise coupling to inner signal layers. Due to the small package of this converter and the overall small solution size, the thermal performance of the PCB layout is important. Many system-dependent issues such as thermal coupling, airflow, added heat sinks and convection surfaces, and the presence of other heat-generating components affect the power dissipation limits of a given component. Proper PCB layout, focusing on thermal performance, results in lower die temperatures. Wide power traces come with the ability to sink dissipated heat. This can be improved further on multi-layer PCB designs with vias to different planes. This results in reduced junction-to-ambient (RθJA) and junction-to-board (RθJB) thermal resistances, thereby reducing the device junction temperature, TJ. It's strongly recommended to perform a careful system-level 2D or full 3D dynamic thermal analysis at the beginning of the product design process, using a thermal modeling analysis software. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LP8754 45 LP8754 SNVS861A – FEBRUARY 2014 – REVISED AUGUST 2014 www.ti.com 10.2 Layout Example Via to GND plane Via to VIN plane VOUT L1 COUT1 L2 L0 COUT0 CIN1 CIN0 VIN GND Input capacitors VIN Pin A1 VIN CVDD GND VIN B2 SW B2 GND B1/ B2 SW B1 VIN B0/ B1 SW B0 GND B0 VIN B2 SW B2 GND B1/ B2 SW B1 VIN B0/ B1 SW B0 GND B0 SDA SYS SCL SYS GND B1/ B2 ADD R VIN B0/ B1 NSLP VLD O FB B5 FB B3-/ B4 FB B3+/ B3 FB B2 FB B0-/ B1 FB B0+/ B0 GND A SDA SR SCL SR GND B4/ B5 NRS T VIN B3/ B4 INT VIO SYS VDD A5V SW B5 GND B4/ B5 SW B4 VIN B3/ B4 SW B3 GND B3 VIN B5 SW B5 GND B4/ B5 SW B4 VIN B3/ B4 SW B3 GND B3 VIN CIN3 GND VIN GND VIN CVLDO CIN4 GND CVIOSYS GND CIN2 Input capacitors COUT2 L5 COUT3 L4 L3 Figure 54. LP8754 Board Layout 46 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LP8754 LP8754 www.ti.com SNVS861A – FEBRUARY 2014 – REVISED AUGUST 2014 11 Device and Documentation Support 11.1 Device Support 11.1.1 Third-Party Products Disclaimer TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE. 11.2 Trademarks All trademarks are the property of their respective owners. 11.3 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 11.4 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LP8754 47 PACKAGE OPTION ADDENDUM www.ti.com 29-Aug-2014 PACKAGING INFORMATION Orderable Device Status (1) LP875484YFQR ACTIVE Package Type Package Pins Package Drawing Qty DSBGA YFQ 49 1000 Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM Op Temp (°C) Device Marking (4/5) -40 to 85 754A (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 29-Aug-2014 Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 29-Aug-2014 TAPE AND REEL INFORMATION *All dimensions are nominal Device LP875484YFQR Package Package Pins Type Drawing SPQ DSBGA 1000 YFQ 49 Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 178.0 12.4 Pack Materials-Page 1 3.06 B0 (mm) K0 (mm) P1 (mm) 3.2 0.71 8.0 W Pin1 (mm) Quadrant 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 29-Aug-2014 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LP875484YFQR DSBGA YFQ 49 1000 210.0 185.0 35.0 Pack Materials-Page 2 MECHANICAL DATA YFQ0049xxx D 0.600±0.075 E TMD49XXX (Rev A) D: Max = 3.022 mm, Min =2.962 mm E: Max = 2.882 mm, Min =2.822 mm 4215087/A NOTES: A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994. B. This drawing is subject to change without notice. www.ti.com 12/12 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products. 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