TI1 MM54C200 256-bit tri-state random access read/write memory Datasheet

MM54C200,MM74C200
MM54C200 MM74C200 256-Bit TRI-STATE Random Access Read/Write Memory
Literature Number: SNOS329A
MM54C200/MM74C200 256-Bit TRI-STATEÉ
Random Access Read/Write Memory
General Description
Read Operation: The data is read out by selecting the
proper address and bringing CE3 low and WE high.
Y
Y
Y
Y
Wide supply voltage range
Guaranteed noise margin
High noise immunity
TTL compatibility
3V to 15V
1V
0.45 VCC (typ.)
Fan out of 1
driving standard TTL
500 nW (typ.)
Y
Y
Low power
Internal address register
bs
ol
Logic and Connection Diagrams
Features
et
Note: The timing is different from the DM74200 in that a positive to negative
transition of the CE3 must occur for the memory to be selected.
Holding either CE1, CE2, or CE3 at a high level forces the
output into TRI-STATE. When used in bus-organized systems, CE1, or CE2, a TRI-STATE control provides for fast
access times by not totally disabling the chip.
Write Operation: Data is written into the memory with CE3
low and WE low. The state of CE1 or CE2 has no effect on
the write cycle. The output assumes TRI-STATE with WE
low.
e
The MM54C200/MM74C200 is a 256-bit random access
read/write memory. Inputs consist of eight address lines
and three chip enables. The eight binary address inputs are
decoded internally to select each of the 256 locations. The
internal address register, latches, and address information
are on the positive to negative edge of CE3. The TRISTATE data output line, working in conjunction with CE1 or
CE2 inputs, provides for easy memory expansion.
Address Operation: Address inputs must be stable tSA prior to the positive to negative transition of CE3. It is therefore
unnecessary to hold address information stable for more
than tHA after the memory is enabled (positive to negative
transition).
O
Dual-In-Line Package
TL/F/5903 – 2
Top View
Order Number MM54C200 or
MM74C200
TL/F/5903 – 1
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
C1995 National Semiconductor Corporation
TL/F/5903
RRD-B30M105/Printed in U. S. A.
MM54C200/MM74C200 256-Bit TRI-STATE Random Access Read/Write Memory
February 1988
Absolute Maximum Ratings (Note 1)
Power Dissipation (PD)
Dual-In-Line
Small Outline
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Voltage at Any Pin
Operating VCC Range
b 0.3V to VCC a 0.3V
Operating Temperature Range (TA)
MM54C200
MM74C200
b 55§ C to a 125§ C
b 40§ C to a 85§ C
Storage Temperature Range (TS)
b 65§ C to a 150§ C
700 mW
500 mW
3V to 15V
18V
Absolute Maximum VCC
Lead Temperature (TL)
(Soldering, 10 seconds)
260§ C
DC Electrical Characteristics Min/Max limits apply across temperature range unless otherwise noted
Symbol
Parameter
Conditions
Min
Typ
Max
Units
CMOS TO CMOS
VIN(1)
Logical ‘‘1’’ Input Voltage
VCC e 5V
VCC e 10V
VIN(0)
Logical ‘‘0’’ Input Voltage
VCC e 5V
VCC e 10V
VOUT(1)
Logical ‘‘1’’ Output Voltage
VCC e 5V, IO eb10 mA
VCC e 10V, IO eb10 mA
VOUT(0)
Logical ‘‘0’’ Output Voltage
VCC e 5V, IO e a 10 mA
VCC e 10V, IO e a 10 mA
IIN(1)
Logical ‘‘1’’ Input Current
VCC e 15V, VIN e 15V
IIN(0)
Logical ‘‘0’’ Input Current
VCC e 15V, VIN e 0V
ICC
Supply Current
VCC e 15V
V
V
V
V
e
1.5
2
4.5
9
V
V
0.5
1
V
V
et
CMOS/TTL INTERFACE
3.5
8
0.005
b1
0.1
Logical ‘‘1’’ Input Voltage
54C VCC e 4.5V
74C VCC e 4.75V
VIN(0)
Logical ‘‘0’’ Input Voltage
54C VCC e 4.5V
74C VCC e 4.75V
VOUT(1)
Logical ‘‘1’’ Output Voltage
54C VCC e 4.5V, IO eb1.6 mA
74C VCC e 4.75V, IO eb1.6 mA
VOUT(0)
Logical ‘‘0’’ Output Voltage
54C VCC e 4.5V, IO e 1.6 mA
74C VCC e 4.75V, IO e 1.6 mA
mA
mA
600
VCCb1.5
VCCb1.5
bs
ol
VIN(1)
1
b 0.005
0.8
0.8
2.4
2.4
mA
V
V
V
V
V
V
0.4
V
OUTPUT DRIVE (See 54C/74C Family Characteristics Data Sheet) (Short Circuit Current)
Output Source Current
(P-Channel)
VCC e 5V, VOUT e 0V
TA e 25§ C
b4
b 1.8
b6
mA
mA
ISOURCE
Output Source Current
(P-Channel)
VCC e 10V, VOUT e 0V
TA e 25§ C
b 16
b 1.5
b 25
mA
mA
ISINK
Output Sink Current
(N-Channel)
VCC e 5V, VOUT e VCC
TA e 25§ C
5
8
mA
ISINK
Output Sink Current
(N-Channel)
VCC e 10V, VOUT e VCC
TA e 25§ C
20
30
mA
O
ISOURCE
Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’
they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device
operation.
2
AC Electrical Characteristics* TA e 25§ C, CL e 50 pF, unless otherwise specified
Max
Units
Access Time from Address
Parameter
VCC e 5V
VCC e 10V
Conditions
Min
450
200
900
400
ns
ns
tpd
Propagation Delay from CE3
VCC e 5V
VCC e 10V
360
120
700
300
ns
ns
tpCE1
Propagation Delay from CE1 or CE2
VCC e 5V
VCC e 10V
250
85
700
200
ns
ns
tSA
Address Setup Time
VCC e 5V
VCC e 10V
200
100
80
30
ns
ns
tHA
Address Hold Time
VCC e 5V
VCC e 10V
50
25
15
5.0
ns
ns
tWE
Write Enable Pulse Width
VCC e 5V
VCC e 10V
300
150
160
70
ns
ns
tCE
CE3 Pulse Widths
VCC e 5V
VCC e 10V
400
160
200
80
ns
ns
CIN
Input Capacity
Any Input (Note 2)
5.0
pF
COUT
Output Capacity in TRI-STATE
(Note 2)
9.0
pF
CPD
Power Dissipation Capacity
(Note 3)
400
pF
et
Symbol
e
Typ
tACC
AC Electrical Characteristics* CL e 50 pF
Symbol
Parameter
Conditions
MM54C200
TA eb55§ C to a 125§ C
Min
tpd
tpdCE1
tSA
tHA
tWE
tHD
Units
Max
Access Time from Address
VCC e 5V
VCC e 10V
1200
520
1100
480
ns
ns
Propagation Delay from CE3
VCC e 5V
VCC e 10V
950
400
850
360
ns
ns
Propagation Delay from
CE1 or CE2
VCC e 5V
VCC e 10V
650
300
600
275
ns
ns
Address Setup Time
VCC e 5V
VCC e 10V
250
120
250
120
ns
ns
Address Hold Time
VCC e 5V
VCC e 10V
100
50
100
50
ns
ns
Write Enable Pulse Width
VCC e 5V
VCC e 10V
450
225
400
200
ns
ns
Disable Pulse Width
VCC e 5V
VCC e 10V
500
250
460
230
ns
ns
VCC e 5V
VCC e 10V
50
25
50
25
ns
ns
O
tCE
Min
bs
ol
tACC
Max
MM74C200
TA eb40§ C to a 85§ C
Data Hold Time
*AC Parameters are guaranteed by DC correlated testing.
Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’
they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device
operation.
Note 2: Capacitance is guaranteed by periodic testing.
Note 3: CPD determines the no load AC power consumption of any CMOS device. For complete explanation see 54C/74C Family Characteristics application note,
AN-90.
3
Switching Time Waveforms
et
e
Read and Write Cycles Using CE3 (CE1 e CE2 e logic 0)
bs
ol
TL/F/5903 – 3
O
Read and Write Cycles Using CE3 and CE1 (or CE2)
TL/F/5903 – 4
Note: Used for fast access time in bused systems.
4
e
Physical Dimensions inches (millimeters)
O
bs
ol
et
Ceramic Dual-In-Line Package (J)
Order Number MM54C200J or MM74C200J
NS Package Number J16A
5
e
bs
ol
et
Molded Dual-In-Line Package (N)
Order Number MM54C200N or MM74C200N
NS Package Number N16E
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DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
O
MM54C200/MM74C200 256-Bit TRI-STATE Random Access Read/Write Memory
Physical Dimensions inches (millimeters) (Continued)
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