Maxim MAX4823 3.3v/5v, 8-channel relay drivers with fast recovery time and power-save mode Datasheet

19-3789; Rev 0; 8/05
+3.3V/+5V, 8-Channel Relay Drivers with Fast
Recovery Time and Power-Save Mode
Features
The MAX4822–MAX4825 8-channel relay drivers offer
built-in kickback protection and drive +3V/+5V nonlatching or dual-coil-latching relays. Each independent
open-drain output features a 2.7Ω (typ) on-resistance
and is guaranteed to sink 70mA (min) of load current.
These devices consume less than 300µA (max) quiescent current and have 1µA output off-leakage current.
A Zener-kickback-protection circuit significantly
reduces recovery time in applications where switching
speed is critical.
The MAX4822/MAX4824 feature a unique power-save
mode where the relay current, after activation, can be
reduced to a level just above the relay hold-current
threshold. This mode keeps the relay activated while
significantly reducing the power consumption.
♦ Built-In Zener Kickback Protection for Fast
Recovery
The MAX4822/MAX4823 feature a 10MHz SPI™-/
QSPI™-/MICROWIRE™-compatible serial interface.
Input data is shifted into a shift register and latched to
the outputs when CS transitions from low to high. Each
data bit in the shift register corresponds to a specific
output, allowing independent control of all outputs.
♦ Serial Digital Output for Daisy Chaining
The MAX4824/MAX4825 feature a 4-bit parallel-input
interface. The first 3 bits (A0, A1, A2) determine the output address, and the fourth bit (LVL) determines whether
the selected output is switched on or off. Data is latched
to the outputs when CS transitions from low to high.
The MAX4822–MAX4825 feature separate set and reset
functions, allowing turn-on or turn-off of all outputs
simultaneously with a single control line. Built-in hysteresis (Schmidt trigger) on all digital inputs allows
these devices to be used with slow-rising and falling
signals, such as those from optocouplers or RC powerup initialization circuits. The MAX4822–MAX4825 are
available in space-saving 4mm x 4mm, 20-pin thin QFN
packages. They are specified over the -40°C to +85°C
extended temperature range.
♦ Programmable Power-Save Mode Reduces Relay
Power Consumption (MAX4822/MAX4824)
♦ 10MHz SPI-/QSPI-/MICROWIRE-Compatible Serial
Interface
♦ Eight Independent Output Channels
♦ Drive +3V and +5V Relays
♦ Guaranteed 70mA (min) Coil Drive Current
♦ Guaranteed 5Ω (max) RON
♦ SET / RESET Functions to Turn On/Off All
Outputs Simultaneously
♦ Optional Parallel Interface (MAX4824/MAX4825)
♦ Low 300µA (max) Quiescent Supply Current
♦ Space-Saving, 4mm x 4mm, 20-Pin TQFN Package
Ordering Information
PART
TEMP RANGE
PINPACKAGE
PACKAGE
CODE
MAX4822ETP
-40°C to +85°C 20 TQFN-EP*
T2044-3
MAX4823ETP
-40°C to +85°C 20 TQFN-EP*
T2044-3
MAX4824ETP
-40°C to +85°C 20 TQFN-EP*
T2044-3
MAX4825ETP
-40°C to +85°C 20 TQFN-EP*
T2044-3
*For maximum heat dissipation, packages have an exposed
pad (EP) on the bottom. Solder exposed pad to GND.
Applications
ATE Equipment
DSL Redundancy Protection (ADSL/VDSL/HDSL)
Selector Guide
T1/E1 Redundancy Protection
T3/E3 Redundancy Protection
PART
INTERFACE
POWER SAVE
Industrial Equipment
MAX4822
Serial
Yes
Test Equipment (Oscilloscopes, Spectrum
Analyzers)
MAX4823
Serial
No
MAX4824
Parallel
Yes
MAX4825
Parallel
No
SPI is a trademark of Motorola, Inc.
QSPI is a trademark of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
Pin Configurations appear at end of data sheet.
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
MAX4822–MAX4825
General Description
MAX4822–MAX4825
+3.3V/+5V, 8-Channel Relay Drivers with Fast
Recovery Time and Power-Save Mode
ABSOLUTE MAXIMUM RATINGS
VCC ........................................................................-0.3V to +6.0V
OUT_ ......................................................................-0.3V to +11V
CS, SCLK, DIN, SET, RESET, A0, A1, A2, LVL......-0.3V to +6.0V
DOUT..........................................................-0.3V to (VCC + 0.3V)
PSAVE ........................................................-0.3V to (VCC + 0.3V)
Continuous OUT_ Current (all outputs turned on) ............150mA
Continuous OUT_ Current (single output turned on) ........300mA
Continuous Power Dissipation (TA = +70°C)
20-Lead Thin QFN (derate 16.9mW/°C above +70°C) ..1350mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Soldering Temperature (10s) ...........................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = +2.7V to +5.5V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = 2.7V, TA = +25°C, unless otherwise
noted.) (Note 1)
PARAMETER
Operating Voltage
Quiescent Current
Dynamic Supply Current
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
5.5
V
VCC = 3.6V
160
300
VCC = 5.5V
180
300
VCC = 3.6V
1.2
VCC = 5.5V
1.6
VCC
ICC
ID
Thermal Shutdown
Power-On Reset
2.3
IOUT_ = 0,
logic inputs = 0 or VCC
fSCLK =10MHz, CDOUT = 50pF
Power-save disable threshold (Note 2)
+130
Output disable threshold (Note 3)
+150
Transform from high voltage to low voltage
0.6
Power-On Reset Hysteresis
1.2
µA
mA
°C
2.0
140
V
mV
DIGITAL INPUTS (SCLK, DIN, CS, LVL, A0, A1, A2, RESET, SET)
Input Logic-High Voltage
VIH
Input Logic-Low Voltage
VIL
Input Logic Hysteresis
VHYST
Input Leakage Current
ILEAK
Input Capacitance
VCC = 2.7V to 3.6V
2.0
VCC = 4.2V to 5.5V
2.4
V
VCC = 2.7V to 3.6V
0.6
VCC = 4.2V to 5.5V
0.8
150
Input voltages = 0 or 5.5V
-1.0
CIN
+0.01
V
mV
+1.0
5
µA
pF
DIGITAL OUTPUT (DOUT)
DOUT Low Voltage
VOL
ISINK = 6mA
DOUT High Voltage
VOH
ISOURCE = 0.5mA
2
0.4
VCC 0.5
_______________________________________________________________________________________
V
V
+3.3V/+5V, 8-Channel Relay Drivers with Fast
Recovery Time and Power-Save Mode
(VCC = +2.7V to +5.5V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = 2.7V, TA = +25°C, unless otherwise
noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
PS = 001
0.65 x
VCC
0.7 x
.
VCC
0.75 x
VCC
PS = 010
0.55 x
VCC
0.6 x
VCC
0.65 x
VCC
UNITS
RELAY OUTPUT DRIVERS (OUT1–OUT8)
OUT_ Drive Voltage,
Power-Save On
(MAX4822)
OUT_ Drive Voltage,
Power-Save On (MAX4824)
OUT_ On-Resistance
OUT_ Off-Leakage Current
Zener Clamping Voltage
VOUTPS_
VOUTPS_
VCC = 2.7V
(Note 4)
PS = 011
0.45 x
VCC
0.5 x
VCC
0.55 x
VCC
PS = 100
0.35 x
VCC
0.4 x
VCC
0.45 x
VCC
PS = 101
0.25 x
VCC
0.3 x
VCC
0.35 x
VCC
PS = 110
0.15 x
VCC
0.2 x
VCC
0.25 x
VCC
PS = 111
0.05 x
VCC
0.1.x
VCC
0.15 x
VCC
0.35 x
VCC
0.4 x
VCC
0.45 x
VCC
V
2.7
5.0
Ω
+1
µA
9
10.5
V
VCC = 2.7V (Note 4)
RON
VCC = 2.7V, IOUT_ = 70mA
ILEAK
VOUT_ = VCC, all outputs off
-1
IOUT_ = 70mA (Note 5)
7.0
VCLAMP
V
SPI TIMING (MAX4822/MAX4823)
Turn-On Time (OUT_)
tON
From rising edge of CS, RL = 50Ω,
CL = 50pF
1.0
µs
Turn-Off Time (OUT_)
tOFF
From rising edge of CS, RL = 50Ω,
CL = 50pF
3.0
µs
10
MHz
SCLK Frequency
fSCLK
0
tCH + tCL
100
ns
CS Fall-to-SCLK Rise Setup
tCSS
50
ns
CS Rise-to-SCLK Hold
tCSH
50
ns
SCLK High Time
tCH
40
ns
SCLK Low Time
tCL
40
ns
Data Setup Time
tDS
20
ns
Cycle Time
_______________________________________________________________________________________
3
MAX4822–MAX4825
ELECTRICAL CHARACTERISTICS (continued)
MAX4822–MAX4825
+3.3V/+5V, 8-Channel Relay Drivers with Fast
Recovery Time and Power-Save Mode
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +2.7V to +5.5V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = 2.7V, TA = +25°C, unless otherwise
noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
0
UNITS
Data Hold Time
tDH
SCLK Fall to DOUT Valid
tDO
Rise Time (DIN, SCLK, CS, SET,
RESET)
tSCR
Fall Time (DIN, SCLK, CS,
RESET, SET)
tSCF
RESET Minimum Pulse Width
tRW
70
ns
SET Minimum Pulse Width
tSW
70
ns
CS Minimum Pulse Width
tCSW
40
ns
50% of SCLK to (VIH, VIL of DIN),
ns
17
28
ns
20% of VCC to 70% of VCC, CL = 50pF
(Note 6)
2
µs
20% of VCC to 70% of VCC, CL = 50pF
(Note 6)
2
µs
CL = 50pF
PARALLEL TIMING (MAX4824/MAX4825)
Turn-On Time
tON
From rising edge of CS, RL = 50Ω,
CL = 50pF
1
µs
Turn-Off Time
tOFF
From rising edge of CS, RL = 50Ω,
CL = 50pF
3
µs
LVL Setup Time
tLS
20
LVL Hold Time
tLH
0
ns
Address to CS Setup Time
tAS
20
ns
Address to CS Hold Time
tAH
0
ns
Rise Time (A2, A1, A0, LVL)
tSCR
20% of VCC to 70% of VCC, CL = 50pF
(Note 6)
2
µs
Fall Time (A2, A1, A0, LVL)
tSCF
20% of VCC to 70% of VCC, CL = 50pF
(Note 6)
2
µs
RESET Pulse Width
tRW
70
ns
SET Pulse Width
tSW
70
ns
tCSW
40
ns
CS Minimum Pulse Width
ns
POWER-SAVE TIMING (MAX4822/MAX4824)
Power-Save Delay Time
tPS
Minimum PSAVE Low Time to
Power-Save Reset
tPSR
Variation from typical value, CL = 100nF
(Note 7)
1.6
3.2
5.4
ms
2
3.5
ms
Specifications at -40°C are guaranteed by design and not production tested.
Thermal shutdown disables power save from all channels to reduce power dissipation inside the device.
Thermal shutdown turns off all channels.
The circuit can set the output voltage in power-save mode only if IOUT x RON < VOUTP.
After relay turn-off, inductive kickback can momentarily cause the OUT_ voltage to exceed VCC. This is considered part of
normal operation and does not damage the device.
Note 6: Guaranteed by design.
Note 7: For other capacitance values, use the equation tPS = 32 x C.
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
4
_______________________________________________________________________________________
+3.3V/+5V, 8-Channel Relay Drivers with Fast
Recovery Time and Power-Save Mode
160
155
150
170
160
150
140
VCC = 3.3V
130
VCC = 2.3V
120
145
100
2.3
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
-15
10
35
0.60
1
2
3
3.25
3.00
RON (Ω)
600
500
300
6
7
8
9
10
ON-RESISTANCE vs. TEMPERATURE
IOUT-SINK = 70mA
2.75
2.50
VCC = 3.3V
3.5
VCC = 2.3V
3.0
2.5
2.25
VCC = 3.3V
5
4.0
RON (Ω)
VCC = 5.5V
4
FREQUENCY (MHz)
IOUT_SINK = 70mA
800
MAX4822-25 toc03
0.80
85
60
3.50
MAX4822-25 toc04
2.00
2.0
200
1.75
100
VCC = 5.5V
1.50
0
1
2
3
4
2.3
5
2.7
3.1
3.5
3.9
4.3
4.7
5.1
VCC = 5.0V
1.5
5.5
-40
-15
10
35
60
LOGIC-INPUT VOLTAGE (V)
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
POWER-ON RESET VOLTAGE
vs. TEMPERATURE
OUTPUT OFF-LEAKAGE CURRENT
vs. SUPPLY VOLTAGE
OUTPUT OFF-LEAKAGE CURRENT
vs. TEMPERATURE
5
4
3
2
10
85
MAX4822-25 toc09
6
OUTPUT OFF-LEAKAGE (nA)
MAX4822-25 toc07
1.70
1.65
1.60
1.55
1.50
1.45
1.40
1.35
1.30
1.25
1.20
1.15
1.10
1.05
1.00
OUTPUT OFF-LEAKAGE (pA)
0
MAX4822-25 toc08
SUPPLY CURRENT (µA)
900
400
VCC = 3.6V
1.00
ON-RESISTANCE vs. SUPPLY VOLTAGE
ALL LOGIC INPUTS
CONNECTED
700
1.20
TEMPERATURE (°C)
QUIESCENT SUPPLY CURRENT
vs. LOGIC-INPUT VOLTAGE
1000
VCC = 5.5V
1.40
0.20
-40
SUPPLY VOLTAGE (V)
1100
1.60
0.40
110
140
CDOUT = 50pF
1.80
MAX4822-25 toc06
165
VCC = 5.0V
180
2.00
DYNAMIC SUPPLY CURRENT (mA)
170
VCC = 5.5V
190
MAX4822-25 toc05
SUPPLY CURRENT (µA)
175
200
MAX4822-25 toc02
ALL CHANNELS OFF
SUPPLY CURRENT (µA)
MAX4822-25 toc01
180
POWER-ON RESET VOLTAGE (V)
DYNAMIC SUPPLY CURRENT
vs. FREQUENCY
QUIESCENT SUPPLY CURRENT
vs. TEMPERATURE
QUIESCENT SUPPLY CURRENT
vs. SUPPLY VOLTAGE
1
2.3V, 3.3V, 5.0V, AND 5.5V
0.1
0.01
1
0
-40
-15
10
35
TEMPERATURE (°C)
60
85
0.001
2.3
2.7
3.1
3.5
3.9
4.3
SUPPLY VOLTAGE (V)
4.7
5.1
5.5
-40
-15
10
35
60
85
TEMPERATURE (°C)
_______________________________________________________________________________________
5
MAX4822–MAX4825
Typical Operating Characteristics
(VCC = 3.3V, TA = +25°C, unless otherwise noted.)
Typical Operating Characteristics (continued)
(VCC = 3.3V, TA = +25°C, unless otherwise noted.)
INPUT-LOGIC THRESHOLD
vs. SUPPLY VOLTAGE
OUT_ TURN-OFF DELAY TIME
vs. SUPPLY VOLTAGE
100
80
60
2.1
2.0
1200
1000
800
40
600
20
400
MAX4822-25 toc12
1400
IOFF DELAY TIME (ns)
120
1600
INPUT-LOGIC THRESHOLD (V)
140
MAX4822-25 toc11
MAX4822-25 toc10
OUT_ TURN-ON DELAY TIME
vs. SUPPLY VOLTAGE
ION DELAY TIME (ns)
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
1.0
2.3
2.7
3.1
SUPPLY VOLTAGE (V)
3.5
3.9
4.3
4.7
5.1
2.3
5.5
2.7
3.1
SUPPLY VOLTAGE (V)
3.5
BACK EMF CLAMPING WITH
STANDARD 3V RELAY VCC = 3.3V
4.3
POWER-SAVE DELAY TIME
vs. CAPACITANCE
MAX4822-25 toc13
40
VCC = 3.3V
35
CS
5V/div
0V
3.9
SUPPLY VOLTAGE (V)
MAX4822-25 toc14
2.3
30
tPS (ms)
25
20
15
VOUT
2V/div
10
0V
5
0
100µs/div
0
200
400
600
800
1000
CAPACITANCE (nF)
OUTPUT VOLTAGE vs. OUTPUT CURRENT
IN POWER-SAVE MODE
(PSAVE REGISTER = 111)
POWER-SAVE DELAY TIME
vs. SUPPLY VOLTAGE
0.7
OUTPUT VOLTAGE (V)
3.90
3.85
3.80
3.75
3.70
3.65
3.60
MAX4822 toc16
CPSAVE = 0.1µF
3.95
0.8
MAX4822-25 toc15
4.00
tPS (ms)
MAX4822–MAX4825
+3.3V/+5V, 8-Channel Relay Drivers with Fast
Recovery Time and Power-Save Mode
0.6
0.5
0.4
3.55
3.50
0.3
2.3
2.7
3.1
3.5
3.9
4.3
SUPPLY VOLTAGE (V)
6
4.7
5.1
5.5
0
50
100
150
200
250
OUTPUT CURRENT (mA)
_______________________________________________________________________________________
300
4.7
5.1
5.5
+3.3V/+5V, 8-Channel Relay Drivers with Fast
Recovery Time and Power-Save Mode
PIN
NAME
FUNCTION
MAX4822
MAX4823
1
1
RESET
Reset Input. Drive RESET low to clear all latches and registers (all outputs are high
impedance). RESET overrides all other inputs. If RESET and SET are pulled low at the
same time, then RESET takes precedence.
2
2
CS
Chip-Select Input. Drive CS low to select the device. When CS is low, data at DIN is
clocked into the shift register on SCLK’s rising edge. Drive CS from low to high to latch
the data to the registers and activate the relay outputs.
3
3
DIN
Serial Data Input
4
4
SCLK
Serial Clock Input
DOUT
Serial Data Output. DOUT is the output of the shift register. DOUT can be used to daisychain multiple MAX4822/MAX4823 devices. The data at DOUT appears synchronous to
SCLK’s falling edge.
5
5
6
6, 13
N.C.
No Connection. Not internally connected.
7
7
GND
Ground
8
8
OUT8
Open-Drain Output 8. Connect OUT8 to the low side of a relay coil. This output is pulled
to PGND when activated, but otherwise is high impedance.
9
9
OUT7
Open-Drain Output 7. Connect OUT7 to the low side of a relay coil. This output is pulled
to PGND when activated, but otherwise is high impedance.
10, 16
10, 16
PGND
Power Ground. PGND is a return for the output sinks. Connect PGND pins together and
to GND.
11
11
OUT6
Open-Drain Output 6. Connect OUT6 to the low side of a relay coil. This output is pulled
to PGND when activated, but otherwise is high impedance.
12
12
OUT5
Open-Drain Output 5. Connect OUT5 to the low side of a relay coil. This output is pulled
to PGND when activated, but otherwise is high impedance.
13
—
PSAVE
Power-Save Control. Connect a timing capacitor from PSAVE to ground. The capacitor
value determines power-save timing as explained under the Applications Information
section. PSAVE can also be driven externally to control power-save mode
asynchronously. When asserted high, PSAVE reduces the current to all active outputs as
determined by the Power-Save Configuration Register (see Figure 1). To disable powersave mode in all channels, drive PSAVE low for at least 3ms after the last output setting.
14
14
OUT4
Open-Drain Output 4. Connect OUT4 to the low side of a relay coil. This output is pulled
to PGND when activated, but otherwise is high impedance.
15
15
OUT3
Open-Drain Output 3. Connect OUT3 to the low side of a relay coil. This output is pulled
to PGND when activated, but otherwise is high impedance.
17
17
OUT2
Open-Drain Output 2. Connect OUT2 to the low side of a relay coil. This output is pulled
to PGND when activated, but otherwise is high impedance.
18
18
OUT1
Open-Drain Output 1. Connect OUT1 to the low side of a relay coil. This output is pulled
to PGND when activated, but otherwise is high impedance.
_______________________________________________________________________________________
7
MAX4822–MAX4825
MAX4822/MAX4823 Pin Description
+3.3V/+5V, 8-Channel Relay Drivers with Fast
Recovery Time and Power-Save Mode
MAX4822–MAX4825
MAX4822/MAX4823 Pin Description (continued)
PIN
NAME
FUNCTION
MAX4822
MAX4823
19
19
VCC
Input Supply Voltage. Bypass VCC to GND with a 0.1µF capacitor.
20
20
SET
Set Input. Drive SET low to set all latches and registers high (all outputs are low
impedance). SET overrides all parallel and serial control inputs. RESET overrides SET
under all conditions.
EP
EP
EP
Exposed Pad. Connect exposed paddle to GND.
MAX4824/MAX4825 Pin Description
PIN
8
NAME
FUNCTION
MAX4824
MAX4825
1
1
RESET
Reset Input. Drive RESET low to clear all latches and registers (all outputs are high
impedance). RESET overrides all other inputs. If RESET and SET are pulled low at the
same time, then RESET takes precedence.
2
2
CS
Chip-Select Input. Drive CS low to select the device. The CS falling edge latches the
output address (A0, A1, A2). The CS rising edge latches level data (LVL).
3
3
LVL
Level Input. LVL determines whether the selected address is switched on or off. Logichigh on LVL switches on the addressed output. A logic-low on LVL switches off the
addressed output.
4
4
A0
Digital Address 0 Input. (See Figure 3 for address mapping.)
5
5
A1
Digital Address 1 Input. (See Figure 3 for address mapping.)
6
6
A2
Digital Address 2 Input. (See Figure 3 for address mapping.)
7
7
GND
Ground
8
8
OUT8
Open-Drain Output 8. Connect OUT8 to the low side of a relay coil. This output is pulled
to PGND when activated, but otherwise is high impedance.
9
9
OUT7
Open-Drain Output 7. Connect OUT7 to the low side of a relay coil. This output is pulled
to PGND when activated, but otherwise is high impedance.
10, 16
10, 16
PGND
Power Ground. PGND is a return for the output sinks. Connect PGND pins together and
to GND.
11
11
OUT6
Open-Drain Output 6. Connect OUT6 to the low side of a relay coil. This output is pulled
to PGND when activated, but otherwise is high impedance.
12
12
OUT5
Open-Drain Output 5. Connect OUT5 to the low side of a relay coil. This output is pulled
to PGND when activated, but otherwise is high impedance.
_______________________________________________________________________________________
+3.3V/+5V, 8-Channel Relay Drivers with Fast
Recovery Time and Power-Save Mode
PIN
MAX4824
MAX4825
NAME
FUNCTION
13
—
PSAVE
Power-Save Control. Connect a timing capacitor from PSAVE to ground. The capacitor
value determines power-save timing as explained under the Applications Information
section. PSAVE can also be driven externally to control power-save mode
asynchronously. When PSAVE is asserted high, the current through the coils is reduced
to 60% of the initial nominal current value. To disable power-save mode in all channels,
drive PSAVE low for at least 3ms after last output setting.
14
14
OUT4
Open-Drain Output 4. Connect OUT4 to the low side of a relay coil. This output is pulled
to PGND when activated, but otherwise is high impedance.
15
15
OUT3
Open-Drain Output 3. Connect OUT3 to the low side of a relay coil. This output is pulled
to PGND when activated, but otherwise is high impedance.
17
17
OUT2
Open-Drain Output 2. Connect OUT2 to the low side of a relay coil. This output is pulled
to PGND when activated, but otherwise is high impedance.
18
18
OUT1
Open-Drain Output 1. Connect OUT1 to the low side of a relay coil. This output is pulled
to PGND when activated, but otherwise is high impedance.
19
19
VCC
Input Supply Voltage. Bypass VCC to GND with a 0.1µF capacitor.
20
20
SET
Set Input. Drive SET low to set all latches and registers high (all outputs are low
impedance). SET overrides all parallel and serial control inputs. RESET overrides SET
under all conditions.
—
13
N.C.
EP
EP
EP
No Connection. Not internally connected.
Exposed Pad. Connect exposed paddle to ground.
Detailed Description
Serial Interface (MAX4822/MAX4823)
Depending on the MAX4822/MAX4823 device, the serial
interface can be controlled by either 8- or 16-bit words
as depicted in Figures 1 and 2. The MAX4823 does not
support power-save mode, so the serial interface consists of an 8-bit-only shift register for faster control.
The MAX4822 consists of a 16-bit shift register and parallel latch controlled by SCLK and CS. The input to the
shift register is a 16-bit word. In the MAX4822, the first
8 bits determine the register address and are followed
by 8 bits of data as depicted in Figure 1. Bit A7 corresponds to the MSB of the 8-bit register address in
Figure 1, while bit D7 corresponds to the MSB of the 8
bits of data in the same Figure 1.
The MAX4823 consists of an 8-bit shift register and parallel latch controlled by SCLK and CS. The input to the
shift register is an 8-bit word. Each data bit controls
one of the eight outputs, with the most significant bit
(D7) corresponding to OUT8, and the least significant
bit (D0) corresponding to OUT1 (see Figure 2).
_______________________________________________________________________________________
9
MAX4822–MAX4825
MAX4824/MAX4825 Pin Description (continued)
MAX4822–MAX4825
+3.3V/+5V, 8-Channel Relay Drivers with Fast
Recovery Time and Power-Save Mode
ADDRESS [A7...A0]
ACTIVE REGISTER
00h
Output Control Register—OUTR
01h
P o we r - S a ve C o n fig u r a tio n
Re gist e r —P S
Serial-Input Address Map
D7
D6
D5
D4
D3
D2
D1
D0
OUT8
OUT7
OUT6
OUT5
OUT4
OUT3
OUT2
OUT1
MSB
LSB
Output Control Register—OUTR (Address = 00h)
Note: Setting DN to logic 1 turns on output OUTN+1. Setting DN to logic 0, turns off OUTN+1. Example: Setting D2 = 1 turns on OUT3.
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
X
PS0
PS1
PS2
MSB
Power-Save Configuration Register—PS (Address= 01h)
LSB
PS0
PS1
PS2
0
0
0
Power-save is disabled (Default Operation)
POWER-SAVE CONFIGURATION
0
0
1
Power-save is enabled. VOUT set to 70% of VCC, typical after tPS ms (see Note 1), causes
IOUT_ to be reduced to approximately 30%, typical after tPS ms.
0
1
0
Power-save is enabled. VOUT set to 60% of VCC, typical after tPS ms (see Note 1), causes
IOUT_ to be reduced to approximately 40%, typical after tPS ms.
0
1
1
Power-save is enabled. VOUT set to 50% of VCC, typical after tPS ms (see Note 1), causes
IOUT_ to be reduced to approximately 50%, typical after tPS ms.
1
0
0
Power-save is enabled. VOUT set to 40% of VCC, typical after tPS ms (see Note 1), causes
IOUT_ to be reduced to approximately 60%, typical after tPS ms.
1
0
1
Power-save is enabled. VOUT set to 30% of VCC, typical after tPS ms (see Note 1), causes
IOUT_ to be reduced to approximately 70%, typical after tPS ms.
1
1
0
Power-save is enabled. VOUT set to 20% of VCC, typical after tPS ms (see Note 1), causes
IOUT_ to be reduced to approximately 80%, typical after tPS ms.
1
1
1
Power-save is enabled. VOUT set to 10% of VCC, typical after tPS ms (see Note 1), causes
IOUT_ to be reduced to approximately 90%, typical after tPS ms.
Power-Save Configuration Options
Note 1: The time period tPS is determined by the capacitor connected to PSAVE.
Figure 1. 16-Bit Register Map for MAX4822
When CS is low (MAX4822/MAX4823 device is selected), data at DIN is clocked into the shift register synchronously with SCLK’s rising edge. Driving CS from
low to high latches the data in the shift register (Figures
5 and 6).
10
DOUT is the output of the shift register. Data appears
on DOUT synchronously with SCLK’s falling edge and
is identical to the data at DIN delayed by eight clock
cycles for the MAX4823, or 16 clock cycles for the
MAX4822. When shifting the input data, A7 is the first
input bit in and out of the shift register for the MAX4822
device. D7 is the first bit in or out of the shift register for
______________________________________________________________________________________
+3.3V/+5V, 8-Channel Relay Drivers with Fast
Recovery Time and Power-Save Mode
LSB
A2
A1
A0
OUTPUT
D7
D6
D5
D4
D3
D2
D1
D0
Low
Low
Low
OUT1
OUT8
OUT7
OUT6
OUT5
OUT4
OUT3
OUT2
OUT1
Low
Low
High
OUT2
Low
High
Low
OUT3
Low
High
High
OUT4
High
Low
Low
OUT5
High
Low
High
OUT6
High
High
Low
OUT7
High
High
High
OUT8
Note: Setting DN to logic 1 turns on output OUTN+1. Setting
DN to logic 0 turns off output OUTN+1.
Example: Setting the D2 = 1 turns OUT3 on.
Figure 2. 8-Bit Register Map for MAX4823
MAX4822–MAX4825
MSB
Figure 3. Register Address Map for MAX4824/MAX4825
CS
tCSW
tCL
tCSS
tCSH
tCH
SCLK
tDH
tDS
DIN
D7
D6
D0
D1
tDO
DOUT
tON,
tOFF
OUT_
Figure 4. 3-Wire Serial-Interface Timing Diagram
the MAX4823 device. If the address A0…….A7 is not
00h or 01h, then the outputs and the PSAVE configuration register are not updated. The address is stored in
the shift register only.
While CS is low, the OUT_ outputs always remain in their
previous state. For the MAX4823, drive CS high after 8
bits of data have been shifted in to update the output
state of the MAX4823, and to further inhibit data from
entering the shift register. For the MAX4822, drive CS high
after 16 bits of data have been shifted in to update the
output state of the MAX4822, and to further inhibit data
from entering the shift register. When CS is high, transitions at DIN and SCLK have no effect on the output, and
the first input bit A7 (or D7) is present at DOUT.
For the MAX4822, if the number of data bits entered
while CS is low is greater or less than 16, the shift register contains only the last 16 bits, regardless of when
they were entered. For the MAX4823, if the number of
data bits entered while CS is low is greater or less than
8, the shift register contains only the last 8 data bits,
regardless of when they were entered.
Parallel Interface (MAX4824/MAX4825)
The parallel interface consists of 3 address bits (A0,
A1, A2) and one level selector bit (LVL). The address
bits determine which output is updated, and the level
bit determines whether the addressed output is
switched on (LVL = high) or off (LVL = low). When CS is
high, the address and level bits have no effect on the
state of the outputs. Driving CS from low to high latches
______________________________________________________________________________________
11
MAX4822–MAX4825
+3.3V/+5V, 8-Channel Relay Drivers with Fast
Recovery Time and Power-Save Mode
CS
SCLK
DIN
A7
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
Figure 5. 3-Wire Serial-Interface Operation for MAX4822
level data to the parallel register and updates the state
of the outputs. Address data entered after CS is pulled
low is not reflected in the state of the outputs following
the next low-to-high transition on CS (Figure 7).
SET/RESET Functions
The MAX4822–MAX4825 feature set and reset inputs
that allow simultaneous turn-on or turn-off of all outputs
using a single control line. Drive SET low to set all latches and registers to 1 and turn all outputs on. SET overrides all serial/parallel control inputs. Drive RESET low
to clear all latches and registers and to turn all outputs
off. RESET overrides all other inputs including SET.
Power-On Reset
The MAX4822–MAX4825 feature power-on reset. The
power-on reset function causes all latches to be
cleared automatically upon power-up. This ensures that
all outputs come up in the off or high-impedance state.
Applications Information
Daisy Chaining
The MAX4822/MAX4823 feature a digital output
(DOUT) that provides a simple way to daisy chain multiple devices. This feature allows driving large banks of
relays using only a single serial interface. To daisy
chain multiple devices, connect all CS inputs together,
and connect the DOUT of one device to the DIN of
another device (see Figure 8). During operation, a
stream of serial data is shifted through the MAX4822/
MAX4823 devices in series. When CS goes high, all
outputs update simultaneously.
The MAX4822/MAX4823 can also be used in a slave
configuration that allows individual addressing of
devices. Connect all the DIN inputs together, and use
12
the CS input to address one device at a time. Drive CS
low to select a slave and input the data into the shift
register. Drive CS high to latch the data and turn on the
appropriate outputs. Typically, in this configuration only
one slave is addressed at a time.
Power-Save Mode
The MAX4822/MAX4824 feature a unique power-save
mode where the relay current, after activation, can be
reduced to a level just above the relay hold-current
threshold. This mode keeps the relay activated while
significantly reducing the power consumption.
In serial mode (MAX4822), choose between seven current levels ranging from 30% to 90% of the nominal current in 10% increments. The actual percentage is
determined by the power-save configuration register
(Figure 1).
In parallel mode (MAX4824), the power-save current is
fixed at 60% of the nominal current.
Power-Save Timer
Every time there is a write operation to the device (CS
transitions from low to high), the MAX4822/MAX4824
start charging the capacitor connected to PSAVE. The
serial power-save implementation is such that a write
operation does not change the state of channels
already in power-save mode (unless the write turns the
channel OFF).
After a certain time period, t PS (determined by the
capacitor value), the capacitor reaches a voltage
threshold that sets all active outputs to power-save
mode. The tPS period should be made long enough to
allow the relay to turn on completely. The time period
tPS can be adjusted by using different capacitor values
______________________________________________________________________________________
+3.3V/+5V, 8-Channel Relay Drivers with Fast
Recovery Time and Power-Save Mode
For example, if the desired t PS is 20ms, then the
required capacitor value is 20 / 32 = 0.625µF.
Power-Save Mode Accuracy
The current through the relay is controlled by setting
the voltage at OUT_ to a percentage of the VCC supply
as specified under the Electrical Characteristics and in
the register description. The current through the relay
(IOUT) depends on the switch on-resistance, RON, in
addition to the relay resistance RR according to the following relation:
IOUT = VCC / (RON + RR)
The power-save, current-setting I PS depends on the
fraction α of the supply voltage VCC that is set by the
loop depending on the following relation:
IPS = VCC - (α x VCC) / RR
CS
SCLK
DIN
D7
D6
D5
D4
D3
D2
D1
Daisy Chaining and Power-Save Mode
In a normal configuration using the power-save feature,
several MAX4822s can be daisy chained as shown in
Figure 9. For each MAX4822, the power-save timing
tPD (time it takes to reduce the relay current once the
relay is actuated) is controlled by the capacitor connected to PSAVE.
An alternative configuration that eliminates the PSAVE
capacitors uses a common PSAVE control line driven by
an open-drain n-channel MOSFET (Figure 10). In this configuration, the PSAVE inputs are connected together to
asynchronously control the power-save timing for all the
MAX4822s in the chain. The µC/µP drives the n-channel
MOSFET low for the duration of a write cycle to the SPI
chain, plus some delay time to allow the relays to close.
D0
Figure 6. 3-Wire Serial-Interface Operation for the MAX4823
CS
tAS
tAH
A_
Therefore:
IPS / IOUT = (1- α) x (1 + RON / RR)
This relation shows how the fraction of reduction in the
current depends on the switch on-resistance, as well as
from the accuracy of the voltage setting (α). The higher
the RON with respect to RR, the higher the inaccuracy.
This is particularly true at low voltage when the relay
resistance is low (less than 40Ω) and the switch can
account for up to 10% of the total resistance. In addition, when the supply-voltage setting (α) is low (10% or
20%) and the supply voltage (VCC) is low, the voltage
drop across the switch (I OUT x R ON ) may already
exceed, or may be very close to, the desired voltagesetting value.
MAX4822–MAX4825
connected to PSAVE. The value tPS is given by the following formula:
tPS = 32 x C
where C is in µF and tPS is in ms.
tLH
tLS
LVL
tON,
tOFF
VOUT
Figure 7. Parallel-Interface Timing Diagram
(This time is typically specified in the relay data sheet.)
Once this delay time has elapsed, the n-channel MOSFET
is turned off, allowing the MAX4822’s internal 35µA pullup
current to raise PSAVE to a logic-high level, activating the
power-save mode in all active outputs.
MOSFET Selection
In the daisy-chain configuration of Figure 10, the n-channel
MOSFET drives PSAVE low. When the n-channel
MOSFET is turned off, PSAVE is pulled high by an internal
35µA pullup in each MAX4822, and the power-save mode
is enabled. Because of the paralleled PSAVE pullup
currents, the required size of the n-channel MOSFET
depends upon the number of MAX4822 devices in the
chain. Determine the size of the n-channel MOSFET by the
following relation:
RON < 1428 / N
______________________________________________________________________________________
13
MAX4822–MAX4825
+3.3V/+5V, 8-Channel Relay Drivers with Fast
Recovery Time and Power-Save Mode
VCC
VCC
0.1µF
VCC
DIN
DIN
MAX4823 OUT1
SCLK
SCLK
CS
GND
DOUT
DIN
DOUT
MAX4823 OUT1
SCLK
OUT8
PGND
SCLK
MAX4823 OUT1
SCLK
OUT8
GND
CS
0.1µF
VCC
VCC
DOUT
DIN
VCC
0.1µF
SCLK
CS
PGND
OUT8
GND
PGND
CS
Figure 8. Daisy-Chain Configuration
VCC
VCC
0.1µF
VCC
DIN
DIN
DIN
CS
DOUT
DIN
MAX4822 OUT1
PSAVE
OUT8
GND
PGND
0.47µF
SCLK
CS
OUT8
GND
PGND
DOUT
MAX4822 OUT1
PSAVE
SCLK
0.1µF
VCC
VCC
DOUT
MAX4822 OUT1
0.47µF
VCC
0.1µF
0.47µF
PSAVE
SCLK
CS
OUT8
GND
PGND
SCLK
CS
Figure 9. Daisy-Chained MAX4822s with a Capacitor Connected to PSAVE
where N is the total number of MAX4822 devices in a
single chain, and R ON is the on-resistance of the
n-channel MOSFET in Ωs.
For example, if N = 10:
RON < 142Ω
An n-channel MOSFET with R ON less than 142Ω is
required for a daisy chain of 10 MAX4822 devices.
14
Inductive Kickback Protection with
Fast Recovery Time
The MAX4822–MAX4825 feature built-in inductive kickback protection to reduce the voltage spike on OUT_
generated by a relay’s coil inductance when the output
is suddenly switched off. An internal Zener clamp
allows the inductor current to flow back to ground. The
Zener configuration significantly reduces the recovery
time (time it takes to turn off the relay) when compared
to protection configurations with just one diode across
the coil.
______________________________________________________________________________________
+3.3V/+5V, 8-Channel Relay Drivers with Fast
Recovery Time and Power-Save Mode
VCC
0.1µF
VCC
DIN
DIN
DOUT
MAX4822 OUT1
PSAVE
OUT8
VCC
CS
N
GND
PGND
DIN
MAX4822 OUT1
PSAVE
SCLK
SCLK
CS
OUT8
GND
0.1µF
VCC
VCC
DOUT
DIN
VCC
0.1µF
MAX4822–MAX4825
VCC
DOUT
MAX4822 OUT1
PSAVE
SCLK
CS
PGND
OUT8
GND
PGND
SCLK
CS
Figure 10. Daisy-Chaining MAX4822s with a PSAVE Connected to an n-Channel MOSFET
Chip Information
TRANSISTOR COUNT: 5799
PROCESS: BiCMOS
______________________________________________________________________________________
15
+3.3V/+5V, 8-Channel Relay Drivers with Fast
Recovery Time and Power-Save Mode
MAX4822–MAX4825
MAX4822/MAX4823 Functional Diagram (Serial Interface)
OUT1
VCC
MAX4822
MAX4823
OUT2
POWERON
RESET
OUT3
PSAVE
POWER-SAVE
CONFIGURATION
REGISTER
RESET
OUT5
OUT6
SET
DIN
SHIFT
REGISTER
DOUT
SCLK
ON1
CONTROL ON2
REGISTER
ON3
ON4
ON5
ON6
ON7
ON8
CS
PSAVE
POWER
SAVE
GND
PGND
MAX4822 ONLY
16
OUT4
______________________________________________________________________________________
OUT7
OUT8
+3.3V/+5V, 8-Channel Relay Drivers with Fast
Recovery Time and Power-Save Mode
OUT1
VCC
OUT2
OUT3
MAX4824
MAX4825
PSAVEON/OFF
OUT4
RESET
OUT5
SET
OUT6
LVL
A2
4-TO-8
DECODER
A1
A0
ON1
CONTROL ON2
REGISTER
ON3
ON4
ON5
ON6
ON7
ON8
OUT7
OUT8
CS
PSAVE
POWER
SAVE
GND
PGND
MAX4824 ONLY
______________________________________________________________________________________
17
MAX4822–MAX4825
MAX4824/MAX4825 Functional Diagram (Parallel Interface)
+3.3V/+5V, 8-Channel Relay Drivers with Fast
Recovery Time and Power-Save Mode
MAX4822–MAX4825
Pin Configurations
SET
VCC
OUT1
OUT2
PGND
18
17
16
PGND
16
19
OUT2
17
20
OUT1
OUT3
14
OUT4
14
OUT4
13
PSAVE
DIN
3
13
N.C.
4
12
OUT5
SCLK
4
12
OUT5
5
11
OUT6
DOUT
5
11
OUT6
10
PGND
9
8
OUT8
OUT7
7
6
N.C.
OUT1
OUT2
PGND
18
17
16
PGND
16
VCC
OUT2
17
19
OUT1
18
SET
VCC
20
SET
19
RESET
1
15
OUT3
RESET
1
15
OUT3
CS
2
14
OUT4
CS
2
14
OUT4
LVL
3
13
PSAVE
LVL
3
13
N.C.
A0
4
12
OUT5
A0
4
12
OUT5
5
11
OUT6
5
11
OUT6
8
9
10
OUT7
PGND
6
A2
OUT8
10
PGND
7
9
OUT7
THIN QFN
GND
8
OUT8
A1
MAX4825
7
A2
6
MAX4824
GND
A1
18
THIN QFN
20
THIN QFN
GND
10
N.C.
MAX4823
PGND
MAX4822
9
DOUT
18
15
2
OUT7
SCLK
VCC
1
CS
8
3
SET
RESET
OUT8
DIN
19
OUT3
15
7
2
6
1
CS
GND
RESET
20
TOP VIEW
THIN QFN
______________________________________________________________________________________
+3.3V/+5V, 8-Channel Relay Drivers with Fast
Recovery Time and Power-Save Mode
24L QFN THIN.EPS
PACKAGE OUTLINE,
12, 16, 20, 24, 28L THIN QFN, 4x4x0.8mm
21-0139
E
1
2
PACKAGE OUTLINE,
12, 16, 20, 24, 28L THIN QFN, 4x4x0.8mm
21-0139
E
2
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 19
© 2005 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products, Inc.
MAX4822–MAX4825
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
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