Cypress CY2DP3120AIT 1:20 differential clock/data fanout buffer Datasheet

FastEdge™ Series
CY2DP3120
1:20 Differential Clock/Data Fanout Buffer
Features
Functional Description
The CY2DP3120 is a low-skew, low propagation delay 1-to-20
differential fanout buffer targeted to meet the requirements of
high-performance clock and data distribution applications. The
device is implemented on SiGe technology and has a fully
differential internal architecture that is optimized to achieve
low signal skews at operating frequencies of up to 1.5 GHz.
• Twenty ECL/PECL differential outputs
• One ECL/PECL compatible differential or single-ended
clock inputs
• One HSTL compatible differential or single-ended clock
inputs
The device features two differential input paths that are multiplexed internally. This mux is controlled by the CLK_SEL pin.
The CY2DP3120 may function not only as a differential clock
buffer but also as a signal-level translator and fanout on
ECL/PECL signal to twenty ECL/PECL differential loads. An
external bias pin, VBB, is provided for this purpose. In such an
application, the VBB pin should be connected to either one of
the CLKA# or CLKB# inputs and bypassed to ground via a
0.01-µF capacitor. Traditionally, in ECL, it is used to provide
the reference level to a receiving single-ended input that might
have a different self-bias point.
• Hot-swappable/-insertable
• 50 ps output-to-output skew
• 150 ps device-to-device skew
• 500 ps propagation delay (typical)
• 1.4 ps RMS period jitter (max.)
• 1.5 GHz Operation (2.7 GHz max. toggle frequency)
• PECL mode supply range: VCC = 2.5V± 5% to 3.3V±5%
with VEE = 0V
Since the CY2DP3120 introduces negligible jitter to the timing
budget, it is the ideal choice for distributing high frequency,
high precision clocks across back-planes and boards in
communication systems. Furthermore, advanced circuit
design schemes, such as internal temperature compensation,
ensure that the CY2DP3120 delivers consistent performance
over various platforms.
• ECL mode supply range: VE E = –2.5V± 5% to –3.3V±5%
with VCC = 0V
• Industrial temperature range: –40°C to 85°C
• 52-pin 1.4-mm TQFP package
• Temperature compensation like 100K ECL
• Pin compatible with MC100ES6221
VCC
CLK_SEL
VCC
Q5#
Q5
Q4#
Q4
Q3#
Q3
Q8
VBB
6
34
Q8#
CLKB
7
33
Q9
CLKB#
8
32
Q9#
VEE
Q19#
9
31
Q10
10
30
Q10#
Q19
11
29
Q11
Q18#
12
28
Q11#
•
San Jose, CA 95134
VCC
Q12
Q12#
Q13
Q13#
Q14
VCC
VEE
13
27
14 15 16 17 18 19 20 21 22 23 24 25 26
Q14#
Q18
CY2DP3120
Q15
CLK_SEL
3901 North First Street
Q2#
35
VEE
•
Q2
5
VBB
Cypress Semiconductor Corporation
Document #: 38-07514 Rev.*C
Q1#
Q7#
CLKA#
Q15#
Q 19
Q 19#
CLKB
CLKB#
Q7
36
Q16
VCC
Q6#
4
Q16#
VEE
Q6
CLKA
Q17
Q0
Q 0#
52 51 50 49 48 47 46 45 44 43 42 41 40
39
1
38
2
37
3
Q17#
CLKA
CLKA#
Q1
Q0
VCC
VCC
Q0#
Pin Configuration
Block Diagram
•
408-943-2600
Revised July 28, 2004
FastEdge™ Series
CY2DP3120
Pin Definitions[1, 2, 3]
Pin
Name
I/O
Type
Description
3
CLK_SEL I,PD
ECL/PECL/HSTL Input clock select
4
CLKA,
I,PD
ECL/PECL
Differential input clocks
6
VBB[3]
O
Bias
Reference voltage output
5
CLKA#
I,PD/PU ECL/PECL
Differential input clocks
7
CLKB,
I,PD
HSTL
Alternate differential input clocks
8
CLKB#
I,PD/PU HSTL
Alternate differential input clocks
9
VEE[2]
-PWR
Power
Negative supply
1,2,14,27,40
VCC
+PWR
Power
Positive Supply
O
ECL/PECL
True output
51,49,47,45,43,41,38,36, Q#(0:19) O
34,32,30,28,25,23,21,19,
17,15,12,10
ECL/PECL
Complement output
52,50,48,46,44,42,39,37, Q(0:19)
35,33,31,29,26,24,22,20,
18,16,13,11
Table 1.
Control
Operation
CLK_SEL
0
CLKA, CLKA# input pair is active (Default condition with no connection to pin)
CLKA can be driven with ECL- or PECL-compatible signals with respective power configurations
1
CLKB, CLKB# input pair is active.
CLKB can be driven with HSTL-compatible signals with respective power configurations
Governing Agencies
The following agencies provide specifications that apply to the
CY2DP3120. The agency name and relevant specification is
listed below in Table 2.
Table 2.
Agency Name
Specification
JEDEC
JESD 020B (MSL)
JESD 51 (Theta JA)
JESD 8–2 (ECL)
JESD 65–B (skew,jitter)
Mil-Spec
883E Method 1012.1 (Thermal Theta JC)
Notes:
1. In the I/O column, the following notation is used: I for Input, O for Output, PD for Pull-Down, PU for Pull-Up, and PWR for Power
2. In ECL mode (negative power supply mode), VEE is either –3.3V or –2.5V and VCC is connected to GND (0V). In PECL mode (positive power supply mode),
VEE is connected to GND (0V) and VCC is either +3.3V or +2.5V. In both modes, the input and output levels are referenced to the most positive supply (VCC)
and are between VCC and VEE.
3. VBB is available for use for single-ended bias mode for |3.3V| supplies (not |2.5V|).
Document #: 38-07514 Rev.*C
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FastEdge™ Series
CY2DP3120
Absolute Maximum Ratings
Parameter
Description
Condition
Min.
Max.
Unit
VCC
Positive Supply Voltage
Non-Functional
–0.3
4.6
V
VEE
Negative Supply Voltage
Non-Functional
-4.6
0.3
V
TS
Temperature, Storage
Non-Functional
–65
+150
°C
TJ
Temperature, Junction
Non-Functional
150
°C
ESDh
ESD Protection
Human Body Model
MSL
Moisture Sensitivity Level
Gate Count Total Number of Used Gates
2000
V
3
N.A.
50
gates
Assembled Die
Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
Operating Conditions
Parameter
Description
Condition
Min.
Max.
Unit
IBB
Output Reference Current
Relative to VBB
LUI
Latch Up Immunity
Functional, typical
TA
Temperature, Operating Ambient
Functional
ØJc
Dissipation, Junction to Case
Functional
22[4]
ØJa
Dissipation, Junction to Ambient
Functional
60[4]
IEE
Maximum Quiescent Supply Current
VEE pin
CIN
Input pin capacitance
3
pF
LIN
Pin Inductance
1
nH
VIN
Input Voltage
Relative to VCC[6]
VTT
Output Termination Voltage
Relative to VCC[6]
VOUT
Output Voltage
IIN
Input Current (ECL,PECL and
uA
mA
–40
+85
°C
°C/W
°C/W
250[5]
Relative to VCC[6]
HSTL)[7]
|200|
100
–0.3
mA
VCC + 0.3
V
VCC – 2
–0.3
V
VCC + 0.3
V
l150l
uA
Min.
Max.
Unit
2.375
3.135
2.625
3.465
V
V
1.2
VCC
V
0.68
0.9
V
VCC – 1.25
VCC – 0.7
V
VCC – 1.995
VCC –1.995
VCC – 1.5
VCC – 1.3
V
V
VIN = VIL, or VIN = VIH
PECL/HSTL DC Electrical Specifications
Parameter
Description
Condition
VCC
Operating Voltage
2.5V ± 5%, VEE = 0.0V
3.3V ± 5%, VEE = 0.0V
VCMR
PECL Input Differential Crosspoint
Voltage[8]
Differential operation
VX
HSTL Input Differential Crosspoint Volt- Standard Load Differential
age[9]
Operation
VOH
Output High Voltage
IOH = –30 mA[10]
VOL
Output Low Voltage
VCC = 3.3V ± 5%
VCC = 2.5V ± 5%
IOL = –5 mA[10]
VIH
Input Voltage, High
Single-ended operation
VCC – 1.165
VCC – 0.880 [11]
V
VIL
Input Voltage, Low
Single-ended operation
VCC – 1.945 [11]
VCC – 1.625
V
VBB[3]
Output Reference Voltage
Relative to VCC[6]
VCC – 1.620
VCC – 1.220
V
Notes:
4. Theta JA EIA JEDEC 51 test board conditions (typical value); Theta JC 883E Method 1012.1
5. Power Calculation: VCC * IEE +0.5 (IOH + IOL) (VOH – VOL) (number of differential outputs used); IEE does not include current going off chip.
6. where VCC is 3.3V±5% or 2.5V±5%
7. Inputs have internal pull-up/pull-down or biasing resistors which affect the input current.
8. Refer to Figure 1
9. VX(AC) is the crosspoint of the differential HSTL input signal. Normal AC operation is obtained when the crosspoint is within the VX(AC) range and the input
swing lies within the VDIF(AC) specification. Violation of VX(AC) or VDIF(AC) impacts the device propagation delay, device and part-to-part skew. Refer to Fig. 2.
10. Equivalent to a termination of 50Ω to VTT. IOHMIN=(VOHMIN-VTT)/50; IOHMAX=(VOHMAX-VTT)/50; IOLMIN=(VOLMIN-VTT)/50; IOLMAX=(VOLMAX-VTT)/50;
11. VIL will operate down to VEE; VIH will operate up to VCC
Document #: 38-07514 Rev.*C
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FastEdge™ Series
CY2DP3120
ECL DC Electrical Specifications
Parameter
Description
Condition
Min.
Max.
Unit
–2.625
–3.465
–2.375
–3.135
V
VEE + 1.2
0V
V
–1.25
–0.7
V
–1.995
–1.995
–1.5
–1.3
V
VEE
Negative Power Supply
–2.5V ± 5%, VCC = 0.0V
–3.3V ± 5%, VCC = 0.0V
VCMR
ECL Input Differential cross point
voltage[8]
Differential operation
VOH
Output High Voltage
IOH = –30 mA[10]
VOL
Output Low Voltage
VEE = –3.3V ± 5%
VEE = –2.5V ± 5%
IOL = –5 mA[10]
VIH
Input Voltage, High
Single-ended operation
–1.165
–0.880 [11]
V
VIL
Input Voltage, Low
Single-ended operation
–1.945 [11]
–1.625
V
VBB[3]
Output Reference Voltage
– 1.620
– 1.220
V
Min.
Max.
Unit
0.1
1.3
V
AC Electrical Specifications
Parameter
Description
Condition
VPP
ECL/PECL Differential Input Voltage[8] Differential operation
FCLK
Input Frequency
50% duty cycle Standard load
1.5
GHz
TPD
Propagation Delay CLKA or CLKB to
Output pair
660 MHz [13]
400
750
ps
VDIF
HSTL Differential Input Voltage[12]
Duty Cycle Standard Load
Differential Operation
0.4
1.9
V
Vo
Output Voltage (peak-to-peak; see
Figure 3)
< 1 GHz
0.375
–
V
VCMRO
Output Common Voltage Range
(typical)
tsk(0)
Output-to-output Skew
VCC – 1.425
660 MHz [13], See Figure 3
–
50
ps
[13]
–
150
ps
–
1.4
ps
–
50
ps
0.08
0.3
ns
tsk(PP)
Part-to-Part Output Skew
660 MHz
TPER
Output Period Jitter (rms)[14]
660 MHz [13]
Skew[]
tsk(P)
Output Pulse
TR,TF
Output Rise/Fall Time (see Figure 3)
660 MHz
V
[13],
See Figure 3
660 MHz 50% duty cycle
Differential 20% to 80%
Notes:
12. VDIF (AC) is the minimum differential HSTL input voltage swing required to maintain AC characteristics including tkpd and device-to-device skew
13. 50% duty cycle; standard load; differential operation
14. For 3.3V supplies. Jitter measured differentially using an Agilent 8133A Pulse Generator with an 8500A LeCroy Wavemaster Oscilloscope using at least 10,000
data points
Output pulse skew is the absolute difference of the propagation delay times: | tPLH – tPHL |.
Document #: 38-07514 Rev.*C
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FastEdge™ Series
CY2DP3120
Timing Definitions
VCC
VCM R M ax = VCC
V IH
VPP
V P P ra n g e
0 .1 V - 1 .3 V
VCM R
V IL
V C M R M in = V E E + 1 . 2
VEE
Figure 1. PECL/ECL Input Waveform Definitions
VCC
V C C = 3 .3 V
V X m a x = 0 .9 V
V IH
V D IF
V D IF = > =
0 .4 V m in
VX
V IL
V X M in = 0 .6 8
V E E = 0 .0 V
VEE
Figure 2. HSTL Differential Input Waveform Definitions
tr, tf,
2 0 -8 0 %
VO
Figure 3. ECL/LVPECL Output
In p u t
C lo c k
V P P
T P L H ,
T P D
T P H L
O u tp u t
C lo c k
V O
tS K (O )
A n o th e r
O u tp u t
C lo c k
Figure 4. Propagation Delay (TPD), output pulse skew (|tPLH-tPHL|), and output-to-output skew (tSK(O))
for both CLKA or CLKB to Output Pair, PECL/ECL to PECL/ECL
Document #: 38-07514 Rev.*C
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FastEdge™ Series
CY2DP3120
Test Configuration
Standard test load using a differential pulse generator and
differential measurement instrument.
VTT
VTT
RT = 50 ohm
RT = 50 ohm
5"
P u ls e
G e n e ra to r
Z = 50 ohm
Zo = 50 ohm
Zo = 50 ohm
5"
RT = 50 ohm
DUT
C Y2D P3120
RT = 50 ohm
VTT
VTT
Figure 5. CY2DP3120 AC Test Reference
Applications Information
Termination Examples
CY2DP3120
VTT
VCC
RT = 50 ohm
5"
Zo = 50 ohm
5"
RT = 50 ohm
VTT
VEE
Figure 6. Standard LVPECL – PECL Output Termination
CY2DP3120
VTT
RT = 50 ohm
VCC
5"
Zo = 50 ohm
5"
VTT
R T = 50 ohm
V B B (3 .3 V )
VEE
Figure 7. Driving a PECL/ECL Single-ended Input
Document #: 38-07514 Rev.*C
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FastEdge™ Series
CY2DP3120
CY2DP3120
3 .3 V
V C C = 3 .3 V
120 ohm
LVDS
5"
Zo = 50 ohm
33 ohm
( 2 p la c e s )
5"
120 ohm
3 .3 V
51 ohm
( 2 p la c e s )
L V P E C L to
LVDS
VEE = 0V
Figure 8. Low-voltage Positive Emitter-coupled Logic (LVPECL) to a Low-voltage Differential Signaling (LVDS) Interface
VDD-2
VCC
X
Y
Z
One output is shown for clarity
Figure 9. Termination for LVPECL to HTSL interface for VCC=2.5V would use X=50 Ohms, Y=2300 Ohms, and Z=1000
Ohms. See application note titled, “PECL Translation, SAW Oscillators, and Specs” for other signalling standards and
supplies.
Ordering Information
Part Number
Package Type
Product Flow
CY2DP3120AI
52-pin TQFP
Industrial, –40° to 85°C
CY2DP3120AIT
52-pin TQFP – Tape and Reel
Industrial, –40° to 85°C
CY2DP3120AXI
52-pin TQFP - Lead Free
Industrial, –40° to 85°C
CY2DP3120AXIT
52-pin TQFP – Tape and Reel - Lead Free
Industrial, –40° to 85°C
Document #: 38-07514 Rev.*C
Page 7 of 9
FastEdge™ Series
CY2DP3120
Package Diagram
52-lead Thin Plastic Quad Flat Pack (10 × 10 × 1.4 mm) A52
51-85131-**
FastEdge is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document
are the trademarks of their respective holders.
Document #: 38-07514 Rev.*C
Page 8 of 9
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
FastEdge™ Series
CY2DP3120
Document History Page
Document Title: CY2DP3120 FastEdge™ Series 1:20 Differential Clock/Data Fanout Buffer
Document Number: 38-07514
REV.
ECN NO.
Issue Date
Orig. of
Change
Description of Change
**
122438
12/05/02
RGL
New data sheet
*A
125457
04/17/03
RGL
Corrected typo Q14 to Q4 in pin 44 in the pin configuration diagram
Changed pin #s 1,14,27 and 40 from VCC to VCCO
Changed title to FastEdge™ Series 1:20 Differential Clock/Data Fanout
Buffer
*B
229391
See ECN
RGL
Supplied data to all TBD’s to match the device
*C
247606
See ECN
Document #: 38-07514 Rev.*C
RGL/GGK Changed VOH and VOL to match the Char Data
Page 9 of 9
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