STMicroelectronics ESDAVLC6-1V2 Single line low capacitance transilâ ¢ for esd protection Datasheet

ESDAVLC6-1V2
Single line low capacitance Transil™ for ESD protection
Datasheet − production data
Description
The ESDAVLC6-1V2 is a single line unidirectional
Transil diode designed specially for the protection
of integrated circuits into portable equipment and
miniaturized electronics devices subject to ESD
transient overvoltage.
The device is ideal for applications where both
reduced printed circuit board space and high ESD
protection level are required.
ST01005
ESDAVLC6-1V2
Complies with following standards:
• IEC 61000-4-2 level 4:
– ±8 kV contact discharge
– ±15 kV air discharge
Features
• Ultra small PCB area = 0.09 mm²
• Unidirectional device
Figure 1. Functional diagram
• Very low diode capacitance
• Low leakage current
• RoHS compliant
Pin1
Applications
Where transient over voltage protection in ESD
sensitive equipment is required, such as:
• Smart phones and accessories
Pin 2
• Portable multimedia devices and accessories
• Tablets
TM: Transil is a trademark of STMicroelectronics
June 2014
This is information on a product in full production.
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Characteristics
1
ESDAVLC6-1V2
Characteristics
Table 1. Absolute maximum ratings (Tamb = 25 °C)
Symbol
Value
Unit
±8
±15
kV
Operating temperature range
-40 to +125
°C
Tstg
Storage temperature range
- 55 to +150
°C
TL
Maximum lead temperature for soldering during 10 s
260
°C
VPP
Tj
Parameter
IEC 61000-4-2 contact discharge
IEC 61000-4-2 air discharge
Peak pulse voltage
Figure 2. Electrical characteristics (definitions)
I
IF
Symbol
VBR
VRM
VCL
IRM
IPP
=
=
=
=
=
RD
=
CLINE
=
Parameter
Breakdown voltage
Stand-off voltage
Clamping voltage
Leakage current @ VRM
Peak pulse current
Dynamic resistance
Line capacitance
VF
VCL VBR
VRM
V
IRM
Slope: 1/Rd
IPP
Table 2. Electrical characteristics (values, Tamb = 25 °C)
Value
Symbol
Parameter
Min.
2/8
Unit
Test conditions
VBR
Breakdown voltage
IR = 1 mA
IRM
Leakage current
VRM = 3 V
Cline
Line capacitance, I/O to GND VR = 0 V, F = 1 MHz, Vosc = 30 mV
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Typ.
Max.
6
V
5
50
nA
7
pF
ESDAVLC6-1V2
Characteristics
Figure 3. ESD response to IEC 61000-4-2
(typical values, +8 kV contact discharge)
Figure 4. ESD response to IEC 61000-4-2
(typical values, -8 kV contact discharge)
20 V/div
20 V/div
88 V
1
2
3
4
1
VPP: ESD peak voltage
VCL :clamping voltage @ 30 ns
VCL :clamping voltage @ 60 ns
VCL :clamping voltage @ 100 ns
-6 V
55 V
2
32 V
-33 V
3
18 V
4
-73 V
2
-18 V
4
3
1
1
2
3
4
20 ns/div
VPP: ESD peak voltage
VCL :clamping voltage @ 30 ns
VCL :clamping voltage @ 60 ns
VCL :clamping voltage @ 100 ns
20 ns/div
Figure 5. S21 attenuation measurement
L
0
S21 (dB)
-3
-6
-9
-12
-15
-18
-21
10M
F (Hz)
30M
100M
300M
1G
3G
10G
ESDAVLC6 -1V2
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Package information
2
ESDAVLC6-1V2
Package information
•
Epoxy meets UL94, V0
•
Lead-free package
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
205 µm ± 20
Figure 6. Package dimensions
25 µm ± 10
75 µm
50 µm
75 µm
200 µm
450 µm ± 20
50 µm
200 µm ± 20
50 µm
50 µm
Figure 7. Footprint recommendation
A
B
H
I
F
J
E
D
C
G
A = 225 µm
B = 225 µm
C = 50 µm E = 180 µm G = 530 µm I = 112.5 µm
D = 180 µm F = 100 µm H = 40 µm
J = 270 µm
Solder pad
PCB opening
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ESDAVLC6-1V2
Recommendation on PCB assembly
3
Recommendation on PCB assembly
3.1
Stencil opening design
Stencil opening thickness: 80 µm
Figure 8. Recommended stencil window position
K
M
N
L
K = 180 µm
L = 180 µm
M = 150 µm N = 30 µm
Solder pad
PCBopening
Stencil aperture (thickness stencil: 80 µm)
3.2
Solder paste
1.
Use halide-free flux, qualification ROL0 according to ANSI/J-STD-004.
2.
“No clean” solder paste recommended.
3.
Offers a high tack force to resist component displacement during PCB movement.
4.
Solder paste with fine particles: type 4 (powder particle size 20-38 µm per IPC J-STD005).
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Recommendation on PCB assembly
3.3
3.4
3.5
ESDAVLC6-1V2
Placement
1.
Manual positioning is not recommended.
2.
It is recommended to use the lead recognition capabilities of the placement system, not
the outline centering.
3.
Tolerance of ± 0.02 mm is recommended.
4.
1.0 N placement force is recommended. Too much placement force can lead to
squeezed out solder paste and cause solder joints to short. Too low placement force
can lead to insufficient contact between package and solder paste that could cause
open solder joints or badly centered packages.
5.
To improve the package placement accuracy, a bottom side optical control should be
performed with a high resolution tool.
6.
For assembly, a perfect supporting of the PCB (all the more on flexible PCB) is
recommended during solder paste printing, pick and place and reflow soldering by
using optimized tools.
PCB design preference
1.
To control the solder paste amount, the closed via is recommended instead of open
vias.
2.
The position of tracks and open vias in the solder area should be well balanced. The
symmetrical layout is recommended, in case any tilt phenomena caused by
asymmetrical solder paste amount due to the solder flow away.
Reflow profile
Figure 9. ST ECOPACK® recommended soldering reflow profile for PCB mounting
240-245 °C
Temperature (°C)
250
-2 °C/s
2 - 3 °C/s
60 sec
(90 max)
200
-3 °C/s
150
-6 °C/s
100
0.9 °C/s
50
Time (s)
0
Note:
6/8
30
60
90
120
150
180
210
240
270
300
Minimize air convection currents in the reflow oven to avoid component movement.
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4
Ordering information
Ordering information
Figure 10. Ordering information scheme
ESDA VLC 6 - 1 V2
ESD array
Very low capacitance
Breakdown voltage
6 = 6 V min.
Directional
1 = Unidirectional
Package
V = ST01005 package
2 = 2 pads
Table 3. Ordering information
5
Order code
Marking
Weight
Base qty
Delivery mode
ESDAVLC6-1V2
L
0.041 mg
20 000
Tape and reel
Revision history
Table 4. Document revision history
Date
Revision
05-Jun-2014
1
Changes
First issue
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ESDAVLC6-1V2
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