FTDI FT51CS-U Advanced microcontroller with 8051 compatible core Datasheet

FT51A Advanced MCU with 8051 Compatible Core IC Datasheet
Version 1.5
D oc ument N o.: FT _000877
C learance N o.: FT DI#420
Future Technology Devices
International Ltd.
FT51A
(Advanced Microcontroller with 8051
Compatible Core)
The FT51A is a multi-featured device that can be
targeted at a wide range of functions or
applications:

Supports DMA operation

I2C Master & Slave functionality

SPI Master & Slave functionality

Industry compatible 8051 core running at a
maximum frequency of 48MHz.

245 FIFO module provides a simple FIFO interface
to transmit and receive data

8 KB of data memory

Timer and Watchdog

16 KB of multi-time programmable (MTP) memory

Up to 16 dedicated digital IO pins

16 KB of shadow memory for fast read access by
the core.

Up to 16 multiplexed analogue / digital IO pins

USB 2.0 Full Speed hub controller allowing
cascading of multiple FT51A devices

Support ADC function on analogue IO pins


USB 2.0 Full Speed device controller compatible to
FT12 series
IO Mux control for maximum flexibility in pin
selection


Supports up to 8 bi-directional endpoints with 2 x
1 KB USB endpoint buffers
Configurable IO pin output drive strength; 4 mA
(min) and 16 mA (max)

+5V Single Supply Operation

Max packet size is 504 bytes for USB isochronous
endpoint and 64 bytes for control / bulk / interrupt
endpoint

Internal 3.3V/1.8V voltage regulators

Integrated power-on-reset circuit

Low operating and suspend current; 20 mA
(active) and 150 uA (suspend)

Extended operating temperature range; -40 to
85⁰C

Available in compact Pb-free, RoHS compliant
packages:

Double buffer scheme for any endpoint, increases
data transfer throughput

Fully integrated clock generation with no external
crystal required

Data transfer rates from 300 baud to 3M baud
(RS422, RS485, and RS232) at TTL levels

PWM Controller

UART interface support for 7 or 8 data bits, 1 or 2
stop bits and odd / even / mark / space / no parity

USB Battery Charger Detection allowing optimized
charging profile
•
48-pin WQFN
•
44-pin LQFP
•
32-pin WQFN
•
28-pin SSOP
N either the whole nor any part of the information c ontained in, or the produc t des c ribed in this manual, may be adapted or re produc ed in any
material or elec tronic form without the prior written c ons ent of the c opyright holder. T his product and its doc umentation are s up plied on an as-is
bas is and no warranty as to their s uitability for any partic ular purpose is either made or implied. Future T ec hno logy D evic es I nternational L td
will not ac c ept any c laim for damages hows oever aris ing as a res ult of us e or failure of this produc t. Y our s tatutory rights are not affec ted. T his
produc t or any variant of it is not intended for us e in any medic al applianc e , devic e or s ys tem in whic h the failure of the produc t might
reas onably be expected to res ult in pers onal injury. T his doc ument provides preliminary information that may be s ubjec t to c h ange without
notic e. N o freedom to us e patents or other intellectual p roperty rights is implied by the public ation of this doc ument. Future T echnology D evices
I nternational L td, U nit 1 , 2 Seaward P lace, C enturion Business P ark, G lasgow G 4 1 1 HH U nited Kingdom. Sc otland Registered Company N umber:
SC 1 3 6 6 4 0
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FT51A Advanced MCU with 8051 Compatible Core IC Datasheet
Version 1.5
D oc ument N o.: FT _000877
C learance N o.: FT DI#420
1 Typical Applications

USB Data Acquisition

General Purpose Microcontroller

Sensor and Monitoring control

Mass storage data transfers across all
segments, including medical, industrial datalogger, power-metering, and test
instrumentation

USB to RS232/RS422/RS485 Converters

Incorporate USB interface to enable PC
transfers for development systems

Interfacing MCU/PLD/FPGA based designs to
add USB connectivity

Industrial equipment control systems

POS systems

USB Bar Code Readers

Internet of things application

Home automation control systems
1.1 Part Numbers
Part Number
Package
FT51AQ-R
48 Pin QFN, body 7x7x0.75 mm, pitch 0.5mm, Taped and Reel, 3000 per reel
FT51AQ-T
48 Pin QFN, body 7x7x0.75 mm, pitch 0.5mm, Tray packing, 490 per tray
FT51AL-R
44 Pin LQFP, body 10x10x1.4 mm, pitch 0.8mm, Taped and Reel, 1000 per reel
FT51AL-T
44 Pin LQFP, body 10x10x1.4 mm, pitch 0.8mm, Tray packing, 160 per tray
FT51BQ-R
32 Pin QFN, body 6x6x0.75 mm, pitch 0.5mm, Taped and Reel, 3000 per reel
FT51BQ-T
32 Pin QFN, body 6x6x0.75 mm, pitch 0.5mm, Tray packing, 490 per tray
FT51CS-R
28 Pin SSOP, body 10.2x5.3x1.75 mm, pitch 0.65mm, Taped and Reel, 2000 per reel
FT51CS-U
28 Pin SSOP, body 10.2x5.3x1.75 mm, pitch 0.65mm, Tube packing, 47 per tube
Table 1-1 – Part Numbers
1.2 USB Compliant
The FT51A is fully compliant with the USB 2.0 specification and has been given the USB-IF Test-ID (TID)
40001701 (Rev C).
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FT51A Advanced MCU with 8051 Compatible Core IC Datasheet
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D oc ument N o.: FT _000877
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Table of Contents
1
Typical Applications...................................................... 2
1.1
Part Numbers ......................................................................... 2
1.2
USB Compliant ........................................................................ 2
2
Device Pin Out and Signal Description ........................... 5
2.1
Pin Out - 28 pin SSOP ............................................................. 5
2.2
Pin Out - 32 pin WQFN ........................................................... 6
2.3
Pin Out - 44-Pin LQFP............................................................. 7
2.4
Pin Out - 48-Pin WQFN ............................................................ 8
2.5
Pin Configuration Description .................................................. 9
3
Functional Description ................................................ 11
3.1
Key Features..........................................................................11
3.1.1
Functional Integration ............................................................................. 11
3.1.2
8051 Core ............................................................................................. 11
3.2
Functional Block Descriptions .................................................12
3.2.1
8051 Ports 0 - 3 ..................................................................................... 12
3.2.2
Timers and Watchdog.............................................................................. 12
3.2.3
PLL Control............................................................................................ 13
3.2.4
16KB Multi-Time Programmable (MTP) memory ........................................... 13
3.2.5
8KB Data RAM ....................................................................................... 13
3.2.6
16KB Shadow RAM ................................................................................. 13
3.2.7
Special Function Register ......................................................................... 13
3.2.8
IO Registers .......................................................................................... 13
3.2.9
LDO Regulators ...................................................................................... 13
3.2.10
BCD Detect ........................................................................................... 13
3.2.11
USB XCVR ............................................................................................. 14
3.2.12
IO Multiplexer ........................................................................................ 14
3.2.13
I2 C Master............................................................................................. 14
3.2.14
I2 C Slave .............................................................................................. 15
3.2.15
SPI Slave .............................................................................................. 15
3.2.16
SPI Master ............................................................................................ 15
3.2.17
Debugger .............................................................................................. 15
3.2.18
245 FIF O .............................................................................................. 16
3.2.19
PWM .................................................................................................... 16
3.2.20
Digital IO pins ........................................................................................ 16
3.2.21
Analogue IO pins .................................................................................... 16
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FT51A Advanced MCU with 8051 Compatible Core IC Datasheet
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3.2.22
4
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ADC ..................................................................................................... 16
Device Characteristics and Ratings.............................. 18
4.1
Absolute Maximum Ratings ....................................................18
4.2
DC Characteristics..................................................................19
4.3
MTP Memory Reliability Characteristics...................................23
4.4
Internal Clock Characteristics.................................................23
4.5
Digital IO AC Characteristics ..................................................24
4.6
Analogue IO Characteristics ...................................................25
5
USB Power Configurations .......................................... 26
5.1
6
USB Bus Powered Configuration .............................................26
Connection Examples.................................................. 27
6.1 USB Upstream and downstream port connections (48pin
package) .......................................................................................27
6.2 USB Upstream and downstream port connections (44pin
package) .......................................................................................28
6.3
USB Upstream port connections (32pin package) ....................28
6.4
USB Upstream port connections (28pin package) ....................29
7
Package Parameters ................................................... 30
7.1
48-Pin WQFN Package Outline ................................................30
7.2
44-Pin LQFP Package Outline .................................................31
7.3
32-Pin WQFN Package Outline ................................................32
7.4
28-Pin SSOP Package Outline .................................................33
7.5
Solder Reflow Profile .............................................................34
8
Contact Information ................................................... 35
Appendix A – References ................................................. 36
Document References ....................................................................36
Acronyms and Abbreviations ..........................................................36
Appendix B - List of Figures and Tables ............................ 37
List of Figures................................................................................37
List of Tables .................................................................................37
Appendix C – List of IO registers ...................................... 39
Appendix D – Revision History ......................................... 43
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FT51A Advanced MCU with 8051 Compatible Core IC Datasheet
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2 Device Pin Out and Signal Description
FT51A is available in 4 packages: 28 pin SSOP, 32 pin WQFN, 44 pin LQFP and 48 pin WQFN .
DEBUGGER
15
GND
AIO10
AIO11
AIO14
AIO15
UP_DP
UP_DM
AIO7
AIO6
AIO5
AIO4
VCC5V
28
VOUT3V3
2.1 Pin Out - 28 pin SSOP
DIO15
DIO14
DIO13
DIO12
DIO11
DIO10
DIO9
GND
DIO8
RST
DIO3
DIO2
DIO1
DIO0
1
14
FTDI
XXXXXXXXXXXX
FT51CS
YYWW-X
Figure 2-1 - 28 Pin SSOP Package
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FT51A Advanced MCU with 8051 Compatible Core IC Datasheet
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DIO8
5
DIO9
6
DIO10
DIO11
DIO3
DIO2
DIO1
DIO0
VOUT3V3
VCC5V
AIO4
25
4
26
RST
27
3
28
DIO7
29
2
30
DIO6
31
1
32
DIO5
DIO4
2.2 Pin Out - 32 pin WQFN
24
AIO5
23
AIO6
22
AIO7
21
UP_DM
20
UP_DP
19
AIO15
7
18
AIO14
8
17
AIO11
FTDI
9
10
11
12
13
14
15
16
DIO12
DIO13
DIO14
DIO15
DEBUGGER
GND
GND
AIO10
XXXXXXXXXX
FT51BQ
YYWW-X
Figure 2-2 - 32 Pin WQFN Package
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FT51A Advanced MCU with 8051 Compatible Core IC Datasheet
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DIO3
DIO2
DIO1
DIO0
VOUT3V3
VCC5V
AIO0
AIO1
AIO2
AIO3
20
21
22
AIO12
16
19
15
17
14
18
12
13
AIO11
11
AIO10
DIO13
AIO9
10
AIO8
DIO12
GND
9
GND
DIO11
GND
8
DEBUGGER
DIO10
XXXXXXXXXX
FT51AL
YYWW-X
DIO15
7
FTDI
DIO14
DIO9
34
6
35
VCCIO
36
5
37
DIO8
38
4
39
RST
40
3
41
DIO7
42
2
43
1
DIO6
44
DIO5
DIO4
2.3 Pin Out - 44-Pin LQFP
33
AIO4
32
AIO5
31
AIO6
30
AIO7
29
UP_DM
28
UP_DP
27
DW_DM
26
DW_DP
25
AIO15
24
AIO14
23
AIO13
Figure 2-3 - 44 Pin LQFP Package
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FT51A Advanced MCU with 8051 Compatible Core IC Datasheet
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AIO1
AIO2
AIO3
VOUT3V3
AIO0
VREF
VCC5V
DIO0
GND
DIO1
37
DIO2
38
40
39
41
43
42
44
47
46
48
45
DIO3
2.4 Pin Out - 48-Pin WQFN
DIO4 1
36
DIO5 2
35
AIO5
34
AIO6
33
AIO7
32
UP_DM
31
UP_DP
FTDI
DIO6 3
DIO7 4
XXXXXXXXXX
FT51AQ
YYWW-X
RST 5
DIO8 6
VCCIO 7
GND 8
AIO4
30
DW_DM
29
DW_DP
AIO9
AIO10
AIO11
AIO12
DIO14
24
DIO13
23
19
22
18
20
17
21
15
14
16
13
AIO8
25 AIO13
GND
26 AIO14
DIO12 12
GND
DIO11 11
GND
AIO15
DEBUGGER
GND
27
DIO9 9
DIO15
28
DIO10 10
Figure 2-4 - 48 Pin WQFN Package
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FT51A Advanced MCU with 8051 Compatible Core IC Datasheet
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2.5 Pin Configuration Description
Pin Nos.
48 pin
44 pin
32 pin
28 pin
42
38
26
27
7
6
-
-
Name
Type
Description
**
POWER
Input
5 V (or 3.3 V) supply to IC
VCC5V
VCCIO
**
43
39
27
28
VOUT3V
3
8, 17, 18,
19, 28,
41, 49*
15,16,
17
14,15,
33*
7, 16
GND
POWER
Input
1.8V – 3.3V supply for the IO
pins. This option is ONLY
available on the 44 & 48 pin
packages. A fixed 3.3V supply
from the internal regulator is
supplied to the IO pins for
the 28 and 32 pin packages
POWER
Output
3.3V regulator output. May be
used to power VCCIO pin.
Note that a 100nF capacitor
should be connected to
VOUT3V3 for proper
operation. This output can
also be used to power
external circuitry up to a
maximum current rating of
50mA (typ).
POWER
Input
Ground
Table 2-1 – Power and Ground
* Pin 49 of WQFN48 or pin 33 of WQFN32 is the exposed centre pad under the packaged IC. Connect to
GND.
** If VCC5V is supplied by 3.3V then VOUT3V3 must also be driven by the same 3.3V source.
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Pin Nos.
Name
Type
Description
INPUT/
Downstream USB Data
Signal Minus.
48 pin
44 pin
32 pin
28 pin
30
27
-
-
DW_DM
29
26
-
-
DW_DP
32
29
21
22
UP_DM
31
28
20
21
UP_DP
5
4
4
5
RST
INPUT
Device Reset. Active
HIGH
44
-
-
-
VREF
INPUT
Reference voltage.
Connect to VOUT3V3.
16
14
13
15
DEBUGG
ER
INPUT/
1,2,3,
4,
P1.0_
P1.7
6,8,9,
10,11
P3.0_
P3.7
(DIO0_D
IO15)
1,2,3,4,6,
9,10,11,12
13,14,15
45,46,47,48
20,21,22,23
24,25,26,27
33,34,35,36
37,38,39,40
1,2,3,5,7,8
9,10,11
12,13,
40,41,42
43,44
18,19,20,21
22,23,24,25
30,31,32,33
34,35,36,37
1,2,3
5,6,7
8,9,10
11,12,
28,29,30
31,32
16,17,181
9,22,23
24,25
12,13
,14
17,18
,19
20,23
,24
25,26
P0.0_
P0.7
P2.0_
P2.7
(AIO0_A
IO15)
OUTPUT
INPUT/
OUTPUT
INPUT/
OUTPUT
INPUT/
OUTPUT
OUTPUT
INPUT/
OUTPUT
INPUT/
OUTPUT
Downstream USB Data
Signal Plus.
Upstream USB Data
Signal Minus.
Upstream USB Data
Signal Plus.
Chip Debug Port
General Purpose
digital IO pins. Weak
internal pull up
enabled on exit from
POR or hardware
reset.
ADC analogue input
pins. Can also be used
as digital IO pins.
AIO0 – AIO7 have no
pull ups when using
44 or 48 pin packages.
Table 2-2 – Common Function pins
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3 Functional Description
Figure 3-1 – FT51A Block Diagram
The FT51A acts as a USB hub supporting two downstream ports; the internal 8051 core and other
peripherals (SPI, UART, etc.) and an external downstream port (typical devices can be a mouse,
keyboard, mass storage device, etc.). The hub can optionally be disabled (under register control)
resulting in the 8051 core appearing at the upstream port.
3.1
3.1.1
Key Features
Functional Integration
Fully integrated MTP memory with built in shadow RAM for fast memory access , internally generated
clock, Power-On-Reset (POR) and LDO regulators.
3.1.2
8051 Core
The FT51A is based around the industry standard 8051 microcontroller capable of running at a maximum
frequency of 48MHz. The core is an ultra-high performance, speed optimized single -chip 8-bit embedded
controller dedicated for operation with fast on-chip memories.
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On-chip Debugger
The 8051 works with a high‐performance “Hardware Assisted Debugger” which manages the
communication between the core and the software.
3.1.2.2
UART / FTDI UART
There are two UARTs in the system – one designed by FTDI and the second incorporated within the 8051
core. The 8051 UART has a maximum baud rate of up to 60kbps. The FTDI UART gives speeds up to
3Mbps.
When the data and control bus are configured in UART mode, the interface implements a standard
asynchronous serial UART port with full modem control. The UART can support baud rates from 183 baud
to 3 Mbaud. The maximum UART speed is limited by the CPU clock. The following maximum UART speed
applies:
3.2
CPU Frequency
Maximum UART Speed
48 MHz
3 Mbaud
24 MHz
3 Mbaud
12 MHz
1.5 Mbaud
Functional Block Descriptions
The following paragraphs detail each function within the FT51A. Please refer to the block diagram shown
in Figure 3-1 – FT51A Block Diagram.
3.2.1
8051 Ports 0 - 3
The 8051 core has four 8-bit bidirectional ports: P0, P1, P2 and P3. These ports can be fully or partially
mapped to external pins on the AIO and DIO bus. Firmware can change the pin mapping through IOMUX
programming. Table 3-1 shows the default pin mapping for all the 4 ports on the LQFP44 and WQFN48
packages.
PIN
TYPE
DESCRIPTION
AIO7 - AIO0
Input / output
P0.7 – P0.0
AIO15 - AIO8
Input / output
P2.7 – P2.0
DIO7 - DIO0
Input / output
P1.7 – P1.0
DIO15 - DIO8
Input / output
P3.7 – P3.0
Table 3-1 – 8051 Ports
3.2.2
Timers and Watchdog
Apart from standard 8051 timers the FT51A has four general purpose 16-bit timers A, B, C and D. A 32bit watchdog timer is also provided.
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PLL Control
The block provides an internally generated 48MHz clock to the system without the need of an external
reference clock. This block is trimmed at factory test to 48MHz. During USB transactions the PLL will
provide an accurate clock, locked to the incoming USB data rate.
3.2.4
16KB Multi-Time Programmable (MTP) memory
16K bytes of MTP memory are available for firmware programming. Code stored with the MTP memory is
copied to the Shadow RAM on power up or an external reset. See section 3.2.6.
3.2.5
8KB Data RAM
8K bytes of data RAM are provided.
3.2.6
16KB Shadow RAM
To facilitate fast program memory access, limit any bottlenecks and to allow fast programming times in a
debug environment, a shadow RAM exists that the CPU will run from. The Shadow RAM has the following
features:


The contents of the MTP are copied to the shadow RAM after a system reset – i.e. a POR reset or
a pin reset.
A single command (register write access) initiates a hard copy of the program memo ry – i.e. the
contents of the shadow RAM are copied to the MTP.
3.2.7
Special Function Register
The 8051 core has a special function register area (SFR) and is limited to 128 locations. This area
facilitates access to IO registers and the USB Full-Speed Device Controller command/data through indirect addressing method.
3.2.8
IO Registers
The FT51A contains approximately 300 IO registers. See Appendix C for a full list of the IO registers.
3.2.9
LDO Regulators
The +3.3V LDO regulator generates the +3.3V re ference voltage for driving the USB transceiver cell
output buffers. It requires an external decoupling capacitor to be attached to the regulator output pin.
The main function of the LDO is to power the USB Transceiver and the Reset Generator Cells rather than
to power external logic. However, it can be used to supply external circuitry requiring a +3.3V nominal
supply with a maximum current of 50mA.
The +1.8V LDO regulator generates the +1.8V supply voltage for internal digital circuits.
3.2.10
BCD Detect
Special circuitry inside the FT51A detects when the USB upstream port is connected to a dedicated
charging port. When it detects that it is connected to a dedicated charging port, the FT51A can use a DIO
or AIO pin to notify a microcontroller or logic on the application board which in turn controls the battery
charging circuits.
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USB XCVR
The USB Transceiver Cell provides the USB 2.0 full-speed physical interface to the USB cable. The output
drivers provide +3.3V level slew rate control signalling, whilst a differential input receiver and two single
ended input receivers provide USB data in, Single -Ended-0 (SE0) and USB reset detection conditions
respectfully. This function also incorporates a 1.5kΩ pull up resistor on the USBUPDP pin.
3.2.12
IO Multiplexer
With the addition of the IO multiplexer any function can be configured to any DIO pin, excluding the
analogue ADC function which is constrained to the AIO pins. All other digital functionality is
recommended to map to DIO pins. The IO multiplexer allows the designer to select which peripherals are
connected to which IO pins. In order to assign a signal to a particular pin, two register writes are
required, one to select the signal and the other to select the IO pin. The FT51A Programmer’s Guide
details the pins and signals which can be connected.
The selectable peripheral interfaces are only limited by the number of IO pins available. The number of
IOs available is dependent on the package type.
Table 3-2 lists the peripherals which can be multiplexed to IO and the typical number of pins required for
each one. The designer can choose any mix of peripheral configurations as long as they are within the
specific package IO pin count.
Peripherals
Number of pins required
(typical)
UART (FTDI)
4
UART (8051)
2
ADC
1-16
8051 Port 0-3
32
SPI Master
4
SPI Slave
4
245 FIFO
12
I2C Master
2
I2C Slave
2
PWM
1-8
Table 3-2 – Peripheral Pin Requirements
3.2.13
I2C Master
The FT51A provides an interface between the core and an I2C bus. It can be programmed to operate with
arbitration and clock synchronization allowing it to operate in multi‐master systems. I2C Master supports
transmission speeds up to 3.4 Mb/s including Normal, Fast and High Speed modes .
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3.2.14
C learance N o.: FT DI#420
I2C Slave
The FT51A provides an interface between the core and an I2C bus. It can work as a slave receiver or
transmitter depending on the working mode determined by the core. The core incorporates all features
required by the I2C specification. The Slave supports all the transmission modes: Standard, Fa st, Fast‐
plus and High Speed. Clock stretching is supported.
3.2.15
SPI Slave
The Serial Peripheral Interface Bus is an industry standard communications interface. Devices
communicate in Master / Slave mode, with the Master initiating the data transfer.
The SPI slave module has four signals – clock, slave select, MOSI (master out – slave in) and MISO
(master in – slave out).
3.2.16
SPI Master
CLK
SS#
SPI Master
MOSI
External - SPI Slave
MISO
Figure 3-2 – SPI Master
The SPI Master interface is used to interface to applications such as SD Cards.
The main purpose of the SPI Master block is to transfer data between an external SPI interface and the
FT51A. It does this under the control of the CPU and DMA engine via the o n-chip IO bus.
The SPI master module has seven signals – clock, slave select 0..3, MOSI (master out – slave in) and
MISO (master in – slave out).
The SPI Master protocol by default does not support any form of handshaking and the only available
mode is unmanaged.
The SPI Master clock can operate up to half of the CPU system clock:

CPU running at 48 Mhz would set the SPI maximum clock to 24 Mhz

CPU running at 24 Mhz would set the SPI maximum clock to 12 Mhz

CPU running at 12 Mhz would set the SPI maximum clock to 6 Mhz
3.2.17
Debugger
The purpose of the debugger interface is to provide the Integrated Development Environment (IDE) with
the following capabilities:

MTP Program.

Application debug - application code can have breakpoints, be single stepped and can be halted.

Detailed internal debug - memory read/write access.
The single wire interface has the following features:

Half Duplex Operation

1Mbps speed

1 start bit
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
1 stop bit

8 data bits

Pull up
3.2.18
C learance N o.: FT DI#420
245 FIFO
The 245 FIFO interface operating in asynchronous mode has an eight bit data bus, individual read and
write strobes with two hardware flow control signals .
3.2.19
PWM
The Pulse Width Modulation (PWM) block can generate a signal in which parameters such as period and
duty cycle are controlled by the 8051 core. It provides 8 outputs and can generate a core interrupt if set.
The main purpose is to generate PWM signals which can be used to control motors, DC/DC converters,
AC/DC supplies, etc.
3.2.20
Digital IO pins
Up to 16 General Purpose digital IO pins are available depending on the package type.
3.2.21
Analogue IO pins
Up to 16 AIO pins are available depending on the package type. The pin can function in either analogue
or digital mode, but not both modes at the same time .
When in analogue mode all 16 AIO pins can be configured to the ADC mode.
AIO_mode_1
AIO_mode_0
Configuration
0
0
Analogue off. If the pin is configured for digital mode, it can be
controlled similar to digital IO pins.
0
1
Reserved.
1
0
ADC mode. Analogue input signal for the internal ADC
convertor.
1
1
Reserved.
Table 3-3 – AIO Modes
To configure these modes, specific registers of the AIOs must be configured. On top of these modes sits a
global mode which allows multiple control of AIO pins. All 16 pins can be configured depending on the
package type.
3.2.22
ADC
The ADC block can convert the analogue input signal to a digital value and store the value in the
registers. The ADC block can be configured to work in single -ended mode and differential mode. In
single-ended mode, an input signal from any of the AIO pins can be the input to the ADC block, with the
reference voltage connected to VOUT3V3. In differential mode, two AIO pins are used together to form a
pair of differential inputs. The voltage difference between these two pins will be converted to digital
values.
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The ADC supports single sample and global sample. In single sample mode only one selected AIO input
will be sampled at a time. In global sample mode, all the selected AIO inputs will be sampled at the same
time.
The sample and hold settling time of the ADC is programmable. Once conversion is done, the respective
interrupt bit will be set, and an interrupt can be generated if enabled.
The accuracy of the ADC convertor is 8-bit.
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4 Device Characteristics and Ratings
4.1 Absolute Maximum Ratings
The absolute maximum ratings for the FT51A devices are as follows. These are in accordance with the
Absolute Maximum Rating System (IEC 60134). Exceeding these may cause permanent damage to the
device.
Parameter
Value
Unit
Storage Temperature
-65°C to 150°C
Degrees C
Conditions
168 Hours
Floor Life (Out of Bag) At Factory Ambient
(30°C / 60% Relative Humidity)
(IPC /JEDEC JSTD-033A MSL
Level 3
C ompliant)*
Ambient Operating Temperature (Power
Applied)
-40°C to 85°C
Degrees C
VC C 5V Supply Voltage
-0.3 to +6.0
V
VC C IO IO Voltage
-0.3 to +3.8
V
DC Input Voltage – USB DP/DM pins
-0.5 to +3.8
V
Hours
-0.3 to
DC Input Voltage – digital pins (powered from
VC C IO)
+ (VC C IO
V
DC Output C urrent – Outputs
22
mA
+0.5)
Table 4-1 – Absolute Maximum Ratings
* If devices are stored out of the packaging beyond this time limit the devices should be baked before
use. The devices should be ramped up to a temperature of +125°C and baked for up to 17 hours.
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4.2 DC Characteristics
DC Characteristics (Ambient Temperature = -40°C to +85°C)
Parameter
Description
Minimum
Typical
Maximum
Units
Conditions
Vcc1
VCC5V Operating
Supply Voltage
4.0
5
5.5
V
Normal Operation
VCC5V and
VOUT3V3 pins
must connect to
the same 3V3
power source
Vcc2
VCC5V Operating
Supply Voltage
3.0
3.3
3.6
V
Vio1
VCCIO Operating
Supply Voltage
3.0
3.3
3.6
V
Vio2
VCCIO Operating
Supply Voltage
2.3
2.5
2.7
V
Vio3
VCCIO Operating
Supply Voltage
1.65
1.8
1.95
V
Icc1
Operating Supply
Current
6.5
20
28.3
mA
Normal Operation
at 48MHz
Icc2
Operating Supply
Current
μA
USB Suspend,
internal clock
stops
VOUT3V3
3.3v regulator output
V
VCC5V=4.0-5.5V
150
3.0
3.3
3.6
Table 4-2 – Operating Voltage and Current
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Parameter
Description
Minimum
Typical
C learance N o.: FT DI#420
Maximum
Units
Conditions
VC C IO
V
IO Drive strength =
4mA
VC C IO
V
IO Drive strength =
8mA
VC C IO
V
IO Drive strength =
12mA
VC C IO
V
IO Drive strength =
16mA
0.4
V
0.4
V
IO Drive strength =
8mA
0.4
V
IO Drive strength =
12mA
0.4
V
IO Drive strength*=
16mA
0.8
V
LVTTL
V
LVTTL
Ioh = +/-2mA
2.9
2.9
Voh
Output Voltage High
2.9
2.9
Iol = +/-2mA
Vol
Output Voltage Low
IO Drive strength =
4mA
Vil
Input low Switching
Threshold
Vih
Input High Switching
Threshold
Vt
Switching Threshold
1.49
V
Vt-
Schmitt trigger negative
going threshold voltage
1.15
V
Vt+
Schmitt trigger positive
going threshold voltage
1.64
V
Rpu
Input pull-up resistance
40
75
190
KΩ
Vin = 0
Rpd
Input pull-down
resistance
40
75
190
KΩ
Vin =VC C IO
Iin
Input Leakage C urrent
-10
10
μA
Vin = 0
2.0
Table 4-3 – IO Characteristics VCCIO = +3V3
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Parameter
Description
Minimum
Typical
C learance N o.: FT DI#420
Maximum
Units
Conditions
2.25
VC C IO
V
2.25
VC C IO
V
IO Drive strength* =
8mA
2.25
VC C IO
V
IO Drive strength =
12mA
2.25
VC C IO
V
IO Drive strength =
16mA
Ioh = +/-2mA
Voh
Output Voltage High
IO Drive strength* =
4mA
Iol = +/-2mA
Vol
Output Voltage Low
0.4
V
0.4
V
IO Drive strength =
8mA
0.4
V
IO Drive strength =
12mA
0.4
V
IO Drive strength =
16mA
0.8
V
LVTTL
V
LVTTL
IO Drive strength =
4mA
Vil
Input low Switching
Threshold
Vih
Input High Switching
Threshold
Vt
Switching Threshold
1.1
V
Vt-
Schmitt trigger negative
going threshold voltage
0.8
V
Vt+
Schmitt trigger positive
going threshold voltage
1.2
V
Rpu
Input pull-up resistance
40
75
190
KΩ
Vin = 0
Rpd
Input pull-down
resistance
40
75
190
KΩ
Vin =VC C IO
Iin
Input Leakage C urrent
-10
10
μA
Vin = 0
1.7
Table 4-4 – IO Characteristics VCCIO = +2V5
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Parameter
Description
Minimum
Typical
C learance N o.: FT DI#420
Maximum
Units
Conditions
1.62
VC C IO
V
IO Drive strength* =
4mA
1.62
VC C IO
V
IO Drive strength* =
8mA
1.62
VC C IO
V
IO Drive strength* =
12mA
1.62
VC C IO
V
IO Drive strength* =
16mA
0.4
V
0.4
V
IO Drive strength* =
8mA
0.4
V
IO Drive strength* =
12mA
0.4
V
IO Drive strength* =
16mA
0.63
V
LVTTL
V
LVTTL
Ioh = +/-2mA
Voh
Output Voltage High
Iol = +/-2mA
Vol
Output Voltage Low
IO Drive strength* =
4mA
Vil
Input low Switching
Threshold
Vih
Input High Switching
Threshold
Vt
Switching Threshold
0.77
V
Vt-
Schmitt trigger negative
going threshold voltage
0.557
V
Vt+
Schmitt trigger positive
going threshold voltage
0.893
V
Rpu
Input pull-up resistance
40
75
190
KΩ
Vin = 0
Rpd
Input pull-down
resistance
40
75
190
KΩ
Vin =VC C IO
Iin
Input Leakage C urrent
-10
10
μA
Vin = 0
1.17
Table 4-5 – IO Characteristics VCCIO = +1V8
* The IO drive strength and slow slew -rate are configurable in the IO registers.
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Parameter
Description
Minimum
Typical
Maximum
Units
Voh
Output Voltage High
2.8
Vol
Output Voltage Low
0.2
V
Vil
Input low Switching
Threshold
0.8
V
Vih
Input High Switching
Threshold
C learance N o.: FT DI#420
Conditions
V
2.0
V
Table 4-6 – USB DP/DM Pin Characteristics
4.3 MTP Memory Reliability Characteristics
The internal 16K Byte MTP memory has the following reliability characteristics:
Parameter
Value
Unit
Data Retention
10
Years
Write C ycle
2,000
C ycles
Read C ycle
Unlimited
C ycles
Table 4-7 – MTP Memory Characteristics
4.4 Internal Clock Characteristics
The internal Clock Oscillator has the following characteristics:
Value
Parameter
Unit
Minimum
Typical
Maximum
Frequency of Operation
(see Note 1)
47.98
48.00
48.02
MHz
Duty Cycle
45
50
55
%
Table 4-8 – Internal Clock Characteristics
Note 1: Equivalent to +/-1667ppm (USB upstream port is active)
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4.5 Digital IO AC Characteristics
Please refer to the DIO section of the FT51A Programmer’s Guide on how to enable / disable the Schmitt
trigger, control the slew rate and determine drive strength.
Parameter
Value
Input
load
load
0.004pF
1.32pF
Timings
tplh
tphl
tplh
tphl
0
1.25
0.98
2.48
2.13
1
1.27
1.08
2.51
2.24
(ns)
Schmitt Trigger
Output
Timings
(ns)
Slew Rate
6pF
120pF
= Normal
tplh
tphl
tplh
tphl
00
3.33
2.37
13.34
11.13
01
3.13
2.21
8.22
6.78
10
3.02
2.15
6.46
5.32
11
2.95
2.10
5.57
4.59
Drive Strength
Output
Timings
(ns)
Slew Rate
6pF
120pF
= Slow
tplh
tphl
tplh
tphl
00
3.33
2.37
13.34
1.13
01
3.33
2.37
9.24
7.81
2.4
7.80
6.61
2.39
7.05
5.97
Drive Strength
10
11
3.33
3.32
Table 4-9 – Digital IO AC Characteristics
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4.6 Analogue IO Characteristics
Parameter
INL
DNL
Description
Min
Max
+/- 2
Non-Linearity
Differential Non-Linearity
+/- 1
Units
Conditions
LSB
LSB
Table 4-10 – ADC Characteristics
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5 USB Power Configurations
The following sections illustrate a possible USB power configuration for the FT51A. The illustrations have
omitted pin numbers for ease of understanding since the pins differ between the various package options.
5.1 USB Bus Powered Configuration
VCC
Ferrite
Bead
1
VCC5V
2
27R
3
27R
USBDM
USBDP
4
47pF
47pF
FT51A
5
SHIELD
10nF
GND
VCC3V3
GND
VCC
100nF
+
4.7uF
100nF
GND
GND
Figure 5-1 Bus Powered Configuration
Figure 5-1 illustrates the FT51A in a typical USB bus powered design configuration. A USB bus powered
device gets its power from the USB bus. Basic rules for USB bus powered devices are as follows –
i)
ii)
iii)
iv)
On plug-in to USB, the device should draw no more current than 50mA.
In USB Suspend mode the device should draw no more than 500uA.
A device that consumes more than 100mA cannot be plugged into a USB bus powered hub.
No device can draw more than 500mA from the USB bus.
The power descriptors in the internal MTP memory of the FT51A should be programmed to match the
current drawn by the device.
A ferrite bead is connected in series with the USB power supply to reduce EMI noise from the FT51A and
associated circuitry being radiated down the USB cable to the USB host. The value of the Ferrite Bead
depends on the total current drawn by the application. A suitable range of Ferrite Beads is available from
Laird Technologies (http://www.lairdtech.com) for example Laird Technologies Part # MI0805K601R-10.
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6 Connection Examples
The following sections illustrate possible connections of the FT51A.
6.1 USB Upstream
package)
and
downstream
port
connections
(48pin
Figure 6-1 Application Example showing USB upstream and downstream connection(48pin
package)
Shown above are the necessary connections to connect the upstream & downstream USB ports. The
debugger module is also included for added information should it be required.
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6.2 USB Upstream
package)
and
downstream
port
C learance N o.: FT DI#420
connections (44pin
Figure 6-2 Application Example showing USB upstream and downstream connection (44pin
package)
6.3 USB Upstream port connections (32pin package)
Figure 6-3 Application Example showing USB upstream connection (32pin package)
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6.4 USB Upstream port connections (28pin package)
Figure 6-4 Application Example showing USB upstream connection (28pin package)
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7 Package Parameters
The FT51A is available in 4 package type s. The package is lead (Pb) free, RoHS compliant, and uses a
‘green’ compound. The package is fully compliant with European Union directive 2002/95/EC.
7.1 48-Pin WQFN Package Outline
48
1
FTDI
XXXXXXXXXX
FT51AQ
YYWW-C
Line 1 – FTDI Logo
Line 2 – Wafer Lot Number
Line 3 – FTDI Part Number
Line 4 – Date Code, Revision
Figure 7-1 48 pin WQFN Package Marking
Figure 7-2 48 pin WQFN Package Dimensions
Note: The centre pad on the base of the FT51A is internally connected to ground. Dimensions are in mm.
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7.2 44-Pin LQFP Package Outline
44
1
FTDI
XXXXXXXXXX
FT51AL
YYWW-C
Line 1 – FTDI Logo
Line 2 – Wafer Lot Number
Line 3 – FTDI Part Number
Line 4 – Date Code, Revision
Figure 7-3 44 pin LQFP Package Marking
Figure 7-4 44 pin LQFP Package Dimensions
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7.3 32-Pin WQFN Package Outline
32
1
FTDI
XXXXXXXXXX
FT51BQ
YYWW-C
Line 1 – FTDI Logo
Line 2 – Wafer Lot Number
Line 3 – FTDI Part Number
Line 4 – Date Code, Revision
Figure 7-5 32 pin WQFN Package Marking
Note: The centre pad on the base of the FT51A is internally connected to ground. Dimensions are in mm.
Figure 7-6 32 pin WQFN Package Dimensions
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7.4 28-Pin SSOP Package Outline
FTDI
XXXXXXXXXX
FT51CS
YYWW-C
Line 1 – FTDI Logo
Line 2 – Wafer Lot Number
Line 3 – FTDI Part Number
Line 4 – Date Code, Revision
Figure 7-7 28 pin SSOP Package Marking
Figure 7-8 28 pin SSOP Package Dimensions
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7.5 Solder Reflow Profile
The FT51A is supplied in a Pb free package. The recommended solder reflow profile is shown in Figure
7-9 FT51A Solder Reflow Profile.
Temperature, T (Degrees C)
tp
Tp
Critical Zone: when
T is in the range
TL to Tp
Ramp Up
TL
tL
TS Max
Ramp
Down
TS Min
tS
Preheat
25
T = 25º C to TP
Time, t (seconds)
Figure 7-9 FT51A Solder Reflow Profile
The recommended values for the solder reflow profile are detailed in Error! Reference source not
found.. Values are shown for both a completely Pb free solder process (i.e. the FT51A is used with Pb
free solder), and for a non-Pb free solder process (i.e. the FT51A is used with non-Pb free solder).
Profile Feature
Pb Free Solder Process
Non-Pb Free Solder Process
Average Ramp Up Rate (T s to Tp)
3°C / second Max.
3°C / Second Max.
Preheat
- Temperature Min (T s Min.)
150°C
100°C
- Temperature Max (T s Max.)
200°C
150°C
- Time (ts Min to ts Max)
60 to 120 seconds
60 to 120 seconds
217°C
183°C
60 to 150 seconds
60 to 150 seconds
260°C
240°C
20 to 40 seconds
20 to 40 seconds
Ramp Down Rate
6°C / second Max.
6°C / second Max.
Time for T= 25°C to Peak Temperature, T p
8 minutes Max.
6 minutes Max.
Time Maintained Above Critical Temperature
T L:
- Temperature (T L)
- Time (tL)
Peak Temperature (T p)
Time within 5°C of actual Peak Temperature
(tp)
Table 7-1 – Reflow Profile Parameters
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8 Contact Information
Head Office – Glasgow, UK
Branch Office – Tigard, Oregon, USA
Future Technology Devices International Limited
Unit 1, 2 Seaward Place, Centurion Business Park
Glasgow G41 1HH
United Kingdom
Tel: +44 (0) 141 429 2777
Fax: +44 (0) 141 429 2758
Future Technology Devices International Limited (USA)
7130 SW Fir Loop
Tigard, OR 97223-8160
USA
Tel: +1 (503) 547 0988
Fax: +1 (503) 547 0987
E-mail (Sales)
E-mail (Support)
E-mail (General Enquiries)
E-mail (Sales)
E-mail (Support)
E-mail (General Enquiries)
[email protected]
[email protected]
[email protected]
[email protected]
[email protected]
[email protected]
Branch Office – Taipei, Taiwan
Branch Office – Shanghai, China
Future Technology Devices International Limited (Taiwan)
2F, No. 516, Sec. 1, NeiHu Road
Taipei 114
Taiwan , R.O.C.
Tel: +886 (0) 2 8791 3570
Fax: +886 (0) 2 8791 3576
Future Technology Devices International Limited (China)
Room 1103, No. 666 West Huaihai Road,
Shanghai, 200052
C hina
Tel: +86 21 62351596
Fax: +86 21 62351595
E-mail (Sales)
E-mail (Support)
E-mail (General Enquiries)
E-mail (Sales)
E-mail (Support)
E-mail (General Enquiries)
[email protected]
[email protected]
[email protected]
[email protected]
[email protected]
[email protected]
Web Site
http://ftdichip.com
Distributor and Sales Representatives
Please visit the Sales Network page of the FTDI Web site for the contact details of our distributor(s) and sales
representative(s) in your country.
Sys tem and equipment manufacturers and des igners are responsible to ens ure that their s ystems, and any Future T echnology D evi c es
I nternational L td (FTDI) devices incorporated in their s ystems, meet all applic able s afety, regulatory and s ys tem- level performanc e
requirements. A ll application-related information in this doc ument (inc luding application descriptions, s uggested FTD I devices and other
materials ) is provided for referenc e only. While FT DI has taken c are to as s ure it is ac c urate, this information is s ubjec t to c us tomer
c onfirmation, and FT DI disclaims all liability for s ys tem des igns and for any applic ations as s is tanc e provided by FT D I . U s e o f FT D I
devic es in life s upport and/or s afety applic ations is e ntirely at the us er’s ris k, and the us er agrees to defend, indemnify and hold
harmles s FTDI from any and all damages , c laims, s uits or expense resulting from s uc h us e. T his document is s ubject to c hange without
notic e. N o freedom to us e patents or other intellectual property rights is implied by the public ation of this doc ument. N either the whole
nor any part of the information c ontained in, or the produc t des cribed in this document, may be adapted or reproduc ed in any material
or elec tronic form without the prior written c ons ent of the c opyright holder. Future T ec hnology D evic es I nternational L td, U nit 1 , 2
Seaward P lac e, C enturion Business P ark, G las gow G 4 1 1 H H , U nited Kingdom. Sc otland Regis tered C ompany N umber: SC 1 3 6 6 4 0
Copyright © Future Technology Devices International Limited
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FT51A Advanced MCU with 8051 Compatible Core IC Datasheet
Version 1.5
D oc ument N o.: FT _000877
C learance N o.: FT DI#420
Appendix A – References
Document References
TN_100 USB Vendor ID / Product ID Guidelines
AN_352 FT51A Installation Guide
AN_345 FT51A Keyboard Sample
AN_346 FT51A Mouse Sample
AN_347 FT51A Test and Measurement Sample
AN_348 FT51A FT800 Sensors Sample
AN_349 FT51A FT800 Spaced Invaders Sample
AN_354 FT51A Standalone Demo Application
AN_289 FT51A Programming Guide
Acronyms and Abbreviations
Terms
Description
ADC
Analog to Digital Converter
CPU
Central Processing Unit
FPGA
Field Programmable Gate Array
LQFP
Low Profile Quad Flat Package
MCU
Micro Controller Unit
PLD
Programmable Logic Device
QFN
Quad Flat No-leads
RoHS
Restriction of Hazardous Substances Directive
SPI
UART
USB
Serial Peripheral Interface
Universal Asynchronous Receiver/Transmitter
Universal Serial Bus
Copyright © Future Technology Devices International Limited
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FT51A Advanced MCU with 8051 Compatible Core IC Datasheet
Version 1.5
D oc ument N o.: FT _000877
C learance N o.: FT DI#420
Appendix B - List of Figures and Tables
List of Figures
Figure 2-1 - 28 Pin SSOP Package .......................................................................................................... 5
Figure 2-2 - 32 Pin WQFN Package ......................................................................................................... 6
Figure 2-3 - 44 Pin LQFP Package ........................................................................................................... 7
Figure 2-4 - 48 Pin WQFN Package ......................................................................................................... 8
Figure 3-1 – FT51A Block Diagram........................................................................................................ 11
Figure 3-2 – SPI Master........................................................................................................................ 15
Figure 5-1 Bus Powered Configuration .................................................................................................. 26
Figure 6-1 Application Example showing USB upstream and downstream connection(48pin package) .... 27
Figure 6-2 Application Example showing USB upstream and downstream connection (44pin package) ... 28
Figure 6-3 Application Example showing USB upstream connection (32pin package) ............................. 28
Figure 6-4 Application Example showing USB upstream connection (28pin package) ............................. 29
Figure 7-1 48 pin WQFN Package Marking............................................................................................. 30
Figure 7-2 48 pin WQFN Package Dimensions ....................................................................................... 30
Figure 7-3 44 pin LQFP Package Marking .............................................................................................. 31
Figure 7-4 44 pin LQFP Package Dimensions ......................................................................................... 31
Figure 7-5 32 pin WQFN Package Marking............................................................................................. 32
Figure 7-6 32 pin WQFN Package Dimensions ....................................................................................... 32
Figure 7-7 28 pin SSOP Package Marking.............................................................................................. 33
Figure 7-8 28 pin SSOP Package Dimensions ........................................................................................ 33
Figure 7-9 FT51A Solder Reflow Profile ................................................................................................. 34
List of Tables
Table 1-1 – Part Numbers....................................................................................................................... 2
Table 2-1 – Power and Ground ............................................................................................................... 9
Table 2-2 – Common Function pins....................................................................................................... 10
Table 3-1 – 8051 Ports ......................................................................................................................... 12
Table 3-2 – Peripheral Pin Requirements............................................................................................... 14
Table 3-3 – AIO Modes ......................................................................................................................... 16
Table 4-1 – Absolute Maximum Ratings ................................................................................................ 18
Table 4-2 – Operating Voltage and Current ........................................................................................... 19
Table 4-3 – IO Characteristics VCCIO = +3V3....................................................................................... 20
Table 4-4 – IO Characteristics VCCIO = +2V5....................................................................................... 21
Table 4-5 – IO Characteristics VCCIO = +1V8....................................................................................... 22
Table 4-6 – USB DP/DM Pin Characteristics........................................................................................... 23
Table 4-7 – MTP Memory Characteristics............................................................................................... 23
Table 4-8 – Internal Clock Characteristics ............................................................................................. 23
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FT51A Advanced MCU with 8051 Compatible Core IC Datasheet
Version 1.5
D oc ument N o.: FT _000877
C learance N o.: FT DI#420
Table 4-9 – Digital IO AC Characteristics .............................................................................................. 24
Table 4-10 – ADC Characteristics.......................................................................................................... 25
Table 7-1 – Reflow Profile Parameters .................................................................................................. 34
Table 0-1 – IO Registers....................................................................................................................... 42
Copyright © Future Technology Devices International Limited
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FT51A Advanced MCU with 8051 Compatible Core IC Datasheet
Version 1.5
D oc ument N o.: FT _000877
C learance N o.: FT DI#420
Appendix C – List of IO registers
User should refer to the FT51A Programmer’s Guide for more detail.
Register
Address
(0x0)
(0x1)
(0x2)
(0x3)
(0x4)
(0x5)
(0x6)
(0x9)
(0xA)
to
(0x19)
(0x1A)
to
(0x29)
(0x2A)
(0x2B)
(0x2C)
(0x2D)
(0x2E)
(0x34)
(0x36)
(0x37)
(0x38)
(0x39)
(0x40)
(0x41)
(0x42)
(0x43)
(0x44)
(0x48)
(0x4A)
(0x4B)
(0x4C)
(0x4D)
(0x4E)
(0x50)
(0x51)
(0x52)
(0x53)
(0x54)
(0x55)
(0x56)
(0x57)
(0x58)
(0x59)
(0x5A)
(0x5B)
(0x60)
(0x61)
(0x62)
(0x63)
(0x64)
Register Name
Description
DEVICE_CONTROL_REGISTER
SYSTEM_CLOCK_DIVIDER
TOP_USB_CONTROL
PERIPHERAL_INT0
PERIPHERAL_IEN0
PERIPHERAL_INT1
PERIPHERAL_IEN1
PIN_CONFIG
DIGITAL_CONTROL_AIO_0
to
DIGITAL_CONTROL_AIO15
DIGITAL_CONTROL_DIO0
to
DIGITAL_CONTROL_DIO15
AIO_DIFFERENTIAL_ENABLE
MTP_CONTROL
MTP_PROG_ADDR_L
MTP_PROG_ADDR_U
MTP_PROG_DATA
PIN_PACKAGE_CONFIG
CRC_CONTROL
CRC_RESULT_L
CRC_RESULT_U
SECURITY_LEVEL
IOMUX_CONTROL
IOMUX_OUTPUT_PIN_SEL
IOMUX_OUTPUT_SIG_SEL
IOMUX_INPUT_SIG_SEL
IOMUX_INPUT_PIN_SEL
SPI_SLAVE_CONTROL
SPI_SLAVE_TX_DATA
SPI_SLAVE_RX_DATA
SPI_SLAVE_IEN
SPI_SLAVE_INT
SPI_SLAVE_SETUP
SPI_MASTER_CONTROL
SPI_MASTER_DATA_TX
SPI_MASTER_DATA_RX
SPI_MASTER_IEN
SPI_MASTER_INT
SPI_MASTER_SETUP
SPI_MASTER_CLK_DIV
SPI_MASTER_DATA_DELAY
SPI_MASTER_SS_SETUP
SPI_MASTER_TRANSFER_SIZE_L
SPI_MASTER_TRANSFER_SIZE_U
SPI_MASTER_TRANSFER_PENDING
UART_CONTROL
UART_DMA_CTRL
UART_RX_DATA
UART_TX_DATA
UART_TX_IEN
Device Control Register
System Clock Divider
USB Top-level Control Register
Peripheral Interrupt Status 0
Peripheral Interrupt Enable 0
Peripheral Interrupt Status 1
Peripheral Interrupt Enable 1
Miscellaneous Pin Configuration
AIO Pins 0 to 15 Digital Control
DIO Pins 0 to 15 Digital Control
AIO Differential Pin Enable
MTP Memory Control
MTP Program Address Lower Byte
MTP Program Address Upper Byte
MTP Program Data
Device Package Information
CRC Control of MTP Memory
CRC Result Lower Byte
CRC Result Upper Byte
Device Security Status Register
IOMUX Control Register
Select Output Pin Number Register
Select Output Signal Register
Select Input Signal Register
Select Input Pin Number Register
SPI_SLAVE Control Register
SPI Slave Transmit Data
SPI Slave Receive Data
SPI Slave Interrupt Enable
SPI Slave Interrupt Status
SPI Slave Setup
SPI_MASTER Control Register
SPI Master Transmit Data
SPI Master Receive Data
SPI Master Interrupt Enable
SPI Master Interrupt Status
SPI Master Setup
SPI Master Clock Divider
SPI Master Data Delay
SPI Master Slave Select Setup
SPI Master Transfer Size Lower Byte
SPI Master Transfer Size Upper Byte
SPI Master Transfer Pending
UART Control Register
UART DMA Control
UART Receive Data
UART Transmit Data
UART Tx Interrupt Enable
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FT51A Advanced MCU with 8051 Compatible Core IC Datasheet
Version 1.5
D oc ument N o.: FT _000877
Register
Address
(0x65)
(0x66)
(0x67)
(0x68)
(0x69)
(0x6A)
(0x6B)
(0x6C)
(0x6D)
(0x70)
(0x71)
to
(0x74)
(0x75)
(0x76)
(0x77)
(0x78)
(0x79)
(0x7A)
(0x7B)
(0x7C)
(0x7D)
(0x80)
(0x81)
(0x82)
C learance N o.: FT DI#420
Register Name
Description
UART_TX_INT
UART_RX_IEN
UART_RX_INT
UART_LINE_CTRL
UART_BAUD_0
UART_BAUD_1
UART_BAUD_2
UART_FLOW_CTRL
UART_FLOW_STAT
TIMER_CONTROL
TIMER_CONTROL_1
to
TIMER_CONTROL_4
TIMER_INT
TIMER_SELECT
TIMER_WDG
TIMER_WRITE_LS
TIMER_WRITE_MS
TIMER_PRESC_LS
TIMER_PRESC_MS
TIMER_READ_LS
TIMER_READ_MS
PWM_CONTROL
PWM_CTRL
PWM_PRESCALER
UART Tx Interrupt Status
UART Rx Interrupt Enable
UART Rx Interrupt Status
UART Line Control
UART Baud Rate Byte 0
UART Baud Rate Byte 1
UART Baud Rate Byte 2
UART Flow Control
UART Flow Control Status
TIMER Top Control
(0x83)
PWM_CNT16_LSB
(0x84)
PWM_CNT16_MSB
(0x85)
to
(0x94)
(0x95)
to
(0x9C)
(0x9D)
(0x9E)
(0x9F)
(0xA0)
(0xA1)
(0xA2)
(0xA3)
(0xA4)
(0xA5)
(0xB0)
(0xB1)
PWM_CMP16_0_LSB
to
PWM_CMP16_7_MSB
PWM_OUT_TOGGLE_EN_0
to
PWM_OUT_TOGGLE_EN_7
PWM_OUT_CLR_EN
PWM_CTRL_BL_CMP8
PWM_INIT
FIFO_CONTROL
FIFO_CTRL_STATUS
FIFO_RX_DATA
FIFO_TX_DATA
FIFO_INTERRUPT_ENA
FIFO_INTERRUPT
DMA_CONTROL_1
DMA_ENABLE_1
(0xB2)
DMA_IRQ_ENA_1
(0xB3)
DMA_IRQ_1
(0xB4)
DMA_SRC_MEM_ADDR_L_1
(0xB5)
DMA_SRC_MEM_ADDR_U_1
(0xB6)
DMA_DEST_MEM_ADDR_L_1
(0xB7)
DMA_DEST_MEM_ADDR_U_1
Timer Control Register 1 to 4
Timer Interrupt Status
Timer Select Register
Watchdog Start Value
Timer Start Value 7:0
Timer Start Value 15:8
Timer Prescaler Value 7:0
Timer Prescaler Value 15:8
Timer Current Value 7:0
Timer Current Value 15:8
PWM Control Register
PWM Control
PWM PRESCALER Comparator value
PWM COUNTER16 Comparator LSB
value
PWM COUNTER16 Comparator MSB
value
PWM Comparator 0 LSB value to PWM
Comparator 7 MSB value
PWM Out toggle enable register 0 to 7
PWM Out clear enable
PWM Control CMP8 value
PWM Initialization register
FIFO Control Register
FIFO Control Status
FIFO Receive Data
FIFO Transmit Data
FIFO Interrupt Enable
FIFO Interrupt
DMA Control Register
IO DMA Enable Register
DMA IO Interrupt Enable & Control
Register
DMA IO Interrupt Register
DMA IO Source Mem Addr Register
(Lower Bits)
DMA IO Source Mem Addr Register
(Upper Bits)
DMA IO Destination Mem Addr Register
(Lower Bits)
DMA IO Destination Mem Addr Register
(Upper Bits)
Copyright © Future Technology Devices International Limited
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FT51A Advanced MCU with 8051 Compatible Core IC Datasheet
Version 1.5
D oc ument N o.: FT _000877
Register
Address
(0xB8)
(0xB9)
C learance N o.: FT DI#420
Register Name
Description
DMA_IO_ADDR_L_1
DMA_IO_ADDR_U_1
DMA IO Addr Register (Lower Bits)
IO DMA IO Addr Register (Upper Bits)
IO DMA Transfer Byte Count Register
(Lower Bits)
IO DMA Transfer Byte Count Register
(Upper Bits)
IO DMA Current Byte Count Register
(Lower Bits)
IO DMA Current Byte Count Register
(Upper Bits)
IO DMA FIFO DATA
IO DMA Almost Full Flag Trigger Value
DMA Control Register
IO DMA Enable Register
DMA IO Interrupt Enable & Control
Register
DMA IO Interrupt Register
DMA IO Source Mem Addr Register
(Lower Bits)
DMA IO Source Mem Addr Register
(Upper Bits)
DMA IO Destination Mem Addr Register
(Lower Bits)
DMA IO Destination Mem Addr Register
(Upper Bits)
DMA IO Addr Register (Lower Bits)
IO DMA IO Addr Register (Upper Bits)
IO DMA Transfer Byte Count Register
(Lower Bits)
IO DMA Transfer Byte Count Register
(Upper Bits)
IO DMA Current Byte Count Register
(Lower Bits)
IO DMA Current Byte Count Register
(Upper Bits)
IO DMA FIFO DATA
IO DMA Almost Full Flag Trigger Value
DMA Control Register
IO DMA Enable Register
DMA IO Interrupt Enable & Control
Register
DMA IO Interrupt Register
DMA IO Source Mem Addr Register
(Lower Bits)
DMA IO Source Mem Addr Register
(Upper Bits)
DMA IO Destination Mem Addr Register
(Lower Bits)
DMA IO Destination Mem Addr Register
(Upper Bits)
DMA IO Addr Register (Lower Bits)
IO DMA IO Addr Register (Upper Bits)
IO DMA Transfer Byte Count Register
(Lower Bits)
IO DMA Transfer Byte Count Register
(Upper Bits)
IO DMA Current Byte Count Register
(Lower Bits)
(0xBA)
DMA_TRANS_CNT_L_1
(0xBB)
DMA_TRANS_CNT_U_1
(0xBC)
DMA_CURR_CNT_L_1
(0xBD)
DMA_CURR_CNT_U_1
(0xBE)
(0xBF)
(0xC0)
(0xC1)
DMA_FIFO_DATA_1
DMA_AFULL_TRIGGER_1
DMA_CONTROL_2
DMA_ENABLE_2
(0xC2)
DMA_IRQ_ENA_2
(0xC3)
DMA_IRQ_2
(0xC4)
DMA_SRC_MEM_ADDR_L_2
(0xC5)
DMA_SRC_MEM_ADDR_U_2
(0xC6)
DMA_DEST_MEM_ADDR_L_2
(0xC7)
DMA_DEST_MEM_ADDR_U_2
(0xC8)
(0xC9)
DMA_IO_ADDR_L_2
DMA_IO_ADDR_U_2
(0xCA)
DMA_TRANS_CNT_L_2
(0xCB)
DMA_TRANS_CNT_U_2
(0xCC)
DMA_CURR_CNT_L_2
(0xCD)
DMA_CURR_CNT_U_2
(0xCE)
(0xCF)
(0xD0)
(0xD1)
DMA_FIFO_DATA_2
DMA_AFULL_TRIGGER_2
DMA_CONTROL_3
DMA_ENABLE_3
(0xD2)
DMA_IRQ_ENA_3
(0xD3)
DMA_IRQ_3
(0xD4)
DMA_SRC_MEM_ADDR_L_3
(0xD5)
DMA_SRC_MEM_ADDR_U_3
(0xD6)
DMA_DEST_MEM_ADDR_L_3
(0xD7)
DMA_DEST_MEM_ADDR_U_3
(0xD8)
(0xD9)
DMA_IO_ADDR_L_3
DMA_IO_ADDR_U_3
(0xDA)
DMA_TRANS_CNT_L_3
(0xDB)
DMA_TRANS_CNT_U_3
(0xDC)
DMA_CURR_CNT_L_3
Copyright © Future Technology Devices International Limited
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FT51A Advanced MCU with 8051 Compatible Core IC Datasheet
Version 1.5
D oc ument N o.: FT _000877
Register
Address
Register Name
(0xDD)
DMA_CURR_CNT_U_3
(0xDE)
(0xDF)
(0xE0)
(0xE1)
DMA_FIFO_DATA_3
DMA_AFULL_TRIGGER_3
DMA_CONTROL_4
DMA_ENABLE_4
(0xE2)
DMA_IRQ_ENA_4
(0xE3)
DMA_IRQ_4
(0xE4)
DMA_SRC_MEM_ADDR_L_4
(0xE5)
DMA_SRC_MEM_ADDR_U_4
(0xE6)
DMA_DEST_MEM_ADDR_L_4
(0xE7)
DMA_DEST_MEM_ADDR_U_4
(0xE8)
(0xE9)
DMA_IO_ADDR_L_4
DMA_IO_ADDR_U_4
(0xEA)
DMA_TRANS_CNT_L_4
(0xEB)
DMA_TRANS_CNT_U_4
(0xEC)
DMA_CURR_CNT_L_4
(0xED)
DMA_CURR_CNT_U_4
(0xEE)
(0xEF)
(0x100)
(0x101)
(0x102)
to
(0x105)
(0x108)
(0x109)
(0x10A)
DMA_FIFO_DATA_4
DMA_AFULL_TRIGGER_4
AIO_CONTROL
AIO_GLOBAL_CTRL
AIO _MODE_0
to
AIO _MODE_3
AIO_SAMPLE_0
AIO_SAMPLE_1
(0x10B)
AIO_GLOBAL_PORT_SELECT_0_7
(0x10C)
AIO_GLOBAL_PORT_SELECT_8_15
(0x13E)
to
(0x15D)
(0x16E)
(0x16F)
(0x170)
(0x171)
AIO_0_ADC_DATA_L
to
AIO_15_ADC_DATA_U
AIO_INTERRUPT_0_7
AIO_INT_ENABLE_0_7
AIO_INTERRUPT_8_15
AIO_INT_ENABLE_8_15
(0x176)
(0x177)
(0x17A)
C learance N o.: FT DI#420
Description
IO DMA Current Byte Count Register
(Upper Bits)
IO DMA FIFO DATA
IO DMA Almost Full Flag Trigger Value
DMA Control Register
IO DMA Enable Register
DMA IO Interrupt Enable & Control
Register
DMA IO Interrupt Register
DMA IO Source Mem Addr Register
(Lower Bits)
DMA IO Source Mem Addr Register
(Upper Bits)
DMA IO Destination Mem Addr Register
(Lower Bits)
DMA IO Destination Mem Addr Register
(Upper Bits)
DMA IO Addr Register (Lower Bits)
IO DMA IO Addr Register (Upper Bits)
IO DMA Transfer Byte Count Register
(Lower Bits)
IO DMA Transfer Byte Count Register
(Upper Bits)
IO DMA Current Byte Count Register
(Lower Bits)
IO DMA Current Byte Count Register
(Upper Bits)
IO DMA FIFO DATA
IO DMA Almost Full Flag Trigger Value
AIO Control Register
AIO Global Control Register
Mode Select for AIO pins 0-15.
Initiates a SAMPLE of AIO 0 to 7
Initiates a SAMPLE of AIO 8 to 15
Selects the AIOs to be included in a
Global function
Selects the AIOs to be included in a
Global function
Sampled ADC data for AIO0 to AIO15
Interrupt status for ports 0-7
Interrupt enable for ports 0-7
Interrupt status for ports 8-15
Interrupt enable for ports 8-15
Sample&Hold Settling time counter,
AIO_SH_COUNTER_L
lower 8 bits
Sample&Hold Settling time, upper 2
AIO_SH_COUNTER_U
bits
AIO_CLOCK_DIVIDER
Clock Divider
Table 0-1 – IO Registers
Copyright © Future Technology Devices International Limited
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FT51A Advanced MCU with 8051 Compatible Core IC Datasheet
Version 1.5
D oc ument N o.: FT _000877
C learance N o.: FT DI#420
Appendix D – Revision History
Document Title
:
FT51A Advanced MCU with 8051 Compatible Core IC Datasheet
Document Reference No.
:
FT_000877
Clearance No.
:
FTDI#420
Product Page
:
http://www.ftdichip.com/Products/ICs/FT51A.html
Document Feedback
:
DS_FT51A
Revision
Changes
Date
Version 1.0
Initial Release
2014-03-17
Version 1.1
Second Release
2014-11-05
Version 1.2
Updated Pin out Diagram
2014-12-12
Version 1.3
Updated branding from FT51 to FT51A
2015-03-23
Version 1.4
Removed DAC references
2015-11-18
Version 1.5
Updated Figure 7.8 28 pin SSOP Package Dimensions
2016-04-07
Copyright © Future Technology Devices International Limited
43