Fairchild GTLP16617MTD 17-bit ttl/gtlp synchronous bus transceiver with buffered clock Datasheet

Revised October 1998
GTLP16617
17-Bit TTL/GTLP Synchronous Bus Transceiver
with Buffered Clock
General Description
Features
The GTLP16617 is a 17-bit registered synchronous bus
transceiver that provides TTL to GTLP signal level translation. It allows for transparent, latched and clocked modes
of data flow and provides a buffered GTLP (CLKOUT)
clock output from the TTL CLKAB. The device provides a
high speed interface between cards operating at TTL logic
levels and a backplane operating at GTLP logic levels.
High speed backplane operation is a direct result of
GTLP’s reduced output swing (<1V), reduced input threshold levels and output edge rate control. The edge rate control minimizes bus settling time. GTLP is a Fairchild
Semiconductor derivative of the Gunning Transceiver logic
(GTL) JEDEC standard JESD8-3.
■ Bidirectional interface between GTLP and TTL logic
levels
Fairchild’s GTLP has internal edge-rate control and is process, voltage, and temperature (PVT) compensated. Its
function is similar to BTL and GTL but with different output
levels and receiver threshold. GTLP output LOW level is
typically less than 0.5V, the output level HIGH is 1.5V and
the receiver threshold is 1.0V.
■ Edge Rate Control to minimize noise on the GTLP port
■ Power up/down/off high impedance for live insertion.
■ External VREF pin for receiver threshold
■ CMOS technology for low power dissipation
■ 5 V tolerant inputs and outputs on the A-Port
■ Bus-hold data inputs on the A-Port eliminates the need
for external pull-up resistors on unused inputs.
■ TTL compatible driver and control inputs
■ Flow through pinout optimizes PCB layout
■ Open drain on GTLP to support wired-or connection
■ A-Port source/sink −32 mA/+32 mA
■ D-type flip-flop, latch and transparent data paths
■ GTLP Buffered CLKAB signal available(CLKOUT)
■ Recommended Operating Temperature −40°C to 85°C
Ordering Code:
Order Number
Package Number
GTLP16617MEA
MS56A
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118 0.300” Wide
Package Description
GTLP16617MTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
© 1998 Fairchild Semiconductor Corporation
DS500031.prf
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GTLP16617 17-Bit TTL/GTLP Synchronous Bus Transceiver with Buffered Clock
June 1997
GTLP16617
Pin Descriptions
Pin Names
Connection Diagram
Description
OEAB
A-to-B Output Enable (Active LOW)
OEBA
B-to-A Output Enable (Active LOW)
CEAB
A-to-B Clock Enable (Active LOW)
CEBA
B-to-A Clock Enable (Active LOW)
LEAB
A-to-B Latch Enable (Transparent HIGH)
LEBA
B-to-A Latch Enable (Transparent HIGH)
VREF
GTLP Reference Voltage
CLKAB
A-to-B Clock
CLKBA
B-to-A Clock
A1-A17
A-to-B Data Inputs or B-to-A 3-STATE
Data Outputs
B1-B17
B-to-A Data Inputs or
A-to-B Open Drain Outputs
CLKIN
B-to-A Buffered Clock Output
CLKOUT
GTLP Buffered Clock Output of CLKAB
Functional Description
The GTLP16617 is a 17 bit registered transceiver containing D-type flip-flop, latch and transparent modes of operation for
the data path and a GTLP translation of the CLKAB signal (CLKOUT). Data flow in each direction is controlled by the clock
enables (CEAB and CEBA), latch enables (LEAB and LEBA), clock (CLKAB and CLKBA) and output enables (OEAB and
OEBA). The clock enables (CEAB and CEBA) enable all 17 data bits. The output enables (OEAB and OEBA) control both
the 17 bits of data and the CLKOUT/CLKIN buffered clock paths and the OEAB is synchronous with the CLKAB signal. The
OEBA can not be synchronous since we are passing the clock through the device with data and we would need to generate
the CLKBA signal elsewhere. It should also be noted that the OEAB register is controlled by CLKAB only, and is also not
inhibited by the CEAB signal.
For A-to-B data flow, when CEAB is LOW, the device operates on the LOW-to-HIGH transition of CLKAB for the flip-flop
and on the HIGH-to-LOW transition of LEAB for the latch path. That is, if CEAB is LOW and LEAB is LOW the A data is
latched regardless as to the state of CLKAB (HIGH or LOW) and if LEAB is HIGH the device is in transparent mode. When
OEAB is registered LOW the outputs are active. When OEAB is registered HIGH the outputs are HIGH impedance. The
data flow of B-to-A is similar except that CEBA, OEBA, LEBA and CLKBA are used.
Truth Table
(Note 1)
Inputs
Output
B
Mode
Latched storage of
A data
CEAB
OEAB(Note 2)
LEAB
CLKAB
A
X
H
X
↑
X
Z (Note 3)
L
L
L
H or L
X
B0(Note 4)
(Note 5)
L
L
L
H or L
X
X
L
H
X
L
L
X
L
H
X
H
H
L
L
L
↑
L
L
L
L
L
↑
H
H
Clocked storage of
A data
H
L
L
X
X
B0(Note 5)
Clock inhibit
Transparent
Note 1: A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA, CLKBA, CEBA.
Note 2: LH edge on CLKAB is required when changing the input on OEAB pin.
Note 3: OEAB met set-up time prior to CLKAB LH transition
Note 4: Output level before the indicated steady state input conditions were established, provided CLKAB was HIGH prior to LEAB going LOW.
Note 5: Output level before the indicated steady state input conditions were established.
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2
GTLP16617
Logic Diagram
3
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GTLP16617
Absolute Maximum Ratings(Note 6)
Supply Voltage (VCC )
−0.5V to +7.0V
DC Input Voltage (VI)
−0.5V to +7.0V
Recommended Operating
Conditions (Note 8)
Supply Voltage VCC
DC Output Voltage (VO)
Outputs 3-STATE
Outputs Active (Note 7)
−0.5V to +7.0V
−0.5V to VCC + 0.5V
64 mA
on A-Port and Control Pins
−64 mA
−50 mA
+50 mA
+34 mA
B-Port
Operating Temperature (TA)
−50 mA
VO > VCC
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+32 mA
A-Port
80 mA
VO < 0V
Storage Temperature (TSTG)
−32 mA
A-Port
−40°C to +85°C
Note 6: The Absolute Maximum Ratings are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum rating.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
DC Output Diode Current (IOK)
ESD Rating
0.0V to 5.5V
LOW Level Output Current (IOL)
DC Input Diode Current (IIK)
VI < 0V
1.35V to 1.65V
HIGH Level Output Current (IOH)
DC Output Sink Current
into B-Port in the LOW State,
IOL
4.75V to 5.25V
Input Voltage (VI)
DC Output Source Current from
A-Port IOH
3.15V to 3.45V
Bus Termination Voltage (VTT) GTLP
DC Output Sink Current into
A-Port IOL
VCC
VCCQ
>2000V
Note 7: IO Absolute Maximum Rating must be observed.
−65°C to +150°C
Note 8: Unused inputs must be held high or low.
4
Over Recommended Operating Free-Air Temperature Range, VREF = 1.0V (Unless Otherwise Noted).
Symbol
Test Conditions
Min
Typ
Max
Units
(Note 9)
VIH
VIL
B-Port
VREF +0.1
Others
2.0
B-Port
0.0
VTT
Others
VREF
GTLP
1.0
GTL
0.8
VCC = 3.15V,
VIK
II = −18 mA
VREF −0.2
V
0.8
V
V
V
−1.2
VCCQ = 4.75V
VOH
VOL
A-Port
A-Port
VCC, VCCQ = Min to Max (Note 10)
IOH = −100 µA
VCC = 3.15V
IOH = −8 mA
2.4
VCCQ = 4.75V
IOH = −32 mA
2.0
V
V
V
VCC −0.2
V
VCC, VCCQ = Min to Max (Note 10)
IOL = 100 µA
0.2
VCC = 3.15V
IOL = 32 mA
0.5
V
VCCQ = 4.75V
II
B-Port
VCC = 3.15V VCCQ = 4.75V
IOL = 34 mA
0.65
V
Control Pins
VCC, VCCQ = 0 or Max
VI = 5.5V or 0V
±10
µA
A-Port
VCC = 3.45V
VI = 5.5V
20
VCCQ = 5.25V
VI = VCC
1
VI = 0
B-Port
VCC = 3.45V
VI = VCCQ
5
VCCQ = 5.25V
VI = 0
−5
IOFF
A-Port and
Control Pins
VCC = VCCQ = 0
VI or VO = 0 to 4.5V
II(hold)
A-Port
VCC = 3.15V,
VI = 0.8V
75
VCCQ = 4.75V
VI = 2.0V
−20
IOZH
A-Port
VCC = 3.45V,
VO = 3.45V
B-Port
VCCQ = 5.25V
VO = 1.5V
A-Port
VCC = 3.45V,
VO = 0
IOZL
100
5
−20
B-Port
VCCQ = 5.25V
VO = 0.65V
A or B
VCC = 3.45V,
Outputs HIGH
30
40
(VCCQ)
Ports
−10
VCCQ = 5.25V,
Outputs LOW
30
40
VI = VCCQ or GND
Outputs Disabled
30
40
VCC = 3.45V, VCCQ = 5.25V, IO = 0,
Outputs HIGH
0
1
Outputs LOW
0
1
VI = VCCQ or GND
Outputs Disabled
0
1
One Input at 2.7V
0
1
IO = 0,
A or B
Ports
∆ICC
A-Port and
VCC = 3.45V,
(Note 11)
Control Pins
VCCQ = 5.25V,
µA
µA
µA
1
ICCQ
ICC
(VCC)
µA
−30
µA
µA
mA
mA
mA
A or Control Inputs at
VCC or GND
CIN
Control Pins
VI = VCCQ or 0
8
CI/O
A-Port
VI = VCCQ or 0
9
CI/O
B-Port
VI = VCCQ or 0
6
pF
Note 9: All typical values are at VCC = 3.3V, VCCQ = 5.0V, and TA = 25°C.
Note 10: For conditions shown as Min or Max, use the appropriate value specified under recommended operating conditions.
Note 11: This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
5
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GTLP16617
DC Electrical Characteristics
GTLP16617
AC Operating Requirements
Over recommended ranges of supply voltage and operating free-air temperature, VREF = 1.0V (unless otherwise noted).
Symbol
fCLOCK
Max Clock Frequency
tW
Pulse Duration
tS
tH
Min
175
LEAB or LEBA HIGH
3.0
CLKAB or CLKBA HIGH or LOW
3.2
A before CLKAB↑
0.5
Max
Unit
MHz
ns
Setup Time
Hold Time
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OEAB before CLKAB↑
1.5
B before CLKBA↑
3.1
A before LEAB↓
1.3
B before LEBA↓
3.7
CEAB before CLKAB↑
0.7
CEBA before CLKBA↑
1.0
A after CLKAB↑
1.5
OEAB after CLKAB↑
1.0
B after CLKBA↑
0.0
A after LEAB↓
0.5
B after LEBA↓
0.0
CEAB after CLKAB↑
1.5
CEBA after CLKBA↑
1.7
6
ns
ns
Over recommended range of supply voltage and operating free-air temperature, VREF = 1.0V (unless otherwise noted). CL = 30 pF for
B-Port and CL = 50 pF for A-Port.
Symbol
tPLH
From
To
(Input)
(Output)
A
B
tPHL
tPLH
LEAB
B
tPHL
tPLH
CLKAB
B
tPHL
tPLH
CLKAB
CLKOUT
tPHL
tPLH
OEAB
tPHL
(CLKAB) (Note 13)
tSKEW
B (Note 14)
B
CLKOUT
tRISE
Transition time, B outputs (20% to 80%)
tFALL
Transition time, B outputs (20% to 80%)
tPLH
ns
1.0
4.3
6.5
1.0
5.0
8.2
1.8
4.5
6.7
1.5
5.3
8.7
1.8
4.6
6.7
1.5
5.4
8.7
3.0
6.2
10.0
3.0
5.7
10.0
1.6
4.4
8.0
1.3
6.1
9.8
0
2
2.6
1.4
5.0
7.2
A
2.1
4.2
6.3
1.9
3.3
5.0
2.3
4.4
6.8
A
CLKOUT
CLKIN
OEBA
A or CLKIN
tPHZ, tPLZ
ns
ns
ns
ns
2.6
LEBA
CLKBA
ns
ns
5.6
tPHL
tPZH, tPZL
Unit
2.0
tPHL
tPLH
Max
A
tPHL
tPLH
Typ
(Note 12)
B
tPHL
tPLH
Min
8.2
2.1
3.5
5.2
3.0
6.0
10.0
3.0
6.43
10.0
1.5
5.0
6.4
1.4
3.9
8.0
ns
ns
ns
ns
ns
Note 12: All typical values are at VCC = 3.3V, VCCQ = 5.0V, and TA = 25°C.
Note 13: Three-state delays are actually synchronous with CLKAB
Note 14: Skew is defined as the absolute value of the difference between the actual propagation delays for the CLKOUT pin and any B output transition
when measured with reference to CLKAB↑. This guarantees the relationship between B output data and CLKOUT such that data is coincident or ahead of
CLKOUT. This specification is guaranteed but not tested.
7
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GTLP16617
AC Electrical Characteristics
GTLP16617
Test Circuits and Timing Waveforms
Test Circuit for B Outputs
Test Circuit for A Outputs
CL includes probes and jig capacitance.
CL includes probes and jig capacitance.
For B-Port outputs, CL = 30 pF is used for worst case
edge rate.
Voltage Waveforms Pulse Duration
(Vm = 1.5V for A-Port and 1.0V for B-Port)
Voltage Waveforms Propagation Delay and Setup and Hold Times
(Vm = 1.5V for A-Port and 1.0V for B-Port)
Voltage Waveforms Enable and Disable Times (A-Port)
Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with
internal conditions such that the output is high except when disabled by the output control.
All input pulses have the following characteristics: frequency = 10 MHz, tr = t f = 2 ns, Z O = 50Ω. The outputs are measured one at a time with one transition
per measurement.
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8
GTLP16617
Physical Dimensions inches (millimeters) unless otherwise noted
56-Lead Shrink Small Outline Package, JEDEC MO-118 0.300” Wide
Package Number MS56A
9
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GTLP16617 17-Bit TTL/GTLP Synchronous Bus Transceiver with Buffered Clock
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
56-Lead Thin Shrink Small Outline Package, JEDEC MO-153, 6.1mm Wide
Package Number MTD56
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
1. Life support devices or systems are devices or systems
device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the
sonably expected to cause the failure of the life support
body, or (b) support or sustain life, and (c) whose failure
device or system, or to affect its safety or effectiveness.
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
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user.
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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