Product Folder Order Now Support & Community Tools & Software Technical Documents ESD401 SLVSE49A – JULY 2017 – REVISED JULY 2017 ESD401 1-Channel ESD Protection Diode With Robust IEC ESD Performance 1 Features 3 Description • The ESD401 is a bidirectional TVS ESD protection diode featuring low RDYN and low clamping voltage. The ESD401 is rated to dissipate ESD strikes exceeding the maximum level specified in the IEC 61000-4-2 international standard (Level 4). The low dynamic resistance (0.7 Ω) to ensure system level protection against transient events. This device features a 0.77 pF IO capacitance making it ideal for protecting interfaces such as USB 2.0. The device can operate with ultra-low leakage up to ±5.5 V and survive DC faults up to 8.3 V. • • • • • • • • The ESD401 is offered in the industry standard 0402 (DPY) package. Device Information(1) PART NUMBER ESD401DPY • End Equipment – Wearables – Laptops and Desktops – Mobile and Tablets – Set-Top Boxes – DVR and NVR – TV and Monitors – EPOS (Electronic Point of Sale) Interfaces – 1 Gbps Ethernet – USB 2.0/1.1 with 5.5 V tolerance – GPIO – Pushbuttons/Keypad – Audio BODY SIZE (NOM) 0.60 mm × 1.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. 2 Applications • PACKAGE X1SON (2) Typical USB 2.0 Application Schematic 5-V Source VBUS DD+ 1 GND 1 USB Transceiver ESD401 • Robust IEC 61000-4-2 Level 4 ESD Protection – ±24-kV Contact Discharge – ±30-kV Air Gap Discharge IEC 61000-4-5 Surge Protection – 4.5 A (8/20 µs) – Low Vclamp of 12 V at 1.8 A IPP (8/20 µs) IEC 61000-4-4 EFT Protection – 80 A (5/50 ns) Bi-directional ESD diode to protect interfaces up to ± 5.5 V IO Capacitance: 0.77 pF (Typical) High DC Breakdown Voltage: 8.3 V (Typical) Ultra Low Leakage Current: 30 pA (Typical) Low Dynamic Resistance 0.7 Ω (Typical) Industrial Temperature Range: –40°C to +125°C Industry Standard 0402 Package ESD401 1 2 2 Copyright © 2017, Texas Instruments Incorporated 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. ESD401 SLVSE49A – JULY 2017 – REVISED JULY 2017 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 6.7 4 4 4 4 4 5 6 Absolute Maximum Ratings ...................................... ESD Ratings — JEDEC Specification ..................... ESD Ratings—IEC Specification .............................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Typical Characteristics .............................................. Detailed Description .............................................. 8 7.1 Overview ................................................................... 8 7.2 Functional Block Diagram ......................................... 8 7.3 Feature Description................................................... 8 7.4 Device Functional Modes.......................................... 9 8 Application and Implementation ........................ 10 8.1 Application Information............................................ 10 8.2 Typical Application ................................................. 10 9 Power Supply Recommendations...................... 12 10 Layout................................................................... 12 10.1 Layout Guidelines ................................................. 12 10.2 Layout Example .................................................... 12 11 Device and Documentation Support ................. 13 11.1 11.2 11.3 11.4 11.5 11.6 Documentation Support ........................................ Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 13 13 13 13 13 13 12 Mechanical, Packaging, and Orderable Information ........................................................... 13 4 Revision History Changes from Original (July 2017) to Revision A • 2 Page Updated Figure 9 andFigure 13 ............................................................................................................................................ 6 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ESD401 ESD401 www.ti.com SLVSE49A – JULY 2017 – REVISED JULY 2017 5 Pin Configuration and Functions DPY Package 2-Pin X1SON Top View 1 2 Pin Functions PIN NO. NAME I/O DESCRIPTION 1 IO I/O ESD Protected Channel. If used as ESD IO, connect pin 2 to ground 2 IO I/O ESD Protected Channel. If used as ESD IO, connect pin 1 to ground Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ESD401 3 ESD401 SLVSE49A – JULY 2017 – REVISED JULY 2017 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN Electrical fast transient Peak pulse MAX UNIT 80 A IEC 61000-4-5 power (tp - 8/20 µs) at 25°C 67 W IEC 61000-4-5 current (tp - 8/20 µs) at 25°C 4.5 A IEC 61000-4-4 (5/50 ns) at 25°C TA Operating free-air temperature –40 125 °C Tstg Storage temperature –65 155 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 6.2 ESD Ratings — JEDEC Specification VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) UNIT ±2500 Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) V ±1000 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 ESD Ratings—IEC Specification VALUE V(ESD) Electrostatic discharge IEC 61000-4-2 contact discharge ±24000 IEC 61000-4-2 air-gap discharge ±30000 UNIT V 6.4 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN MAX VIO Input pin voltage –5.5 5.5 UNIT V TA Operating free-air temperature –40 125 °C 6.5 Thermal Information ESD401 THERMAL METRIC (1) DPY (X1SON) UNIT 2 PINS RθJA Junction-to-ambient thermal resistance 420 °C/W RθJC(top) Junction-to-case (top) thermal resistance 169.3 °C/W RθJB Junction-to-board thermal resistance 276.1 °C/W ψJT Junction-to-top characterization parameter 122.1 °C/W ψJB Junction-to-board characterization parameter 157.3 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W (1) 4 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ESD401 ESD401 www.ti.com SLVSE49A – JULY 2017 – REVISED JULY 2017 6.6 Electrical Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER VRWM VBRF VBRR VHOLD VCLAMP Reverse stand-off voltage Breakdown voltage, Pin 1 to Pin 2 (1) Breakdown voltage, Pin 2 to Pin 1 (1) Holding voltage (2) Clamping voltage TEST CONDITIONS IIO < 10 nA MAX UNIT 5.5 V IIO =1 mA, at TA = 25°C 7.5 9.1 V IIO =1 mA, at TA = 25°C 7.5 9.1 V IIO =1 mA 8.3 IPP = 1 A, TLP, from Pin 1 to Pin 2 and Pin 2 to Pin 1, TA = 25°C 11 IPP = 5 A, TLP, from Pin 1 to Pin 2 and Pin 2 to Pin 1, TA = 25°C 16 IPP = 16 A, TLP, from Pin 1 to Pin 2 and Pin 2 to Pin 1, TA = 25°C 24 IPP = 1.8 A, IEC-61000-4-5 (tp - 8/20 µs) from Pin 1 to Pin 2 and Pin 2 to Pin 1, TA = 25°C 12 IPP = 4.5 A, IEC-61000-4-5 (tp - 8/20 µs) from Pin 1 to Pin 2 and Pin 2 to Pin 1, TA = 25°C 15 Leakage current, Pin 1 to Pin2 and PIn2 to Pin 1 VIO = ±2.5 V RDYN Dynamic resistance Measured between TLP IPP of 10 A and 20 A, Pin 2 to Pin 1 and Pin 1 to Pin2, TA = 25°C CL Line capacitance VIO = 0 V, f = 1 MHz, Pin 1 to Pin 2 and Pin2 to Pin1, TA = 25°C (2) TYP –5.5 ILEAK (1) MIN V V 0.03 10 0.7 0.77 nA Ω 0.95 pF VBRF and VBRR are defined as the voltage obtained at 1 mA when sweeping the voltage up, before the device latches into the snapback state. VHOLD is defined as the voltage when 1 mA is applied, after the device has successfully latched into the snapback state. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ESD401 5 ESD401 SLVSE49A – JULY 2017 – REVISED JULY 2017 www.ti.com 32 32 28 28 24 24 20 20 Current (A) Current (A) 6.7 Typical Characteristics 16 12 8 4 4 0 0 4 8 12 16 20 Voltage (V) 24 28 32 0 36 60 0 50 -10 40 -20 Voltage (V) Voltage (V) 10 30 20 0 -60 30 45 60 75 Time (ns) 90 -70 -15 105 120 135 150 4.5 80 Current (A) Power (W) 72 4 64 0.9 3.5 56 0.85 48 40 2 32 15 30 45 60 75 Time (ns) 90 105 120 135 150 D004 0.7 24 0.6 8 0.55 0 150 0.5 125 D002 0.8 16 100 36 0.75 1 50 75 Time (Ps) 32 0.95 1.5 25 28 1 Capacitance (pF) 3 2.5 0.5 24 Figure 4. –8-kV IEC 61000-4-2 Waveform, Pin 1 to Pin 2 Power (W) 5 0 0 D003 Figure 3. 8-kV IEC 61000-4-2 Waveform, Pin1 to Pin 2 0 -25 16 20 Voltage (V) -40 -50 15 12 -30 10 0 8 Figure 2. Negative TLP Curve, Pin 1 to Pin 2 (Plotted as Positive TLP Curve Pin 2 to Pin 1 70 -10 -15 4 D001 Figure 1. Positive TLP Curve, Pin 1 to Pin 2 Current (A) 12 8 0 0.65 -40 25 85 125 0 D005 Figure 5. Surge (IEC 61000-4-5) Curve (tp = 8/20 µs), Pin 1 to Pin 2 6 16 0.5 1 1.5 2 Bias Voltage (V) 2.5 3 3.5 D006 Figure 6. Capacitance vs Bias Voltage, Pin 1 to Pin 2 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ESD401 ESD401 www.ti.com SLVSE49A – JULY 2017 – REVISED JULY 2017 Typical Characteristics (continued) 0.001 2 1.8 1.6 0.0005 Leakage (nA) Current (A) 1.4 0 1.2 1 0.8 0.6 -0.0005 0.4 0.2 -0.001 -10 -8 -6 -4 -2 0 2 Voltage (V) 4 6 8 0 -40 10 -20 0 20 D007 Figure 7. DC Voltage Sweep I-V Curve, Pin 1 to Pin 2 40 60 80 Temperature (qC) 100 120 140 D008 Figure 8. Leakage Current vs. Temperature, Pin 1 to Pin 2 1 1.6 0 1.4 -1 Capacitance (pF) Insertion Loss (dB) 1.2 -2 -3 -4 -5 -6 1 0.8 0.6 0.4 -7 0.2 -8 -9 0.001 0 0.01 0.1 Frequency (GHz) 1 Figure 9. Insertion Loss 10 1 D009 2 3 4 5 Frequency (GHz) 6 7 8 D010 Figure 10. Capacitance vs. Frequency, Pin 1 to Pin 2 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ESD401 7 ESD401 SLVSE49A – JULY 2017 – REVISED JULY 2017 www.ti.com 7 Detailed Description 7.1 Overview The ESD401 is a bidirectional ESD Protection Diode with ultra-low clamping voltage. This device can dissipate ESD strikes above the maximum level specified by the IEC 61000-4-2 International Standard. The ultra-low clamping makes this device ideal for protecting any sensitive signal pins. 7.2 Functional Block Diagram IO GND Copyright © 2017, Texas Instruments Incorporated 7.3 Feature Description 7.3.1 IEC 61000-4-2 ESD Protection The I/O pins can withstand ESD events up to ±24-kV contact and ±30-kV air gap. An ESD-surge clamp diverts the current to ground. 7.3.2 IEC 61000-4-4 EFT Protection The I/O pins can withstand an electrical fast transient burst of up to 80 A (5/50 ns waveform, 4 kV with 50-Ω impedance). An ESD-surge clamp diverts the current to ground. 7.3.3 IEC 61000-4-5 Surge Protection The I/O pins can withstand surge events up to 4.5 A and 67W (8/20 µs waveform). An ESD-surge clamp diverts this current to ground. 7.3.4 IO Capacitance The capacitance between each I/O pin to ground is 0.77 pF (typical) and 0.95 pF (maximum). 7.3.5 DC Breakdown Voltage The DC breakdown voltage of each I/O pin is ±8.3 V typical. This ensures that sensitive equipment is protected from surges above the reverse standoff voltage of ±5.5 V. 7.3.6 Low Leakage Current The I/O pins feature an low leakage current of 10 nA (maximum) with a bias of ±2.5 V. 7.3.7 Low ESD Clamping Voltage The I/O pins feature an ESD clamp that is capable of clamping the voltage to 24 V (TLP IPP = 16 A). 7.3.8 Industrial Temperature Range This device features an industrial operating range of –40°C to +125°C. 7.3.9 Industry Standard Footprint The layout of this device makes it simple and easy to add protection to an existing layout. The packages offers flow-through routing, requiring minimal modification to an existing layout. 8 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ESD401 ESD401 www.ti.com SLVSE49A – JULY 2017 – REVISED JULY 2017 7.4 Device Functional Modes The ESD401 is a passive integrated circuit that triggers when voltages are above VBRF or below VBRR. During ESD events, voltages as high as ±24 kV (contact) or ±30 kV ( air) can be directed to ground via the internal diode network. When the voltages on the protected line fall below the trigger levels of ESD401 (usually within 10s of nano-seconds) the device reverts to passive. Figure 11 shows typical TLP behavior of bi-directional ESD device that does not exhibit snapback. + ve Ipp RDYN+ -Vhold-TLP -VBR-TLP -Vclamp-Ipp - ve -Vrwm Vrwm VBR-TLP Vhold-TLP Vclamp-Ipp + ve RDYNNote 1: VBR-TLP and Vhold-TLP shown here are from the TLP measurements and not to be confused with the DC measurements of VBRF,VBRR, and VHOLD in Table 6.6 -Ipp Note 2: Vrwm is not measured from the TLP curve. ,W¶V VKRZQ KHUH RQO\ WR VKRZ WKDW 9rwm < VBR-TLP - ve Figure 11. Typical TlpLP Behavior Of Bi-directional ESD Device that Does Not Exhibit Snapback Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ESD401 9 ESD401 SLVSE49A – JULY 2017 – REVISED JULY 2017 www.ti.com 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The ESD401 is a diode type TVS which is used to provide a path to ground for dissipating ESD events on highspeed signal lines between a human interface connector and a system. As the current from ESD passes through the TVS, only a small voltage drop is present across the diode. This is the voltage presented to the protected IC. The low RDYN of the triggered TVS holds this voltage, VCLAMP, to a safe level for the protected IC. 8.2 Typical Application 5-V Source VBUS DD+ 1 USB Transceiver 1 ESD401 ESD401 GND 2 2 Copyright © 2017, Texas Instruments Incorporated Figure 12. USB 2.0 ESD Schematic 8.2.1 Design Requirements For this design example, two ESD401 devices are being used in a USB 2.0 application. This provides a complete ESD protection scheme. Given the USB 2.0 application, the parameters listed in Table 1 are known. Table 1. Design Parameters DESIGN PARAMETER VALUE Signal range on DP-DM lines 0 V to 3.6 V Operating frequency on DP-DM lines up to 240 MHz or 480 Mbps 8.2.2 Detailed Design Procedure 8.2.2.1 Signal Range The ESD401 supports signal ranges between –5.5 V and 5.5 V, which supports the USB 2.0 signal range of 0 to 3.6 V on the DM/DP lines.. 8.2.2.2 Operating Frequency The ESD401 has a 0.85 pF (typical) capacitance, which supports the USB 2.0 data rates of 480 Mbps. 10 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ESD401 ESD401 www.ti.com SLVSE49A – JULY 2017 – REVISED JULY 2017 8.2.3 Application Curves 1 0 Insertion Loss (dB) -1 -2 -3 -4 -5 -6 -7 -8 -9 0.001 0.01 0.1 Frequency (GHz) 1 10 D009 Figure 13. Insertion Loss Figure 14. Eye Diagram - 3-Gbps Signal No Device Figure 15. Eye Diagram - 3-Gbps Signal With ESD401 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ESD401 11 ESD401 SLVSE49A – JULY 2017 – REVISED JULY 2017 www.ti.com 9 Power Supply Recommendations The ESD401 is a passive ESD device so there is no need to power it. Take care not to violate the recommended I/O specification (–5.5 V to 5.5 V) to ensure the device functions properly. 10 Layout 10.1 Layout Guidelines • • • The optimum placement is as close to the connector as possible. – EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces, resulting in early system failures. – The PCB designer must minimize the possibility of EMI coupling by keeping any unprotected traces away from the protected traces which are between the TVS and the connector. Route the protected traces as straight as possible. Eliminate any sharp corners on the protected traces between the TVS and the connector by using rounded corners with the largest radii possible. – Electric fields tend to build up on corners, increasing EMI coupling. 10.2 Layout Example VBUS To Power Supply ESD401 D- To USB Transceiver D+ ESD401 Legend Pin to GND GND USB2.0 Connector Figure 16. USB 2.0 ESD Layout 12 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ESD401 ESD401 www.ti.com SLVSE49A – JULY 2017 – REVISED JULY 2017 11 Device and Documentation Support 11.1 Documentation Support For related documentation see the following: ESD401DPY Evaluation Module 11.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 11.3 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.4 Trademarks E2E is a trademark of Texas Instruments. 11.5 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 11.6 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ESD401 13 PACKAGE OPTION ADDENDUM www.ti.com 3-Aug-2017 PACKAGING INFORMATION Orderable Device Status (1) ESD401DPYR ACTIVE Package Type Package Pins Package Drawing Qty X1SON DPY 2 10000 Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Op Temp (°C) Device Marking (4/5) -40 to 125 8I (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. 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Addendum-Page 1 Samples PACKAGE MATERIALS INFORMATION www.ti.com 3-Aug-2017 TAPE AND REEL INFORMATION *All dimensions are nominal Device ESD401DPYR Package Package Pins Type Drawing X1SON DPY 2 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 10000 180.0 9.5 Pack Materials-Page 1 0.72 B0 (mm) K0 (mm) P1 (mm) 1.12 0.43 2.0 W Pin1 (mm) Quadrant 8.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 3-Aug-2017 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ESD401DPYR X1SON DPY 2 10000 189.0 185.0 36.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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