TI1 LM48520TLBD Boosted stereo class d audio power amplifier Datasheet

LM48520, LM48520TLBD
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LM48520
SNAS367C – FEBRUARY 2008 – REVISED APRIL 2013
Boosted Stereo Class D Audio Power Amplifier
with Output Speaker Protection and Spread Spectrum
Check for Samples: LM48520, LM48520TLBD
FEATURES
DESCRIPTION
•
•
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•
•
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The LM48520 integrates a boost converter with a
high efficiency Class D stereo audio power amplifier
to provide up to 1W/ch continuous power into an 8Ω
speaker when operating from 2.7V to 5.0V power
supply with boost voltage (PV1) of 5.0V. The
LM48520 utilizes a proprietary spread spectrum pulse
width modulation technique that lowers RF
interference and EMI levels. The Class D amplifier is
a low noise, filterless PWM architecture that
eliminates the output filter, reducing external
component count, board area, power consumption,
system cost, and simplifying design.
1
2
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Click and Pop Suppression
Low 0.04μA Shutdown Current
78% Efficiency
Filterless Class D
2.7V - 5.0V Operation
4 Adjustable Gain Settings
Adjustable Output Swing Limiter with Soft
Clipping
Speaker Protection
Short Circuit Protection on Audio Amps
Independent Boost and Amplifier Shutdown
Pins
APPLICATIONS
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•
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Mobile Phones
PDAs
Portable media
Cameras
Handheld games
KEY SPECIFICATIONS
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Quiescent Power Supply Current: 11.5 mA(typ)
Output Power (RL = 8Ω, THD+N ≤ 1%,
VDD = 3.3V,PV1 = 5.0V): 1.1 W(typ)
Shutdown Current: 0.04 μA(typ)
The LM48520 is designed for use in mobile phones
and other portable communication devices. The high
(78%) efficiency extends battery life when compared
to Boosted Class AB amplifiers. The LM48520
features a low-power consumption shutdown mode.
Shutdown may be enabled by driving the Shutdown
pin to a logic low (GND). Also, external leakage is
minimized via control of the ground reference via the
SW-OUT pin .
The LM48520 has 4 gain options which are pin
selectable via Gain0 and Gain1 pins. Output short
circuit prevents the device from damage during fault
conditions. Superior click and pop suppression
eliminates audible transients during power-up and
shutdown.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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Typical Application
L1
V1 = VFB ( 1+ R1/R2)
6.8 PH
Cs1
2.2 PF
2.7V to 5.0V
D1
Cf1
330 pF
BstFB
SW-GND
R2
16.2k
SS
Boost SD
Amp SD
Gain0
FB-GND
Cs
Cs2
4.7 PF
PV1
Boost SD
V1
Amp SD
Gain0
Gain1
Gain1
Vlimit
Vlimit
GND
PGND
1 PF
INPUT R
Co
100 PF
SW
VDD
0.1 PF
R1
40.2k
INROUTR+
Ci
OUTR-
1 PF
INR+
Ci
1 PF
INPUT L
INLCi
OUTL+
1 PF
OUTLINL+
Ci
Figure 1. Typical LM48520 Audio Amplifier Application Circuit
Connection Diagram
Top View
1
2
3
4
5
A
VDD
BstFB
Soft
Start
SW_
GND
SW
B
INR+
INR-
FB_GND
INL-
INL+
C
V1
BstSD
GND
Gain0
PV1
D
AmpSD
OUTR+
NC
OUTL+
GAIN1
E
VLimit
OUTR-
PGND
OUTL-
NC
Figure 2. DSBGA Package
See Package Number YZR0025AAA
2
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Pin Descriptions
Pin Designator
Pin Name
Pin Function
A1
VDD
A2
BstFB
A3
Soft Start
Soft start capacitor
A4
SW_GND
Booster ground
A5
SW
Drain of the Internal FET switch
B1
INR+
Non-inverting right channel input
B2
INR-
Inverting right channel input
B3
FB_GND
B4
INL-
Inverting left channel input
Non-inverting left channel input
Power Supply
Regulator Feedback Input. Connect BstFB to an external resistive voltage divider to
set the boost output voltage.
Ground return for R1, R2 resistor divider
B5
INL+
C1
V1
C2
BstSD
C3
GND
Ground
C4
Gain0
Gain setting input 0
C5
PV1
D1
AmpSD
Amplifier active low shutdown
D2
OUTR+
Non-inverting right channel output
D3
NC
D4
OUTL+
Amplifier supply voltage. Connect to PV1.
Regulator active low shutdown
Amplifier H-bridge power supply. Connect to V1.
No connect
Non-inverting left channel output
D5
Gain1
Gain setting input 1
E1
VLimit
Set to control output clipping level
E2
OUTR-
Inverting right channel output
E3
PGND
Power ground
E4
OUTL-
Inverting left channel output
E5
NC
No connect
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings
(1) (2)
Supply Voltage (VDD, V1)
6V
−65°C to +150°C
Storage Temperature
−0.3V to VDD + 0.3V
Input Voltage
Power Dissipation
(3)
Internally limited
ESD Susceptibility
(4)
2000V
ESD Susceptibility
(5)
200V
Junction Temperature
150°C
Thermal Resistance θJA (YZR0025AAA)
(1)
(2)
(3)
(4)
(5)
40.5 °C/W
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the
Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication
of device performance.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θJA, and the ambient temperature,
TA. The maximum allowable power dissipation is PDMAX = (TJMAX − TA) / θJA or the given in Absolute Maximum Ratings, whichever is
lower.
Human body model, 100pF discharged through a 1.5kΩ resistor.
Machine Model, 220pF–240pF discharged through all pins.
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Operating Ratings
Temperature Range
TMIN ≤ TA ≤ TMAX
−40°C ≤ TA ≤ +85°C
2.7V ≤ VDD ≤ 5.0V
Supply Voltage (VDD)
Amplifier Voltage (V1 )
2.4V ≤ V1 ≤ 5.5V
Not under Boosted Condition
Amplifier Voltage (PV1 )
3.0V ≤ PV1 ≤ 5.0V
Under Boosted Condition
Electrical Characteristics VDD = 3.3V
(1) (2)
The following specifications apply for VDD = 3.3V, AV = 6dB, RL = 15µH + 8Ω +15µH, fIN = 1kHz, unless otherwise specified.
Limits apply for TA = 25°C, R1 = 40.2kΩ, R2 = 16.2kΩ, V1 = PV1 = 5V, Vlimit = GND. All electrical specifications are for amplifier
and booster.
LM48520
Parameter
Test Conditions
Typ
(3)
Limit
(4) (5)
Units
(Limits)
15.5
mA (max)
VIN = 0, RLOAD = ∞
IDD
Quiescent Power Supply Current
VDD = 2.7V
14.8
VDD = 3.3V
11.5
VDD = 5.0V
8.0
0.04
ISD
Shutdown Current
VSHUTDOWN = GND
1.0
μA (max)
VSDIH
Shutdown Voltage Input High
For SD Boost, SD Amp
1.4
V
VSDIL
Shutdown Voltage Input Low
For SD Boost, SD Amp
0.4
TWU
Wake-up Time
Amplifier + Booster Wakeup
VOS
Output Offset Voltage
AV
Gain
PO
Output Power
5
mV
6
dB
G0 = VDD, G1 = GND
RL = ∞
12
dB
G0 = GND, G1 = VDD
RL = ∞
18
dB
G0, G1 = VDD
RL = ∞
24
dB
RL = 15μH + 8Ω + 15μH
THD+N = 1% (max),
f = 1kHz, 22kHz, BW
VDD = 3.3V
1.1
RL = 15μH + 8Ω + 15μH
THD+N = 10% (max),
f = 1kHz, 22kHz, BW
VDD = 3.3V
1.3
W
0.04
%
32
µVRMS
Total Harmonic Distortion + Noise
PO = 500mW, f = 1kHz,
RL = 15μH + 8Ω + 15μH,
VDD = 3.3V
εOS
Output Noise
VDD = 3.6V, f = 20Hz – 20kHz
Inputs to AC GND, A weighted
(3)
(4)
(5)
4
ms
G0, G1 = GND
RL = ∞
THD+N
(1)
(2)
V
3
0.87
W (min)
All voltages are measured with respect to the GND pin, unless otherwise specified.
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the
Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication
of device performance.
Typicals are measured at 25°C and represent the parametric norm.
Limits are specified to AOQL (Average Outgoing Quality Level).
Datasheet min/max specification limits are ensured by design, test, or statistical analysis.
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Electrical Characteristics VDD = 3.3V (1)(2) (continued)
The following specifications apply for VDD = 3.3V, AV = 6dB, RL = 15µH + 8Ω +15µH, fIN = 1kHz, unless otherwise specified.
Limits apply for TA = 25°C, R1 = 40.2kΩ, R2 = 16.2kΩ, V1 = PV1 = 5V, Vlimit = GND. All electrical specifications are for amplifier
and booster.
LM48520
Parameter
Test Conditions
Typ
(3)
Limit
(4) (5)
Units
(Limits)
VRIPPLE = 200mVP-P Sine,
fRIPPLE = = 217Hz
82
dB
VRIPPLE = 200mVP-P Sine,
fRIPPLE = = 1kHz
79
dB
Common Mode Rejection Ratio
VRIPPLE = 1VP-P, fRIPPLE = 217Hz
67
dB
η
Efficiency
PO = 1W, f = 1kHz,
RL = 15μH + 8Ω + 15μH
VDD = 3.3V
VDD = 4.2V
78
%
VFB
Feedback Pin Reference Voltage
See
Vout clipped
Output Voltage in clipped state with
soft clip activated
Vlimit = 2V, RL = 8Ω, VIN = 2VP
Vout clipped = 8/3 (PV1 – 2Vlimit)
PSRR
CMRR
(6)
Power Supply Rejection Ratio
(6)
1.24
2.5
V
1.9
3.2
Vpk (min)
Vpk (max)
Feedback pin reference voltage is measured with the Audio Amplifier disconnected from the Boost converter (the Boost converter is
unloaded).
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Typical Performance Characteristics
THD+N vs Frequency
VDD = 3.3V, POUT = 900mW, RL = 8Ω
100
100
10
10
THD + N (%)
THD + N (%)
THD+N vs Frequency
VDD = 2.7V, POUT = 800mW, RL = 8Ω
1
0.1
0.01
0.1
0.01
100
1k
0.001
20
10k 20k
Figure 4.
THD+N vs Frequency
VDD = 5.0V, POUT = 1W, RL = 8Ω
THD+N vs Output Power
VDD = 2.7V, RL = 8Ω
10
10
1
0.1
0.01
1
0.1
0.01
100
1k
0.001
10m
10k 20k
1
Figure 5.
Figure 6.
THD+N vs Output Power
VDD = 3.3V, RL = 8Ω
THD+N vs Output Power
VDD = 5.0V, RL = 8Ω
100
100
10
10
THD + N (%)
THD + N (%)
100m
2
OUTPUT POWER (W)
FREQUENCY (Hz)
1
0.1
0.01
1
0.1
0.01
100m
1
2
0.001
10m
OUTPUT POWER (W)
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100m
1
2
OUTPUT POWER (W)
Figure 7.
6
10k 20k
FREQUENCY (Hz)
100
0.001
10m
1k
Figure 3.
100
0.001
20
100
FREQUENCY (Hz)
THD + N (%)
THD + N (%)
0.001
20
1
Figure 8.
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Typical Performance Characteristics (continued)
Power Dissipation vs Output Power
VDD = 2.7V, RL = 8Ω, f = 1kHz
Power Dissipation vs Output Power
VDD = 3.3V, RL = 8Ω, f = 1kHz
800
750
POWER DISSIPATION (mW)
POWER DISSIPATION (mW)
700
600
450
300
150
600
500
400
300
200
100
POUT = POUTL + POUTR
POUT = POUTL + POUTR
0
0
0
0
500
1000
1500
2000
2500
500
2000
2500
Figure 9.
Figure 10.
Power Dissipation vs Output Power
VDD = 5.0V, RL = 8Ω, f = 1kHz
Efficiency vs Output Power
VDD = 2.7V, RL = 8Ω, f = 1kHz
3000
100
800
90
700
80
EFFICIENCY (%)
600
500
400
300
200
70
60
50
40
30
20
100
10
POUT = POUTL + POUTR
0
0
0
500 1000 1500 2000 2500 3000 3500
0
500
Figure 11.
Efficiency vs Output Power
VDD = 3.3V, RL = 8Ω, f = 1kHz
90
80
80
70
70
EFFICIENCY (%)
90
60
50
40
30
50
40
30
20
10
10
1000 1500
2500
60
20
500
2000
Efficiency vs Output Power
VDD = 5.0V, RL = 8Ω, f = 1kHz
100
0
1500
Figure 12.
100
0
1000
OUTPUT POWER (mW)
OUTPUT POWER (mW)
EFFICIENCY (%)
1500
OUTPUT POWER (mW)
OUTPUT POWER (mW)
POWER DISSIPATION (mW)
1000
2000 2500 3000
0
0
500
1000
1500
2000
OUTPUT POWER (mW)
OUTPUT POWER (mW)
Figure 13.
Figure 14.
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Typical Performance Characteristics (continued)
PSRR vs Frequency
VDD =3.3V, VRIPPLE = 200mVP-P, RL = 8Ω
0
0
-10
-10
-20
-20
-30
-30
PSRR (dB)
CMRR (dB)
CMRR vs Frequency
VDD =3.3V, VRIPPLE = 1VP-P, RL = 8Ω
-40
-50
-60
-40
-50
-60
-70
-70
-80
-80
-90
-90
10
100
1000
10000
-100
10
100000
100
10000
100000
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 15.
Figure 16.
Supply Current vs Supply Voltage
No Load
Output Power vs Supply Voltage
RL = 8Ω, f = 1kHz
4
16
THD+N = 10%
OUTPUT POWER (W)
14
SUPPLY CURRENT (mA)
1000
12
10
8
6
4
3
2
THD+N = 1%
1
2
0
0
2
2.5
3
3.5
4
4.5
5
2
5.5
3.5
4
4.5
5
5.5
Figure 17.
Figure 18.
Boost Output Voltage vs Load Current
VDD = 2.7V
Boost Output Voltage vs Load Current
VDD = 3.3V
5.4
5.2
BOOST OUTPUT VOLTAGE (V)
BOOST OUTPUT VOLTAGE (V)
3
SUPPLY VOLTAGE (V)
5.4
5
4.8
4.6
4.4
4.2
4
0
8
2.5
SUPPLY VOLTAGE (V)
200
400
600
800 1000 1200 1400
5.2
5
4.8
4.6
4.4
0
200
400
600
800 1000 1200 1400
LOAD CURRENT (mA)
LOAD CURRENT (mA)
Figure 19.
Figure 20.
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Typical Performance Characteristics (continued)
Boost Output Voltage vs Load Current
VDD = 5.0V
BOOST OUTPUT VOLTAGE (V)
5.4
5.3
5.2
5.1
5
0
200
400
600
800 1000 1200 1400
LOAD CURRENT (mA)
Figure 21.
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APPLICATION INFORMATION
General Amplifier Function
The LM48520 features a Class D audio power amplifier that utilizes a filterless modulation scheme, reducing
external component count, conserving board space and reducing system cost. The outputs of the device
transition from PV1 to GND with a 300kHz switching frequency. With no signal applied, the outputs (VLS+ and
VLS-) switch with a 50% duty cycle, in phase, causing the two outputs to cancel. This cancellation results in no
net voltage across the speaker, thus there is no current to the load in the idle state.
With the input signal applied, the duty cycle (pulse width) of the LM48520 outputs changes. For increasing output
voltage, the duty cycle of VLS+ increases, while the duty cycle of VLS-decreases. For decreasing output voltages,
the converse occurs. The difference between the two pulse widths yields the differential output voltage.
Differential Amplifier Explanation
The amplifier portion of the LM48520 is a fully differential amplifier that features differential input and output
stages. A differential amplifier amplifies the difference between the two input signals. Traditional audio power
amplifiers have typically offered only single-ended inputs resulting in a 6dB reduction in signal to noise ratio
relative to differential inputs. The amplifier also offers the possibility of DC input coupling which eliminates the
two external AC coupling, DC blocking capacitors. The amplifier can be used, however, as a single ended input
amplifier while still retaining it's fully differential benefits. In fact, completely unrelated signals may be placed on
the input pins. The amplifier portion of the LM48520 simply amplifies the difference between the signals. A major
benefit of a differential amplifier is the improved common mode rejection ratio (CMRR) over single input
amplifiers. The common-mode rejection characteristic of the differential amplifier reduces sensitivity to ground
offset related noise injection, especially important in high noise applications.
Amplifier Dissipation and Efficiency
The major benefit of a Class D amplifier is increased efficiency versus a Class AB. The efficiency of the
LM48520 is attributed to the region of operation of the transistors in the output stage. The Class D output stage
acts as current steering switches, consuming negligible amounts of power compared to their Class AB
counterparts. Most of the power loss associated with the output stage is due to the IR loss of the MOSFET onresistance, along with switching losses due to gate charge.
Regulator Power Dissipation
At higher duty cycles, the increased ON-time of the switch FET means the maximum output current will be
determined by power dissipation within the LM48520 FET switch. The switch power dissipation from ON-time
conduction is calculated by:
PD(SWITCH) = DC x (IINDUCTOR(AVE))2 x RDS(ON)
(W)
(1)
where:
Where DC is the duty cycle
Shutdown Function
The LM48520 features independent amplifier and regulator shutdown controls, allowing each portion of the
device to be disabled or enabled independently. AmpSD controls the Class D amplifiers, while BstSD controls
the regulator. Driving either inputs low disables the corresponding portion of the device, and reducing supply
current.
When the regulator is disabled, both FB_GND switches open, further reducing shutdown current by eliminating
the current path to GND through the regulator feedback network. With the regulator disabled, there is still a
current path from VDD, through the inductor and diode, to the amplifier power supply. This allows the amplifier to
operate even when the regulator is disabled. The voltage at PV1 and V1 will be:
VDD — [VD + (IL x DCR)]
(2)
where:
VD is the forward voltage of the Schottky diode
IL is the current through the inductor
10
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DCR is the DC resistance of the inductor
Additionally, when the regulator is disabled, an external voltage between 2.4V and 5.5V can be applied directly to
PV1 and V1 to power the amplifier.
It is best to switch between ground and VDD for minimum current consumption while in shutdown. The LM48520
may be disabled with shutdown voltages in between GND and VDD, the idle current will be greater than the
typical 0.1µA value. Increased THD+N may also be observed when a voltage of less than VDD is applied to
AmpSD.
Proper Selection of External Components
Proper selection of external components in applications using integrated power amplifiers, and switching DC-DC
converters, is critical for optimizing device and system performance. Consideration to component values must be
used to maximize overall system quality.
The best capacitors for use with the switching converter portion of the LM48520 are multi-layer ceramic
capacitors. They have the lowest ESR (equivalent series resistance) and highest resonance frequency, which
makes them optimum for high frequency switching converters.
When selecting a ceramic capacitor, only X5R and X7R dielectric types should be used. Other types such as
Z5U and Y5F have such severe loss of capacitance due to effects of temperature variation and applied voltage,
they may provide as little as 20% of rated capacitance in many typical applications. Always consult capacitor
manufacturer’s data curves before selecting a capacitor. High-quality ceramic capacitors can be obtained from
Taiyo-Yuden, AVX, and Murata.
Power Supply Bypassing for Amplifier
As with any amplifier, proper supply bypassing is critical for low noise performance and high power supply
rejection. The capacitor location on both PV1, V1 and VDD pins should be as close to the device as possible.
Selecting Input Capacitor for Audio Amplifier
Input capacitors, CIN, in conjunction with the input impedance of the LM48520 forms a high pass filter that
removes the DC bias from an incoming signal. The AC-coupling capacitor allows the amplifier to bias the signal
to an optimal DC level. Assuming zero source impedance, the -3dB point of the high pass filter is given by:
f(–3dB) = 1/2πRINCIN
(3)
Choose CIN such that f-3dB is well below that lowest frequency of interest. Setting f-3dB too high affects the lowfrequency responses of the amplifier. Use capacitors with low voltage coefficient dielectrics, such as tantalum or
aluminum electrolytic. Capacitors with high-voltage coefficients, such as ceramics, may result in increased
distortion at low frequencies. Other factors to consider when designing the input filter include the constraints of
the overall system. Although high fidelity audio requires a flat frequency response between 20Hz and 20kHz,
portable devices such as cell phones may only concentrate on the frequency range of the frequency range of the
spoken human voice (typically 300Hz to 4kHz). In addition, the physical size of the speakers used in such
portable devices limits the low frequency response; in this case, frequencies below 150Hz may be filtered out.
Selecting Output Capacitor (CO) for Boost Converter
A single 100µF low ESR tantalum capacitor provides sufficient output capacitance for most applications. Higher
capacitor values improve line regulation and transient response. Typical electrolytic capacitors are not suitable
for switching converters that operate above 500kHz because of significant ringing and temperature rise due to
self-heating from ripple current. An output capacitor with excessive ESR reduces phase margin and causes
instability.
Selecting Input Capacitor (Cs1) for Boost Converter
An input capacitor is required to serve as an energy reservoir for the current which must flow into the coil each
time the switch turns ON. This capacitor must have extremely low ESR, so ceramic is the best choice. We
recommend a nominal value of 2.2µF, but larger values can be used. Since this capacitor reduces the amount of
voltage ripple seen at the input pin, it also reduces the amount of EMI passed back along that line to other
circuitry.
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Selecting Soft-Start (CSS) Capacitor
The soft-start function charges the boost converter reference voltage slowly. This allows the output of the boost
converter to ramp up slowly thus limiting the transient current at startup. Selecting a soft-start capacitor (CSS)
value presents a trade off between the wake-up time and the startup transient current. Using a larger capacitor
value will increase wake-up time and decrease startup transient current while the apposite effect happens with a
smaller capacitor value. A general guideline is to use a capacitor value 1000 times smaller than the output
capacitance of the boost converter (CO). A 0.1uF soft-start capacitor is recommended for a typical application.
Setting the Output Voltage (V1) of boost Converter
The output voltage is set using the external resistors R1 and R2 (see Figure 1). A value of approximately 13.3kΩ
is recommended for R2 to establish a divider current of approximately 92µA. R1 is calculated using the formula:
R1 = R2 X (V1/1.23 − 1)
(4)
Feed-Forward Compensation for Boost Converter
Although the LM48520's internal Boost converter is internally compensated, the external feed-forward capacitor
Cf is required for stability (see Figure 1). Adding this capacitor puts a zero in the loop response of the converter.
The recommended frequency for the zero fz should be approximately 6kHz. Cf1 can be calculated using the
formula:
Cf = 1 / (2 X R1 X fz)
(5)
Selecting Diodes for Boost
The external diode used in Figure 1 should be a Schottky diode. A 20V diode such as the MBRS320T3 is
recommended.
The MBRS320T3 series of diodes are designed to handle a maximum average current of 3A.
Duty Cycle
The maximum duty cycle of the boost converter determines the maximum boost ratio of output-to-input voltage
that the converter can attain in continuous mode of operation. The duty cycle for a given boost application is
defined as:
Duty Cycle = VOUT + VDIODE - VIN/ VOUT + VDIODE - VSW
(6)
This applies for continuous mode operation.
Selecting Inductor Value
Inductor value involves trade-offs in performance. Larger inductors reduce inductor ripple current, which typically
means less output voltage ripple (for a given size of output capacitor). Larger inductors also mean more load
power can be delivered because the energy stored during each switching cycle is:
E = L/2 X (IP)2
(7)
Where “lp” is the peak inductor current. The LM48520 will limit its switch current based on peak current. With IP
fixed, increasing L will increase the maximum amount of power available to the load. Conversely, using too little
inductance may limit the amount of load current which can be drawn from the output. Best performance is usually
obtained when the converter is operated in “continuous” mode at the load current range of interest, typically
giving better load regulation and less output ripple. Continuous operation is defined as not allowing the inductor
current to drop to zero during the cycle. Boost converters shift over to discontinuous operation if the load is
reduced far enough, but a larger inductor stays continuous over a wider load current range.
During the TBDµs ON-time, the inductor current ramps up TBDA and ramps down an equal amount during the
OFF-time. This is defined as the inductor “ripple current”. It can also be seen that if the load current drops to
about TBDmA, the inductor current will begin touching the zero axis which means it will be in discontinuous
mode. A similar analysis can be performed on any boost converter, to make sure the ripple current is reasonable
and continuous operation will be maintained at the typical load current values.
12
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SNAS367C – FEBRUARY 2008 – REVISED APRIL 2013
Maximum Switch Current
The maximum FET switch current available before the current limiter cuts in is dependent on duty cycle of the
application. This is illustrated in a graph in the Typical Performance Characteristics section which shows typical
values of switch current as a function of effective (actual) duty cycle.
Calculating Output Current of Boost Converter (IAMP)
The load current is related to the average inductor current by the relation:
ILOAD = IIND(AVG) x (1 - DC)
(8)
where:
"DC" is the duty cycle of the application
The switch current can be found by:
ISW = IIND(AVG) + 1/2 (IRIPPLE)
(9)
Inductor ripple current is dependent on inductance, duty cycle, input voltage and frequency:
IRIPPLE = DC x (VIN-VSW) / (f x L)
(10)
combining all terms, we can develop an expression which allows the maximum available load current to be
calculated:
ILOAD(max) = (1–DC)x(ISW(max)–DC(VIN-VSW))/fL
(11)
The equation shown to calculate maximum load current takes into account the losses in the inductor or turn-OFF
switching losses of the FET and diode.
Design Parameters VSW and ISW
The value of the FET "ON" voltage (referred to as VSW in Equation 4 thru Equation 9) is dependent on load
current. A good approximation can be obtained by multiplying the "ON Resistance" of the FET times the average
inductor current.
FET on resistance increases at VIN values below 5V, since the internal N-FET has less gate voltage in this input
voltage range (see Typical Performance Characteristics curves). Above VIN = 5V, the FET gate voltage is
internally clamped to 5V.
The maximum peak switch current the device can deliver is dependent on duty cycle. For higher duty cycles, see
Typical Performance Characteristics curves.
Inductor Suppliers
The recommended inductor for the LM48520 is the NR8040T6R8N from Taiyo Yuden. When selecting an
inductor, make certain that the continuous current rating is high enough to avoid saturation at peak currents,
where:
IIND = (PV1 / VDD) x ILOAD(BOOST)
(12)
A suitable core type must be used to minimize core (switching) losses, and wire power losses must be
considered when selecting the current rating.
PCB Layout Guidelines
High frequency boost converters require very careful layout of components in order to get stable operation and
low noise.
All components must be as close as possible to the LM48520 device. It is recommended that a four layer PCB
be used so that internal ground planes are available.
Some additional guidelines to be observed (all designators are referencing Figure 1):
1. Keep the path between L1, D1, and Co extremely short. Parasitic trace inductance in series with D1 and Co
will increase noise and ringing.
2. The feedback components R1, R2 and Cf1 must be kept close to the FB pin to prevent noise injection on the
FB pin trace.
3. Since the external components of the boost converter are switching, L1 and D1 should be kept away from
Copyright © 2008–2013, Texas Instruments Incorporated
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SNAS367C – FEBRUARY 2008 – REVISED APRIL 2013
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the input traces to prevent the noise from injecting into the input.
4. The power supply bypass capacitors, Cs1 and Cs2 should be placed as close to the LM48520 device as
possible.
GROUNDING GUIDELINES
There are three grounds on the LM48520, GND, SW_GND, and PGND. When laying out the PCB, it is critical to
connect the grounds as close to the device as possible. The simplest way to do that is to place vias close to the
GND, SW_GND, and PGND bumps and connect the GND, SW_GND, and PGND vias using a single ground
plane in an inner layer of the PCB.
Output Speaker Protection Function
The LM48520’s output voltage limiter can be used to set a minimum and maximum output voltage swing
magnitude. The voltage applied to the VLimit pin controls the limit on the output voltage level. The output level is
determined by the following equation:
Vout clipped = 8/3 * (PV1 — 2 * Vlimit)
(13)
where:
Vout clipped = the desired output level measured in Vpk
PV1 = Boost output voltage
Vlimit is the voltage applied the the Vlimit pin on the LM48520
or
Vout clipped = 1/2 * (PV1 — 3/8 * Vout clipped)
(14)
To disable the limiter, set Vlimit = 0V.
Figure 22 provides an example of how the output voltage limiter functions with VDD = 3.3V, AV = 6dB, PV1 = 5V,
Vlimit = 2V, RL = 8Ω, VIN = 2VP.
4
No Clipping
3
OUTPUT (V)
2
With Soft
Clipping
1
0
-1
-2
-3
-4
200 Ps
Figure 22. Soft Clipping vs No Clipping
Revision History
14
Rev
Date
1.0
02/27/08
Initial release.
1.01
03/07/08
Added the Soft clipping vs No clipping curve.
1.02
03/12/08
Text edits.
C
04/05/13
Changed layout of National Data Sheet to TI format.
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Description
Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: LM48520 LM48520TLBD
PACKAGE OPTION ADDENDUM
www.ti.com
24-Sep-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
LM48520TL/NOPB
ACTIVE
Package Type Package Pins Package
Drawing
Qty
DSBGA
YZR
25
250
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
Op Temp (°C)
Device Marking
(4/5)
-40 to 85
GI5
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
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24-Sep-2015
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Sep-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
LM48520TL/NOPB
Package Package Pins
Type Drawing
SPQ
DSBGA
250
YZR
25
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
178.0
8.4
Pack Materials-Page 1
2.69
B0
(mm)
K0
(mm)
P1
(mm)
2.69
0.76
4.0
W
Pin1
(mm) Quadrant
8.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Sep-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LM48520TL/NOPB
DSBGA
YZR
25
250
210.0
185.0
35.0
Pack Materials-Page 2
MECHANICAL DATA
YZR0025xxx
0.600±0.075
D
E
TLA25XXX (Rev D)
D: Max = 2.511 mm, Min =2.451 mm
E: Max = 2.511 mm, Min =2.451 mm
4215055/A
NOTES:
A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994.
B. This drawing is subject to change without notice.
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12/12
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