Fairchild NM25C640 64k-bit serial cmos eeprom (serial peripheral interface (spi) synchronous bus) Datasheet

March 1999
NM25C640
64K-Bit Serial CMOS EEPROM
(Serial Peripheral Interface (SPI) Synchronous Bus)
General Description
Features
The NM25C640 is a 65,536-bit CMOS EEPROM with an SPI
compatible serial interface. The NM25C640 is designed for data
storage in applications requiring both non-volatile memory and insystem data updates. This EEPROM is well suited for applications
using the 68HC11 series of microcontrollers that support the SPI
interface for high speed communication with peripheral devices
via a serial bus to reduce pin count. The NM25C640 is implemented in Fairchild Semiconductor’s floating gate CMOS process
that provides superior endurance and data retention.
■ 2.75 MHz clock rate @ 4.5V to 5.5V
2.1 MHz @ 2.7V to 4.5V
■ 65,536 bits organized as 8,192 x 8
■ Multiple chips on the same 3-wire bus with separate chip
select lines
■ Self-timed programming cycle
■ Simultaneous programming of 1 to 32 bytes at a time
■ Status register can be polled during programming to monitor
READY/BUSY
The serial data transmission of this device requires four signal
lines to control the device operation: Chip Select (CS), Clock
(SCK), Data In (SI), and Serial Data Out (SO). All programming
cycles are completely self-timed and do not require an erase
before WRITE.
■ Write Protect (WP) pin and write disable instruction for both
hardware and software write protection
■ Block write protect feature to protect against accidental
writes
BLOCK WRITE protection is provided by programming the STATUS REGISTER with one of four levels of write protection.
Additionally, separate WRITE enable and WRITE disable instructions are provided for data protection.
■ Endurance: 1,000,000 data changes
■ Data retention greater than 40 years
■ Packages available: 8-pin DIP or 8-Pin SO
Hardware data protection is provided by the WP pin to protect
against inadvertent programming. The HOLD pin allows the serial
communication to be suspended without resetting the serial
sequence.
Block Diagram
CS
HOLD
SCK
SI
Instruction
Register
Program
Enable
Address
Counter/
Register
VPP
Decoder
1 of 8,192
VCC
VSS
Instruction
Decoder
Control Logic
and Clock
Generators
WP
High Voltage
Generator
and
Program
Timer
EEPROM Array
65,536 Bits
(8,192 x 8)
Read/Write Amps
Data In/Out Register
8 Bits
Data Out
Buffer
SO
Non-Volatile
Status Register
DS500041-1
© 1999 Fairchild Semiconductor Corporation
NM25C640 Rev. D.2
1
www.fairchildsemi.com
NM25C640 64K-Bit Serial CMOS EEPROM
(Serial Periphrial Interface (SPI) Synchronous Bus)
PRELIMINARY
NM25C640 64K-Bit Serial CMOS EEPROM
(Serial Periphrial Interface (SPI) Synchronous Bus)
Connection Diagram
Dual-In-Line Package (N)
and SO Package (M8)
CS
1
8
VCC
SO
2
7
HOLD
WP
3
6
SCK
VSS
4
5
SI
NM25C640
DS500041-2
Top View
Pin Names
CS
Chip Select Input
SO
Serial Data Output
WP
Write Protect
VSS
Ground
SI
Serial Data Input
SCK
Serial Clock Input
HOLD
Suspends Serial Data
VCC
Power Supply
Ordering Information
NM
25
C
XX
LZ E
XX
Letter
Description
N
M8
8-Pin DIP
8-Pin SO
Temp. Range
None
V
E
0 to 70°C
-40 to +125°C
-40 to +85°C
Voltage Operating Range
Blank
L
LZ
4.5V to 5.5V
2.7V to 4.5V
2.7V to 4.5V and
<1µA Standby Current
640
64K, mode 0
C
CMOS
Package
Density/Mode
Interface
2
NM25C640 Rev. D.2
25
SPI
NM
Fairchild Nonvolatile
Memory
www.fairchildsemi.com
Ambient Storage Temperature
Ambient Operating Temperature
NM25C640
NM25C640E
NM25C640V
-65°C to +150°C
All Input or Output Voltage with
Respect to Ground
+6.5V to -0.3V
Lead Temp. (Soldering, 10 sec.)
+300°C
ESD Rating
0°C to +70°C
-40°C to +85°C
-40°C to +125°C
Power Supply (VCC)
2000V
4.5V to 5.5V
DC and AC Electrical Characteristics 4.5V ≤ VCC ≤ 5.5V (unless otherwise specified)
Symbol
ICC
ICCSB
Parameter
Conditions
Min
Max
Units
Operating Current
CS = VIL
3
mA
Standby Current
CS = VCC
50
µA
IIL
Input Leakage
VIN = 0 to VCC
-1
+1
µA
IOL
Output Leakage
VOUT = GND to VCC
-1
+1
µA
VIL
CMOS Input Low Voltage
-0.3
VCC * 0.3
V
VCC * 0.7
VCC + 0.3
V
0.4
V
VIH
CMOS Input High Voltage
VOL
Output Low Voltage
IOL = 2.1 mA
VOH
Output High Voltage
IOH = -0.8 mA
fOP
SCK Frequency
2.75
MHz
tRI
Input Rise Time
2.0
µs
tFI
Input Fall Time
2.0
µs
VCC - 0.8
V
tCLH
Clock High Time
(Note 2)
155
ns
tCLL
Clock Low Time
(Note 2)
155
ns
tCSH
Min CS High Time
(Note 3)
240
ns
tCSS
CS Setup Time
176
ns
tDIS
Data Setup Time
50
ns
tHDS
HOLD Setup Time
90
ns
tCSN
CS Hold Time
155
ns
tDIN
Data Hold Time
50
ns
tHDN
HOLD Hold Time
90
ns
tPD
Output Delay
tDH
Output Hold Time
tLZ
HOLD to Output Low Z
tDF
Output Disable Time
tHZ
HOLD to Output High Z
tWP
Write Cycle Time
CL = 200 pF
135
ns
240
ns
290
ns
240
ns
10
ms
0
CL = 200 pF
1–32 Bytes
Capacitance TA = 25°C, f = 2.1/1 MHz (Note 4)
ns
AC Test Conditions
Output Load
Test
COUT
Output Capacitance
3
8
pF
Input Pulse Levels
0.1 * VCC – 0.9 * VCC
Input Capacitance
2
6
pF
Timing Measurement Reference Level
0.3 * VCC - 0.7 • VCC
CIN
Typ Max Units
CL = 200 pF
Symbol
Note 1: Stress above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the
device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Note 2: The fOP frequency specification specifies a minimum clock period of 1/fOP. Therefore, for every fOP clock cycle, tCLH + tCLL must be equal to or greater than 1/fOP. For
example, if the 2.1MHz period = 476ns and tCLH = 190ns, tCLL must be 286ns.
Note 3: CS must be brought high for a minimum of tCSH between consecutive instruction cycles.
Note 4: This parameter is periodically sampled and not 100% tested.
3
NM25C640 Rev. D.2
www.fairchildsemi.com
NM25C640 64K-Bit Serial CMOS EEPROM
(Serial Periphrial Interface (SPI) Synchronous Bus)
Standard Voltage 4.5 ≤ VCC ≤ 5.5V Specifications
Operating Conditions
Absolute Maximum Ratings (Note 1)
Ambient Storage Temperature
Ambient Operating Temperature
NM25C640L/LZ
NM25C640LZ/LZE
NM25C640LV
-65°C to +150°C
All Input or Output Voltage with
Respect to Ground
+6.5V to -0.3V
Lead Temp. (Soldering, 10 sec.)
+300°C
ESD Rating
0°C to +70°C
-40°C to +85°C
-40°C to +125°C
Power Supply (VCC)
2000V
2.7V–4.5V
DC and AC Electrical Characteristics 2.7V ≤ VCC ≤ 4.5V (unless otherwise specified)
Symbol
Parameter
Part
Conditions
25C640L/LE
25C640LZ/LZE
Min.
Max.
25C640LV
Min
Max
Units
ICC
Operating Current
ICCSB
Standby Current
IIL
Input Leakage
VIN = 0 to VCC
-1
1
IOL
Output Leakage
VOUT = GND to VCC
-1
1
VIL
Input Low Voltage
-0.3
0.3 * VCC
-0.3
0.3 * VCC
V
VIH
Input High Voltage
0.7 * VCC
VCC + 0.3
0.7 * VCC
VCC + 0.3
V
VOL
Output Low Voltage
IOL = 1.6 mA
0.4
V
VOH
Output High Voltage
IOH = –0.8 mA
fOP
SCK Frequency
2.1
1.0
MHz
tRI
Input Rise Time
2.0
2.0
µs
tFI
Input Fall Time
2.0
µs
tCLH
Clock High Time
(Note 6)
190
410
ns
tCLL
Clock Low Time
(Note 6)
190
410
ns
tCSH
Min. CS High Time
(Note 7)
240
500
ns
tCSS
CS Setup Time
240
500
ns
tDIS
Data Setup Time
100
100
ns
tHDS
HOLD Setup Time
90
240
ns
tCSN
CS Hold Time
240
500
ns
tDIN
Data Hold Time
100
100
ns
tHDN
HOLD Hold Time
90
240
ns
tPD
Output Delay
tDH
Output Hold Time
tLZ
HOLD Output Low Z
tDF
Output Disable Time
tHZ
HOLD to Output Hi Z
tWP
Write Cycle Time
L
LZ
CS = VIL
3
3
mA
CS = VCC
10
1
10
N/A
µA
µA
-1
1
µA
-1
1
µA
0.4
VCC - 0.8
VCC - 0.8
2.0
CL = 200 pF
240
500
ns
100
240
ns
240
500
ns
100
240
ns
15
15
ms
0
CL = 200 pF
1-32 Bytes
Capacitance TA = 25°C, f = 2.1/1 MHz (Note 8)
V
0
ns
AC Test Conditions
Output Load
Test
COUT
Output Capacitance
3
8
pF
Input Pulse Levels
0.1 * VCC - 0.9 * VCC
Input Capacitance
2
6
pF
Timing Measurement Reference Level
0.3 * VCC - 0.7 * VCC
CIN
Typ Max Units
CL = 200pF
Symbol
Note 5: Stress above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the
device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Note 6: The fOP frequency specification specifies a minimum clock period of 1/fOP. Therefore, for every fOP clock cycle, tCLH + tCLL must be equal to or greater than 1/fOP. For
example, if the 2.1MHz period = 476ns and tCLH = 190ns, tCLL must be 286ns.
Note 7: CS must be brought high for a minimum of tCSH between consecutive instruction cycles.
Note 8: This parameter is periodically sampled and not 100% tested.
4
NM25C640 Rev. D.2
www.fairchildsemi.com
NM25C640 64K-Bit Serial CMOS EEPROM
(Serial Periphrial Interface (SPI) Synchronous Bus)
Low Voltage 2.7V ≤ VCC ≤ 4.5V Specifications
Operating Conditions
Absolute Maximum Ratings (Note 5)
FIGURE 1. Synchronous Data Timing Diagram
tCSH
VIH
CS
VIL
VIH
tCSS
tCLH
SCK
tCSN
tCLL
VIL
tDIS
tDIN
VIH
SI
VIL
tPD
tDF
tDH
VOH
SO
VOL
FIGURE 2. Hold Timing
DS500041-3
SCK
tHDS
tHDN
tHDS
tHDN
HOLD
tHZ
tLZ
SO
DS500041-6
FIGURE 3. SPI Serial Interface
MASTER MCU
NM25C640
DATA OUT (MOSI)
SI
SO
SCK
CS
DATA IN (MISO)
SERIAL CLOCK (CLK)
SPI
CHIP
SELECTION
SS0
SS1
SI
SO
SCK
CS
SS2
SS3
SI
SO
SCK
CS
SI
SO
SCK
CS
DS500041-4
5
NM25C640 Rev. D.2
www.fairchildsemi.com
NM25C640 64K-Bit Serial CMOS EEPROM
(Serial Periphrial Interface (SPI) Synchronous Bus)
,,
,
AC Test Conditions (Continued)
HOLD: The HOLD pin is used in conjunction with the CS to select
the device. Once the device is selected and a serial sequence is
underway, HOLD may be forced low to suspend further serial
communication with the device without resetting the serial sequence. Note that HOLD must be brought low while the SCK pin
is low. The device must remain selected during this sequence. To
resume serial communication HOLD is brought high while the
SCK pin is low. The SO pin is at a high impedance state during
HOLD.
TABLE 1. Instruction Set
Instruction Instruction
Name
Opcode
Operation
WREN
00000110
Set Write Enable Latch
WRDI
00000100
Reset Write Enable Latch
RDSR
00000101
Read Status Register
WRSR
00000001
Write Status Register
READ
00000011
Read Data from Memory
Array
WRITE
00000010
Write Data to Memory Array
INVALID OP-CODE: After an invalid code is received, no data is
shifted into the NM25C640, and the SO data output pin remains
high impedance until a new CS falling edge reinitializes the serial
communication. See Figure 5 .
FIGURE 5. Invalid Op-Code
MASTER: The device that generates the serial clock is designated as the master. The NM25C640 can never function as a
master.
SLAVE: The NM25C640 always operates as a slave as the serial
clock pin is always an input.
TRANSMITTER/RECEIVER: The NM25C640 has separate pins
for data transmission (SO) and reception (SI).
MSB: The Most Significant Bit is the first bit transmitted and
received.
CHIP SELECT: The chip is selected when pin CS is low. When the
chip is not selected, data will not be accepted from pin SI, and the
output pin SO is in high impedance.
CS
SI
INVALID CODE
SO
DS500041-7
SERIAL OP-CODE: The first byte transmitted after the chip is
selected with CS going low contains the op-code that defines the
operation to be performed.
PROTOCOL: When connected to the SPI port of a 68HC11
microcontroller, the NM25C640 accepts a clock phase of 0 and a
clock polarity of 0. The SPI protocol for this device defines the byte
transmitted on the SI and SO data lines for proper chip operation.
See Figure 4.
FIGURE 4. SPI Protocol
CS
…
SCK
SI
Bit 7 Bit 6
…
Bit 0
SO
Bit 7
…
Bit 1
Bit 0
DS500041-5
Data is clocked in on the positive SCK edge and out on the
negative SCK edge.
6
NM25C640 Rev. D.2
NM25C640 64K-Bit Serial CMOS EEPROM
(Serial Periphrial Interface (SPI) Synchronous Bus)
Functional Description
www.fairchildsemi.com
TABLE 3. Block Write Protection Levels
READ SEQUENCE: Reading the memory via the serial SPI link
requires the following sequence. The CS line is pulled low to select
the device. The READ op-code is transmitted on the SI line
followed by the high order address byte (A12–A8), and the low
order address byte (A7–A0). The leading three bits in the high
order address byte will be ignored. After this is done, data on the
SI line becomes don’t care. The data (D7–D0) at the address
specified is then shifted out on the SO line. If only one byte is to
be read, the CS line can be pulled back to the high level. It is
possible to continue the READ sequence as the byte adress is
automatically incremented and data will continue to be shifted out.
When the highest address is reached (1FFF), the address counter
rolls over to lowest address (000) allowing the entire memory to be
read in one continuous READ cycle. See Figure 6.
Level
Status Register Bits
BP1
BP0
Array
Address
Protected
0
0
0
None
1
0
1
1800-1FFF
2
1
0
1000-1FFF
3
1
1
0000–1FFF
NM25C640 64K-Bit Serial CMOS EEPROM
(Serial Periphrial Interface (SPI) Synchronous Bus)
Functional Description (Continued)
WRITE ENABLE (WREN): When VCC is applied to the chip, it
“powers up” in the write disable state. Therefore, all programming
modes must be preceded by a WRITE ENABLE (WREN) instruction. Additionally, the WP must be held high during a write engble
instruction. At the completion of a WRITE or WRSR cycle the
device is automatically returned to the write disable state. Note
that a WRITE DISABLE (WRD) instruction will also return the
device to the write disable state. See Figure 8.
FIGURE 6. Read Sequence
CS
Read Byte H
Op-Code Addr. n
SI
Byte L
Addr. n
FIGURE 8. Write Enable
Data
n
SO
Data
n+1
Data
n+2
CS
Data
n+3
DS500041-8
SI
READ STATUS REGISTER (RDSR) : The Read Status Register
(RDSR) instruction provides access to the status register is used
to interrogate the READY/BUSY and WRITE ENABLE status of
the chip. Two non-volatile status register bits are used to select
one of four levels of BLOCK WRITE PROTECTION. The status
register format is shown in Table 2.
SO
DS500041-10
WRITE DISABLE (WRDI): To protect against accidental data
disturbance the WRITE DISABLE (WRDI) instruction disables all
programming modes. See Figure 9.
TABLE 2. Status Register Format
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
X
X
X
X
BP1
BP0
WEN
RDY
WREN Op-Code
FIGURE 9. Write Disable
CS
X = Don't Care.
SI
Status register Bit 0 = 0 (RDY) indicates that the device is READY;
Bit 0 = 1 indicates that a program cycle is in progress. Bit 1 = 0
(WEN) indicates that the device is not WRITE ENABLED; Bit 1 =
1 indicates that the device is WRITE ENABLED. Non-volatile
status register Bits 2 and 3 (BP0 and BP1) indicate the level of
BLOCK WRITE PROTECTION selected. The block write protection levels and corresponding status register control bits are
shown in Table 3. Note that if a RDSR instruction is executed
during a programming cycle only the RDY bit is valid. All
other bits are 1s. See Figure 7.
SO
WRDI Op-Code
DS500041-11
FIGURE 7. Read Status
CS
SI
SO
RDSR
Op-Code
SR Data
MSB…LSB
DS500041-9
7
NM25C640 Rev. D.2
www.fairchildsemi.com
At the completion of a WRITE cycle the device is automatically
returned to the write disable state.
WRITE SEQUENCE: To program the device, the WRITE PROTECT (WP) pin must be held high and two separate instructions
must be executed. The chip must first be write enabled via the
WRITE ENABLE instruction and then a WRITE instruction must
be executed. Moreover, the address of the memory location(s) to
be programmed must be outside the protected address field
selected by the Block Write Protection Level. See Table 3.
If the device is not WRITE enabled, the device will ignore the
WRITE instruction and return to the standby state when CS is
forced high. A new CS falling edge is required to re-initialize the
serial communication.
WRITE STATUS REGISTER (WRSR): The WRITE STATUS
REGISTER (WRSR) instruction is used to program the nonvolatile status register Bits 2 and 3 (BP0 and BP1). The WRITE
PROTECT (WP) pin must be held high and two separate instructions must be executed. The chip must first be write enabled via
the WRITE ENABLE instruction and then a WRSR instruction
must be executed.
A WRITE command requires the following sequence. The CS line
is pulled low to select the device, then the WRITE op-code is
transmitted on the SI line followed by the high order address byte
(A12-A8) and the low order address byte (A7–A0). The leading
five bits in the high order address byte will be ignored. The address
is followed by the data (D7–D0) to be written. Programming will
start after the CS pin is forced back to a high level. Note that the
LOW to HIGH transition of the CS pin must occur during the SCK
low time immediately after clocking in the D0 data bit. See Figure
10.
The WRSR command requires the following sequence. The CS
line is pulled low to select the device and then the WRSR op-code
is transmitted on the SI line followed by the data to be programmed. See Figure 12.
NM25C640 64K-Bit Serial CMOS EEPROM
(Serial Periphrial Interface (SPI) Synchronous Bus)
Functional Description (Continued)
FIGURE 10. End of WRITE Sequence
FIGURE 12. Write Status Register
CS
CS
SCK
WRSR
Op-Code
SI
SI
D2
D1
SR Data
xxxxBP1BP0xx
D0
SO
SO
DS500041-14
DS500041-12
The READY/BUSY status of the device can be determined by
executing a READ STATUS REGISTER (RDSR) instruction. Bit 0
= 1 indicates that the WRITE cycle is still in progress and Bit 0 =
0 indicates that the WRITE cycle has ended. During the WRITE
programming cycle (Bit 0 = 1) only the READ STATUS REGISTER instruction is enabled.
Note that the first four bits are don’t care bits followed by BP1 and
BP0 then two additional don’t care bits. Programming will start
after the CS pin is forced back to a high level. As in the WRITE
instruction the LOW to HIGH transition of the CS pin must occur
during the SCK low time immediately after clocking in the last don’t
care bit. See Figure 13.
The NM25C640 is capable of a 32 byte PAGE WRITE operation.
After receipt of each byte of data the five low order address bits are
internally incremented by one. The eight high order bits of the
address will remain constant. If the master should transmit more
than 32 bytes of data, the address counter will “roll over,” and the
previously loaded data will be reloaded. See Figure 11.
FIGURE 13. Start WRSR Condition
CS
SCK
FIGURE 11. 32 Byte Page Write
SI
CS
SI
Write Byte H Byte L
Op-Code Addr (n) Addr (n)
Data
(n)
Data
(n+1)
Data
(n+2)
Data
(n+3)
...
Data
(n+31)
SO
BP0
DS500041-15
The READY/BUSY status of the device can be determined by
executing a READ STATUS REGISTER (RDSR) instruction. Bit 0
= 1 indicates that the WRSR cycle is still in progress and Bit 0 =
0 indicates that the WRSR cycle has ended.
SO
DS500041-13
At the completion of a WRITE cycle the device is automatically
returned to the write disable state.
8
NM25C640 Rev. D.2
www.fairchildsemi.com
NM25C640 64K-Bit Serial CMOS EEPROM
(Serial Periphrial Interface (SPI) Synchronous Bus)
Physical Dimensions inches (millimeters) unless otherwise noted
0.189 - 0.197
(4.800 - 5.004)
8 7 6 5
0.228 - 0.244
(5.791 - 6.198)
1 2 3 4
Lead #1
IDENT
0.010 - 0.020
x 45°
(0.254 - 0.508)
0.0075 - 0.0098
(0.190 - 0.249)
Typ. All Leads
0.150 - 0.157
(3.810 - 3.988)
0.053 - 0.069
(1.346 - 1.753)
8° Max, Typ.
All leads
0.04
(0.102)
All lead tips
0.004 - 0.010
(0.102 - 0.254)
Seating
Plane
0.014
(0.356)
0.016 - 0.050
(0.406 - 1.270)
Typ. All Leads
0.014 - 0.020 Typ.
(0.356 - 0.508)
0.050
(1.270)
Typ
Molded Small Out-Line Package (M8)
Package Number M08A
0.373 - 0.400
(9.474 - 10.16)
0.090
(2.286)
8
0.092
DIA
(2.337)
7
6
0.250 - 0.005
(6.35 ± 0.127)
+
Pin #1 IDENT
0.032 ± 0.005
(0.813 ± 0.127)
RAD
5
1
1
0.300 - 0.320
(7.62 - 8.128)
7
Pin #1
IDENT
Option 1
0.280 MIN
(7.112)
8
2
3
0.040 Typ.
(1.016)
0.030
MAX
(0.762)
20° ± 1°
4
Option 2
0.145 - 0.200
(3.683 - 5.080)
0.039
(0.991)
0.130 ± 0.005
(3.302 ± 0.127)
95° ± 5°
0.009 - 0.015
(0.229 - 0.381)
+0.040
0.325 -0.015
+1.016
8.255 -0.381
0.125
(3.175)
DIA
NOM
0.125 - 0.140
(3.175 - 3.556)
0.065
(1.651)
90° ± 4°
Typ
0.018 ± 0.003
(0.457 ± 0.076)
0.100 ± 0.010
(2.540 ± 0.254)
0.045 ± 0.015
(1.143 ± 0.381)
0.020
(0.508)
Min
0.060
(1.524)
0.050
(1.270)
Molded Dual-In-Line Package (N)
Package Number N08E
9
NM25C640 Rev. D.2
www.fairchildsemi.com
NM25C640 64K-Bit Serial CMOS EEPROM
(Serial Periphrial Interface (SPI) Synchronous Bus)
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Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written
approval of the President of Fairchild Semiconductor Corporation. As used herein:
1. Life support devices or systems are devices or systems which,
(a) are intended for surgical implant into the body, or (b) support
or sustain life, and whose failure to perform, when properly
used in accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a significant
injury to the user.
Fairchild Semiconductor
Americas
Customer Response Center
Tel. 1-888-522-5372
2. A critical component is any component of a life support device
or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system,
or to affect its safety or effectiveness.
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Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
10
NM25C640 Rev. D.2
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