STMicroelectronics M39208-12WNB5T Single chip 2 mbit flash and 64 kbit parallel eeprom memory Datasheet

M39208
Single Chip 2 Mbit Flash and 64 Kbit Parallel EEPROM Memory
PRELIMINARY DATA
2.7V to 3.6V SUPPLY VOLTAGE for
PROGRAM, ERASE and READ OPARATIONS
100ns ACCESS TIME
(Flash and EEPROM blocks)
WRITE, PROGRAM and ERASE STATUS BITS
CONCURRENT MODE (Read Flash while
writing to EEPROM)
100,000 ERASE/WRITE CYCLES
10 YEARS DATA RETENTION
LOW POWER CONSUMPTION
– Stand-by mode: 60µA
– Automatic Stand-by mode
– Deep Power Down mode
64 bytes ONE TIME PROGRAMMABLE
MEMORY
STANDARD EPROM/OTP MEMORY
PACKAGE
EXTENDED TEMPERATURE RANGES
DESCRIPTION
The M39208 is a memory device combining Flash
and EEPROM into a single chip and using single
supply voltage. The memory is mapped in two
blocks: 2 Mbit of Flash memory and 64 Kbit of
EEPROM memory. Each space is independant for
writing, in concurrent mode the Flash Memory can
be read while the EEPROM is being written.
Table 1. Signal Names
A0-A17
Address Inputs
DQ0-DQ7
Data Input / Outputs
EE
EEPROM Block Enable
EF
Flash Block Enable
G
Output Enable
W
Write Enable
VCC
Supply Voltage
VSS
Ground
TSOP32 (NA)
8 x 20 mm
TSOP32 (NB)
8 x 14 mm
Figure 1. Logic Diagram
VCC
18
8
A0-A17
DQ0-DQ7
W
EE
M39208
EF
G
VSS
February 1999
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
AI02589
1/30
M39208
Table 2. Absolute Maximum Ratings (1)
Symbol
Parameter
Value
Unit
Ambient Operating Temperature
–40 to 85
°C
TBIAS
Temperature Under Bias
–50 to 125
°C
TSTG
Storage Temperature
–65 to 150
°C
VIO (2)
Input or Output Voltages
–0.6 to 5
V
Supply Voltage
–0.6 to 5
V
A9, G, EF Voltage
–0.6 to 13.5
V
TA
VCC
VA9, VG, VEF
(2)
Notes: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings"
may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other
relevant quality documents.
2. Minimum Voltage may undershoot to –2V during transition and for less than 20ns.
Figure 2. TSOP Pin Connections
A11
A9
A8
A13
A14
A17
W
VCC
EE
A16
A15
A12
A7
A6
A5
A4
1
8
9
16
32
M39208
25
24
17
G
A10
EF
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
A1
A2
A3
AI02587
DESCRIPTION (Cont’d)
An additional 64 bytes of EPROM are One Time
Programmable.
The M39208 EEPROM memory block may be written by byte or by page of 64 bytes and the integrity
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of the data can be secured with the help of the
Software Data Protection (SDP).
The M39208 Flash Memory block offers 4 sectors
of 64 Kbytes, each sector may be erased individually, and programmed Byte-by-Byte. Each sector
can be separately protected and unprotected
against program and erase. Sector erasure may be
suspended, while data is read from other sectors
of the Flash memory block (or EEPROM memory
block), and then resumed.
During a Program or Erase cycle in the Flash
memory block or during a Write in the EEPROM
memory block, the status of the M39208 internal
logic can be read on the Data Outputs DQ7,DQ6,
DQ5 and DQ3.
PIN DESCRIPTION
Address Inputs (A0-A17). The address inputs for
the memory array are latched during a write operation. A0-A12 access locations in the EEPROM
memory block A0-A17 access locations in the Flash
memory block. The memory block selected is given
by the state on the EE and EF inputs respectively.
When a specific voltage (VID) is applied on the A9
address input, additional specific areas can be
accessed: Read the Manufacturer identifier, Read
the Flash block identifier, Read/Write the EEPROM
block identifier, Verify the Flash Sector Protection
Status.
Data Input/Output (DQ0-DQ7). A write operation
inputs one byte which is latched when EE (or EF)
and Write Enable W are driven active.
Data read is valid when one Chip Enable (Chip
Enable Flash or Chip Enable EEPROM) and Output Enable are driven active. The output is high
M39208
Figure 3. Flash Block Sectors
A17
A16
TOP
ADDRESS
BOTTOM
ADDRESS
1
1
3FFFFh
30000h
1
0
2FFFFh
20000h
0
1
64K Bytes Block
1FFFFh
10000h
0
0
64K Bytes Block
0FFFFh
00000h
AI02588
impedance when the chip is deselected (both EE
and EF driven high) or the outputs are disabled (G
driven high).
Read operations are used to output the contents
from the memory, the Manufacturer identifier, the
Flash Sector protection Status, the Flash block
Identifier, the EEPROM identifier or the OTP row
content.
Memory Block Enable (EE and EF). The Memory
Block Enable (EE or EF) activates the memory
control logic, input buffers, decoders and sense
amplifiers. When the EE input is driven high, the
EEPROM memory block is not selected; when the
EF input is driven high, the Flash memory block is
not selected. Attempts to access both EEPROM
and Flash blocks (EE low and EF low) are forbidden. Switching between the two memory block
enables (EE and EF) must not be made on the
same clock cycle, a delay of greater than tEHFL must
be inserted.
The M39208 is in standby when both EF and EE
are High (when no internal Erase or programming
is running). The power consumption is reduced to
the standby level and the outputs are in the high
impedance state, independent of the Output Enable G or Write Enable W inputs.
After 150ns of inactivity and when the addresses
are driven at CMOS levels, the chip automatically
enters a pseudo standby mode where consumption
is reduced to the CMOS standby value, while the
outputs continue to drive the bus.
Output Enable (G). The Output Enable gates the
outputs through the data buffers during a read
operation. The data outputs are in the high impedance state when the Output Enable G is High.
During Sector Protect and Sector Unprotect operations, the G input must be forced to VID level (12V
+ 0.5V) (for Flash memory block only).
Write Enable (W). Addresses are latched on the
falling edge of W, and Data Inputs are latched on
the rising edge of W.
OPERATIONS
The M39208 memory is addressed through 18
inputs A0-A17 and provides data on eight Data
Inputs/Outputs DQ0-DQ7 with the help of four control lines: Chip Enable EEPROM (EE), Chip Enable
Flash (EF), Output Enable (E) and Write Enable
(W) inputs.
An operation is defined as the basic decoding of
the logic level applied to the control input pins (EF,
EE, G, W) and the specified voltages applied on
the relevant address pins. These operations are
detailed in Table 3.
Read. Both Chip Enable and Output Enable (that
is EF and G or EE and G) must be low in order to
read the output of the memory.
Read operations are used to output the contents
from the Flash or EEPROM block, the Manufacturer identifier, the Flash Sector protection Status,
the Flash block Identifier, the EEPROM identifier or
the OTP row content.
Notes:
– The Chip Enable input mainly provides power
control and should be used for device selection.
The Output Enable input should be used to gate
data onto the output in combination with active
EF or EE input signals.
– The data read depends on the previous instruction entered into the memory (see Table 4).
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M39208
Table 3. Basic Operations
Operation
Read
Write
Output Disable
Standby
EF
EE
G
W
DQ0 - DQ7
VIL
VIH
VIL
VIH
Read in Flash Block
VIH
VIL
VIL
VIH
Read in EEPROM Block
VIL
VIH
VIH
VIL
Write in Flash Block
VIH
VIL
VIH
VIL
Write in EEPROM Block
VIL
VIH
VIH
X
Hi-Z
VIH
VIL
VIH
X
Hi-Z
VIH
VIH
X
X
Hi-Z
Note: X = VIL or VIH.
Write. A Write operation can be used for two goals:
– either write data in the EEPROM memory block
– or enter a sequence of bytes composing an
instruction.
The reader should note that Programming a Flash
byte is an instruction (see Instructions paragraph).
Writing data requires:
– the Chip Enable (either EE or EF) to be Low
– the Write Enable (W) to be Low with Output
Enable (G) High.
Addresses in Flash block (or EEPROM block) are
latched on the falling edge of W or EF (EE) whichever occurs last; the data to be written in Flash
block (EEPROM block) is latched on the rising edge
of W or EF (EE) whichever occurs first.
Specific Read and Write Operations. Device
specific data is accessed through operations decoding the VID level applied on A9 (VID = 12V +
0.5V) and the logic levels applied on address inputs
(A0, A1, A6). These specific operations are:
– Read the Manufacturer identifier
– Read the Device identifier
– Define the Flash Sector protection
– Read the EEPROM identifier
– Write the EEPROM identifier
Note: The OTP row (64 bytes) is accessed with a
specific software sequence detailed in the paragraph "Write in OTP row".
Instructions
An instruction is defined as a sequence of specific
Write operations. Each received byte is sequentially decoded (and not executed as standard Write
operations) and the instruction is executed when
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the correct number of bytes are properly received
and the time between two consecutive bytes is
shorter than the time-out value.
The sequencing of any instruction must be followed
exactly, any invalid combination of instruction bytes
or time-out between two consecutive bytes will
reset the device logic into a Read memory state
(when addressing the Flash block) or directly decoded as a single operation when addressing the
EEPROM block.
The M39208 set of instructions includes:
– Program a byte in the Flash block
– Read a Flash sector protection status
– Erase instructions: Flash Sector Erase, Flash
Block Erase, Flash Sector Erase Suspend, Flash
Sector Erase Resume
– EEPROM power down
– Deep power down
– Set/Reset the EEPROM software write protection (SDP)
– OTP row access
– Reset and Return
– Read identifiers: read the manufacturer identifier, Read the Flash block identifier
These instructions are detailed in Table 4.
For efficient decoding of the instruction, the two first
bytes of an instruction are the coded cycles and are
followed by a command byte or a confirmation byte.
The coded cycles consist of writing the data AAh at
address 5555h during the first cycle and data 55h
at address 2AAAh during the second cycle.
In the specific case of the Erase instruction, the
instruction expects confirmation by two additional
coded cycles.
M39208
Table 4. Instructions (1)
Instruction
Read Manufacturer
Identifier (2)
EE
1
EF
0
Cycle 1
AAh
@5555h
Cycle 2
Cycle 3
Cycle 4
55h
@2AAAh
Read
Identifier
90h
with
@5555h
(A0,A1,A6)
at (0,0,0)
Read Flash
Identifier (2)
1
0
AAh
@5555h
55h
@2AAAh
Read
identifier
90h
with
@5555h
(A0,A1,A6)
at (1,0,0)
Read OTP Row
0
1
AAh
@5555h
55h
@2AAAh
90h
@5555h
Read
byte 1
55h
@2AAAh
90h
@5555h
Read
Identifier
with
(A0,A1,A6)
at (0,1,0)
Cycle 5
Cycle 6
Read
byte 2
Cycle 7
Read
byte N
Read Block
Protection Status (2)
1
0
AAh
@5555h
Program a Flash Byte
1
0
AAh
@5555h
55h
@2AAAh
A0h
@5555h
Data
@address
Erase one Flash
Block
1
0
AAh
@5555h
55h
@2AAAh
80h
@5555h
AAh
@5555h
55h
@2AAAh
30h
@Sector
address
Erase the Whole Flash
1
0
AAh
@5555h
55h
@2AAAh
80h
@5555h
AAh
@5555h
55h
@2AAAh
10h
@5555h
Suspend Block Erase
1
0
B0h
@any
address
Resume Block Erase
1
0
30h
@any
address
EEPROM Power
Down
0
1
AAh
@5555h
55h
@2AAAh
30h
@5555h
Deep Power Down
1
0
20h
@5555h
SDP Enable
(EEPROM)
0
1
AAh
@5555h
55h
@2AAAh
A0h
@5555h
Write
byte 1
Write
byte 2
SDP Disable
(EEPROM)
0
1
AAh
@5555h
55h
@2AAAh
80h
@5555h
AAh
@5555h
55h
@2AAAh
Write in OTP Row
0
1
AAh
@5555h
55h
@2AAAh
B0h
@5555h
Write
byte 1
Write
byte 2
Return (from OTP
Read or EEPROM
Power Down)
0
1
F0h @
any
address
Reset
1
0
AAh
@5555h
55h
@2AAAh
F0h
@any
Address
Reset (short
instruction)
1
0
F0h
@any
address
30h
@Sector
address(3)
Write
byte N
20h
@5555h
Write
byte N
Notes: 1. AAh @5555h means Write byte AAh at address 5555h.
2. This instruction can also be performed as a simple Read operation with A9=VID (refer to READ chapter).
3. Additional blocks to be erased must be entered within 80µs.
5/30
M39208
Table 5. Device Identifiers
Identifier
EF
EE
G
W
A0
A1
A6
A9
Other
Addresses
DQ0 - DQ7
Read the
Manufacturer
Identifier
VIL
VIH
VIL
VIH
VIL
VIL
VIL
VID
Don’t Care
20h
Read the Flash
Block Identifier
VIL
VIH
VIL
VIH
VIH
VIL
VIL
VID
Don’t Care
t.b.d.
Read the
EEPROM Block
Identifier
VIH
VIL
VIL
VIH
X
X
VIL
VID
Don’t Care
64 bytes
user
defined
Note: X = Don’t Care.
POWER SUPPLY and CURRENT CONSUMPTION
EEPROM Power Down. The M39208 can be set
with the EEPROM in power down with the help of
the EEPROM power down instruction (see Table
4). Once the EEPROM power down instruction is
decoded, the EEPROM block cannot be accessed
unless a further Return instruction is decoded.
Deep Power Down. The M39208 can be set in the
lowest ICC consumption mode with the help of the
Deep Power Down instruction (see Table 4). Once
the instruction is decoded, the device is set in a
sleep mode until a Reset instruction is decoded.
Power Up. The M39208 internal logic is reset upon
a power-up condition to Read memory status. Any
Write operation in EEPROM is inhibited during the
first 5 ms following the power-up.
Either EF, EE or W must be tied to VIH during
Power-up for the maximum security of the data
contents and to remove the possibility of a byte
being written on the first rising edge of EF, EE or
W. Any write cycle initiation is locked when Vcc is
below VLKO.
READ
Read operations and instructions can be used to:
– read the contents of the Memory Array (Flash
block and EEPROM block)
– read the Memory Array (Flash block and
EEPROM block) status and identifiers.
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Read data (Flash and EEPROM blocks)
Both Chip Enable EF (or EE) and Output Enable
(G) must be low in order to read the data from the
memory.
Read the Manufacturer Identifier
The manufacturer’s identifier can be read with two
methods: a Read operation or a Read instruction.
Read Operation. The manufacturer’s identifier can
be read with a Read operation with specific logic
levels applied on A0, A1, A6 and the VID level (VID
= 12V + 0.5V) on A9 (see Table 5).
Read Instruction. The manufacturer’s identifier
can also be read with a single instruction composed
of 4 operations: 3 specific Write operations (see
Table 4) and a Read which outputs the Manufacturer identifier, the Flash block identifier or the Flash
sector protection status.
Read the Flash Block Identifier
The Flash block identifier can be read with two
methods: a Read operation or a Read instruction.
Read Operation. The Flash block identifier (t.b.d.)
can be read with a single Read operation with
specific logic levels applied on A0, A1, A6 and the
VID level on A9 (see Table 5).
Read Instruction. The Flash block identifier can
also be read with an instruction composed of 4
operations: 3 specific Write operations and a Read
(see Table 4).
M39208
Table 6. Status Bit
EF
EE
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
Flash
VIL
VIH
Data
Polling
Toggle
Flag
Error
Flag
X
Erase
Time-out
X
X
X
EEPROM
VIH
VIL
Data
Polling
Toggle
Flag
X
X
X
X
X
X
Note: X = Not guaranteed value, can be read either ’1’ or ’0’.
Read the EEPROM Block Identifier
The EEPROM block identifier (64 bytes, user defined) can be read with a single Read operation with
A6 = ’0’ and A9 = VID (see Table 5).
Read the OTP Row
The OTP row is mapped in the EEPROM block
(EE = ’0’, EF = ’1’). Read of the OTP row (64 bytes)
is by an instruction (see Table 4) composed of three
specific Write operations of data bytes at three
specific memory locations (each location in a different page) before reading the OTP row content.
When accessing the OTP row, only the LSB addresses (A6 to A0) are decoded where A6 must be
’0’.
Each Read of the OTP row has to be followed by
the Return instruction (see Table 4).
Read the Flash Sector Protection Status
Reading the Flash sector protection status is by an
instruction similar to the Read Manufacturer identifier instruction, the only difference being the value
of the logic levels applied on A0, A1, A6, while A16
and A17 define the Flash sector whose protection
has to be verified. Such a read instruction will
output a 01h if the Flash sector is protected and a
00h if the Flash sector is not protected.
The Flash sector protection status can also be
verified with a Read operation (see chapter: Flash
block specific features), with VID on A9.
Read the Status Bits
The M39208 provides several Write operation
status flags which may be used to minimize the
application write (or erase or program) time. These
signals are available on the I/O port bits when
programming (or erasing) are in progress.
Data Polling flag, DQ7. When Erasing or Programming into the Flash block (or when Writing into
the EEPROM block), bit DQ7 outputs the complement of the bit being entered for Programming/ Writing on DQ7. Once the Program
instruction or the Write operation is performed, the
true logic value is read on DQ7 (in a Read operation).
Flash memory block specific features:
– Data Polling is effective after the fourth W pulse
(for programming) or after the sixth W pulse (for
Erase). It must be performed at the address
being programmed or at an address within the
Flash sector being erased.
– During an Erase instruction, DQ7 outputs a ’0’.
After completion of the instruction, DQ7 will output the last bit programmed (that is a ’1’ after
erasing).
– if the byte to be programmed is in a protected
Flash sector, the instruction is ignored.
– If all the Flash sectors to be erased are protected, DQ7 will be set to ’0’ for about 100µs, and
then return to the previous addressed byte. No
erasure will be performed.
– if all sectors are protected, a Bulk Erase instruction is ignored.
Toggle flag, DQ6. The M39208 also offers another
way for determining when the EEPROM write or
the Flash memory Program instruction is completed. During the internal Write operation, the DQ6
will toggle from ’0’ to ’1’ and ’1’ to ’0’ on subsequent
attempts to read any byte of the memory, when
either G , EE or EF is low.
When the internal cycle is completed the toggling
will stop and the data read on DQ0-DQ7 is the
addressed memory byte. The device is now accessible for a new Read or Write operation. The operation is completed when two successive reads yield
the same output data.
Flash memory block specific features:
a. the Toggle bit is effective after the fourth W pulse
(for programming) or after the sixth W pulse (for
Erase).
b. If the byte to be programmed belongs to a protected Flash sector, the instruction is ignored and:
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M39208
Figure 4. EEPROM SDP Enable Flowcharts
SDP
Set
Page
Write
Instruction
SDP
not Set
WRITE AAh in
Address 5555h
WRITE AAh in
Address 5555h
WRITE 55h in
Address 2AAAh
WRITE 55h in
Address 2AAAh
WRITE A0h in
Address 5555h
Page
Write
Instruction
WRITE A0h in
Address 5555h
WRITE
is enabled
SDP is set
SDP ENABLE ALGORITHM
WRITE Data to
be Written in
any Address
Write
in Memory
Write Data
+
SDP Set
after tWC
AI01698B
– if all the Flash sectors selected for erasure
are protected, DQ6 will toggle to ’0’ for about
100µs, and then return to the previous addressed byte.
– if all sectors are protected, the Bulk Erase instruction is ignored.
Error flag, DQ5 (Flash block only). This bit is set
to ’1’ when there is a failure during either a Flash
byte programming or a Sector erase or the Bulk
Erase.
In case of error in Flash sector erase or byte
program, the Flash sector in which the error occurred or to which the programmed byte belongs,
must not be used any longer (other Flash sectors
may still be used). The Error bit resets after Reset
instruction.
During a correct Program or Erase, the Error bit will
set to ’0’.
Erase Time-out flag, DQ3 (Flash block only).
The Erase Timer bit reflects the time-out period
allowed between two consecutive Sector Erase
instructions. The Erase timer bit is set to ’0’ after a
Sector Erase instruction for a time period of 100µs
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± 20% unless an additional Sector Erase instruction
is decoded. After this time period or when the
additional Sector Erase instruction is decoded,
DQ3 is set to ’1’.
WRITE a BYTE (or a PAGE) in EEPROM
It should be noticed that writing in the EEPROM
block is an operation, it is not an instruction (as for
Programming a byte in the Flash block).
Write a Byte in EEPROM Block
A write operation is initiated when Chip Enable EE
is Low and Write Enable W is Low with Output
Enable G High. Addresses are latched on the falling
edge of W, EE whichever occurs last.
Once initiated, the write operation is internally
timed until completion, that is during a time tW.
The status of the write operation can be found by
reading the Data Polling and Toggle bits (as detailed in the READ chapter) or the Ready/Busy
output. This Ready/Busy output is driven low from
the write of the byte being written until the completion of the internal Write sequence.
M39208
Table 7. Write the EEPROM Block Identifier
EF
EE
G
W
A6
A9
Other
Addresses
DQ0 - DQ7
VIH
VIL
VIH
VIL
VIL
VID
Don’t Care
64 bytes User Defined
Figure 5. SDP disable Flowchart
WRITE AAh in
Address 5555h
WRITE 55h in
Address 2AAAh
Page
Write
Instruction
WRITE 80h in
Address 5555h
WRITE AAh in
Address 5555h
WRITE 55h in
Address 2AAAh
WRITE 20h in
Address 5555h
Unprotected State
after
tWC (Write Cycle time)
AI01699B
Write a Page in EEPROM Block
The Page write allows up to 64 bytes within the
same EEPROM page to be consecutively latched
into the memory prior to initiating a programming
cycle. All bytes must be located in a single page
address, that is A6-A12 must be the same for all
bytes. Once initiated, the Page write operation is
internally timed until completion, that is during a
time tWC.
The status of the write operation can be seen by
reading the Data Polling and Toggle bits (as detailed in the READ chapter).
A Page write is composed of successive Write
instructions which must be sequenced within a time
period (between two consecutive Write operations)
that is smaller than the tWLWL value. If this period of
time exceeds the tWLWL value, the internal programming cycle will start.
EEPROM Block Software Data Protection
A protection instruction allows the user to inhibit all
write modes to the EEPROM block: the Software
Data Protection (referenced as SDP in the following). The SDP feature is useful for protecting the
EEPROM memory from inadvertent write cycles
that may occur during uncontrolled bus conditions.
The M39208 is shipped as standard in the unprotected state meaning that the EEPROM memory
contents can be changed by the user. After the SDP
enable instruction, the device enters the Protect
Mode where no further write operations have any
effect on the EEPROM memory contents.
The device remains in this mode until a valid SDP
disable instruction is received whereby the device
reverts to the unprotected state.
To enable the Software Data Protection, the device
has to be written (with a Page Write) with three
specific data bytes at three specific memory locations (each location in a different page) as shown
in Figure 4. This sequence provides an unlock key
to enable the write action, and, at the same time,
SDP continues to be set. Any further Write in
EEPROM when the SDP is set will use this same
sequence of three specific data bytes at three
specific memory locations followed by the bytes to
write. The first SDP enable sequence can be directly followed by the bytes to written.
Similarly, to disable the Software Data Protection
the user has to write specific data bytes into six
different locations with a Page Write addressing
different bytes in different pages, as shown in Figure 5.
The Software Data Protection state is non-volatile
and is not changed by power on/off sequences. The
SDP enable/disable instructions set/reset an internal non-volatile bit and therefore will require a write
time tWC, This Write operation can be monitored
only on the Toggle bit (status bit DQ6).
9/30
M39208
Figure 6. Data Polling Flowchart
Figure 7. Data Toggle Flowchart
START
START
READ DQ5 & DQ7
at VALID ADDRESS
READ
DQ5 & DQ6
DQ7
=
DATA
DQ6
=
TOGGLE
YES
YES
NO
NO
NO
DQ5
=1
YES
READ DQ7
READ DQ6
DQ6
=
TOGGLE
YES
NO
FAIL
NO
YES
PASS
AI01369
Write OTP Row
Writing (only one time) in the OTP row (64 bytes)
is enabled by an instruction. This instruction is
composed of three specific Write operations of data
bytes at three specific memory locations (each
location in a different page) followed by the the data
to store in the OTP row (refer to Table 4).
When accessing the OTP row, the only LSB addresses (A6 to A0) are decoded, with A6 = ’0’.
Write the EEPROM Block Identifier
The EEPROM block identifier can be written with a
single Write operation with specific logic levels
applied on A6 and the VID level on A9 (see Table
7).
PROGRAM in the Flash BLOCK
It should be noted that writing data into the
EEPROM block and the Flash block is not per-
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DQ5
=1
YES
DQ7
=
DATA
NO
FAIL
PASS
AI01370
formed in a similar way: the Flash memory requires
an instruction (see Instruction chapter) for Erasing
and another instruction for Programming one (or
more) byte(s), the EEPROM memory is directly
written with a simple operation (see Operation
chapter).
Program Instuction. During the execution of the
Program instruction, the Flash block memory will
not accept any further instructions.
The Flash block memory can be programmed byteby-byte. The program instruction is a sequence of
three specific Write operations followed by writing
the address and data byte to be programmed into
the Flash block memory (see Table 4). The M39208
automatically starts and performs the programming
after the fourth write operation.
During programming, the memory status may be
checked by reading the status bits DQ5, DQ6 and
DQ7, as detailed in the following sections.
M39208
Data Polling. Polling on DQ7 is a method of checking whether a Program or an Erase instruction is in
progress or completed (see Figure 6). When a
Program instruction is in progress, data bit DQ7 is
the complement of the original data bit 7; when
DQ7 is identical to the old data and the Error bit
DQ5 is still ’0’, the instruction is complete. To determine if DQ7 is valid, each poll must store the
original data for comparison, and if they are the
same, it can be considered that the operation was
successful. The Error bit DQ5 is checked to ensure
timing limits have not exceeded.
When an Erase operation is in progress, DQ7 is
always ’0’, and will be ’1’ when finished, so long as
DQ5= ’0’.
In all cases, when DQ5 is ’1’, DQ7 should be
checked again, in case DQ7 changed simultaneously with DQ5. If DQ7 = true data (Program) or
DQ7 = ’1’ (Erase), the operation is successful and
execution should return to the caller. A suggested
second read will provide all true data (Program) or
all FFh (Erase). Otherwise, this should be flagged
as an error, and the device should be Reset.
Data Toggle. Checking the Toggle bit DQ6 is an
alternative method of checking if Program or Erase
operations are in progress or completed (see Figure 7). When an operation is in progress, data bit
DQ6 constantly toggles for successive read operations. When DQ6 no longer toggles and the Error
bit DQ5 is ’0’, the operation is completed. To determine if DQ6 has toggled, each polling action requires 2 consecutive read operations of the data,
and if the data read is the same, it can be considered that the operation was successful. The Error
bit DQ5 is checked to ensure timing limits have not
been exceeded. In all cases, when DQ5 is ’1’, DQ6
should be checked again, in case DQ6 has
changed simultaneously with DQ5. If DQ6 has
stopped toggling, the operation is successful and
execution should return to the caller. A suggested
second read will provide all true data (Program) or
all FFh (Erase). Otherwise, this event should be
flagged as an error, and the device should be
Reset.
ERASE in the Flash BLOCK
It should be noted that:
a. Programming any byte of one Flash sector (or
bulk) requires that the Flash sector (or bulk) has
been previously erased (once for all bytes within
the sector or bulk) with the correct instruction (see
Instructions chapter).
b. Writing in the EEPROM memory is an operation
triggering an automatic sequencing of byte erase
followed by a byte write. Writing in EEPROM does
not require a specific erase operation before writing.
Bulk Erase Instruction. The Bulk Erase instruction uses six write operations followed by Read
operations of the status register bits, as described
in Table 4. If any byte of the Bulk Erase instruction
is wrong, the Bulk Erase instruction aborts and the
device is reset to the Read Flash memory status.
During a Bulk Erase, the memory status may
checked by reading the status bits DQ5, DQ6 and
DQ7, as detailed in the "PROGRAM in the Flash
BLOCK" chapter. The Error bit (DQ5) returns a ’1’
if there has been an Erase Failure (maximum number of erase cycles have been executed).
It is not necessary to program the array with 00h,
the M39208 will automatically do this before erasing to FFh.
During the execution of the Bulk Erase instruction,
the Flash block logic does not accept any instruction.
Sector Erase in Flash Block. The Sector Erase
instruction uses six write operations, as described
in Table 4. Additional Flash Sector Erase confirm
commands and Flash sector addresses can written
subsequently to erase other Flash sectors in parallel, without further coded cycles, if the additional
instruction is transmited in a shorter time than the
timeout period to end of period. The input of a new
Sector Erase instruction will restart the time-out
period.
The status of the internal timer can be monitored
through the level of DQ3 (Erase time-out bit), if DQ3
is ’0’ the Sector Erase instruction has been received and the timeout is counting; if DQ3 is ’1’, the
timeout has expired and the M39208 is erasing the
Flash sector(s). Before and during Erase timeout,
any instruction different than Erase suspend and
Erase Resume will abort the instruction and reset
the device to read array mode.
It is not necessary to program the Flash sector with
00h as the M39208 will do this automatically before
erasing (byte = FFh).
During a Sector Erase, the memory status may be
checked by reading the status bits DQ5, DQ6 and
DQ7, as detailed in the "Program instruction" chapter. During the execution of the erase instruction,
the Flash block logic accepts only the Reset and
Erase Suspend instructions (erasure of one Flash
sector may be suspended, in order to read data
from another Flash sector, and then resumed).
11/30
M39208
Table 8. Flash Sector Protection
EF
EE
G
W
A0
A1
A6
A9
A12
A16
A17
DQ0 - DQ7
VIL
VIH
VID
VIL
X
X
X
VID
X
SA
SA
Protection Activation
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VID
X
SA
SA
Verify the protection status:
when DQ0= 1, the sector is
protected
Notes:
X = Don’t care.
SA = Software Address.
Table 9. Flash Unprotection
EF
EE
G
W
A0
A1
A6
A9
A12
A15
A16
A17
VID
VIH
VID
VIL
X
X
X
VID
VIH
VIH
X
X
VIL
VIH
VIL
VIH
VIL
VIH
VIH
VID
X
X
SA
SA
Notes:
Activation of Unprotected
Mode
Verify the protection status:
when 00h, the sector is
unprotected
X = Don’t care.
SA = Software Address.
Erase Suspend Instruction. When a Flash Sector
Erase operation is in progress, the Erase Suspend
instruction may suspend the operation by writing
B0h at any address (see Table 4). This allows
reading of data from another Flash sector while
erase is in progress. Erase suspend is accepted
only during the Flash Sector Erase instruction execution and defaults to read array mode. An Erase
Suspend instruction entered during an Erase
timeout will, in addition to suspending the erase,
terminates the timeout.
The Toggle bit DQ6 stops toggling when the
M39208 internal logic is suspended. The Toggle bit
status must be monitored at an address out of the
Flash sector being erased. Toggle bit will stop
toggling between 0.1µs and 15µs after the Erase
Suspend instruction has been written. The M39208
will then automatically be set into Read Flash Block
Memory Array mode.
When erase is suspended, Reading from Flash
sectors being erased will output invalid data, a
Read from Flash sector not being erased is valid.
During an Erase Suspend, the Flash memory will
respond only to Erase Resume and Reset instructions.
A Reset instruction will definitively abort erasure
and can leave invalid data in the Flash sectors
being erased.
Erase Resume Instruction. If an Erase Suspend
instruction was previously executed, the erase op-
12/30
DQ0 - DQ7
eration may be resumed by this instruction. The
Erase Resume instruction consists of writing 30h
at any address (see Table 4).
FLASH BLOCK SPECIFIC FEATURES
Flash Sector Protection. Each Flash sector can
be separately protected against Program or Erase.
Flash Sector Protection provides additional data
security, as it disables all program or erase operations. This mode is activated when both A9 and G
are set to VID (12V + 0.5V) and the Flash sector
address is applied on A16 and A17, as shown in
Figure 8 and Table 8.
Flash sector protection is programmed with the
help of a specific sequence of levels applied on EF,
EE, G, A0, A1, A6, A9, A16 and A17; this sequence
includes a verification of the Protection status on
DQ0 as shown in Table 8.
Any attempt to program or erase a protected Flash
sector will be ignored by the device.
Remarks:
– The Verify operation is a read with a simulated
worst case conditions. This allows a guarantee
of the retention of the Protection status
– During the application life, the Sector protection
status can be accessed with a regular Read
instruction without applying a "high voltage" VID
on A9. This instruction is detailed in Table 4.
M39208
Figure 8. Sector Protection Flowchart
START
SECTOR ADDRESS
on A16, A17
EE = VIH
n=0
G, A9 = VID,
EF = VIL
Wait 4µs
W = VIL
Wait 100µs
W = VIH
G = VIH
Wait 4µs
READ DQ0 at PROTECTION
ADDRESS: A0, A6 = VIL, A1 = VIH and
A16, A17 DEFINING SECTOR
DQ0
=1
NO
YES
A9 = VIH
++n
= 25
NO
PASS
YES
A9 = VIH
FAIL
AI02598
13/30
M39208
Figure 9. Sector Unprotecting Flowchart
START
EE = EF = VIH
n=0
A6, A12, A15 = VIH
G, A9 = VIH
Wait 4µs
EF, G, A9 = VID
Wait 4µs
W = VIL
Wait 10ms
W = VIH
EF, G = VIH
Wait 4µs
READ at UNPROTECTION
ADDRESS: A1, A6 = VIH, A0 = VIL and
A16, A17 DEFINING SECTOR
(see Note 1)
NO
NO
++n
= 1000
YES
FAIL
DATA
=
00h
INCREMENT
SECTOR
YES
LAST
SECT.
NO
YES
PASS
AI02597
Note: 1. A6 is kept at VIH during unprotection algorithm in order to secure best unprotection verification. During all other protection status
reads, A6 must be kept at VIL.
14/30
M39208
Table 10. AC Measurement Conditions
Input Rise and Fall Times
≤ 10ns
Input Pulse Voltages
0.45V to 2.4V
Input Timing Ref. Voltages
0.8V and 2V
Output Timing Ref. Voltages
Figure 11. Output AC Testing Load Circuit
VCC
IOL
1.5V
DEVICE
UNDER
TEST
Figure 10. AC Testing Input Output Waveform
CL = 30pF
IOH
2.4V
1.5V
CL includes JIG capacitance
VOUT = 1.5V when the DEVICE
UNDER TEST is in the
Hi-Z output state.
0.45V
AI01950
AI02596B
Table 11. Capacitance (1) (TA = 25 °C, f = 1 MHz )
Symbol
CIN
COUT
Parameter
Test Condition
Max
Unit
VIN = 0V
6
pF
VOUT = 0V
12
pF
Input Capacitance
Output Capacitance
Min
Note: 1. Sampled only, not 100% tested.
Flash Sector Unprotection. Flash sectors can be
unprotected to allow updating of their contents.
Note that the Sector Unprotection unprotects all
sectors (sector 0 up to sector 7).
Flash Sector Unprotection is activated with a specific sequence of levels applied on EF, EE, G, A0,
A1, A6, A9, A12 and A15; this sequence includes a
verification of the Protection status on DQ0-DQ7
as shown in Figure 9 and Table 9.
This allows a guarantee of the retention of the
Protection status.
Remarks:
– The Verify operation is a read with a simulated
worst case conditions. This allows a guarantee
of the retention of the Protection status
– During the application life, the Sector protection
status can be accessed with a regular Read
instruction without "high voltage" VID on A9. This
instruction is detailed in Table 4.
Reset Instruction. The Reset instruction resets
the device internal logic in a few µs. Reset is an
instruction of either one write operation or three
write operations (refer to Table 4).
Supply Rails. Normal precautions must be taken
for supply voltage decoupling, each device in a
system should have the VCC rail decoupled with a
0.1µF capacitor close to the VCC and VSS pins. The
printed circuit board trace width should be sufficient
to carry the VCC program and erase currents required.
15/30
M39208
Table 12. DC Characteristics
(TA = 0 to 70°C or –20 to 85°C or –40 to 85°C; VCC = 2.7 V to 3.6V)
Symbol
Parameter
ILI
Input Leakage Current
ILO
Output Leakage Current
Test Condition
Min
Max
Unit
0V ≤ VIN ≤ VCC
±1
µA
0V ≤ VOUT ≤ VCC
±1
µA
ICC1 (1)
Supply Current (Read Flash) TTL
EE = VIH, EF = VIL, G =
VIH, f = 6MHz
15
mA
ICC2
Supply Current (Read EEPROM)
TTL
EE = VIL, EF = VIH, G =
VIH, f = 6MHz
15
mA
ICC3
Supply Current (Standby) CMOS
EF = EE = VCC ± 0.2V
60
µA
ICC4
Supply Current (Flash Block
Program or Erase)
Byte program, Sector or
Chip Erase in progress
20
mA
ICC5
Supply Current (EEPROM Write)
During tWC
20
mA
ICC6
Supply Current in Deep Power
Down Mode
After a Deep Power Down
instruction (see Table 4)
2
µA
VIL
Input Low Voltage
–0.5
0.8
V
VIH
Input High Voltage
0.7 VCC
VCC + 0.3
V
VOL
Output Low Voltage
IOL = 1.8mA
0.45
V
VOH
Output High Voltage
IOH = –100µA
VID
A9 High Voltage
IID
VID Current
VLKO
VCC Minimum for Write, Erase and
Program
VCC –0.4
11.5
A9 = VID
2
V
12.5
V
100
µA
2.3
V
Note: 1. When reading the Flash block when an EEPROM byte(s) is under a write cycle, the supply current is ICC1 + ICC5.
GLOSSARY
Block: EEPROM block (64 Kbit) or Flash block (2
Mbit)
Bulk: the whole Flash block (2 Mbit)
Sector: 64 Kbyte of Flash memory
Page: 64 bytes of EEPROM
Write and Program: Writing (into the EEPROM
block) and programming (the Flash block) is not
performed in a similar way:
16/30
– the Flash memory requires an instruction (see
Instruction chapter) for Erasing and another instruction for Programming one (or more) byte(s)
– the EEPROM memory is directly written with a
simple operation (see Operation chapter).
SDP: Software Data Protection. Used for protecting the EEPROM block against false Write operations (as in noisy environments).
Note: Write Enable (W) = High
DQ0-DQ7
G
EF (EE)
EE (EF)
A0-A17
tEHFL
ADDRESS VALID
AND CHIP ENABLE
tAVQV
tGLQV
OUTPUT ENABLE
tGLQX
tELQX
tELQV
VALID
tAVAV
DATA VALID
tEHFL
VALID
tGHQX
tGHQZ
tEHQZ
tEHQX
tAXQX
AI02595
M39208
Figure 12. Read Mode AC Waveforms
17/30
M39208
Table 13. Read AC Characteristics
(TA = 0 to 70°C or –20 to 85°C or –40 to 85°C; VCC = 2.7 V to 3.6V)
M39208
Symbol
Alt
Parameter
Test Condition
-100
Min
tAVAV
tRC
Address Valid to Next
Address Valid
(EE, EF) = (VIL, VIH) or
(EE, EF) = (VIH, VIL),
G = VIL
tAVQV
tACC
Address Valid to
Output Valid
(EE, EF) = (VIL, VIH) or
(EE, EF) = (VIH, VIL),
G = VIL
tELQX (1)
tLZ
Chip Enable Low to
Output Transition
G = VIL
tELQV (2)
tCE
Chip Enable Low to
Output Valid
G = VIL
tGLQX (1)
tOLZ
Output Enable Low to
Output Transition
(EE, EF) = (VIL, VIH) or
(EE, EF) = (VIH, VIL)
tGLQV (2)
tOE
Output Enable Low to
Output Valid
(EE, EF) = (VIL, VIH) or
(EE, EF) = (VIH, VIL)
tEHQX
tOH
Chip Enable High to
Output Transition
G = VIL
tEHQZ (1)
tHZ
Chip Enable High to
Output Hi-Z
G = VIL
tGHQX
tOH
Output Enable High to
Output Transition
(EE, EF) = (VIL, VIH) or
(EE, EF) = (VIH, VIL)
tGHQZ (1)
tDF
Output Enable High to
Output Hi-Z
(EE, EF) = (VIL, VIH) or
(EE, EF) = (VIH, VIL)
tAXQX
tOH
Address Transition to
Output Transition
(EE, EF) = (VIL, VIH) or
(EE, EF) = (VIH, VIL),
G = VIL
tEHFL
tCED
EE (EF) Active to EF
(EE)
-120
Max
100
Min
120
100
0
100
0
0
40
0
0
0
0
0
0
30
ns
ns
40
0
40
ns
ns
55
40
ns
ns
150
55
30
ns
150
120
Unit
Max
150
0
0
Min
120
ns
ns
40
ns
0
0
0
ns
100
100
100
ns
Notes: 1. Sampled only, not 100% tested.
2. G may be delayed by up to t ELQV - tGLQV after the falling edge of EE (or EF) without increasing tELQV.
18/30
Max
-150
M39208
Figure 13. Write AC Waveforms, W Controlled
WRITE CYCLE
A0-A17
VALID
tWLAX
tAVWL
E
tWHEH
(1)
tELWL
tWHGL
G
tGHWL
tWLWH
W
tWHWL
tDVWH
DQ0-DQ7
tWHDX
VALID
VCC
tVCHEL
AI02594
Notes: Address are latched on the falling edge of W, Data is latched on the rising edge of W.
E is either EF when EE = VIH or EE when EF = VIH.
19/30
M39208
Figure 14. Write AC Waveforms, E Controlled
WRITE CYCLE
VALID
A0-A17
tELAX
tAVEL
tEHWH
W
tWLEL
tEHGL
G
tGHEL
tELEH
E (1)
tEHEL
tDVEH
tEHDX
VALID
DQ0-DQ7
VCC
tVCHWL
Notes:
20/30
Address are latched on the falling edge of E, Data is latched on the rising edge of E.
E is either EF when EE = VIH or EE when EF = VIH.
AI02593
M39208
Table 14. Write AC Characteristics, Write Enable Controlled
(TA = 0 to 70°C or –20 to 85°C or –40 to 85°C; VCC = 2.7 V to 3.6V)
M39208
Symbol
Alt
Parameter
-100
Min
tAVAV
tWC
Address Valid to Next
Address Valid
tELWL (2)
tCS
tWLWH
-120
Max
Min
Unit
-150
Max
Min
Max
100
120
150
ns
Chip Enable Low to Write
Enable Low
0
0
0
ns
tWP
Write Enable Low to Write
Enable High
50
50
65
ns
tDVWH
tDS
Input Valid to Write Enable
High
50
50
65
ns
tWHDX
tDH
Write Enable High to Input
Transition
0
0
0
ns
tWHEH (2)
tCH
Write Enable High to Chip
Enable High
0
0
0
ns
tWHWL
tWPH
Write Enable High to Write
Enable Low
30
30
35
ns
tAVWL
tAS
Address Valid to Write
Enable Low
0
0
0
ns
tWLAX
tAH
Write Enable Low to Address
Transition
50
50
65
ns
Output Enable High to Write
Enable Low
0
0
0
ns
VCC High to Chip Enable Low
50
50
50
µs
tWHQV1 (1)
Write Enable High to Output
Valid (Program)
8
8
8
µs
tWHQV2 (1)
Write Enable High to Output
Valid (Sector Erase)
0.5
tGHWL
tVCHEL
tVCS
Time Out between 2
consecutive Section Erase
tWHWL0
tWHGL
tOEH
Write Enable High to Output
Enable Low
30
0.5
80
0
30
0.5
80
0
0
30
sec
80
µs
ns
Notes: 1. Time is measured to Data Polling or Toggle Bit, tWHQV = tWHQ7V + tQ7VQV
2. Chip Enable means (EE, EF) = (VIL, VIH) or (EE, EF) = (VIH, VIL).
21/30
M39208
Table 15. Write AC Characteristics, EE or EF Controlled
(TA = 0 to 70°C or –20 to 85°C or –40 to 85°C; VCC = 2.7 V to 3.6V)
M39208
Symbol
Alt
Parameter
-100
Min
tWLWL
tBLC
Time-out after the Last Byte
Write
tWC
Write Cycle Time (EEPROM)
tAVAV
Address Valid to Next Address
Valid
-120
Max
150
Min
Max
150
10
Unit
-150
Min
Max
µs
150
10
10
ms
100
120
150
ns
tWLEL
tWS
Write Enable Low to Memory
Block Enable Low
0
0
0
ns
tELEH
tCP
Memory Block Enable Low to
Memory Block Enable High
50
50
65
ns
tDVEH
tDS
Input Valid to Memory Block
Enable High
50
50
65
ns
tEHDX
tDH
Memory Block Enable High to
Input Transition
0
0
0
ns
tEHWH
tWH
Memory Block Enable High to
Write Enable High
0
0
0
ns
tEHEL
tCPH
Memory Block Enable High to
Memory Block Enable Low
30
30
35
ns
tAVEL
tAS
Address Valid to Memory Block
Enable Low
0
0
0
ns
tELAX
tAH
Memory Block Enable Low to
Address Transition
50
50
65
ns
Output Enable High to Memory
Block Enable Low
0
0
0
ns
VCC High to Write Enable Low
50
50
50
µs
tEHQV1 (1)
Memory Block Enable High to
Output Valid (Program)
8
8
8
µs
tEHQV2 (1)
Memory Block Enable High to
Output Valid (Sector Erase)
0.5
Memory Block Enable High to
Output Enable Low
0
tGHEL
tVCHWL
tEHGL
tVCS
tOEH
30
Notes: 1. Time is measured to Data Polling or Toggle Bit, tWHQV = tWHQ7V + tQ7VQV.
22/30
0.5
0
30
0.5
0
30
sec
ns
Notes: 1.
2.
3.
4.
5.
LAST CYCLE
OF PROGRAM
OR ERASE
DATA POLLING
READ CYCLES
tWHQ7V
tEHQ7V
tELQV
tAVQV
tQ7VQV
IGNORE
DQ7
DATA POLLING (LAST) CYCLE
tGLQV
BYTE ADDRESS (WITHIN SECTORS)
All other timings are as a normal Read cycle.
DQ7 and DQ0-DQ6 can transmit to valid at any point during the data output valid period.
tWHQ7V is the Program or Erase time.
During erasing operation Byte address must be within Sector being erased.
E is either EF when EE = VIH or EE when EF = VIH.
DQ0-DQ6
DQ7
W
G
E
(5)
A0-A17
VALID
VALID
DATA OUTPUT VALID
AI02592
DATA VERIFY
READ CYCLE
M39208
Figure 15. Data Polling DQ7 AC Waveforms
23/30
M39208
Table 16. Data Polling and Toggle Bit AC Characteristics (1)
(TA = 0 to 70°C or –20 to 85°C or –40 to 85°C; VCC = 2.7 V to 3.6V)
M39208
Symbol
Test
Conditions
Parameter
-100
Min
tWHQ7V1
EF = 0
EE = 1
Write Enable High to DQ7 Valid
(Program, W Controlled)
10
tWHQ7V2
EF = 0
EE = 1
Write Enable High to DQ7 Valid
(Sector Erase, W Controlled)
1.5
tEHQ7V1
EF = 0
EE = 1
Flash Block Enable High to
DQ7 Valid (Program, EF
Controlled)
10
tEHQ7V2
EF = 0
EE = 1
Flash Block Enable High to
DQ7 Valid (Sector Erase, EF
Controlled)
1.5
tQ7VQV
EF = 0
EE = 1
Q7 Valid to Output Valid (Data
Polling)
-120
Max
Min
Max
10
30
Min
Max
µs
10
1.5
30
10
30
Unit
-150
1.5
30
sec
µs
10
1.5
30
40
1.5
50
30
sec
55
ns
Notes: 1. All other timings are defined in Read AC Characteristics table.
Table 17. Program, Erase Times and Program, Erase Endurance Cycles (Flash Block)
(TA = 0 to 70°C or –20 to 85°C or –40 to 85°C; VCC = 2.7 V to 3.6V)
M39208
Parameter
Min
Typ
Unit
Max
Chip Program (Byte)
8
Chip Erase (Preprogrammed)
3
Chip Erase
10
Sector Erase (Preprogrammed)
1
Sector Erase
2
sec
Byte Program
10
µs
Program/Erase Cycles (per Sector)
24/30
100,000
sec
30
sec
sec
30
sec
cycles
LAST CYCLE
OF PROGRAM
OF ERASE
DATA
TOGGLE
READ CYCLE
Notes: 1. All other timings are as a normal Read cycle.
2. E is either EF when EE = VIH or EE when EF = VIH.
DQ0-DQ5,
DQ7
DQ6
W
G
E (2)
A0-A17
DATA TOGGLE
READ CYCLE
IGNORE
DQ6 TOGGLE
tWHQV
tEHQV
tAVQV
READ CYCLE
VALID
VALID
tGLQV
tELQV
VALID
AI02591
M39208
Figure 16. Data Toggle DQ6 AC Waveforms
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M39208
Figure 17. EEPROM Page Write Mode AC Waveforms, W Controlled
A0-A12
Addr 0
Addr 1
Addr 2
Addr n
E
G
tWHWL
tWLWL
W
tWLWH
DQ0-DQ7
Byte 0
Byte 1
Byte 2
Byte n
AI00600
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M39208
ORDERING INFORMATION SCHEME
Example:
Speed
-10 100ns
-12 120ns
-15 150ns
M39208
-15 W
Operating Voltage
W
2.7V to 3.6V
NA
1
Package
NA TSOP32
8 x 20mm
NB
TSOP32
8 x 14mm
T
Temp. Range
1
0 to 70 °C
5
–20 to 85 °C
6
–40 to 85 °C
Option
T
Tape & Reel
Packing
Devices are shipped from the factory with the memory content set at all "1’s" (FFh).
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device,
please contact the STMicroelectronics Sales Office nearest to you.
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M39208
TSOP32 - 32 lead Plastic Thin Small Outline, 8 x 14mm
mm
Symb
Typ
inches
Min
Max
A
Typ
Min
1.20
0.047
A1
0.05
0.15
0.002
0.006
A2
0.95
1.05
0.037
0.041
B
0.17
0.27
0.007
0.011
C
0.10
0.21
0.004
0.008
D
13.80
14.20
0.543
0.559
D1
12.30
12.50
0.484
0.492
E
7.90
8.10
0.311
0.319
-
-
-
-
L
0.50
0.70
0.020
0.028
α
0°
5°
0°
5°
N
32
e
0.50
0.020
32
CP
0.10
0.004
A2
1
N
e
E
B
N/2
D1
A
CP
D
DIE
C
TSOP-a
Drawing is not to scale.
28/30
Max
A1
α
L
M39208
TSOP32 - 32 lead Plastic Thin Small Outline, 8 x 20mm
mm
Symb
Typ
inches
Min
Max
A
Typ
Min
1.20
Max
0.047
A1
0.05
0.15
0.002
0.007
A2
0.95
1.05
0.037
0.041
B
0.15
0.27
0.006
0.011
C
0.10
0.21
0.004
0.008
D
19.80
20.20
0.780
0.795
D1
18.30
18.50
0.720
0.728
E
7.90
8.10
0.311
0.319
-
-
-
-
L
0.50
0.70
0.020
0.028
α
0°
5°
0°
5°
N
32
e
0.50
0.020
32
CP
0.10
0.004
A2
1
N
e
E
B
N/2
D1
A
CP
D
DIE
C
TSOP-a
A1
α
L
Drawing is not to scale.
29/30
M39208
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to
change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
© 1999 STMicroelectronics - All Rights Reserved
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