Lyontek LY62W51216ML-70LL 512k x 16 bit low power cmos sram Datasheet


LY62W51216
512K X 16 BIT LOW POWER CMOS SRAM
Rev. 1.7
REVISION HISTORY
Revision
Rev. 1.0
Rev. 1.1
Rev. 1.2
Rev. 1.3
Rev. 1.4
Rev. 1.5
Rev. 1.6
Rev. 1.7
Description
Initial Issue
Added ISB Spec.
Revised ICC1/ISB1/VDR/IDR Spec.
Revised typos in Page 1(ICC TYP.)
Revised FEATURES & ORDERING INFORMATION
Lead free and green package available to Green package
available
Added packing type in ORDERING INFORMATION
Deleted TSOLDER in ABSOLUTE MAXIMUN RATINGS
Revised PACKAGE OUTLINE DIMENSION in page 10
Revised VIH to 0.7*Vcc
Revised ORDERING INFORMATION in page 11
Deleted E grade
Added SL grade
Revised VIH in page 3
Revised TEST CONDITION of VIH in page 3
Revised PACKAGE OUTLINE DIMENSION in page 10
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
0
Issue Date
Oct.14.2007
Feb.1.2008
Mar.2.2009
May.7.2010
Aug.25.2010
Apr.25.2011
May.13.2011
Jul.27.2011

LY62W51216
512K X 16 BIT LOW POWER CMOS SRAM
Rev. 1.7
FEATURES
GENERAL DESCRIPTION
 Fast access time : 55/70ns
 Low power consumption:
Operating current : 30/20mA (TYP.)
Standby current : 6A (TYP.) LL-version
3A (TYP.) SL-version
 Single 2.7V ~ 5.5V power supply
 All inputs and outputs TTL compatible
 Fully static operation
 Tri-state output
 Data byte control : LB# (DQ0 ~ DQ7)
UB# (DQ8 ~ DQ15)
 Data retention voltage : 1.5V (MIN.)
 Green package available
 Package : 44-pin 400 mil TSOP-II
48-ball 6mm x 8mm TFBGA
The LY62W51216 is a 8,388,608-bit low power
CMOS static random access memory organized as
524,288 words by 16 bits. It is fabricated using very
high performance, high reliability CMOS technology.
Its standby current is stable within the range of
operating temperature.
The LY62W51216 is well designed for low power
application, and particularly well suited for battery
back-up nonvolatile memory application.
The LY62W51216 operates from a single power
supply of 2.7V ~ 5.5V and all inputs and outputs are
fully TTL compatible
PRODUCT FAMILY
Product
Family
LY62W51216
LY62W51216(I)
Operating
Temperature
0 ~ 70℃
-40 ~ 85℃
Vcc Range
Speed
2.7 ~ 5.5V
2.7 ~ 5.5V
55/70ns
55/70ns
FUNCTIONAL BLOCK DIAGRAM
PIN DESCRIPTION
Vcc
Vss
A0-A18
DQ0-DQ7
Lower Byte
DQ8-DQ15
Upper Byte
CE#
WE#
OE#
LB#
UB#
Power Dissipation
Standby(ISB1,TYP.) Operating(Icc,TYP.)
6µA(LL)/3µA(SL)
30/20mA
6µA(LL)/3µA(SL)
30/20mA
SYMBOL
DESCRIPTION
A0 - A18
Address Inputs
DQ0 – DQ15 Data Inputs/Outputs
DECODER
I/O DATA
CIRCUIT
512Kx16
MEMORY ARRAY
CE#
Chip Enable Input
WE#
Write Enable Input
OE#
Output Enable Input
LB#
Lower Byte Control
UB#
Upper Byte Control
VCC
Power Supply
VSS
Ground
COLUMN I/O
CONTROL
CIRCUIT
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
1

LY62W51216
512K X 16 BIT LOW POWER CMOS SRAM
Rev. 1.7
PIN CONFIGURATION
A4
1
44
A5
A3
2
43
A6
A2
3
42
A7
A1
4
41
OE#
5
40
UB#
6
39
LB#
DQ0
7
38
DQ15
DQ1
8
37
DQ14
DQ2
9
36
DQ13
DQ3
10
35
DQ12
Vcc
11
34
Vss
Vss
12
33
Vcc
DQ4
13
32
DQ11
DQ5
14
31
DQ10
DQ6
15
30
LY62W51216
A0
CE#
A
LB# OE#
A0
A1
B
DQ8 UB#
A3
A4
CE# DQ0
DQ9
C
DQ9 DQ10 A5
A6
DQ1 DQ2
D
Vss DQ11 A17
A7
DQ3 Vcc
E
Vcc DQ12 NC
A16 DQ4 Vss
F
DQ14 DQ13 A14
A15 DQ5 DQ6
DQ15 NC
A12
A13 WE# DQ7
A10
DQ7
16
29
DQ8
WE#
17
28
A8
A18
18
27
A9
A17
19
26
A10
A16
20
25
A11
G
A15
21
24
A12
H
A14
22
23
A13
A2
A18
A8
A9
1
2
3
4
5
TFBGA
TSOP II
A11
NC
NC
6
ABSOLUTE MAXIMUN RATINGS*
PARAMETER
Voltage on VCC relative to VSS
Voltage on any other pin relative to VSS
Operating Temperature
Storage Temperature
Power Dissipation
DC Output Current
SYMBOL
VT1
VT2
TA
TSTG
PD
IOUT
RATING
-0.5 to 6.5
-0.5 to VCC+0.5
0 to 70(C grade)
-40 to 85(I grade)
-65 to 150
1
50
UNIT
V
V
℃
℃
W
mA
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
2

LY62W51216
512K X 16 BIT LOW POWER CMOS SRAM
Rev. 1.7
TRUTH TABLE
MODE
CE#
OE#
H
X
L
L
L
L
L
L
L
L
X
X
H
H
L
L
L
X
X
X
Standby
Output Disable
Read
Write
Note:
WE# LB#
X
X
H
H
H
H
H
L
L
L
UB#
X
H
L
X
L
H
L
L
H
L
X
H
X
L
H
L
L
H
L
L
I/O OPERATION
DQ0-DQ7
DQ8-DQ15
High – Z
High – Z
High – Z
High – Z
High – Z
High – Z
High – Z
High – Z
DOUT
High – Z
High – Z
DOUT
DOUT
DOUT
DIN
High – Z
High – Z
DIN
DIN
DIN
SUPPLY CURRENT
ISB,ISB1
ICC,ICC1
ICC,ICC1
ICC,ICC1
H = VIH, L = VIL, X = Don't care.
DC ELECTRICAL CHARACTERISTICS
PARAMETER
Supply Voltage
SYMBOL
VCC
Input High Voltage
VIH
Input Low Voltage
Input Leakage Current
Output Leakage
Current
Output High Voltage
Output Low Voltage
VIL
ILI
*1
VCC = 2.7 ~ 3.6V
VCC = 4.5 ~ 5.5V
*2
ILO
VOH
VOL
ICC
Average Operating
Power supply Current
ICC1
ISB
Standby Power
Supply Current
TEST CONDITION
ISB1
VCC ≧ VIN ≧ VSS
VCC ≧ VOUT ≧ VSS,
Output Disabled
IOH = -1mA
IOL = 2mA
Cycle time = Min.
- 55
CE# = VIL , II/O = 0mA
- 70
Other pins at VIL or VIH
Cycle time = 1µ s
CE# = 0.2V , II/O = 0mA
Other pins at 0.2V or VCC - 0.2V
CE# = VIH, Other pins at VIL or VIH
LL
LLI
CE# ≧VCC - 0.2V
*5
25℃
SL
Others at 0.2V or
*5
SLI
40℃
VCC - 0.2V
SL
SLI
MIN.
2.7
2.2
2.4
- 0.2
-1
*4
MAX.
5.5
VCC+0.5
VCC+0.5
0.6
1
UNIT
V
V
V
V
µA
-1
-
1
µA
2.4
-
2.7
-
0.4
V
V
-
30
60
mA
-
20
50
mA
-
4
12
mA
-
0.15
6
6
3
3
3
3
2
30
50
10
10
20
25
mA
µA
µA
µA
µA
µA
µA
Notes:
1. VIH(max) = VCC + 3.0V for pulse width less than 10ns.
2. VIL(min) = VSS - 3.0V for pulse width less than 10ns.
3. Over/Undershoot specifications are characterized, not 100% tested.
4. Typical values are included for reference only and are not guaranteed or tested.
Typical values are measured at VCC = VCC(TYP.) and TA = 25℃
5. This parameter is measured at VCC = 3.0V
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
3
TYP.
3.0
-

LY62W51216
512K X 16 BIT LOW POWER CMOS SRAM
Rev. 1.7
CAPACITANCE (TA = 25℃, f = 1.0MHz)
PARAMETER
Input Capacitance
Input/Output Capacitance
SYMBOL
CIN
CI/O
MIN.
MAX
6
8
-
UNIT
pF
pF
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Reference Levels
Output Load
0.2V to VCC - 0.2V
3ns
1.5V
CL = 30pF + 1TTL, IOH/IOL = -1mA/2mA
AC ELECTRICAL CHARACTERISTICS
(1) READ CYCLE
PARAMETER
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Chip Enable to Output in Low-Z
Output Enable to Output in Low-Z
Chip Disable to Output in High-Z
Output Disable to Output in High-Z
Output Hold from Address Change
LB#, UB# Access Time
LB#, UB# to High-Z Output
LB#, UB# to Low-Z Output
(2) WRITE CYCLE
PARAMETER
Write Cycle Time
Address Valid to End of Write
Chip Enable to End of Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Data to Write Time Overlap
Data Hold from End of Write Time
Output Active from End of Write
Write to Output in High-Z
LB#, UB# Valid to End of Write
SYM.
tRC
tAA
tACE
tOE
tCLZ*
tOLZ*
tCHZ*
tOHZ*
tOH
tBA
tBHZ*
tBLZ*
SYM.
tWC
tAW
tCW
tAS
tWP
tWR
tDW
tDH
tOW *
tWHZ*
tBW
LY62W51216-55
MIN.
MAX.
55
55
55
30
10
5
20
20
10
55
25
10
-
LY62W51216-70
MIN.
MAX.
70
70
70
35
10
5
25
25
10
70
30
10
-
UNIT
LY62W51216-55
MIN.
MAX.
55
50
50
0
45
0
25
0
5
20
45
-
LY62W51216-70
MIN.
MAX.
70
60
60
0
55
0
30
0
5
25
60
-
UNIT
*These parameters are guaranteed by device characterization, but not production tested.
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
4
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

LY62W51216
512K X 16 BIT LOW POWER CMOS SRAM
Rev. 1.7
TIMING WAVEFORMS
READ CYCLE 1 (Address Controlled) (1,2)
tRC
Address
tAA
Dout
tOH
Previous Data Valid
Data Valid
READ CYCLE 2 (CE# and OE# Controlled) (1,3,4,5)
tRC
Address
tAA
CE#
tACE
LB#,UB#
tBA
OE#
tOE
tOH
tOHZ
tBHZ
tCHZ
tOLZ
tBLZ
tCLZ
Dout
High-Z
Data Valid
High-Z
Notes :
1.WE#is high for read cycle.
2.Device is continuously selected OE# = low, CE# = low, LB# or UB# = low.
3.Address must be valid prior to or coincident with CE# = low, LB# or UB# = low transition; otherwise tAA is the limiting parameter.
4.tCLZ, tBLZ, tOLZ, tCHZ, tBHZ and tOHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.
5.At any given temperature and voltage condition, tCHZ is less than tCLZ , tBHZ is less than tBLZ, tOHZ is less than tOLZ.
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
5

LY62W51216
512K X 16 BIT LOW POWER CMOS SRAM
Rev. 1.7
WRITE CYCLE 1 (WE# Controlled) (1,2,3,5,6)
tWC
Address
tAW
CE#
tCW
tBW
LB#,UB#
tAS
tWP
tWR
WE#
tWHZ
Dout
TOW
High-Z
(4)
tDW
Din
(4)
tDH
Data Valid
WRITE CYCLE 2 (CE# Controlled) (1,2,5,6)
tWC
Address
tAW
CE#
tAS
tWR
tCW
tBW
LB#,UB#
tWP
WE#
tWHZ
Dout
High-Z
(4)
tDW
Din
tDH
Data Valid
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
6

LY62W51216
512K X 16 BIT LOW POWER CMOS SRAM
Rev. 1.7
WRITE CYCLE 3 (LB#,UB# Controlled) (1,2,5,6)
tWC
Address
tAW
tWR
CE#
tAS
tCW
tBW
LB#,UB#
tWP
WE#
tWHZ
Dout
High-Z
(4)
tDW
Din
tDH
Data Valid
Notes :
1.WE#,CE#, LB#, UB# must be high during all address transitions.
2.A write occurs during the overlap of a low CE#, low WE#, LB# or UB# = low.
3.During a WE# controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be
placed on the bus.
4.During this period, I/O pins are in the output state, and input signals must not be applied.
5.If the CE#, LB#, UB# low transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance
state.
6.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
7

LY62W51216
512K X 16 BIT LOW POWER CMOS SRAM
Rev. 1.7
DATA RETENTION CHARACTERISTICS
PARAMETER
SYMBOL
TEST CONDITION
VCC for Data Retention
VDR
CE# ≧ VCC - 0.2V
Data Retention Current
Chip Disable to Data
Retention Time
Recovery Time
tRC* = Read Cycle Time
IDR
tCDR
tR
MIN.
1.5
LL
LLI
VCC = 1.5V
SL 25℃
CE# ≧ VCC - 0.2V
SLI 40℃
Other pins at 0.2V or VCC-0.2V
SL
SLI
See Data Retention
0
Waveforms (below)
tRC*
DATA RETENTION WAVEFORM
Low Vcc Data Retention Waveform (1) (CE# controlled)
VDR ≧ 1.5V
Vcc
Vcc(min.)
Vcc(min.)
tCDR
CE#
VIH
tR
CE# ≧ Vcc-0.2V
VIH
Low Vcc Data Retention Waveform (2) (LB#, UB# controlled)
VDR ≧ 1.5V
Vcc
Vcc(min.)
Vcc(min.)
tCDR
LB#,UB#
VIH
tR
LB#,UB# ≧ Vcc-0.2V
VIH
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
8
TYP.
4
4
3
3
3
3
MAX.
5.5
30
50
10
10
20
25
UNIT
V
µA
µA
µA
µA
µA
µA
-
-
ns
-
-
ns

LY62W51216
512K X 16 BIT LOW POWER CMOS SRAM
Rev. 1.7
PACKAGE OUTLINE DIMENSION
θ
44-pin 400mil TSOP-Ⅱ Package Outline Dimension
SYMBOLS
A
A1
A2
b
c
D
E
E1
e
L
ZD
y
Θ
DIMENSIONS IN MILLMETERS
MIN.
NOM.
MAX.
1.20
0.05
0.10
0.15
0.95
1.00
1.05
0.30
0.45
0.12
0.21
18.212
18.415
18.618
11.506
11.760
12.014
9.957
10.160
10.363
0.800
0.40
0.50
0.60
0.805
0.076
o
o
o
0
3
6
DIMENSIONS IN MILS
MIN.
NOM.
MAX.
47.2
2.0
3.9
5.9
37.4
39.4
41.3
11.8
17.7
4.7
8.3
717
725
733
453
463
473
392
400
408
31.5
15.7
19.7
23.6
31.7
3
o
o
o
0
3
6
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
9

LY62W51216
Rev. 1.7
512K X 16 BIT LOW POWER CMOS SRAM
48-ball 6mm × 8mm TFBGA Package Outline Dimension
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
10

LY62W51216
Rev. 1.7
512K X 16 BIT LOW POWER CMOS SRAM
ORDERING INFORMATION
LY62W51216 U V - WW XX Y Z
Z : Packing Type
Blank : Tube or Tray
Tray : 44-pin 400 mil TSOP-II
48-ball 6 mm x 8 mm TFBGA
T : Tape Reel
Y : Temperature Range
Blank : (Commercial) 0°C ~ 70°C
I : (Industrial) -40°C ~ +85°C
XX : Power Type
LL : Ultra Low Power
SL : Special Ultra Low Power
WW : Access Time(Speed)
V : Lead Information
L : Green Package
U : Package Type
M : 44-pin 400 mil TSOP-II
G : 48-ball 6 mm x 8 mm TFBGA
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
11

LY62W51216
Rev. 1.7
512K X 16 BIT LOW POWER CMOS SRAM
THIS PAGE IS LEFT BLANK INTENTIONALLY.
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
12
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