MB9B110R Series
32-bit Arm® Cortex®-M3
FM3 Microcontroller
The MB9B110R Series are a highly integrated 32-bit microcontrollers dedicated for embedded controllers with high-performance
and competitive cost. These series are based on the Arm Cortex-M3 Processor with on-chip Flash memory and SRAM, and has
peripheral functions such as Motor Control Timers, ADCs and Communication Interfaces (UART, CSIO, I 2C, LIN). The products
which are described in this data sheet are placed into TYPE4 product categories in FM3 Family Peripheral Manual.
Features
Integrated Nested Vectored Interrupt Controller (NVIC): 1
External Bus Interface
Supports SRAM, NOR and NAND Flash device
Up to 8 chip selects
8-/16-bit Data width
Up to 25-bit Address bit
Maximum area size: Up to 256 Mbytes
Supports Address/Data multiplex
Supports external RDY input
24-bit System timer (Sys Tick): System timer for OS task
Multi-function Serial Interface (Max eight channels)
4 channels with 16 steps×9-bit FIFO (ch.4-ch.7), 4 channels
32-bit Arm Cortex-M3 Core
Processor version: r2p1
Up to 144 MHz Frequency Operation
Memory Protection Unit (MPU): improves the reliability of an
embedded system
NMI (non-maskable interrupt) and 48 peripheral interrupts
and 16 priority levels
management
without FIFO (ch.0-ch.3)
Operation mode is selectable from the followings for each
channel.
UART
CSIO
LIN
I2 C
On-chip Memories
[Flash memory]
These series are based on two independent on-chip Flash
memories.
MainFlash
to 512 Kbyte
Built-in Flash Accelerator System with 16 Kbyte trace buffer
memory
The read access to Flash memory can be achieved without
wait cycle up to operation frequency of 72 MHz. Even at the
operation frequency more than 72 MHz, an equivalent
access to Flash memory can be obtained by Flash
Accelerator System.
Security function for code protection
UART
Full-duplex
double buffer
with or without parity supported
Built-in dedicated baud rate generator
External clock available as a serial clock
Hardware Flow control: Automatically control the
transmission by CTS/RTS (only ch.4)
Various error detect functions available (parity errors,
framing errors, and overrun errors)
Up
Selection
CSIO
Full-duplex
double buffer
dedicated baud rate generator
Overrun error detect function available
WorkFlash
32
Kbyte
Read cycle
4 wait-cycle: the operation frequency more than 72 MHz
2 wait-cycle: the operation frequency more than 40 MHz, and
to 72 MHz
0wait-cycle: the operation frequency to 40 MHz
Security function is shared with code protection
Built-in
LIN
LIN
protocol Rev.2.1 supported
double buffer
Master/Slave mode supported
LIN break field generate (can be changed 13 to 16-bit
length)
LIN break delimiter generate (can be changed 1 to 4-bit
length)
Various error detect functions available (parity errors,
framing errors, and overrun errors)
Full-duplex
[SRAM]
This Series contain a total of up to 64 Kbyte on-chip SRAM.
This is composed of two independent SRAM (SRAM0,
SRAM1). SRAM0 is connected to I-code bus and D-code bus
of Cortex-M3 core. SRAM1 is connected to System bus.
SRAM0: Up to 32 Kbyte
SRAM1: Up to 32 Kbyte
Cypress Semiconductor Corporation
Document Number: 002-05622 Rev. *D
•
I2 C
198 Champion Court
Standard-mode
supported
•
(Max 100 kbps) / Fast-mode (Max 400 kbps)
San Jose, CA 95134-1709
•
408-943-2600
Revised February 9, 2018
MB9B110R Series
DMA Controller (Eight channels)
Multi-function Timer (Max three units)
DMA Controller has an independent bus for CPU, so CPU
and DMA Controller can process simultaneously.
The Multi-function timer is composed of the following blocks.
8 independently configured and operated channels
Input capture × 4 ch./unit
Transfer can be started by software or request from the
Output compare × 6 ch./unit
built-in peripherals
Transfer address area: 32 bit (4 Gbyte)
Transfer mode: Block transfer/Burst transfer/Demand
transfer
16-bit free-run timer × 3 ch./unit
A/D activating compare × 3 ch./unit
Waveform generator × 3 ch./unit
16-bit PPG timer × 3 ch./unit
Transfer data type: byte/half-word/word
Transfer block count: 1 to 16
Number of transfers: 1 to 65536
A/D Converter (Max 16 channels)
12-bit A/D Converter
The following function can be used to achieve the motor
control.
PWM signal output function
DC chopper waveform output function
Dead time function
Successive Approximation
Input capture function
Built-in
A/D convertor activate function
Register type
3 unit
Conversion time: 1.0 μs @ 5 V
Priority conversion available (priority at 2 levels)
Scanning conversion mode
Built-in FIFO for conversion data storage (for SCAN
conversion: 16 steps, for Priority conversion: 4 steps)
Base Timer (Max eight channels)
Operation mode is selectable from the followings for each
channel.
16-bit PWM timer
16-bit PPG timer
DTIF (Motor emergency stop) interrupt function
Real-time clock (RTC)
The Real-time clock can count
Year/Month/Day/Hour/Minute/Second/A day of the week from
00 to 99.
Interrupt function with specifying date and time
(Year/Month/Day/Hour/Minute) is available. This function is
also available by specifying only Year, Month, Day, Hour or
Minute.
16-/32-bit reload timer
Timer interrupt function after set time or each set time.
16-/32-bit PWC timer
Capable of rewriting the time with continuing the time count.
Leap year automatic count is available.
General Purpose I/O Port
This series can use its pins as general purpose I/O ports
when they are not used for external bus or peripherals.
Moreover, the port relocate function is built in. It can set
which I/O port the peripheral function can be allocated.
Quadrature Position/Revolution Counter (QPRC)
(Max three channels)
Capable of pull-up control per pin
The Quadrature Position/Revolution Counter (QPRC) is used
to measure the position of the position encoder. Moreover, it
is possible to use up/down counter.
Capable of reading pin level directly
The detection edge of the three external event input pins AIN,
Built-in the port relocate function
Up 103 fast general purpose I/O Ports@120 pin Package
Some pin is 5 V tolerant I/O.
See4. List of Pin Functions to confirm the corresponding
pins.
Document Number: 002-05622 Rev. *D
BIN and ZIN is configurable.
16-bit position counter
16-bit revolution counter
Two 16-bit compare registers
Page 2 of 117
MB9B110R Series
Dual Timer (32-/16-bit Down Counter)
The Dual Timer consists of two programmable 32-/16-bit
down counters.
Operation mode is selectable from the followings for each
channel.
Free-running
Periodic (=Reload)
One-shot
Resets
Reset
requests from INITX pin
on reset
Software reset
Watchdog timers reset
Low-voltage detector reset
Clock supervisor reset
Power
Clock Super Visor (CSV)
Clocks generated by internal CR oscillators are used to
supervise abnormality of the external clocks.
Watch Counter
The Watch counter is used for wake up from power
consumption mode.
External OSC clock failure (clock stop) is detected, reset is
Interval timer: up to 64 s (Max) @ Sub Clock: 32.768 kHz
External OSC frequency anomaly is detected, interrupt or
External Interrupt Controller Unit
Up to 16 external interrupt input pin
Include one non-maskable interrupt (NMI)
Watchdog Timer (Two channels)
A watchdog timer can generate interrupts or a reset when a
time-out value is reached.
This series consists of two different watchdogs, a "Hardware"
watchdog and a "Software" watchdog.
"Hardware" watchdog timer is clocked by low-speed internal
CR oscillator. Therefore, "Hardware" watchdog is active in
any power consumption mode except Stop mode.
asserted.
reset is asserted.
Low-Voltage Detector (LVD)
This Series include 2-stage monitoring of voltage on the VCC
pins. When the voltage falls below the voltage has been set,
Low-Voltage Detector generates an interrupt or reset.
LVD1: error reporting via interrupt
LVD2: auto-reset operation
Low-Power Consumption Mode
Three power consumption modes supported.
Sleep
Timer
CRC (Cyclic Redundancy Check) Accelerator
The CRC accelerator helps a verify data transmission or
storage integrity.
CCITT CRC16 and IEEE-802.3 CRC32 are supported.
CCITT CRC16 Generator Polynomial: 0x1021
IEEE-802.3 CRC32 Generator Polynomial: 0x04C11DB7
Stop
Debug
Serial Wire JTAG Debug Port (SWJ-DP)
Embedded Trace Macrocells (ETM) provide comprehensive
debug and trace facilities.
Clock and Reset
Clocks
Power Supply
Five clock sources (2 external oscillators, 2 internal CR
oscillator, and Main PLL) that are dynamically selectable.
Wide range voltage:
Main
Clock:
Sub Clock:
High-speed internal CR Clock:
Low-speed internal CR Clock:
Main PLL Clock
Document Number: 002-05622 Rev. *D
VCC
= 2.7 V to 5.5 V
4 MHz to 48 MHz
32.768 kHz
4 MHz
100 kHz
Page 3 of 117
MB9B110R Series
Table of Contents
Features .............................................................................................................................................................................. 1
1.
Product Lineup ............................................................................................................................................................ 6
2.
Packages ...................................................................................................................................................................... 8
3.
Pin Assignment ........................................................................................................................................................... 9
4.
List of Pin Functions ................................................................................................................................................. 13
5.
I/O Circuit Type .......................................................................................................................................................... 44
6.
Handling Precautions................................................................................................................................................ 49
6.1
Precautions for Product Design ................................................................................................................................ 49
6.2
Precautions for Package Mounting ........................................................................................................................... 50
6.3
Precautions for Use Environment ............................................................................................................................. 52
7.
Handling Devices....................................................................................................................................................... 53
8.
Block Diagram ........................................................................................................................................................... 55
9.
Memory Size .............................................................................................................................................................. 55
10.
Memory Map .............................................................................................................................................................. 56
11.
Pin Status in Each CPU State ................................................................................................................................... 60
12.
Electrical Characteristics.......................................................................................................................................... 65
12.1
Absolute Maximum Ratings ...................................................................................................................................... 65
12.2
Recommended Operating Conditions ....................................................................................................................... 67
12.3
DC Characteristics .................................................................................................................................................... 68
12.3.1
Current Rating ....................................................................................................................................................... 68
12.3.2
Pin Characteristics ................................................................................................................................................. 70
12.4
AC Characteristics .................................................................................................................................................... 72
12.4.1
Main Clock Input Characteristics ........................................................................................................................... 72
12.4.2
Sub Clock Input Characteristics ............................................................................................................................. 73
12.4.3
Internal CR Oscillation Characteristics................................................................................................................... 73
12.4.4
Operating Conditions of Main PLL (In the case of using main clock for input of PLL) ............................................ 74
12.4.5
Operating Conditions of Main PLL (In the case of using high-speed internal CR) ................................................. 74
12.4.6
Reset Input Characteristics .................................................................................................................................... 75
12.4.7
Power-on Reset Timing ......................................................................................................................................... 75
12.4.8
External Bus Timing ............................................................................................................................................... 76
12.4.9
Base Timer Input Timing ........................................................................................................................................ 85
12.4.10 CSIO/UART Timing................................................................................................................................................ 86
12.4.11 External Input Timing ............................................................................................................................................. 94
12.4.12 Quadrature Position/Revolution Counter timing ..................................................................................................... 95
12.4.13 I2C Timing .............................................................................................................................................................. 97
12.4.14 ETM Timing ........................................................................................................................................................... 98
12.4.15 JTAG Timing .......................................................................................................................................................... 99
12.5
12-bit A/D Converter ............................................................................................................................................... 100
12.6
Low-Voltage Detection Characteristics ................................................................................................................... 103
12.6.1
Low-Voltage Detection Reset .............................................................................................................................. 103
12.6.2
Interrupt of Low-Voltage Detection ...................................................................................................................... 103
12.7
MainFlash Memory Write/Erase Characteristics ..................................................................................................... 104
12.7.1
Write / Erase time ................................................................................................................................................ 104
12.7.2
Erase/write cycles and data hold time.................................................................................................................. 104
12.8
WorkFlash Memory Write/Erase Characteristics .................................................................................................... 104
12.8.1
Write / Erase time ................................................................................................................................................ 104
12.8.2
Erase/write cycles and data hold time.................................................................................................................. 104
Document Number: 002-05622 Rev. *D
Page 4 of 117
MB9B110R Series
12.9
Return Time from Low-Power Consumption Mode ................................................................................................. 105
12.9.1
Return Factor: Interrupt........................................................................................................................................ 105
12.9.2
Return Factor: Reset............................................................................................................................................ 107
13.
Ordering Information............................................................................................................................................... 109
14.
Package Dimensions............................................................................................................................................... 110
15.
Major Changes ......................................................................................................................................................... 114
Document History ............................................................................................................................................................... 116
Sales, Solutions, and Legal Information ........................................................................................................................... 117
Document Number: 002-05622 Rev. *D
Page 5 of 117
MB9B110R Series
1. Product Lineup
Memory Size
Product name
MainFlash
WorkFlash
On-chip RAM
SRAM0
SRAM1
MB9BF112N/R
MB9BF114N/R
MB9BF115N/R
MB9BF116N/R
128 Kbyte
256 Kbyte
384 Kbyte
512 Kbyte
32 Kbyte
32 Kbyte
32 Kbyte
32 Kbyte
16 Kbyte
32 Kbyte
48 Kbyte
64 Kbyte
8 Kbyte
8 Kbyte
16 Kbyte
16 Kbyte
24 Kbyte
24 Kbyte
32 Kbyte
32 Kbyte
Function
Product name
Pin count
CPU
MB9BF112N
MB9BF114N
MB9BF115N
MB9BF116N
MB9BF112R
MB9BF114R
MB9BF115R
MB9BF116R
100/112
120
Cortex-M3
Freq.
Power supply voltage range
DMAC
External Bus Interface
MF Serial Interface
(UART/CSIO/LIN/I2C)
Base Timer
(PWC/Reload timer/PWM/PPG)
A/D
activation
3 ch.
compare
Input
4 ch.
capture
Free-run
MF3 ch.
timer
Timer
Output
6 ch.
compare
Waveform
3 ch.
generator
PPG
3 ch.
QPRC
Dual Timer
Real-Time Clock
Watch Counter
CRC Accelerator
Watchdog timer
External Interrupts
I/O ports
12-bit A/D converter
CSV (Clock Super Visor)
LVD (Low-Voltage Detector)
High-speed
Internal
OSC
Low-speed
Debug Function
Document Number: 002-05622 Rev. *D
144 MHz
VCC: 2.7 V to 5.5 V
8 ch.
Addr: 25-bit (Max)
Addr: 25-bit (Max)
R/Wdata: 8-/16-bit (Max)
R/Wdata: 8-/16-bit (Max)
CS: 8 (Max)
CS: 8 (Max)
Support: SRAM, NOR & NAND
Support: SRAM, NOR Flash
Flash
8 ch. (Max)
ch.4 to ch.7: FIFO (16steps × 9-bit)
ch.0 to ch.3: No FIFO
8 ch. (Max)
3 units (Max)
3 ch. (Max)
1 unit
1 unit
1 unit
Yes
1 ch. (SW) + 1 ch. (HW)
16 pins (Max) + NMI × 1
83 pins (Max)
103 pins (Max)
16 ch. (3 units)
Yes
2 ch.
4 MHz
100 kHz
SWJ-DP/ETM
Page 6 of 117
MB9B110R Series
Note:
− All signals of the peripheral function in each product cannot be allocated by limiting the pins of package.
It is necessary to use the port relocate function of the General I/O port according to your function use.
See 12.4.3 Internal CR Oscillation Characteristics for accuracy of built-in CR.
Document Number: 002-05622 Rev. *D
Page 7 of 117
MB9B110R Series
2. Packages
Package
QFP: PQH100 (0.65 mm pitch)
LQFP: LQI100 (0.5 mm pitch)
LQFP: LQM120 (0.5 mm pitch)
FBGA: LBC112 (0.8 mm pitch)
Product name
MB9BF112N
MB9BF114N
MB9BF115N
MB9BF116N
MB9BF112R
MB9BF114R
MB9BF115R
MB9BF116R
-
: Supported
Note:
− See 14. Package Dimensions for detailed information on each package.
Document Number: 002-05622 Rev. *D
Page 8 of 117
MB9B110R Series
3. Pin Assignment
LQI100
VSS
P81
P80
VCC
P60/SIN5_0/TIOA2_2/INT15_1/MRDY_0
P61/SOT5_0/TIOB2_2
P62/SCK5_0/ADTG_3/MOEX_0
P63/INT03_0/SIN5_1/MWEX_0
P0F/NMIX/CROUT_1/RTCCO_0/DTTI2X_0/DTTI2X_1/SUBOUT_0
P0E/CTS4_0/TIOB3_2/IC13_0/IC23_0/RTO25_1/MDQM1_0
P0D/RTS4_0/TIOA3_2/IC12_0/IC22_0/RTO24_1/MDQM0_0
P0C/SCK4_0/TIOA6_1/IC11_0/IC21_0/RTO23_1/MALE_0
P0B/SOT4_0/TIOB6_1/IC10_0/IC20_0/RTO22_1/MCSX0_0
P0A/SIN4_0/INT00_2/FRCK1_0/FRCK2_0/RTO21_1/MCSX1_0
P09/TRACECLK/TIOB0_2/RTS4_2/RTO20_1/MCSX2_0
P08/TRACED3/TIOA0_2/CTS4_2/ZIN2_1/MCSX3_0
P07/TRACED2/ADTG_0/SCK4_2/BIN2_1/MCLKOUT_0
P06/TRACED1/TIOB5_2/SOT4_2/INT01_1/AIN2_1/MCSX4_0
P05/TRACED0/TIOA5_2/SIN4_2/INT00_1/MCSX5_0
P04/TDO/SWO
P03/TMS/SWDIO
P02/TDI/MCSX6_0
P01/TCK/SWCLK
P00/TRSTX/MCSX7_0
VCC
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
(TOP VIEW)
VCC
1
75
VSS
P50/INT00_0/AIN0_2/SIN3_1/RTO10_0/MADATA00_0
2
74
P20/INT05_0/CROUT_0/AIN1_1/MAD24_0
P51/INT01_0/BIN0_2/SOT3_1/RTO11_0/MADATA01_0
3
73
P21/SIN0_0/INT06_1/BIN1_1
P52/INT02_0/ZIN0_2/SCK3_1/RTO12_0/MADATA02_0
4
72
P22/SOT0_0/TIOB7_1/ZIN1_1
P53/SIN6_0/TIOA1_2/INT07_2/RTO13_0/MADATA03_0
5
71
P23/SCK0_0/TIOA7_1
P54/SOT6_0/TIOB1_2/RTO14_0/MADATA04_0
6
70
P1F/AN15/ADTG_5/FRCK0_1/MAD23_0
P55/SCK6_0/ADTG_1/RTO15_0/MADATA05_0
7
69
P1E/AN14/RTS4_1/DTTI0X_1/MAD22_0
P56/INT08_2/DTTI1X_0/MADATA06_0
8
68
P1D/AN13/CTS4_1/IC03_1/MAD21_0
P30/AIN0_0/TIOB0_1/INT03_2/MADATA07_0
9
67
P1C/AN12/SCK4_1/IC02_1/MAD20_0
P31/BIN0_0/TIOB1_1/SCK6_1/INT04_2/MADATA08_0
10
66
P1B/AN11/SOT4_1/IC01_1/MAD19_0
P32/ZIN0_0/TIOB2_1/SOT6_1/INT05_2/MADATA09_0
11
65
P1A/AN10/SIN4_1/INT05_1/IC00_1/MAD18_0
P33/INT04_0/TIOB3_1/SIN6_1/ADTG_6/MADATA10_0
12
64
P19/AN09/SCK2_2/MAD17_0
P34/FRCK0_0/TIOB4_1/MADATA11_0
13
63
P18/AN08/SOT2_2/MAD16_0
P35/IC03_0/TIOB5_1/INT08_1/MADATA12_0
14
62
AVSS
P36/IC02_0/SIN5_2/INT09_1/MADATA13_0
15
61
AVRH
P37/IC01_0/SOT5_2/INT10_1/MADATA14_0
16
60
AVCC
P38/IC00_0/SCK5_2/INT11_1/MADATA15_0
17
59
P17/AN07/SIN2_2/INT04_1/MAD15_0
P39/DTTI0X_0/ADTG_2
18
58
P16/AN06/SCK0_1/MAD14_0
P3A/RTO00_0/TIOA0_1/RTCCO_2/SUBOUT_2
19
57
P15/AN05/SOT0_1/IC03_2/MAD13_0
P3B/RTO01_0/TIOA1_1
20
56
P14/AN04/SIN0_1/INT03_1/IC02_2/MAD12_0
P3C/RTO02_0/TIOA2_1
21
55
P13/AN03/SCK1_1/RTCCO_1/SUBOUT_1/IC01_2/MAD11_0
P3D/RTO03_0/TIOA3_1
22
54
P12/AN02/SOT1_1/IC00_2/MAD10_0
P3E/RTO04_0/TIOA4_1
23
53
P11/AN01/SIN1_1/INT02_1/FRCK0_2/MAD09_0
P3F/RTO05_0/TIOA5_1
24
52
P10/AN00
VSS
25
51
VCC
43
44
45
46
47
48
49
50
P4D/TIOB4_0/FRCK1_1/SOT7_1/BIN1_2/MAD07_0
P4E/TIOB5_0/INT06_2/SIN7_1/ZIN1_2/MAD08_0
PE0/MD1
MD0
PE2/X0
PE3/X1
VSS
37
P47/X1A
P4C/TIOB3_0/IC13_1/SCK7_1/AIN1_2/MAD06_0
36
P46/X0A
42
35
VCC
P4B/TIOB2_0/IC12_1/ZIN0_1/MAD05_0
34
VSS
41
33
C
P4A/TIOB1_0/IC11_1/BIN0_1/SCK3_2/MAD04_0
32
P45/TIOA5_0/RTO15_1/MAD01_0
40
31
P44/TIOA4_0/RTO14_1/MAD00_0
39
30
P43/TIOA3_0/RTO13_1/ADTG_7
P49/TIOB0_0/IC10_1/AIN0_1/SOT3_2/MAD03_0
29
P42/TIOA2_0/RTO12_1
38
28
P41/TIOA1_0/RTO11_1/INT13_1
INITX
27
P48/DTTI1X_1/INT14_1/SIN3_2/MAD02_0
26
VCC
P40/TIOA0_0/RTO10_1/INT12_1
LQFP - 100
Note:
− The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
Document Number: 002-05622 Rev. *D
Page 9 of 117
MB9B110R Series
LQM120
VSS
P81
P80
VCC
P60/SIN5_0/TIOA2_2/INT15_1/MRDY_0
P61/SOT5_0/TIOB2_2
P62/SCK5_0/ADTG_3/MOEX_0
P63/INT03_0/SIN5_1/RTO20_0/MWEX_0
P64/TIOA7_0/SOT5_1/INT10_2/FRCK2_1/RTO21_0
P65/TIOB7_0/SCK5_1/IC23_1/RTO22_0
P66/SIN3_0/ADTG_8/INT11_2/IC22_1/RTO23_0
P67/SOT3_0/TIOA7_2/IC21_1/RTO24_0
P68/SCK3_0/TIOB7_2/INT12_2/IC20_1/RTO25_0
P0F/NMIX/CROUT_1/RTCCO_0/DTTI2X_0/DTTI2X_1/SUBOUT_0
P0E/CTS4_0/TIOB3_2/IC13_0/IC23_0/RTO25_1/MDQM1_0
P0D/RTS4_0/TIOA3_2/IC12_0/IC22_0/RTO24_1/MDQM0_0
P0C/SCK4_0/TIOA6_1/IC11_0/IC21_0/RTO23_1/MALE_0
P0B/SOT4_0/TIOB6_1/IC10_0/IC20_0/RTO22_1/MCSX0_0
P0A/SIN4_0/INT00_2/FRCK1_0/FRCK2_0/RTO21_1/MCSX1_0
P09/TRACECLK/TIOB0_2/RTS4_2/RTO20_1/MCSX2_0
P08/TRACED3/TIOA0_2/CTS4_2/ZIN2_1/MCSX3_0
P07/TRACED2/ADTG_0/SCK4_2/BIN2_1/MCLKOUT_0
P06/TRACED1/TIOB5_2/SOT4_2/INT01_1/AIN2_1/MCSX4_0
P05/TRACED0/TIOA5_2/SIN4_2/INT00_1/MCSX5_0
P04/TDO/SWO
P03/TMS/SWDIO
P02/TDI/MCSX6_0
P01/TCK/SWCLK
P00/TRSTX/MCSX7_0
VCC
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
(TOP VIEW)
VCC
1
90
VSS
P50/INT00_0/AIN0_2/SIN3_1/RTO10_0/MADATA00_0
2
89
P20/INT05_0/CROUT_0/AIN1_1/MAD24_0
P51/INT01_0/BIN0_2/SOT3_1/RTO11_0/MADATA01_0
3
88
P21/SIN0_0/INT06_1/BIN1_1
P52/INT02_0/ZIN0_2/SCK3_1/RTO12_0/MADATA02_0
4
87
P22/SOT0_0/TIOB7_1/ZIN1_1
P53/SIN6_0/TIOA1_2/INT07_2/RTO13_0/MADATA03_0
5
86
P23/SCK0_0/TIOA7_1/RTO00_1
P54/SOT6_0/TIOB1_2/RTO14_0/MADATA04_0
6
85
P24/SIN2_1/INT01_2/RTO01_1
P55/SCK6_0/ADTG_1/RTO15_0/MADATA05_0
7
84
P25/SOT2_1/RTO02_1
P56/SIN1_0/INT08_2/DTTI1X_0/MADATA06_0
8
83
P26/SCK2_1/RTO03_1
P57/SOT1_0/MADATA07_0
9
82
P27/TIOA6_2/INT02_2/RTO04_1
P58/SCK1_0/AIN2_0/MADATA08_0
10
81
P28/TIOB6_2/ADTG_4/RTO05_1
P59/SIN7_0/INT09_2/BIN2_0/MADATA09_0
11
80
P1F/AN15/ADTG_5/FRCK0_1/MAD23_0
P5A/SOT7_0/ZIN2_0/MADATA10_0
12
79
P1E/AN14/RTS4_1/DTTI0X_1/MAD22_0
P5B/SCK7_0/MADATA11_0
13
78
P1D/AN13/CTS4_1/IC03_1/MAD21_0
LQFP - 120
51
52
53
54
55
56
57
58
59
60
P71/INT13_2/TIOB4_2
P72/SIN2_0/INT14_2/TIOA6_0
P73/SOT2_0/INT15_2/TIOB6_0
P74/SCK2_0
PE0/MD1
MD0
PE2/X0
PE3/X1
VSS
VCC
50
61
P70/TIOA4_2
30
49
P10/AN00
VSS
P4E/TIOB5_0/INT06_2/SIN7_1/ZIN1_2/MAD08_0
P11/AN01/SIN1_1/INT02_1/FRCK0_2/MAD09_0
62
P4D/TIOB4_0/FRCK1_1/SOT7_1/BIN1_2/MAD07_0
63
29
48
28
P3F/RTO05_0/TIOA5_1
P4C/TIOB3_0/IC13_1/SCK7_1/AIN1_2/MAD06_0
P12/AN02/SOT1_1/IC00_2/MAD10_0
P3E/RTO04_0/TIOA4_1
47
64
46
27
P4B/TIOB2_0/IC12_1/ZIN0_1/MAD05_0
P13/AN03/SCK1_1/RTCCO_1/SUBOUT_1/IC01_2/MAD11_0
P3D/RTO03_0/TIOA3_1
P4A/TIOB1_0/IC11_1/BIN0_1/SCK3_2/MAD04_0
65
45
26
P49/TIOB0_0/IC10_1/AIN0_1/SOT3_2/MAD03_0
P14/AN04/SIN0_1/INT03_1/IC02_2/MAD12_0
P3C/RTO02_0/TIOA2_1
44
P15/AN05/SOT0_1/IC03_2/MAD13_0
66
43
67
25
P48/DTTI1X_1/INT14_1/SIN3_2/MAD02_0
24
P3B/RTO01_0/TIOA1_1
42
P16/AN06/SCK0_1/MAD14_0
P3A/RTO00_0/TIOA0_1/RTCCO_2/SUBOUT_2
INITX
68
P47/X1A
23
41
P17/AN07/SIN2_2/INT04_1/MAD15_0
P39/DTTI0X_0/ADTG_2
P46/X0A
AVCC
69
40
70
22
39
21
P38/IC00_0/SCK5_2/INT11_1
VSS
AVRH
P37/IC01_0/SOT5_2/INT10_1/MNREX_0
VCC
71
38
20
C
AVSS
P36/IC02_0/SIN5_2/INT09_1/MNWEX_0
37
72
36
19
P45/TIOA5_0/RTO15_1/MAD01_0
P18/AN08/SOT2_2/MAD16_0
P35/IC03_0/TIOB5_1/INT08_1/MNCLE_0
35
P19/AN09/SCK2_2/MAD17_0
73
P43/TIOA3_0/RTO13_1/ADTG_7
74
18
P44/TIOA4_0/RTO14_1/MAD00_0
17
P34/FRCK0_0/TIOB4_1/MNALE_0
34
P1A/AN10/SIN4_1/INT05_1/IC00_1/MAD18_0
P33/INT04_0/TIOB3_1/SIN6_1/ADTG_6/MADATA15_0
P42/TIOA2_0/RTO12_1
75
33
16
32
P1B/AN11/SOT4_1/IC01_1/MAD19_0
P32/ZIN0_0/TIOB2_1/SOT6_1/INT05_2/MADATA14_0
31
P1C/AN12/SCK4_1/IC02_1/MAD20_0
76
VCC
77
15
P41/TIOA1_0/RTO11_1/INT13_1
14
P40/TIOA0_0/RTO10_1/INT12_1
P30/AIN0_0/TIOB0_1/INT03_2/MADATA12_0
P31/BIN0_0/TIOB1_1/SCK6_1/INT04_2/MADATA13_0
Note:
− The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
Document Number: 002-05622 Rev. *D
Page 10 of 117
MB9B110R Series
PQH100
VCC
VSS
P20/INT05_0/CROUT_0/AIN1_1/MAD24_0
P21/SIN0_0/INT06_1/BIN1_1
52
51
55
54
53
P02/TDI/MCSX6_0
P01/TCK/SWCLK
P00/TRSTX/MCSX7_0
57
56
P05/TRACED0/TIOA5_2/SIN4_2/INT00_1/MCSX5_0
P04/TDO/SWO
P03/TMS/SWDIO
60
59
58
P08/TRACED3/TIOA0_2/CTS4_2/ZIN2_1/MCSX3_0
P07/TRACED2/ADTG_0/SCK4_2/BIN2_1/MCLKOUT_0
P06/TRACED1/TIOB5_2/SOT4_2/INT01_1/AIN2_1/MCSX4_0
63
62
61
P0B/SOT4_0/TIOB6_1/IC10_0/IC20_0/RTO22_1/MCSX0_0
P0A/SIN4_0/INT00_2/FRCK1_0/FRCK2_0/RTO21_1/MCSX1_0
P09/TRACECLK/TIOB0_2/RTS4_2/RTO20_1/MCSX2_0
66
65
64
P0E/CTS4_0/TIOB3_2/IC13_0/IC23_0/RTO25_1/MDQM1_0
P0D/RTS4_0/TIOA3_2/IC12_0/IC22_0/RTO24_1/MDQM0_0
P0C/SCK4_0/TIOA6_1/IC11_0/IC21_0/RTO23_1/MALE_0
69
68
67
P62/SCK5_0/ADTG_3/MOEX_0
P63/INT03_0/SIN5_1/MWEX_0
P0F/NMIX/CROUT_1/RTCCO_0/DTTI2X_0/DTTI2X_1/SUBOUT_0
72
71
70
VCC
P60/SIN5_0/TIOA2_2/INT15_1/MRDY_0
P61/SOT5_0/TIOB2_2
75
74
73
VSS
P81
P80
78
77
76
P50/INT00_0/AIN0_2/SIN3_1/RTO10_0/MADATA00_0
VCC
80
79
(TOP VIEW)
P51/INT01_0/BIN0_2/SOT3_1/RTO11_0/MADATA01_0
81
50
P22/SOT0_0/TIOB7_1/ZIN1_1
P52/INT02_0/ZIN0_2/SCK3_1/RTO12_0/MADATA02_0
82
49
P23/SCK0_0/TIOA7_1
P53/SIN6_0/TIOA1_2/INT07_2/RTO13_0/MADATA03_0
83
48
P1F/AN15/ADTG_5/FRCK0_1/MAD23_0
P54/SOT6_0/TIOB1_2/RTO14_0/MADATA04_0
84
47
P1E/AN14/RTS4_1/DTTI0X_1/MAD22_0
P55/SCK6_0/ADTG_1/RTO15_0/MADATA05_0
85
46
P1D/AN13/CTS4_1/IC03_1/MAD21_0
P56/INT08_2/DTTI1X_0/MADATA06_0
86
45
P1C/AN12/SCK4_1/IC02_1/MAD20_0
P30/AIN0_0/TIOB0_1/INT03_2/MADATA07_0
87
44
P1B/AN11/SOT4_1/IC01_1/MAD19_0
P31/BIN0_0/TIOB1_1/SCK6_1/INT04_2/MADATA08_0
88
43
P1A/AN10/SIN4_1/INT05_1/IC00_1/MAD18_0
P32/ZIN0_0/TIOB2_1/SOT6_1/INT05_2/MADATA09_0
89
42
P19/AN09/SCK2_2/MAD17_0
P33/INT04_0/TIOB3_1/SIN6_1/ADTG_6/MADATA10_0
90
41
P18/AN08/SOT2_2/MAD16_0
QFP - 100
29
30
VCC
VSS
P10/AN00
26
27
28
PE3/X1
24
25
MD0
PE0/MD1
PE2/X0
21
22
23
P4C/TIOB3_0/IC13_1/SCK7_1/AIN1_2/MAD06_0
P4E/TIOB5_0/INT06_2/SIN7_1/ZIN1_2/MAD08_0
P4B/TIOB2_0/IC12_1/ZIN0_1/MAD05_0
P4D/TIOB4_0/FRCK1_1/SOT7_1/BIN1_2/MAD07_0
18
19
20
P49/TIOB0_0/IC10_1/AIN0_1/SOT3_2/MAD03_0
P4A/TIOB1_0/IC11_1/BIN0_1/SCK3_2/MAD04_0
15
16
17
INITX
P47/X1A
P48/DTTI1X_1/INT14_1/SIN3_2/MAD02_0
12
13
VSS
P41/TIOA1_0/RTO11_1/INT13_1
14
P11/AN01/SIN1_1/INT02_1/FRCK0_2/MAD09_0
VCC
31
P46/X0A
P12/AN02/SOT1_1/IC00_2/MAD10_0
P3D/RTO03_0/TIOA3_1 100
9
32
10
99
11
P13/AN03/SCK1_1/RTCCO_1/SUBOUT_1/IC01_2/MAD11_0
P3C/RTO02_0/TIOA2_1
C
P14/AN04/SIN0_1/INT03_1/IC02_2/MAD12_0
33
P44/TIOA4_0/RTO14_1/MAD00_0
34
98
P45/TIOA5_0/RTO15_1/MAD01_0
97
P3B/RTO01_0/TIOA1_1
6
P15/AN05/SOT0_1/IC03_2/MAD13_0
P3A/RTO00_0/TIOA0_1/RTCCO_2/SUBOUT_2
7
35
8
96
P42/TIOA2_0/RTO12_1
P16/AN06/SCK0_1/MAD14_0
P39/DTTI0X_0/ADTG_2
P43/TIOA3_0/RTO13_1/ADTG_7
P17/AN07/SIN2_2/INT04_1/MAD15_0
36
3
37
95
4
94
P38/IC00_0/SCK5_2/INT11_1/MADATA15_0
5
AVCC
P37/IC01_0/SOT5_2/INT10_1/MADATA14_0
VSS
38
VCC
93
P40/TIOA0_0/RTO10_1/INT12_1
AVRH
P36/IC02_0/SIN5_2/INT09_1/MADATA13_0
1
AVSS
39
2
40
92
P3F/RTO05_0/TIOA5_1
91
P3E/RTO04_0/TIOA4_1
P34/FRCK0_0/TIOB4_1/MADATA11_0
P35/IC03_0/TIOB5_1/INT08_1/MADATA12_0
Note:
− The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
Document Number: 002-05622 Rev. *D
Page 11 of 117
MB9B110R Series
LBC112
(TOP VIEW)
1
2
3
4
5
6
7
8
A
VSS
P81
P80
VCC
P0E
P0B
P07
B
VCC
VSS
P52
P61
P0F
P0C
P08
TDO/
SWO
C
P50
P51
VSS
P60
P62
P0D
P09
D
P53
P54
P55
VSS
P56
P63
P0A
E
P30
P31
P32
P33
Index
F
P34
P35
P36
G
P37
P38
H
P3B
J
9
10
11
VCC
VSS
TCK/
SWCLK
VSS
TDI
P05
VSS
P20
P21
VSS
P06
P23
AN15
P22
AN14
AN12
AN11
P39
AN13
AN10
AN09
AVRH
P3A
P3D
AN08
AN07
AN06
AVSS
P3C
P3E
VSS
P44
P4C
AN05
VSS
AN04
AN03
AVCC
VCC
P3F
VSS
P40
P43
P49
P4D
AN02
VSS
AN01
AN00
K
VCC
VSS
X1A
INITX
P42
P48
P4B
P4E
MD1
VSS
VCC
L
VSS
C
X0A
VSS
P41
P45
P4A
MD0
X0
X1
VSS
TMS/
TRSTX
SWDIO
PFBGA - 112
Note:
− The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
Document Number: 002-05622 Rev. *D
Page 12 of 117
MB9B110R Series
4. List of Pin Functions
List of pin numbers
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
LQFP-100
1
Pin No
FBGA-112
LQFP-120
B1
1
QFP-100
79
2
C1
2
80
3
C2
3
81
4
B3
4
82
5
D1
5
83
6
D2
6
84
Document Number: 002-05622 Rev. *D
Pin Name
I/O circuit
type
VCC
P50
INT00_0
AIN0_2
SIN3_1
RTO10_0
(PPG10_0)
MADATA00_0
P51
INT01_0
BIN0_2
SOT3_1
(SDA3_1)
RTO11_0
(PPG10_0)
MADATA01_0
P52
INT02_0
ZIN0_2
SCK3_1
(SCL3_1)
RTO12_0
(PPG12_0)
MADATA02_0
P53
SIN6_0
TIOA1_2
INT07_2
RTO13_0
(PPG12_0)
MADATA03_0
P54
SOT6_0
(SDA6_0)
TIOB1_2
RTO14_0
(PPG14_0)
MADATA04_0
Pin state
type
-
E
H
E
H
E
H
E
H
E
I
Page 13 of 117
MB9B110R Series
LQFP-100
Pin No
FBGA-112
LQFP-120
7
D3
8
D5
7
QFP-100
85
86
8
-
-
-
-
9
-
-
-
10
-
-
-
11
-
-
-
-
12
-
Pin Name
P55
SCK6_0
(SCL6_0)
ADTG_1
RTO15_0
(PPG14_0)
MADATA05_0
P56
I/O circuit
type
Pin state
type
E
I
E
H
E
I
E
I
E
H
E
I
E
I
INT08_2
DTTI1X_0
MADATA06_0
SIN1_0
(120pin only)
P57
SOT1_0
(SDA1_0)
MADATA07_0
P58
SCK1_0
(SCL1_0)
AIN2_0
MADATA08_0
P59
SIN7_0
INT09_2
BIN2_0
MADATA09_0
P5A
SOT7_0
(SDA7_0)
ZIN2_0
MADATA10_0
-
-
Document Number: 002-05622 Rev. *D
13
-
P5B
SCK7_0
(SCL7_0)
MADATA11_0
Page 14 of 117
MB9B110R Series
LQFP-100
Pin No
FBGA-112
LQFP-120
QFP-100
14
9
E1
87
-
-
14
-
Pin Name
P30
AIN0_0
TIOB0_1
INT03_2
MADATA07_0
(100pin only)
MADATA12_0
(120pin only)
P31
I/O circuit
type
Pin state
type
E
H
E
H
E
H
E
H
E
I
BIN0_0
15
10
E2
88
-
-
11
E3
15
-
16
89
-
-
12
E4
16
-
17
90
-
-
13
F1
17
-
18
91
-
-
Document Number: 002-05622 Rev. *D
18
-
TIOB1_1
SCK6_1
(SCL6_1)
INT04_2
MADATA08_0
(100pin only)
MADATA13_0
(120pin only)
P32
ZIN0_0
TIOB2_1
SOT6_1
(SDA6_1)
INT05_2
MADATA09_0
(100pin only)
MADATA14_0
(120pin only)
P33
INT04_0
TIOB3_1
SIN6_1
ADTG_6
MADATA10_0
(100pin only)
MADATA15_0
(120pin only)
P34
FRCK0_0
TIOB4_1
MADATA11_0
(100pin only)
MNALE_0
(120pin only)
Page 15 of 117
MB9B110R Series
LQFP-100
Pin No
FBGA-112
LQFP-120
QFP-100
19
14
F2
92
-
-
-
15
F3
19
-
20
93
-
-
16
G1
20
-
21
94
-
-
17
G2
21
-
22
95
18
F4
23
96
19
G3
24
97
-
B2
-
-
Document Number: 002-05622 Rev. *D
Pin Name
P35
IC03_0
TIOB5_1
INT08_1
MADATA12_0
(100pin only)
MNCLE_0
(120pin only)
P36
IC02_0
SIN5_2
INT09_1
MADATA13_0
(100pin only)
MNWEX_0
(120pin only)
P37
IC01_0
SOT5_2
(SDA5_2)
INT10_1
MADATA14_0
(100pin only)
MNREX_0
(120pin only)
P38
IC00_0
SCK5_2
(SCL5_2)
INT11_1
MADATA15_0
(100pin only)
P39
DTTI0X_0
ADTG_2
P3A
RTO00_0
(PPG00_0)
TIOA0_1
RTCCO_2
SUBOUT_2
VSS
I/O circuit
type
Pin state
type
E
H
E
H
E
H
E
H
E
I
G
I
-
Page 16 of 117
MB9B110R Series
LQFP-100
Pin No
FBGA-112
LQFP-120
QFP-100
20
H1
25
98
21
H2
26
99
22
G4
27
100
23
H3
28
1
24
J2
29
2
25
26
L1
J1
30
31
3
4
27
J4
32
5
28
L5
33
6
29
K5
34
7
30
J5
35
8
-
K2
J3
H4
-
-
Document Number: 002-05622 Rev. *D
Pin Name
P3B
RTO01_0
(PPG00_0)
TIOA1_1
P3C
RTO02_0
(PPG02_0)
TIOA2_1
P3D
RTO03_0
(PPG02_0)
TIOA3_1
P3E
RTO04_0
(PPG04_0)
TIOA4_1
P3F
RTO05_0
(PPG04_0)
TIOA5_1
VSS
VCC
P40
TIOA0_0
RTO10_1
(PPG10_1)
INT12_1
P41
TIOA1_0
RTO11_1
(PPG10_1)
INT13_1
P42
TIOA2_0
RTO12_1
(PPG12_1)
P43
TIOA3_0
RTO13_1
(PPG12_1)
ADTG_7
VSS
VSS
VSS
I/O circuit
type
Pin state
type
G
I
G
I
G
I
G
I
G
I
-
G
H
G
H
G
I
G
I
-
Page 17 of 117
MB9B110R Series
LQFP-100
Pin No
FBGA-112
LQFP-120
QFP-100
31
H5
36
9
32
L6
37
10
33
34
35
L2
L4
K1
38
39
40
11
12
13
36
L3
41
14
37
K3
42
15
38
K4
43
16
39
K6
44
17
40
J6
45
18
41
L7
46
19
42
K7
47
20
Document Number: 002-05622 Rev. *D
Pin Name
P44
TIOA4_0
RTO14_1
(PPG14_1)
MAD00_0
P45
TIOA5_0
RTO15_1
(PPG14_1)
MAD01_0
C
VSS
VCC
P46
X0A
P47
X1A
INITX
P48
DTTI1X_1
INT14_1
SIN3_2
MAD02_0
P49
TIOB0_0
IC10_1
AIN0_1
SOT3_2
(SDA3_2)
MAD03_0
P4A
TIOB1_0
IC11_1
BIN0_1
SCK3_2
(SCL3_2)
MAD04_0
P4B
TIOB2_0
IC12_1
ZIN0_1
MAD05_0
I/O circuit
type
Pin state
type
G
I
G
I
D
M
D
N
B
C
E
H
E
I
E
I
E
I
Page 18 of 117
MB9B110R Series
LQFP-100
Pin No
FBGA-112
LQFP-120
QFP-100
43
H6
48
21
44
J7
49
22
45
K8
50
23
-
-
51
-
-
-
52
-
-
-
53
-
-
-
54
-
-
-
55
-
46
K9
56
24
47
L8
57
25
Document Number: 002-05622 Rev. *D
Pin Name
P4C
TIOB3_0
IC13_1
SCK7_1
(SCL7_1)
AIN1_2
MAD06_0
P4D
TIOB4_0
FRCK1_1
SOT7_1
(SDA7_1)
BIN1_2
MAD07_0
P4E
TIOB5_0
INT06_2
SIN7_1
ZIN1_2
MAD08_0
P70
TIOA4_2
P71
INT13_2
TIOB4_2
P72
SIN2_0
INT14_2
TIOA6_0
P73
SOT2_0
(SDA2_0)
INT15_2
TIOB6_0
P74
SCK2_0
(SCL2_0)
PE0
MD1
MD0
I/O circuit
type
Pin state
type
I*
I
I*
I
I*
H
E
I
E
H
E
H
E
H
E
I
C
P
J
D
Page 19 of 117
MB9B110R Series
LQFP-100
Pin No
FBGA-112
LQFP-120
QFP-100
48
L9
58
26
49
L10
59
27
50
51
L11
K11
60
61
28
29
52
J11
62
30
53
J10
63
31
-
K10
J9
-
-
54
J8
64
32
55
H10
65
33
Document Number: 002-05622 Rev. *D
Pin Name
PE2
X0
PE3
X1
VSS
VCC
P10
AN00
P11
AN01
SIN1_1
INT02_1
FRCK0_2
MAD09_0
VSS
VSS
P12
AN02
SOT1_1
(SDA1_1)
IC00_2
MAD10_0
P13
AN03
SCK1_1
(SCL1_1)
RTCCO_1
SUBOUT_1
IC01_2
MAD11_0
I/O circuit
type
Pin state
type
A
A
A
B
-
F
K
F
L
-
F
K
F
K
Page 20 of 117
MB9B110R Series
LQFP-100
Pin No
FBGA-112
LQFP-120
QFP-100
56
H9
66
34
57
H7
67
35
58
G10
68
36
59
G9
69
37
60
61
62
H11
F11
G11
70
71
72
38
39
40
63
G8
73
41
64
F10
74
42
65
F9
75
43
-
H8
-
-
Document Number: 002-05622 Rev. *D
Pin Name
P14
AN04
SIN0_1
INT03_1
IC02_2
MAD12_0
P15
AN05
SOT0_1
(SDA0_1)
IC03_2
MAD13_0
P16
AN06
SCK0_1
(SCL0_1)
MAD14_0
P17
AN07
SIN2_2
INT04_1
MAD15_0
AVCC
AVRH
AVSS
P18
AN08
SOT2_2
(SDA2_2)
MAD16_0
P19
AN09
SCK2_2
(SCL2_2)
MAD17_0
P1A
AN10
SIN4_1
INT05_1
IC00_1
MAD18_0
VSS
I/O circuit
type
Pin state
type
F
L
F
K
F
K
F
L
-
F
K
F
K
F
L
-
Page 21 of 117
MB9B110R Series
LQFP-100
Pin No
FBGA-112
LQFP-120
QFP-100
66
E11
76
44
67
E10
77
45
68
F8
78
46
69
E9
79
47
70
D11
80
48
-
-
81
-
-
-
82
-
-
-
83
-
Document Number: 002-05622 Rev. *D
Pin Name
P1B
AN11
SOT4_1
(SDA4_1)
IC01_1
MAD19_0
P1C
AN12
SCK4_1
(SCL4_1)
IC02_1
MAD20_0
P1D
AN13
CTS4_1
IC03_1
MAD21_0
P1E
AN14
RTS4_1
DTTI0X_1
MAD22_0
P1F
AN15
ADTG_5
FRCK0_1
MAD23_0
P28
TIOB6_2
ADTG_4
RTO05_1
(PPG04_1)
P27
TIOA6_2
INT02_2
RTO04_1
(PPG04_1)
P26
SCK2_1
(SCL2_1)
RTO03_1
(PPG02_1)
I/O circuit
type
Pin state
type
F
K
F
K
F
K
F
K
F
K
E
I
E
H
E
I
Page 22 of 117
MB9B110R Series
LQFP-100
Pin No
FBGA-112
LQFP-120
QFP-100
-
-
84
-
-
B10
C9
-
-
-
-
85
-
71
D10
49
86
-
-
-
72
E8
87
50
73
C11
88
51
74
C10
89
52
75
76
A11
A10
90
91
53
54
77
A9
92
55
Pin Name
P25
SOT2_1
(SDA2_1)
RTO02_1
(PPG02_1)
VSS
VSS
P24
SIN2_1
INT01_2
RTO01_1
(PPG00_1)
P23
SCK0_0
(SCL0_0)
TIOA7_1
RTO00_1
(PPG00_1)
P22
SOT0_0
(SDA0_0)
TIOB7_1
ZIN1_1
P21
SIN0_0
INT06_1
BIN1_1
P20
INT05_0
CROUT_0
AIN1_1
MAD24_0
VSS
VCC
P00
TRSTX
MCSX7_0
I/O circuit
type
Pin state
type
E
I
-
E
H
E
I
E
I
E
H
E
H
E
E
E
E
P01
78
B9
Document Number: 002-05622 Rev. *D
93
56
TCK
SWCLK
Page 23 of 117
MB9B110R Series
LQFP-100
Pin No
FBGA-112
LQFP-120
QFP-100
79
B11
94
57
80
A8
95
58
81
B8
96
59
82
C8
97
60
-
D8
-
-
83
D9
98
61
84
A7
99
62
85
B7
100
63
86
C7
101
64
Document Number: 002-05622 Rev. *D
Pin Name
P02
TDI
MCSX6_0
P03
TMS
SWDIO
P04
TDO
SWO
P05
TRACED0
TIOA5_2
SIN4_2
INT00_1
MCSX5_0
VSS
P06
TRACED1
TIOB5_2
SOT4_2
(SDA4_2)
INT01_1
AIN2_1
MCSX4_0
P07
TRACED2
ADTG_0
SCK4_2
(SCL4_2)
BIN2_1
MCLKOUT_0
P08
TRACED3
TIOA0_2
CTS4_2
ZIN2_1
MCSX3_0
P09
TRACECLK
TIOB0_2
RTS4_2
RTO20_1
(PPG20_1)
MCSX2_0
I/O circuit
type
Pin state
type
E
E
E
E
E
E
E
F
-
E
F
E
G
E
G
E
G
Page 24 of 117
MB9B110R Series
LQFP-100
Pin No
FBGA-112
LQFP-120
QFP-100
87
D7
102
65
88
A6
103
66
89
B6
104
67
90
C6
105
68
91
A5
106
69
-
D4
C3
-
-
Document Number: 002-05622 Rev. *D
Pin Name
P0A
SIN4_0
INT00_2
FRCK1_0
FRCK2_0
RTO21_1
(PPG20_1)
MCSX1_0
P0B
SOT4_0
(SDA4_0)
TIOB6_1
IC10_0
IC20_0
RTO22_1
(PPG22_1)
MCSX0_0
P0C
SCK4_0
(SCL4_0)
TIOA6_1
IC11_0
IC21_0
RTO23_1
MALE_0
P0D
RTS4_0
TIOA3_2
IC12_0
IC22_0
RTO24_1
(PPG24_1)
MDQM0_0
P0E
CTS4_0
TIOB3_2
IC13_0
IC23_0
RTO25_1
(PPG24_1)
MDQM1_0
VSS
VSS
I/O circuit
type
Pin state
type
I*
H
I*
I
I*
I
E
I
E
I
-
Page 25 of 117
MB9B110R Series
LQFP-100
Pin No
FBGA-112
LQFP-120
QFP-100
Pin Name
I/O circuit
type
Pin state
type
E
J
G
H
G
I
G
H
G
I
G
H
P0F
92
B5
107
70
-
-
108
-
-
-
109
-
-
-
110
-
-
-
111
-
-
-
112
-
Document Number: 002-05622 Rev. *D
NMIX
CROUT_1
RTCCO_0
SUBOUT_0
DTTI2X_0
DTTI2X_1
P68
SCK3_0
(SCL3_0)
TIOB7_2
INT12_2
IC20_1
RTO25_0
(PPG24_0)
P67
SOT3_0
(SDA3_0)
TIOA7_2
IC21_1
RTO24_0
(PPG24_0)
P66
SIN3_0
ADTG_8
INT11_2
IC22_1
RTO23_0
(PPG22_0)
P65
TIOB7_0
SCK5_1
(SCL5_1)
IC23_1
RTO22_0
(PPG22_0)
P64
TIOA7_0
SOT5_1
(SDA5_1)
INT10_2
FRCK2_1
RTO21_0
(PPG20_0)
Page 26 of 117
MB9B110R Series
LQFP-100
Pin No
FBGA-112
LQFP-120
QFP-100
Pin Name
I/O circuit
type
Pin state
type
G
H
E
I
E
I
I*
H
-
-
94
C5
114
72
95
B4
115
73
96
C4
116
74
97
A4
117
75
P63
INT03_0
SIN5_1
MWEX_0
RTO20_0
(PPG20_0)
P62
SCK5_0
(SCL5_0)
ADTG_3
MOEX_0
P61
SOT5_0
(SDA5_0)
TIOB2_2
P60
SIN5_0
TIOA2_2
INT15_1
MRDY_0
VCC
98
A3
118
76
P80
H
99
100
A2
A1
119
120
77
78
P81
VSS
H
93
D6
71
113
-
O
O
-
*: 5 V tolerant I/O
Document Number: 002-05622 Rev. *D
Page 27 of 117
MB9B110R Series
List of pin functions
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
Module
Pin name
ADC
ADTG_0
ADTG_1
ADTG_2
ADTG_3
ADTG_4
ADTG_5
ADTG_6
ADTG_7
ADTG_8
AN00
AN01
AN02
AN03
AN04
AN05
AN06
AN07
AN08
AN09
AN10
AN11
AN12
AN13
AN14
AN15
TIOA0_0
TIOA0_1
TIOA0_2
TIOB0_0
TIOB0_1
TIOB0_2
TIOA1_0
TIOA1_1
TIOA1_2
TIOB1_0
TIOB1_1
TIOB1_2
TIOA2_0
TIOA2_1
TIOA2_2
TIOB2_0
TIOB2_1
TIOB2_2
Base Timer
0
Base Timer
1
Base Timer
2
Function
A/D converter external trigger input pin
A/D converter analog input pin.
ANxx describes ADC ch.xx.
Base timer ch.0 TIOA pin
Base timer ch.0 TIOB pin
Base timer ch.1 TIOA pin
Base timer ch.1 TIOB pin
Base timer ch.2 TIOA pin
Base timer ch.2 TIOB pin
Document Number: 002-05622 Rev. *D
LQFP100
84
7
18
94
70
12
30
52
53
54
55
56
57
58
59
63
64
65
66
67
68
69
70
27
19
85
40
9
86
28
20
5
41
10
6
29
21
96
42
11
95
Pin No
FBGA- LQFP112
120
A7
99
D3
7
F4
23
C5
114
81
D11
80
E4
17
J5
35
110
J11
62
J10
63
J8
64
H10
65
H9
66
H7
67
G10
68
G9
69
G8
73
F10
74
F9
75
E11
76
E10
77
F8
78
E9
79
D11
80
J4
32
G3
24
B7
100
J6
45
E1
14
C7
101
L5
33
H1
25
D1
5
L7
46
E2
15
D2
6
K5
34
H2
26
C4
116
K7
47
E3
16
B4
115
QFP100
62
85
96
72
48
90
8
30
31
32
33
34
35
36
37
41
42
43
44
45
46
47
48
5
97
63
18
87
64
6
98
83
19
88
84
7
99
74
20
89
73
Page 28 of 117
MB9B110R Series
Module
Pin name
Base Timer
3
TIOA3_0
TIOA3_1
TIOA3_2
TIOB3_0
TIOB3_1
TIOB3_2
TIOA4_0
TIOA4_1
TIOA4_2
TIOB4_0
TIOB4_1
TIOB4_2
TIOA5_0
TIOA5_1
TIOA5_2
TIOB5_0
TIOB5_1
TIOB5_2
TIOA6_0
TIOA6_1
TIOA6_2
TIOB6_0
TIOB6_1
TIOB6_2
TIOA7_0
TIOA7_1
TIOA7_2
TIOB7_0
TIOB7_1
TIOB7_2
Base Timer
4
Base Timer
5
Base Timer
6
Base Timer
7
Function
Base timer ch.3 TIOA pin
Base timer ch.3 TIOB pin
Base timer ch.4 TIOA pin
Base timer ch.4 TIOB pin
Base timer ch.5 TIOA pin
Base timer ch.5 TIOB pin
Base timer ch.6 TIOA pin
Base timer ch.6 TIOB pin
Base timer ch.7 TIOA pin
Base timer ch.7 TIOB pin
Document Number: 002-05622 Rev. *D
LQFP100
30
22
90
43
12
91
31
23
44
13
32
24
82
45
14
83
89
88
71
72
-
Pin No
FBGA- LQFP112
120
J5
35
G4
27
C6
105
H6
48
E4
17
A5
106
H5
36
H3
28
51
J7
49
F1
18
52
L6
37
J2
29
C8
97
K8
50
F2
19
D9
98
53
B6
104
82
54
A6
103
81
112
D10
86
109
111
E8
87
108
QFP100
8
100
68
21
90
69
9
1
22
91
10
2
60
23
92
61
67
66
49
50
-
Page 29 of 117
MB9B110R Series
Module
Pin name
Function
Debugger
SWCLK
Serial wire debug interface clock input pin
Serial wire debug interface data input / output
pin
Serial wire viewer output pin
JTAG test clock input pin
JTAG test data input pin
JTAG debug data output pin
JTAG test mode state input/output pin
Trace CLK output pin of ETM
SWDIO
External
Bus
SWO
TCK
TDI
TDO
TMS
TRACECLK
TRACED0
TRACED1
TRACED2
TRACED3
TRSTX
MAD00_0
MAD01_0
MAD02_0
MAD03_0
MAD04_0
MAD05_0
MAD06_0
MAD07_0
MAD08_0
MAD09_0
MAD10_0
MAD11_0
MAD12_0
MAD13_0
MAD14_0
MAD15_0
MAD16_0
MAD17_0
MAD18_0
MAD19_0
MAD20_0
MAD21_0
MAD22_0
MAD23_0
MAD24_0
MCSX0_0
MCSX1_0
MCSX2_0
MCSX3_0
MCSX4_0
MCSX5_0
MCSX6_0
MCSX7_0
Trace data output pin of ETM
JTAG test reset input pin
External bus interface address bus
External bus interface chip select output pin
Document Number: 002-05622 Rev. *D
LQFP100
78
Pin No
FBGA- LQFP112
120
B9
93
QFP100
56
80
A8
95
58
81
78
79
81
80
86
82
83
84
85
77
31
32
39
40
41
42
43
44
45
53
54
55
56
57
58
59
63
64
65
66
67
68
69
70
74
88
87
86
85
83
82
79
77
B8
B9
B11
B8
A8
C7
C8
D9
A7
B7
A9
H5
L6
K6
J6
L7
K7
H6
J7
K8
J10
J8
H10
H9
H7
G10
G9
G8
F10
F9
E11
E10
F8
E9
D11
C10
A6
D7
C7
B7
D9
C8
B11
A9
96
93
94
96
95
101
97
98
99
100
92
36
37
44
45
46
47
48
49
50
63
64
65
66
67
68
69
73
74
75
76
77
78
79
80
89
103
102
101
100
98
97
94
92
59
56
57
59
58
64
60
61
62
63
55
9
10
17
18
19
20
21
22
23
31
32
33
34
35
36
37
41
42
43
44
45
46
47
48
52
66
65
64
63
61
60
57
55
Page 30 of 117
MB9B110R Series
Module
Pin name
External
Bus
MADATA0_0
MADATA1_0
MADATA2_0
MADATA3_0
MADATA4_0
MADATA5_0
MADATA6_0
MADATA7_0
MADATA8_0
MADATA9_0
MADATA10_0
MADATA11_0
MADATA12_0
MADATA13_0
MADATA14_0
MADATA15_0
MDQM0_0
MDQM1_0
MALE_0
MRDY_0
MCLKOUT_0
MNALE_0
MNCLE_0
MNREX_0
MNWEX_0
MOEX_0
MWEX_0
Function
External bus interface data bus
(Address / data multiplex bus)
External bus interface byte mask signal
output pin
External bus interface Address Latch
enable output signal for multiplex
External bus interface external RDY input
signal
External bus interface external clock output
pin
External bus interface ALE signal to control
NAND Flash output pin
External bus interface CLE signal to control
NAND Flash output pin
External bus interface read enable signal to
control NAND Flash
External bus interface write enable signal to
control NAND Flash
External bus interface read enable signal
for SRAM
External bus interface write enable signal
for SRAM
Document Number: 002-05622 Rev. *D
LQFP100
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
90
91
Pin No
FBGA- LQFP112
120
C1
2
C2
3
B3
4
D1
5
D2
6
D3
7
D5
8
E1
9
E2
10
E3
11
E4
12
F1
13
F2
14
F3
15
G1
16
G2
17
C6
105
A5
106
QFP100
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
68
69
89
B6
104
67
96
C4
116
74
84
A7
99
62
-
-
18
-
-
-
19
-
-
-
21
-
-
-
20
-
94
C5
114
72
93
D6
113
71
Page 31 of 117
MB9B110R Series
Module
Pin name
External
Interrupt
INT00_0
INT00_1
INT00_2
INT01_0
INT01_1
INT01_2
INT02_0
INT02_1
INT02_2
INT03_0
INT03_1
INT03_2
INT04_0
INT04_1
INT04_2
INT05_0
INT05_1
INT05_2
INT06_1
INT06_2
INT07_2
INT08_1
INT08_2
INT09_1
INT09_2
INT10_1
INT10_2
INT11_1
INT11_2
INT12_1
INT12_2
INT13_1
INT13_2
INT14_1
INT14_2
INT15_1
INT15_2
NMIX
Function
External interrupt request 00 input pin
External interrupt request 01 input pin
External interrupt request 02 input pin
External interrupt request 03 input pin
External interrupt request 04 input pin
External interrupt request 05 input pin
External interrupt request 06 input pin
External interrupt request 07 input pin
External interrupt request 08 input pin
External interrupt request 09 input pin
External interrupt request 10 input pin
External interrupt request 11 input pin
External interrupt request 12 input pin
External interrupt request 13 input pin
External interrupt request 14 input pin
External interrupt request 15 input pin
Non-Maskable Interrupt input pin
Document Number: 002-05622 Rev. *D
LQFP100
2
82
87
3
83
4
53
93
56
9
12
59
10
74
65
11
73
45
5
14
8
15
16
17
27
28
39
96
92
Pin No
FBGA- LQFP112
120
C1
2
C8
97
D7
102
C2
3
D9
98
85
B3
4
J10
63
82
D6
113
H9
66
E1
14
E4
17
G9
69
E2
15
C10
89
F9
75
E3
16
C11
88
K8
50
D1
5
F2
19
D5
8
F3
20
11
G1
21
112
G2
22
110
J4
32
108
L5
33
52
K6
44
53
C4
116
54
B5
107
QFP100
80
60
65
81
61
82
31
71
34
87
90
37
88
52
43
89
51
23
83
92
86
93
94
95
5
6
17
74
70
Page 32 of 117
MB9B110R Series
Module
Pin name
GPIO
P00
P01
P02
P03
P04
P05
P06
P07
P08
P09
P0A
P0B
P0C
P0D
P0E
P0F
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P1A
P1B
P1C
P1D
P1E
P1F
P20
P21
P22
P23
P24
P25
P26
P27
P28
Function
General-purpose I/O port 0
General-purpose I/O port 1
General-purpose I/O port 2
Document Number: 002-05622 Rev. *D
LQFP100
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
52
53
54
55
56
57
58
59
63
64
65
66
67
68
69
70
74
73
72
71
-
Pin No
FBGA- LQFP112
120
A9
92
B9
93
B11
94
A8
95
B8
96
C8
97
D9
98
A7
99
B7
100
C7
101
D7
102
A6
103
B6
104
C6
105
A5
106
B5
107
J11
62
J10
63
J8
64
H10
65
H9
66
H7
67
G10
68
G9
69
G8
73
F10
74
F9
75
E11
76
E10
77
F8
78
E9
79
D11
80
C10
89
C11
88
E8
87
D10
86
85
84
83
82
81
QFP100
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
30
31
32
33
34
35
36
37
41
42
43
44
45
46
47
48
52
51
50
49
-
Page 33 of 117
MB9B110R Series
Module
Pin name
GPIO
P30
P31
P32
P33
P34
P35
P36
P37
P38
P39
P3A
P3B
P3C
P3D
P3E
P3F
P40
P41
P42
P43
P44
P45
P46
P47
P48
P49
P4A
P4B
P4C
P4D
P4E
P50
P51
P52
P53
P54
P55
P56
P57
P58
P59
P5A
P5B
Function
General-purpose I/O port 3
General-purpose I/O port 4
General-purpose I/O port 5
Document Number: 002-05622 Rev. *D
LQFP100
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
27
28
29
30
31
32
36
37
39
40
41
42
43
44
45
2
3
4
5
6
7
8
-
Pin No
FBGA- LQFP112
120
E1
14
E2
15
E3
16
E4
17
F1
18
F2
19
F3
20
G1
21
G2
22
F4
23
G3
24
H1
25
H2
26
G4
27
H3
28
J2
29
J4
32
L5
33
K5
34
J5
35
H5
36
L6
37
L3
41
K3
42
K6
44
J6
45
L7
46
K7
47
H6
48
J7
49
K8
50
C1
2
C2
3
B3
4
D1
5
D2
6
D3
7
D5
8
9
10
11
12
13
QFP100
87
88
89
90
91
92
93
94
95
96
97
98
99
100
1
2
5
6
7
8
9
10
14
15
17
18
19
20
21
22
23
80
81
82
83
84
85
86
-
Page 34 of 117
MB9B110R Series
Module
Pin name
GPIO
P60
P61
P62
P63
P64
P65
P66
P67
P68
P70
P71
P72
P73
P74
P80
P81
PE0
PE2
PE3
SIN0_0
SIN0_1
Multifunction
Serial
0
SOT0_0
(SDA0_0)
SOT0_1
(SDA0_1)
SCK0_0
(SCL0_0)
SCK0_1
(SCL0_1)
Multifunction
Serial
1
SIN1_0
SIN1_1
SOT1_0
(SDA1_0)
SOT1_1
(SDA1_1)
SCK1_0
(SCL1_0)
SCK1_1
(SCL1_1)
Function
General-purpose I/O port 6
General-purpose I/O port 7
General-purpose I/O port 8
General-purpose I/O port E
Multi-function serial interface ch.0 input pin
Multi-function serial interface ch.0 output pin.
This pin operates as SOT0 when it is used in a
UART/CSIO/LIN (operation modes 0 to 3) and
as SDA0 when it is used in an I2C (operation
mode 4).
Multi-function serial interface ch.0 clock I/O
pin.
This pin operates as SCK0 when it is used in a
UART/CSIO/LIN (operation modes 0 to 3) and
as SCL0 when it is used in an I2C (operation
mode 4).
Multi-function serial interface ch.1 input pin
Multi-function serial interface ch.1 output pin.
This pin operates as SOT1 when it is used in a
UART/CSIO/LIN (operation modes 0 to 3) and
as SDA1 when it is used in an I2C (operation
mode 4).
Multi-function serial interface ch.1 clock I/O
pin.
This pin operates as SCK1 when it is used in a
CSIO (operation modes 4) and as SCL1 when
it is used in an I2C (operation mode 4).
Document Number: 002-05622 Rev. *D
LQFP100
96
95
94
93
98
99
46
48
49
73
56
Pin No
FBGA- LQFP112
120
C4
116
B4
115
C5
114
D6
113
112
111
110
109
108
51
52
53
54
55
A3
118
A2
119
K9
56
L9
58
L10
59
C11
88
H9
66
QFP100
74
73
72
71
76
77
24
26
27
51
34
72
E8
87
50
57
H7
67
35
71
D10
86
49
58
G10
68
36
53
J10
8
63
31
-
-
9
-
54
J8
64
32
-
-
10
-
55
H10
65
33
Page 35 of 117
MB9B110R Series
Module
Pin name
Multifunction
Serial
2
SIN2_0
SIN2_1
SIN2_2
SOT2_0
(SDA2_0)
SOT2_1
(SDA2_1)
SOT2_2
(SDA2_2)
SCK2_0
(SCL2_0)
SCK2_1
(SCL2_1)
SCK2_2
(SCL2_2)
SIN3_0
Multifunction
Serial
3
SIN3_1
SIN3_2
SOT3_0
(SDA3_0)
SOT3_1
(SDA3_1)
SOT3_2
(SDA3_2)
SCK3_0
(SCL3_0)
SCK3_1
(SCL3_1)
SCK3_2
(SCL3_2)
Function
Multi-function serial interface ch.2 input pin
Multi-function serial interface ch.2 output pin.
This pin operates as SOT2 when it is used in a
UART/CSIO/LIN (operation modes 0 to 3) and
as SDA2 when it is used in an I2C (operation
mode 4).
LQFP100
59
Pin No.
FBGA- LQFP112
120
53
85
G9
69
QFP100
37
-
-
54
-
-
-
84
-
63
G8
73
41
-
-
55
-
Multi-function serial interface ch.2 clock I/O
pin.
This pin operates as SCK2 when it is used in a
CSIO (operation modes 2) and as SCL2 when
it is used in an I2C (operation mode 4).
-
-
83
-
64
F10
74
42
-
-
110
-
Multi-function serial interface ch.3 input pin
2
C1
2
80
39
K6
44
17
-
-
109
-
3
C2
3
81
40
J6
45
18
-
-
108
-
4
B3
4
82
41
L7
46
19
Multi-function serial interface ch.3 output pin.
This pin operates as SOT3 when it is used in a
UART/CSIO/LIN (operation modes 0 to 3) and
as SDA3 when it is used in an I2C (operation
mode 4).
Multi-function serial interface ch.3 clock I/O
pin.
This pin operates as SCK3 when it is used in a
CSIO (operation modes 2) and as SCL3 when
it is used in an I2C (operation mode 4).
Document Number: 002-05622 Rev. *D
Page 36 of 117
MB9B110R Series
Module
Pin name
Multifunction
Serial
4
SIN4_0
SIN4_1
SIN4_2
SOT4_0
(SDA4_0)
SOT4_1
(SDA4_1)
SOT4_2
(SDA4_2)
SCK4_0
(SCL4_0)
SCK4_1
(SCL4_1)
SCK4_2
(SCL4_2)
RTS4_0
RTS4_1
RTS4_2
CTS4_0
CTS4_1
CTS4_2
SIN5_0
SIN5_1
SIN5_2
SOT5_0
(SDA5_0)
SOT5_1
(SDA5_1)
SOT5_2
(SDA5_2)
SCK5_0
(SCL5_0)
SCK5_1
(SCL5_1)
SCK5_2
(SCL5_2)
Multifunction
Serial
5
Function
Multi-function serial interface ch.4 input pin
LQFP100
87
65
82
Pin No
FBGA- LQFP112
120
D7
102
F9
75
C8
97
QFP100
65
43
60
Multi-function serial interface ch.4 output pin.
This pin operates as SOT4 when it is used in
a UART/CSIO/LIN (operation modes 0 to 3)
and as SDA4 when it is used in an I2C
(operation mode 4).
88
A6
103
66
66
E11
76
44
83
D9
98
61
Multi-function serial interface ch.4 clock I/O
pin.
This pin operates as SCK4 when it is used in
a CSIO (operation modes 2) and as SCL4
when it is used in an I2C (operation mode 4).
89
B6
104
67
67
E10
77
45
84
A7
99
62
90
69
86
91
68
85
96
93
15
C6
E9
C7
A5
F8
B7
C4
D6
F3
105
79
101
106
78
100
116
113
20
68
47
64
69
46
63
74
93
93
Multi-function serial interface ch.5 output pin.
This pin operates as SOT5 when it is used in
a UART/CSIO/LIN (operation modes 0 to 3)
and as SDA5 when it is used in an I2C
(operation mode 4).
95
B4
115
73
-
-
112
-
16
G1
21
94
Multi-function serial interface ch.5 clock I/O
pin.
This pin operates as SCK5 when it is used in
a CSIO (operation modes 2) and as SCL5
when it is used in an I2C (operation mode 4).
94
C5
114
72
-
-
111
-
17
G2
22
95
Multi-function serial interface ch.4 RTS output
pin
Multi-function serial interface ch.4 CTS input
pin
Multi-function serial interface ch.5 input pin
Document Number: 002-05622 Rev. *D
Page 37 of 117
MB9B110R Series
Module
Pin name
Multifunction
Serial
6
SIN6_0
SIN6_1
SOT6_0
(SDA6_0)
SOT6_1
(SDA6_1)
SCK6_0
(SCL6_0)
SCK6_1
(SCL6_1)
Multifunction
Serial
7
SIN7_0
SIN7_1
SOT7_0
(SDA7_0)
SOT7_1
(SDA7_1)
SCK7_0
(SCL7_0)
SCK7_1
(SCL7_1)
Function
Multi-function serial interface ch.6 input pin
Multi-function serial interface ch.6 output pin.
This pin operates as SOT6 when it is used in
a UART/CSIO/LIN (operation modes 0 to 3)
and as SDA6 when it is used in an I2C
(operation mode 4).
Multi-function serial interface ch.6 clock I/O
pin.
This pin operates as SCK6 when it is used in
a CSIO (operation modes 2) and as SCL6
when it is used in an I2C (operation mode 4).
Multi-function serial interface ch.7 input pin
Multi-function serial interface ch.7 output pin.
This pin operates as SOT7 when it is used in
a UART/CSIO/LIN (operation modes 0 to 3)
and as SDA7 when it is used in an I2C
(operation mode 4).
Multi-function serial interface ch.7 clock I/O
pin.
This pin operates as SCK7 when it is used in
a CSIO (operation modes 2) and as SCL7
when it is used in an I2C (operation mode 4).
Document Number: 002-05622 Rev. *D
LQFP100
5
12
Pin No
FBGA- LQFP112
120
D1
5
E4
17
QFP100
83
90
6
D2
6
84
11
E3
16
89
7
D3
7
85
10
E2
15
88
45
K8
11
50
23
-
-
12
-
44
J7
49
22
-
-
13
-
43
H6
48
21
Page 38 of 117
MB9B110R Series
Module
Pin name
Multifunction
Timer
0
DTTI0X_0
DTTI0X_1
FRCK0_0
FRCK0_1
FRCK0_2
IC00_0
IC00_1
IC00_2
IC01_0
IC01_1
IC01_2
IC02_0
IC02_1
IC02_2
IC03_0
IC03_1
IC03_2
RTO00_0
(PPG00_0)
RTO00_1
(PPG00_1)
RTO01_0
(PPG00_0)
RTO01_1
(PPG00_1)
RTO02_0
(PPG02_0)
RTO02_1
(PPG02_1)
RTO03_0
(PPG02_0)
RTO03_1
(PPG02_1)
RTO04_0
(PPG04_0)
RTO04_1
(PPG04_1)
RTO05_0
(PPG04_0)
RTO05_1
(PPG04_1)
Function
Input signal controlling wave form generator
outputs RTO00 to RTO05 of Multi-function
timer 0.
LQFP100
18
Pin No
FBGA- LQFP112
120
F4
23
QFP100
96
69
E9
79
47
13
70
53
17
65
54
16
66
55
15
67
56
14
68
57
F1
D11
J10
G2
F9
J8
G1
E11
H10
F3
E10
H9
F2
F8
H7
18
80
63
22
75
64
21
76
65
20
77
66
19
78
67
91
48
31
95
43
32
94
44
33
93
45
34
92
46
35
Wave form generator output pin of
Multi-function timer 0.
This pin operates as PPG00 when it is used in
PPG0 output modes.
19
G3
24
97
-
-
86
-
Wave form generator output pin of
Multi-function timer 0.
This pin operates as PPG00 when it is used in
PPG0 output modes.
20
H1
25
98
-
-
85
-
Wave form generator output pin of
Multi-function timer 0.
This pin operates as PPG02 when it is used in
PPG0 output modes.
21
H2
26
99
-
-
84
-
Wave form generator output pin of
Multi-function timer 0.
This pin operates as PPG02 when it is used in
PPG0 output modes.
22
G4
27
100
-
-
83
-
Wave form generator output pin of
Multi-function timer 0.
This pin operates as PPG04 when it is used in
PPG0 output modes.
23
H3
28
1
-
-
82
-
Wave form generator output pin of
Multi-function timer 0.
This pin operates as PPG04 when it is used in
PPG0 output modes.
24
J2
29
2
-
-
81
-
16-bit free-run timer ch.0 external clock input
pin
16-bit input capture ch.0 input pin of
Multi-function timer 0.
ICxx describes channel number.
Document Number: 002-05622 Rev. *D
Page 39 of 117
MB9B110R Series
Module
Pin name
Multifunction
Timer
1
DTTI1X_0
DTTI1X_1
FRCK1_0
FRCK1_1
IC10_0
IC10_1
IC11_0
IC11_1
IC12_0
IC12_1
IC13_0
IC13_1
RTO10_0
(PPG10_0)
RTO10_1
(PPG10_1)
RTO11_0
(PPG10_0)
RTO11_1
(PPG10_1)
RTO12_0
(PPG12_0)
RTO12_1
(PPG12_1)
RTO13_0
(PPG12_0)
RTO13_1
(PPG12_1)
RTO14_0
(PPG14_0)
Function
Input signal controlling wave form generator
outputs RTO10 to RTO15 of Multi-function
timer 1.
16-bit free-run timer ch.1 external clock input
pin
16-bit input capture ch.1 input pin of
Multi-function timer 1.
ICxx describes channel number.
Wave form generator output pin of
Multi-function timer 1.
This pin operates as PPG10 when it is used in
PPG1 output modes.
Wave form generator output pin of
Multi-function timer 1.
This pin operates as PPG10 when it is used in
PPG1 output modes.
Wave form generator output pin of
Multi-function timer 1.
This pin operates as PPG12 when it is used in
PPG1 output modes.
Wave form generator output pin of
Multi-function timer 1.
This pin operates as PPG12 when it is used in
PPG1 output modes.
RTO14_1
(PPG14_1)
Wave form generator output pin of
Multi-function timer 1.
This pin operates as PPG14 when it is used in
PPG1 output modes.
RTO15_0
(PPG14_0)
RTO15_1
(PPG14_1)
Wave form generator output pin of
Multi-function timer 1.
This pin operates as PPG14 when it is used in
PPG1 output modes.
Document Number: 002-05622 Rev. *D
LQFP100
8
Pin No
FBGA- LQFP112
120
D5
8
QFP100
86
39
K6
44
17
87
44
88
40
89
41
90
42
91
43
D7
J7
A6
J6
B6
L7
C6
K7
A5
H6
102
49
103
45
104
46
105
47
106
48
65
22
66
18
67
19
68
20
69
21
2
C1
2
80
27
J4
32
5
3
C2
3
81
28
L5
33
6
4
B3
4
82
29
K5
34
7
5
D1
5
83
30
J5
35
8
6
D2
6
84
31
H5
36
9
7
D3
7
85
32
L6
37
10
Page 40 of 117
MB9B110R Series
Module
Pin name
Multifunction
Timer
2
DTTI2X_0
DTTI2X_1
FRCK2_0
FRCK2_1
IC20_0
IC20_1
IC21_0
IC21_1
IC22_0
IC22_1
IC23_0
IC23_1
RTO20_0
(PPG20_0)
RTO20_1
(PPG20_1)
RTO21_0
(PPG20_0)
RTO21_1
(PPG20_1)
RTO22_0
(PPG22_0)
RTO22_1
(PPG22_1)
RTO23_0
(PPG22_0)
RTO23_1
(PPG22_1)
RTO24_0
(PPG24_0)
Function
Input signal controlling wave form generator
outputs RTO20 to RTO25 of Multi-function
timer 2.
16-bit free-run timer ch.2 external clock input
pin
16-bit input capture ch.2 input pin of
Multi-function timer 2.
ICxx describes channel number.
Wave form generator output pin of
Multi-function timer 2.
This pin operates as PPG20 when it is used in
PPG2 output modes.
Wave form generator output pin of
Multi-function timer 2.
This pin operates as PPG20 when it is used in
PPG2 output modes.
Wave form generator output pin of
Multi-function timer 2.
This pin operates as PPG22 when it is used in
PPG2 output modes.
Wave form generator output pin of
Multi-function timer 2.
This pin operates as PPG22 when it is used in
PPG2 output modes.
RTO24_1
(PPG24_1)
Wave form generator output pin of
Multi-function timer 2.
This pin operates as PPG24 when it is used in
PPG2 output modes.
RTO25_0
(PPG24_0)
RTO25_1
(PPG24_1)
Wave form generator output pin of
Multi-function timer 2.
This pin operates as PPG24 when it is used in
PPG2 output modes.
Document Number: 002-05622 Rev. *D
LQFP100
92
Pin No
FBGA- LQFP112
120
B5
107
QFP100
70
92
B5
107
70
87
88
89
90
91
-
D7
A6
B6
C6
A5
-
102
112
103
108
104
109
105
110
106
111
65
66
67
68
69
-
-
-
113
-
86
C7
101
64
-
-
112
-
87
D7
102
65
-
-
111
-
88
A6
103
66
-
-
110
-
89
B6
104
67
-
-
109
-
90
C6
105
68
-
-
108
-
91
A5
106
69
Page 41 of 117
MB9B110R Series
Module
Pin name
Quadrature
Position/
Revolution
Counter
0
AIN0_0
AIN0_1
AIN0_2
BIN0_0
BIN0_1
BIN0_2
ZIN0_0
ZIN0_1
ZIN0_2
AIN1_1
AIN1_2
BIN1_1
BIN1_2
ZIN1_1
ZIN1_2
AIN2_0
AIN2_1
BIN2_0
BIN2_1
ZIN2_0
ZIN2_1
Quadrature
Position/
Revolution
Counter
1
Quadrature
Position/
Revolution
Counter
2
Real-time
clock
RTCCO_0
RTCCO_1
RTCCO_2
SUBOUT_0
SUBOUT_1
SUBOUT_2
Function
QPRC ch.0 AIN input pin
QPRC ch.0 BIN input pin
QPRC ch.0 ZIN input pin
QPRC ch.1 AIN input pin
QPRC ch.1 BIN input pin
QPRC ch.1 ZIN input pin
QPRC ch.2 AIN input pin
QPRC ch.2 BIN input pin
QPRC ch.2 ZIN input pin
0.5 seconds pulse output pin of Real-time
clock
Sub clock output pin
Document Number: 002-05622 Rev. *D
LQFP100
9
40
2
10
41
3
11
42
4
74
43
73
44
72
45
83
84
85
Pin No
FBGA- LQFP112
120
E1
14
J6
45
C1
2
E2
15
L7
46
C2
3
E3
16
K7
47
B3
4
C10
89
H6
48
C11
88
J7
49
E8
87
K8
50
10
D9
98
11
A7
99
12
B7
100
QFP100
87
18
80
88
19
81
89
20
82
52
21
51
22
50
23
61
62
63
92
B5
107
70
55
19
92
55
19
H10
G3
B5
H10
G3
65
24
107
65
24
33
97
70
33
97
Page 42 of 117
MB9B110R Series
Module
Reset
Pin name
Analog
Power
QFP100
VCC
Power supply Pin
76
A10
91
54
Power supply Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
Main clock (oscillation) input pin
Sub clock (oscillation) input pin
Main clock (oscillation) I/O pin
Sub clock (oscillation) I/O pin
97
25
34
50
75
100
48
36
49
37
74
92
60
A4
B2
L1
K2
J3
H4
L4
L11
K10
J9
H8
B10
C9
A11
D8
D4
C3
A1
L9
L3
L10
K3
C10
B5
H11
117
30
39
60
90
120
58
41
59
42
89
107
70
75
61
F11
71
39
MD1
Clock
Pin No
FBGA- LQFP112
120
VCC
VCC
VCC
VCC
MD0
GND
LQFP100
External Reset Input pin.
A reset is valid when INITX="L".
Mode 0 pin.
During normal operation, MD0="L" must be
input. During serial programming to Flash
memory, MD0="H" must be input.
Mode 1 pin.
During serial programming to Flash memory,
MD1="L" must be input.
Power supply Pin
Power supply Pin
Power supply Pin
Power supply Pin
INITX
Mode
Power
Function
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
X0
X0A
X1
X1A
CROUT_0
CROUT_1
AVCC
AVRH
Built-in high-speed CR-osc clock output port
A/D converter analog power pin
A/D converter analog reference voltage input
pin
38
K4
43
16
47
L8
57
25
46
K9
56
24
1
26
35
51
B1
J1
K1
K11
1
31
40
61
79
4
13
29
3
12
28
53
78
26
14
27
15
52
70
38
Analog
A/D converter GND pin
AVSS
62
G11
72
40
GND
Power stabilization capacity pin
C pin
C
33
L2
38
11
Note:
− While this device contains a Test Access Port (TAP) based on the IEEE 1149.1-2001 JTAG standard, it is not fully compliant to all
requirements of that standard. This device may contain a 32-bit device ID that is the same as the 32-bit device ID in other
devices with different functionality. The TAP pins may also be configurable for purposes other than access to the TAP controller.
Document Number: 002-05622 Rev. *D
Page 43 of 117
MB9B110R Series
5. I/O Circuit Type
Type
A
Circuit
Remarks
It is possible to select the main
oscillation / GPIO function
Pull-up
resistor
P-ch
When the main oscillation is
selected.
P-ch
Digital output
−
Oscillation feedback resistor:
−
With Standby mode control
X1
Approximately 1 MΩ
N-ch
Digital output
R
Pull-up resistor control
When the GPIO is selected.
−
CMOS level output.
−
CMOS level hysteresis input
−
With pull-up resistor control
−
With standby mode control
−
Pull-up resistor:
−
IOH = -4 mA, IOL = 4 mA
−
CMOS level hysteresis input
−
Pull-up resistor:
Approximately 50 kΩ
Digital input
Standby mode Control
Clock input
Feedback
resistor
Standby mode Control
Digital input
Standby mode Control
Pull-up
resistor
R
P-ch
P-ch
Digital output
N-ch
Digital output
X0
Pull-up resistor control
B
Approximately 50 kΩ
Pull-up resistor
Digital input
Document Number: 002-05622 Rev. *D
Page 44 of 117
MB9B110R Series
Type
C
Circuit
Remarks
Digital input
−
Open drain output
−
CMOS level hysteresis input
Digital output
N-ch
It is possible to select the sub
oscillation / GPIO function
D
Pull-up
When the sub oscillation is
selected.
resistor
−
P-ch
P-ch
Digital output
X1A
Oscillation feedback resistor:
Approximately 5 MΩ
−
With Standby mode control
When the GPIO is selected.
N-ch
−
CMOS level output.
−
CMOS level hysteresis input
−
With pull-up resistor control
−
With standby mode control
Pull-up resistor control
−
Pull-up resistor:
Digital input
−
IOH = -4 mA, IOL= 4 mA
Digital output
R
Approximately 50 kΩ
Standby mode Control
Clock input
Feedback
resistor
Standby mode Control
Digital input
Standby mode Control
Pull-up
resistor
R
P-ch
P-ch
Digital output
N-ch
Digital output
X0A
Pull-up resistor control
Document Number: 002-05622 Rev. *D
Page 45 of 117
MB9B110R Series
Type
E
Circuit
P-ch
Remarks
P-ch
−
CMOS level output
−
CMOS level hysteresis input
−
With pull-up resistor control
−
With standby mode control
−
Pull-up resistor:
−
IOH = -4 mA, IOL = 4 mA
−
When this pin is used as an I2C
Digital output
Approximately 50 kΩ
pin, the digital output P-ch
N-ch
transistor is always off
Digital output
R
−
+B input is available
−
CMOS level output
−
CMOS level hysteresis input
−
With input control
−
Analog input
−
With pull-up resistor control
−
With standby mode control
−
Pull-up resistor:
−
IOH = -4 mA, IOL = 4 mA
−
When this pin is used as an I2C
Pull-up resistor control
Digital input
Standby mode Control
F
P-ch
P-ch
Digital output
Approximately 50 kΩ
N-ch
Digital output
pin, the digital output P-ch
transistor is always off
−
R
+B input is available
Pull-up resistor control
Digital input
Standby mode Control
Analog input
Input control
Document Number: 002-05622 Rev. *D
Page 46 of 117
MB9B110R Series
Type
G
Circuit
P-ch
Remarks
P-ch
N-ch
−
CMOS level output
−
CMOS level hysteresis input
−
With pull-up resistor control
−
With standby mode control
−
Pull-up resistor:
−
IOH= -12 mA, IOL= 12 mA
−
+B input is available
−
CMOS level output
−
CMOS level hysteresis input
−
With standby mode control
−
IOH= -20.5 mA,
Digital output
Approximately 50 kΩ
Digital output
R
Pull-up resistor control
Digital input
Standby mode Control
H
IOL= 18.5 mA
P-ch
N-ch
Digital output
Digital output
R
Digital input
Standby mode Control
Document Number: 002-05622 Rev. *D
Page 47 of 117
MB9B110R Series
Type
I
Circuit
P-ch
Remarks
P-ch
Digital output
−
CMOS level output
−
CMOS level hysteresis input
−
With pull-up resistor control
−
5 V tolerant
−
With standby mode control
−
IOH = -4 mA, IOL = 4 mA
−
Available to control of PZR
registers.
−
N-ch
Digital output
When this pin is used as an I2C
pin, the digital output
P-ch transistor is always off
R
Pull-up resistor control
Digital input
Standby mode Control
CMOS level hysteresis input
J
Mode input
Document Number: 002-05622 Rev. *D
Page 48 of 117
MB9B110R Series
6. Handling Precautions
Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected by the conditions in
which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions that must be observed to
minimize the chance of failure and to obtain higher reliability from your Cypress semiconductor devices.
6.1
Precautions for Product Design
This section describes precautions when designing electronic equipment using semiconductor devices.
Absolute Maximum Ratings
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of
certain established limits, called absolute maximum ratings. Do not exceed these ratings.
Recommended Operating Conditions
Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical
characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely
affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users
considering application outside the listed conditions are advised to contact their sales representative beforehand.
Processing and Protection of Pins
These precautions must be followed when handling the pins which connect semiconductor devices to power supply and
input/output functions.
1. Preventing Over-Voltage and Over-Current Conditions
Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the
device, and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or over-current
conditions at the design stage.
2. Protection of Output Pins
Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows.
Such conditions if present for extended periods of time can damage the device.
Therefore, avoid this type of connection.
3. Handling of Unused Input Pins
Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such pins should be
connected through an appropriate resistance to a power supply pin or ground pin.
Latch-up
Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When subjected to
abnormally high voltages, internal parasitic PNPN junctions (called thyristor structures) may be formed, causing large current
levels in excess of several hundred mA to flow continuously at the power supply pin. This condition is called latch-up.
CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause injury or
damage from high heat, smoke or flame. To prevent this from happening, do the following:
1. Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include attention to abnormal
noise, surge levels, etc.
2. Be sure that abnormal current flows do not occur during the power-on sequence.
Observance of Safety Regulations and Standards
Most countries in the world have established standards and regulations regarding safety, protection from electromagnetic
interference, etc. Customers are requested to observe applicable regulations and standards in the design of products.
Document Number: 002-05622 Rev. *D
Page 49 of 117
MB9B110R Series
Fail-Safe Design
Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such
failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating conditions.
Precautions Related to Usage of Devices
Cypress semiconductor devices are intended for use in standard applications (computers, office automation and other office
equipment, industrial, communications, and measurement equipment, personal or household devices, etc.).
CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such
as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support,
etc.) are requested to consult with sales representatives before such use. The company will not be responsible for damages
arising from such use without prior approval.
6.2
Precautions for Package Mounting
Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during soldering,
you should only mount under Cypress' recommended conditions. For detailed information about mount conditions, contact your
sales representative.
Lead Insertion Type
Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board,
or mounting by using a socket.
Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and using the flow
soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually causes leads to be
subjected to thermal stress in excess of the absolute ratings for storage temperature. Mounting processes should conform to
Cypress recommended mounting conditions.
If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to contact
deterioration after long periods. For this reason it is recommended that the surface treatment of socket contacts and IC leads be
verified before mounting.
Surface Mount Type
Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily
deformed or bent. The use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open
connections caused by deformed pins, or shorting due to solder bridges.
You must use appropriate mounting techniques. Cypress recommends the solder reflow method, and has established a ranking of
mounting conditions for each product. Users are advised to mount packages in accordance with Cypress ranking of
recommended conditions.
Lead-Free Packaging
CAUTION: When ball grid array (FBGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction
strength may be reduced under some conditions of use.
Document Number: 002-05622 Rev. *D
Page 50 of 117
MB9B110R Series
Storage of Semiconductor Devices
Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption
of moisture. During mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel,
reducing moisture resistance and causing packages to crack. To prevent, do the following:
1. Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. Store products in
locations where temperature changes are slight.
2. Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures between 5°C
and 30°C.
When you open Dry Package that recommends humidity 40% to 70% relative humidity.
3. When necessary, Cypress packages semiconductor devices in highly moisture-resistant aluminum laminate bags, with a silica
gel desiccant. Devices should be sealed in their aluminum laminate bags for storage.
4. Avoid storing packages where they are exposed to corrosive gases or high levels of dust.
Baking
Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Cypress recommended
conditions for baking.
Condition: 125°C/24 h
Static Electricity
Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following
precautions:
1. Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus for ion generation may be
needed to remove electricity.
2. Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment.
3. Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of 1
MΩ).
Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is
recommended.
4. Ground all fixtures and instruments, or protect with anti-static measures.
5. Avoid the use of styrofoam or other highly static-prone materials for storage of completed board assemblies.
Document Number: 002-05622 Rev. *D
Page 51 of 117
MB9B110R Series
6.3
Precautions for Use Environment
Reliability of semiconductor devices depends on ambient temperature and other conditions as described above.
For reliable performance, do the following:
1. Humidity
Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels are
anticipated, consider anti-humidity processing.
2. Discharge of Static Electricity
When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In such cases,
use anti-static measures or processing to prevent discharges.
3. Corrosive Gases, Dust, or Oil
Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. If
you use devices in such conditions, consider ways to prevent such exposure or to protect the devices.
4. Radiation, Including Cosmic Radiation
Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should provide
shielding as appropriate.
5. Smoke, Flame
CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible substances. If devices
begin to smoke or burn, there is danger of the release of toxic gases.
Customers considering the use of Cypress products in other special environmental conditions should consult with sales
representatives.
Document Number: 002-05622 Rev. *D
Page 52 of 117
MB9B110R Series
7. Handling Devices
Power supply pins
In products with multiple VCC and VSS pins, respective pins at the same potential are interconnected within the device in order to
prevent malfunctions such as latch-up. However, all of these pins should be connected externally to the power supply or ground
lines in order to reduce electromagnetic emission levels, to prevent abnormal operation of strobe signals caused by the rise in the
ground level, and to conform to the total output current rating.
Moreover, connect the current supply source with each POWER pins and GND pins of this device at low impedance. It is also
advisable that a ceramic capacitor of approximately 0.1 µF be connected as a bypass capacitor between each Power supply pin
and GND pin, between AVCC pin and AVSS pin near this device.
Stabilizing power supply voltage
A malfunction may occur when the power supply voltage fluctuates rapidly even though the fluctuation is within the recommended
operating conditions of the VCC power supply voltage. As a rule, with voltage stabilization, suppress the voltage fluctuation so that
the fluctuation in VCC ripple (peak-to-peak value) at the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the VCC
value in the recommended operating conditions, and the transient fluctuation rate does not exceed 0.1 V/μs when there is a
momentary fluctuation on switching the power supply.
Crystal oscillator circuit
Noise near the X0/X1 and X0A/X1A pins may cause the device to malfunction. Design the printed circuit board so that X0/X1,
X0A/X1A pins, the crystal oscillator (or ceramic oscillator), and the bypass capacitor to ground are located as close to the device
as possible.
It is strongly recommended that the PC board artwork be designed such that the X0/X1 and X0A/X1A pins are surrounded by
ground plane as this is expected to produce stable operation.
Evaluate oscillation of your using crystal oscillator by your mount board.
Using an external clock
When using an external clock, the clock signal should be input to the X0, X0A pin only and the X1, X1A pin should be kept open.
Example of Using an External Clock
Device
X0(X0A)
Open
X1(X1A)
Handling when using Multi function serial pin as I2C pin
If it is using multi function serial pin as I2C pins, P-ch transistor of digital output is always disable. However, I 2C pins need to keep
the electrical characteristic like other pins and not to connect to external I 2C bus system with power OFF.
Document Number: 002-05622 Rev. *D
Page 53 of 117
MB9B110R Series
C Pin
This series contains the regulator. Be sure to connect a smoothing capacitor (CS) for the regulator between the C pin and the
GND pin. Please use a ceramic capacitor or a capacitor of equivalent frequency characteristics as a smoothing capacitor.
However, some laminated ceramic capacitors have the characteristics of capacitance variation due to thermal fluctuation (F
characteristics and Y5V characteristics). Please select the capacitor that meets the specifications in the operating conditions to
use by evaluating the temperature characteristics of a capacitor.
A smoothing capacitor of about 4.7 μF would be recommended for this series.
C
Device
CS
VSS
GND
Mode pins (MD0)
Connect the MD pin (MD0) directly to VCC or VSS pins. Design the printed circuit board such that the pull-up/down resistance
stays low, as well as the distance between the mode pins and VCC pins or VSS pins is as short as possible and the connection
impedance is low, when the pins are pulled-up/down such as for switching the pin level and rewriting the Flash memory data. It is
because of preventing the device erroneously switching to test mode due to noise.
Notes on power-on
Turn power on/off in the following order or at the same time.
If not using the A/D converter, connect AVCC = VCC and AVSS = VSS.
Turning on:
Turning off:
VCC → AVCC → AVRH
AVRH → AVCC → VCC
Serial Communication
There is a possibility to receive wrong data due to the noise or other causes on the serial communication.
Therefore, design a printed circuit board so as to avoid noise.
Consider the case of receiving wrong data due to noise, perform error detection such as by applying a checksum of data at the
end. If an error is detected, retransmit the data.
Differences in features among the products with different memory sizes and between Flash products and
MASK products
The electric characteristics including power consumption, ESD, latch-up, noise characteristics, and oscillation characteristics
among the products with different memory sizes and between Flash products and MASK products are different because chip
layout and memory structures are different.
If you are switching to use a different product of the same series, please make sure to evaluate the electric characteristics.
Pull-Up function of 5 V tolerant I/O
Please do not input the signal more than VCC voltage at the time of Pull-Up function use of 5 V tolerant I/O.
Document Number: 002-05622 Rev. *D
Page 54 of 117
MB9B110R Series
8. Block Diagram
MB9BF112N/R, MB9BF114N/R, MB9BF115N/R, MB9BF116N/R
TRACED[3:0],
TRACECLK
SWJ-DP
ETM
TPIU
ROM
Table
SRAM0
8/16/24/32Kbyte
Cortex-M3 Core
144MHz(Max)
I
Multi-layer AHB (Max 144MHz)
TRSTX,TCK,
TDI,TMS
TDO
D
MPU NVIC
Sys
AHB-APB Bridge:
APB0(Max 72MHz)
Dual-Timer
Watchdog Timer
(Software)
Clock Reset
Generator
INITX
Watchdog Timer
(Hardware)
SRAM1
8/16/24/32Kbyte
MainFlash I/F
Trace Buffer
(16Kbyte)
Security
WorkFlash I/F
MainFlash
128Kbyte/
256Kbyte/
384Kbyte/
512Kbyte
WorkFlash
32Kbyte
DMAC
8ch.
CSV
CLK
X0
X1
X0A
X1A
CROUT
AVCC,
AVSS, AVRH
Main
Osc
Sub
Osc
PLL
Source Clock
CR
4MHz
AHB-AHB
Bridge
CR
100kHz
12-bit A/D Converter × 3
MAD[24:00]
MADATA[15:00]
Unit 0
External Bus I/F
AN[15:00]
MRDY
Unit 1
ADTG[8:0]
Unit 2
AIN[2:0]
BIN[2:0]
QPRC
3ch.
ZIN[2:0]
A/D Activation
Compare
3ch.
IC0[3:0]
IC1[3:0]
IC2[3:0]
16-bit Input Capture
4ch.
FRCK[2:0]
16-bit Free-run Timer
3ch.
Power On
Reset
AHB-APB Bridge : APB2 (Max 72MHz)
TIOB[7:0]
Base Timer
16-bit 8ch./
32-bit 4ch.
AHB-APB Bridge : APB1 (Max 72MHz)
TIOA[7:0]
16-bit Output
Compare
6ch.
DTTI[2:0]X
RTO0[5:0]
RTO1[5:0]
RTO2[5:0]
LVD Ctrl
IRQ-Monitor
Multi-function Timer x 3
LVD
Regulator
C
CRC
Accelerator
RTCCO
SUBOUT
Real-Time Clock
Watch Counter
External Interrupt
Controller
16-pin + NMI
INT[15:00]
NMIX
MODE-Ctrl
GPIO
Waveform Generator
3ch.
16-bit PPG
3ch.
MCSX[7:0],
MALE,
MOEX,MWEX,
MNALE,
MNCLE,
MNWEX,
MNREX,
MDQM[1:0]
MD[1:0]
P0[F:0],
P1[F:0],
PIN-Function-Ctrl
.
.
.
Px[x:0]
Multi-function Serial I/F
8ch.
(with FIFO ch.4-ch.7)
HW flow control(ch.4)
SCK[7:0]
SIN[7:0]
SOT[7:0]
CTS4
RTS4
9. Memory Size
See 1. Product Lineup of "Memory size" to confirm the memory size.
Document Number: 002-05622 Rev. *D
Page 55 of 117
MB9B110R Series
10. Memory Map
Memory Map (1)
Peripherals Area
0x41FF_FFFF
Reserved
0x4006_1000
0x4006_0000
0xFFFF_FFFF
Reserved
0x4004_0000
0xE010_0000
0xE000_0000
Cortex-M3 Private
Peripherals
Reserved
0x6000_0000
Reserved
0x4400_0000
0x4200_0000
0x4000_0000
32Mbyte
Bit band alias
Peripherals
0x4003_F000
EXT-bus I/F
Reserved
0x4003_B000
RTC
0x4003_A000
Watch Counter
0x4003_9000
CRC
0x4003_8000
MFS
Reserved
0x4003_5000
LVD Ctrl
0x4003_4000
Reserved
0x4003_3000
GPIO
0x4003_2000
Reserved
0x4003_1000
Int-Req. Read
0x4003_0000
EXTI
0x4002_F000
Reserved
CR Trim
0x4002_8000
0x4002_7000
Reserved
A/DC
0x4002_6000
QPRC
0x2200_0000
32Mbyte
Bit band alias
0x4002_5000
Base Timer
0x200E_1000
Reserved
0x4002_4000
PPG
0x2400_0000
0x200E_0000
WorkFlash I/F
0x4002_3000
0x200C_0000
WorkFlash
0x4002_2000
Reserved
MFT unit2
0x2008_0000
Reserved
0x4002_1000
MFT unit1
0x2000_0000
SRAM1
0x4002_0000
MFT unit0
0x1FFF_0000
SRAM0
0x0010_2000
0x0010_0000
0x4001_6000
Reserved
Reserved
0x4001_5000
Dual Timer
Security/CR Trim
0x4001_3000
Reserved
MainFlash
0x0000_0000
Document Number: 002-05622 Rev. *D
0x4003_6000
0x4002_E000
Reserved
See the next page
"Memory Map (2), (3)"
for the memory size
details.
Reserved
0x4003_C000
0x7000_0000
External Device
Area
DMAC
0x4001_2000
SW WDT
0x4001_1000
HW WDT
0x4001_0000
Clock/Reset
0x4000_1000
Reserved
0x4000_0000
MainFlash I/F
Page 56 of 117
MB9B110R Series
Memory Map (2)
MB9BF115N/R
MB9BF116N/R
0x200E_0000
0x200E_0000
0x200C_0000
SA0-3 (8KBx4)
Reserved
0x200C_8000
0x200C_0000
WorkFlash
32Kbyte
0x200C_8000
WorkFlash
32Kbyte
Reserved
SA0-3 (8KBx4)
Reserved
0x2000_8000
Reserved
0x2000_6000
SRAM1
32Kbyte
SRAM1
24Kbyte
0x2000_0000
0x2000_0000
SRAM0
24Kbyte
SRAM0
32Kbyte
0x1FFF_A000
0x1FFF_8000
Reserved
Reserved
0x0010_2000
0x0010_2000
0x0010_1000
CR trimming
0x0010_1000
CR trimming
0x0010_0000
Security
0x0010_0000
Security
Reserved
0x0008_0000
Reserved
0x0006_0000
SA10-15 (64KBx6)
MainFlash
512Kbyte
SA10-13 (64KBx4)
MainFlash
384Kbyte
SA8-9 (48KBx2)
SA8-9 (48KBx2)
0x0000_0000
SA4-7 (8KBx4)
0x0000_0000
SA4-7 (8KBx4)
See "MB9B510R/410R/310R/110R Series Flash programming Manual" for sector structure of Flash.
Document Number: 002-05622 Rev. *D
Page 57 of 117
MB9B110R Series
Memory Map (3)
MB9BF112N/R
MB9BF114N/R
0x200E_0000
0x200E_0000
Reserved
0x200C_8000
WorkFlash
32Kbyte
0x200C_8000
WorkFlash
32Kbyte
Reserved
SA0-3 (8KBx4)
SA0-3 (8KBx4)
0x200C_0000
0x200C_0000
Reserved
Reserved
0x2000_4000
0x2000_2000
0x2000_0000
0x1FFF_C000
SRAM1
16Kbyte
SRAM0
16Kbyte
0x2000_0000
SRAM1
8Kbyte
0x1FFF_E000
SRAM0
8Kbyte
Reserved
Reserved
0x0010_2000
0x0010_2000
0x0010_1000
0x0010_0000
CR trimming
0x0010_1000
CR trimming
Security
0x0010_0000
Security
Reserved
Reserved
0x0004_0000
SA10-11 (64KBx2)
SA4-7 (8KBx4)
SA8-9 (48KBx2)
0x0000_0000
SA4-7 (8KBx4)
MainFlash
128Kbyte
0x0000_0000
MainFlash
256Kbyte
SA8-9 (48KBx2)
0x0002_0000
See "MB9B510R/410R/310R/110R Series Flash programming Manual" for sector structure of Flash.
Document Number: 002-05622 Rev. *D
Page 58 of 117
MB9B110R Series
Peripheral Address Map
Start address
0x4000_0000
0x4000_1000
0x4001_0000
0x4001_1000
0x4001_2000
0x4001_3000
0x4001_5000
0x4001_6000
0x4002_0000
0x4002_1000
0x4002_2000
0x4002_4000
0x4002_5000
0x4002_6000
0x4002_7000
0x4002_8000
0x4002_E000
0x4002_F000
0x4003_0000
0x4003_1000
0x4003_2000
0x4003_3000
0x4003_4000
0x4003_5000
0x4003_6000
0x4003_7000
0x4003_8000
0x4003_9000
0x4003_A000
0x4003_B000
0x4003_C000
0x4003_F000
0x4004_0000
0x4006_0000
0x4006_1000
0x200E_0000
End address
0x4000_0FFF
0x4000_FFFF
0x4001_0FFF
0x4001_1FFF
0x4001_2FFF
0x4001_4FFF
0x4001_5FFF
0x4001_FFFF
0x4002_0FFF
0x4002_1FFF
0x4002_3FFF
0x4002_4FFF
0x4002_5FFF
0x4002_6FFF
0x4002_7FFF
0x4002_DFFF
0x4002_EFFF
0x4002_FFFF
0x4003_0FFF
0x4003_1FFF
0x4003_2FFF
0x4003_3FFF
0x4003_4FFF
0x4003_5FFF
0x4003_6FFF
0x4003_7FFF
0x4003_8FFF
0x4003_9FFF
0x4003_AFFF
0x4003_BFFF
0x4003_EFFF
0x4003_FFFF
0x4005_FFFF
0x4006_0FFF
0x41FF_FFFF
0x200E_FFFF
Document Number: 002-05622 Rev. *D
Bus
AHB
APB0
APB1
APB2
AHB
Peripherals
MainFlash I/F register
Reserved
Clock/Reset Control
Hardware Watchdog timer
Software Watchdog timer
Reserved
Dual-Timer
Reserved
Multi-function timer unit0
Multi-function timer unit1
Multi-function timer unit2
PPG
Base Timer
Quadrature Position/Revolution Counter
A/D Converter
Reserved
Internal CR trimming
Reserved
External Interrupt Controller
Interrupt Request Batch-Read Function
Reserved
GPIO
Reserved
Low-Voltage Detector
Reserved
Reserved
Multi-function serial Interface
CRC
Watch Counter
Real-time clock
Reserved
External Memory interface
Reserved
DMAC register
Reserved
WorkFlash I/F register
Page 59 of 117
MB9B110R Series
11. Pin Status in Each CPU State
The terms used for pin status have the following meanings.
INITX = 0
This is the period when the INITX pin is the "L" level.
INITX = 1
This is the period when the INITX pin is the "H" level.
SPL = 0
This is the status that standby pin level setting bit (SPL) in standby mode control register (STB_CTL) is set to "0".
SPL = 1
This is the status that standby pin level setting bit (SPL) in standby mode control register (STB_CTL) is set to "1".
Input enabled
Indicates that the input function can be used.
Internal input fixed at "0"
This is the status that the input function cannot be used. Internal input is fixed at "L".
Hi-Z
Indicates that the output drive transistor is disabled and the pin is put in the Hi-Z state.
Setting disabled
Indicates that the setting is disabled.
Maintain previous state
Maintains the state that was immediately prior to entering the current mode.
If a built-in peripheral function is operating, the output follows the peripheral function.
If the pin is being used as a port, that output is maintained.
Analog input is enabled
Indicates that the analog input is enabled.
Trace output
Indicates that the trace function can be used.
Document Number: 002-05622 Rev. *D
Page 60 of 117
MB9B110R Series
Pin status type
List of Pin Status
Function
group
Power-on
reset or
low-voltage
detection
state
Power supply
unstable
B
E
F
Power supply stable
Run mode
or sleep
mode
state
Timer mode or sleep mode
state
Power
supply
stable
INITX=1
Maintain
previous
state
Input
enabled
INITX=1
SPL=0
SPL=1
Maintain
Hi-Z/ Internal
previous
input fixed at
state
"0"
Input
Input
enabled
enabled
Power supply stable
INITX=0
Setting
disabled
INITX=1
Setting
disabled
Main crystal
oscillator input
pin
GPIO selected
Input enabled
Input
enabled
Input
enabled
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous
state
Maintain
previous
state
Hi-Z/
Internal input
fixed at "0"
Main crystal
oscillator output
pin
Hi-Z/
Internal input
fixed at "0"/
or Input enable
Hi-Z/
Internal input
fixed at "0"
Hi-Z/
Internal
input fixed
at "0"
Maintain
previous
state
INITX input pin
Pull-up/
Input
enabled
Input enabled
Pull-up/ Input
enabled
Pull-up/
Input
enabled
Input
enabled
Maintain
previous
state
Maintain
previous
state/ Hi-Z at
oscillation
stop*1/
Internal input
fixed at "0"
Pull-up/ Input
enabled
Maintain
previous
state/ Hi-Z at
oscillation
stop*1/
Internal input
fixed at "0"
Pull-up/ Input
enabled
Input
enabled
Maintain
previous
state
Maintain
previous
state
Input
enabled
Maintain
previous
state
Hi-Z/ Internal
input fixed at
"0"
Trace output
Maintain
previous
state
JTAG
selected
Hi-Z
GPIO
selected
Setting
disabled
Setting
disabled
Pull-up/
Input
enabled
Input
enabled
Pull-up/
Input
enabled
Setting
disabled
Trace selected
External
interrupt
enabled
selected
GPIO
selected, or
other than
above resource
selected
Setting
disabled
Setting
disabled
Setting
disabled
Hi-Z
Hi-Z/
Input
enabled
Hi-Z/
Input
enabled
C
D
Device
internal
reset state
Setting
disabled
GPIO selected
A
INITX input
state
Mode input pin
Document Number: 002-05622 Rev. *D
Input
enabled
Pull-up/ Input
enabled
Maintain
previous
state
Hi-Z/
Internal input
fixed at "0"
Page 61 of 117
Pin status type
MB9B110R Series
Function group
Power-on
reset or
low-voltage
detection
state
Power supply
unstable
Trace selected
G
H
I
J
GPIO selected,
or other than
above resource
selected
External
interrupt
enabled
selected
GPIO selected,
or other than
above resource
selected
GPIO selected,
resource
selected
NMIX selected
GPIO selected,
or other than
above resource
selected
Document Number: 002-05622 Rev. *D
INITX input
state
Device
internal
reset state
Power supply stable
Setting
disabled
Hi-Z
INITX=0
Setting
disabled
Hi-Z/
Input
enabled
INITX=1
Setting
disabled
Hi-Z/
Input
enabled
Setting
disabled
Setting
disabled
Setting
disabled
Hi-Z
Hi-Z/
Input
enabled
Hi-Z/
Input
enabled
Hi-Z
Hi-Z/
Input
enabled
Setting
disabled
Hi-Z/
Input
enabled
Setting
disabled
Hi-Z/
Input
enabled
Hi-Z/
Input
enabled
Setting
disabled
Hi-Z
Run mode
or sleep
mode
state
Power
supply
stable
INITX=1
Maintain
previous
state
Maintain
previous
state
Timer mode or sleep mode
state
Power supply stable
INITX=1
SPL=0
SPL=1
Maintain
Trace output
previous
state
Hi-Z/
Internal input
fixed at "0"
Maintain
previous
state
Maintain
previous
state
Hi-Z/
Internal input
fixed at "0"
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Hi-Z/ Internal
input fixed at
"0"
Maintain
previous
state
Hi-Z/
Internal input
fixed at "0"
Page 62 of 117
Pin status type
MB9B110R Series
Function
group
Power-on
reset or
low-voltage
detection
state
Power supply
unstable
INITX input
state
Device
internal
reset state
Power supply stable
Run mode
or sleep
mode
state
Power
supply
stable
INITX=1
Hi-Z/
Internal
input fixed
at "0"/
Analog
input
enabled
Maintain
previous
state
Timer mode or sleep
mode state
Power supply stable
Hi-Z
INITX=0
Hi-Z/
Internal input
fixed at "0"/
Analog input
enabled
GPIO selected,
or other than
above resource
selected
External
interrupt
enabled
selected
Analog input
selected
Setting
disabled
Setting
disabled
INITX=1
Hi-Z/
Internal
input fixed
at "0"/
Analog
input
enabled
Setting
disabled
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous
state
Hi-Z
Hi-Z/
Internal input
fixed at "0"/
Analog input
enabled
Setting
disabled
Setting
disabled
Hi-Z/
Internal
input fixed
at "0"/
Analog
input
enabled
Maintain
previous
state
Hi-Z/
Internal input
fixed at "0"/
Analog input
enabled
GPIO selected,
or other than
above resource
selected
GPIO selected
Hi-Z/
Internal
input fixed
at "0"/
Analog
input
enabled
Setting
disabled
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous
state
Maintain
previous
state
Sub crystal
oscillator input
pin
Input enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Analog input
selected
K
L
INITX=1
SPL=0
SPL=1
Hi-Z/
Hi-Z/
Internal input
Internal
fixed at "0"/
input fixed
Analog input
at "0"/
enabled
Analog
input
enabled
Maintain
Hi-Z/
previous
Internal
state
input fixed
at "0"
Maintain
Maintain
previous
previous
state
state
Maintain
previous
state
M
Document Number: 002-05622 Rev. *D
Hi-Z/
Internal
input fixed
at "0"/
Analog
input
enabled
Hi-Z/
Internal
input fixed
at "0"
Hi-Z/
Internal
input fixed
at "0"
Input
enabled
Page 63 of 117
Pin status type
MB9B110R Series
Function
group
Power-on
reset or
low-voltage
detection
state
Power supply
unstable
Device
internal
reset state
Power supply stable
Run mode
or sleep
mode
state
Power
supply
stable
INITX=1
Maintain
previous
state
Timer mode or sleep
mode state
Power supply stable
Setting
disabled
INITX=0
Setting
disabled
INITX=1
Setting
disabled
Sub crystal
oscillator
output pin
Hi-Z/
Internal input
fixed at "0"/
or Input enable
Hi-Z/
Internal input
fixed at "0"
Hi-Z/
Internal
input fixed
at "0"
Maintain
previous
state
GPIO selected
Hi-Z
Hi-Z/
Input
enabled
Hi-Z/
Input
enabled
Maintain
previous
state
Mode input pin
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
GPIO selected
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous
state
Maintain
previous
state
Hi-Z/
Input
enabled
GPIO selected
N
INITX input
state
O
P
INITX=1
SPL=0
SPL=1
Maintain
Hi-Z/
previous state
Internal
input fixed
at "0"
Maintain
Maintain
previous state/ previous
Hi-Z at
state/ Hi-Z
oscillation
at
stop*2/
oscillation
Internal input
stop*2/
fixed at "0"
Internal
input fixed
at "0"
Maintain
Hi-Z/
previous state
Internal
input fixed
at "0"
*1: Oscillation is stopped at Sub Timer mode, Low-speed CR Timer mode, and Stop mode.
*2: Oscillation is stopped at Stop mode.
Document Number: 002-05622 Rev. *D
Page 64 of 117
MB9B110R Series
12. Electrical Characteristics
12.1 Absolute Maximum Ratings
Parameter
voltage*1, *2
Power supply
Analog power supply voltage*1, *3
Analog reference voltage*1, *3
Input voltage*1
Symbol
VCC
AVCC
AVRH
VI
Min
VSS - 0.5
VSS - 0.5
VSS - 0.5
VSS - 0.5
VSS - 0.5
Analog pin input voltage*1
VIA
VSS - 0.5
Output voltage*1
VO
VSS - 0.5
ICLAMP
Σ[ICLAMP]
-2
IOL
-
IOLAV
-
∑IOL
∑IOLAV
-
IOH
-
IOHAV
-
Clamp maximum current
Clamp total maximum current
L level maximum output current*4
L level average output current*6
L level total maximum output current
L level total average output current*6
H level maximum output current*4
H level average output current*5
H level total maximum output current
∑IOH
H level total average output current*6
∑IOHAV
Power consumption
PD
Storage temperature
TSTG
- 55
*1: These parameters are based on the condition that VSS = AVSS = 0.0 V.
Rating
Max
VSS + 6.5
VSS + 6.5
VSS + 6.5
VCC + 0.5
(≤ 6.5 V)
VSS + 6.5
AVCC + 0.5
(≤ 6.5 V)
VCC + 0.5
(≤ 6.5 V)
+2
+20
10
20
39
4
12
18.5
100
50
- 10
- 20
- 39
-4
- 12
- 20.5
- 100
- 50
1000
+ 150
Unit
Remarks
V
V
V
V
V
5 V tolerant
V
V
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mW
°C
*7
*7
4 mA type
12 mA type
P80, P81
4 mA type
12 mA type
P80, P81
4 mA type
12 mA type
P80, P81
4 mA type
12 mA type
P80, P81
*2: VCC must not drop below VSS - 0.5 V.
*3: Ensure that the voltage does not exceed VCC + 0.5 V, for example, when the power is turned on.
*4: The maximum output current is the peak value for a single pin.
*5: The average output is the average current for a single pin over a period of 100 ms.
*6: The total average output current is the average current for all pins over a period of 100 ms.
*7:
•
•
•
•
•
•
•
•
See "4 List of Pin Functions" and "5 I/O Circuit Type" about +B input available pin.
Use within recommended operating conditions.
Use at DC voltage (current) the +B input.
The +B signal should always be applied a limiting resistance placed between the +B signal and the device.
The value of the limiting resistance should be set so that when the +B signal is applied the input current to the device pin
does not exceed rated values, either instantaneously or for prolonged periods.
Note that when the device drive current is low, such as in the low-power consumption modes, the +B input potential may
pass through the protective diode and increase the potential at the VCC and AVCC pin, and this may affect other devices.
Note that if a +B signal is input when the device power supply is off (not fixed at 0 V), the power supply is provided from the
pins, so that incomplete operation may result.
The following is a recommended circuit example (I/O equivalent circuit).
Document Number: 002-05622 Rev. *D
Page 65 of 117
MB9B110R Series
Protection Diode
VCC
VCC
Limiting
resistor
P-ch
Digital output
+B input (0V to 16V)
N-ch
Digital input
R
AVCC
Analog input
WARNING:
− Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of
absolute maximum ratings. Do not exceed these ratings.
Document Number: 002-05622 Rev. *D
Page 66 of 117
MB9B110R Series
12.2 Recommended Operating Conditions
(VSS = AVSS = 0.0V)
Parameter
Symbol
Conditions
VCC
Analog power supply voltage
Analog reference voltage
CS
Power supply voltage
Smoothing capacitor
Operating
temperature
LQI100
LQM120
Value
Unit
Min
Max
-
2.7*2
5.5
V
AVCC
-
2.7
5.5
V
AVRH
-
2.7
AVCC
V
When
mounted on
four-layer
PCB
1
10
μF
- 40
+ 85
°C
TA
PQH100
TA
- 40
+ 85
LBC112
*1: See "C Pin" in "7 Handling Devices" for the connection of the smoothing capacitor.
Remarks
AVCC = VCC
For built-in 1.2 V regulator*1
°C
*2: In between less than the minimum power supply voltage and low voltage reset/interrupt detection voltage or more, instruction
execution and low voltage detection function by built-in High-speed CR(including Main PLL is used) or built-in Low-speed CR
is possible to operate only.
WARNING:
− The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of
the device's electrical characteristics are warranted when the device is operated within these ranges.
− Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may
adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or
combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to
contact their representatives beforehand.
Document Number: 002-05622 Rev. *D
Page 67 of 117
MB9B110R Series
12.3 DC Characteristics
12.3.1 Current Rating
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
Pin
name
Conditions
PLL
Run mode
Run
mode
current
ICC
High-speed
CR
Run mode
VCC
Sub
Run mode
Low-speed
CR
Run mode
Sleep
mode
current
ICCS
PLL
Sleep mode
High-speed
CR
Sleep mode
Sub
Sleep mode
Low-speed
CR
Sleep mode
CPU: 144 MHz,
Peripheral: 72 MHz,
Main Flash 2 Wait
TraceBuffer: ON
FRWTR.RWT = 10
FSYNDN.SD = 000
FBFCR.BE = 1
CPU: 72 MHz,
Peripheral: 72 MHz,
Main Flash 0 Wait
TraceBuffer: OFF
FRWTR.RWT = 00
FSYNDN.SD = 000
FBFCR.BE = 0
CPU/ Peripheral: 4 MHz*2
Main Flash 0 Wait
FRWTR.RWT = 00
FSYNDN.SD = 000
CPU/ Peripheral: 32 kHz
Main Flash 0 Wait
FRWTR.RWT = 00
FSYNDN.SD = 000
CPU/ Peripheral: 100 kHz
Main Flash 0 Wait
FRWTR.RWT = 00
FSYNDN.SD = 000
Value
Unit
Remarks
Typ*3
Max*4
85
117
mA
*1, *5
52
70
mA
*1, *5
5
17
mA
*1
mA
*1, *6
1.3
14
1.3
14
mA
*1
Peripheral: 72 MHz
28
43
mA
*1, *5
Peripheral: 4 MHz*2
3
16
mA
*1
Peripheral: 32 kHz
1
14
mA
*1, *6
Peripheral: 100 kHz
1
14
mA
*1
*1: When all ports are fixed.
*2: When setting it to 4 MHz by trimming.
*3: TA=+25°C, VCC=5.5 V
*4: TA=+85°C, VCC=5.5 V
*5: When using the crystal oscillator of 4 MHz(Including the current consumption of the oscillation circuit)
*6: When using the crystal oscillator of 32 kHz(Including the current consumption of the oscillation circuit)
Document Number: 002-05622 Rev. *D
Page 68 of 117
MB9B110R Series
Parameter
Symbol
Timer
mode
current
Pin
name
Main
Timer mode
ICCT
VCC
Stop
mode
current
Conditions
ICCH
Sub
Timer mode
Stop mode
TA = + 25°C,
When LVD is off
TA = + 85°C,
When LVD is off
TA = + 25°C,
When LVD is off
TA = + 85°C,
When LVD is off
TA = + 25°C,
When LVD is off
TA = + 85°C,
When LVD is off
Value
Typ*2
Max*2
Unit
Remarks
3.2
6
mA
*1, *3
-
15
mA
*1, *3
0.9
3
mA
*1, *4
-
12
mA
*1, *4
0.8
3
mA
*1
-
12
mA
*1
*1: When all ports are fixed
*2: VCC = 5.5 V
*3: When using the crystal oscillator of 4 MHz(Including the current consumption of the oscillation circuit)
*4: When using the crystal oscillator of 32 kHz(Including the current consumption of the oscillation circuit)
Low-Voltage Detection Current
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Low voltage
detection circuit
(LVD) power
supply current
Symbol
Pin
name
Conditions
ICCLVD
VCC
At operation
for interrupt
VCC = 5.5 V
Value
Typ
Max
4
7
Unit
μA
Remarks
At not detect
Flash Memory Current
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Flash memory
write/erase
current
Symbol
ICCFLASH
Pin
name
Conditions
VCC
MainFlash
At Write/Erase
WorkFlash
At Write/Erase
Value
Typ
Max
Unit
11.4
13.1
mA
11.4
13.1
mA
Remarks
*
*: The current at which to write or erase Flash memory, ICCFLASH is added to ICC.
A/D Converter Current
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V, TA = - 40°C to + 85°C)
Parameter
Power supply
current
Reference power
supply current
Symbol
Pin
name
ICCAD
AVCC
ICCAVRH
Document Number: 002-05622 Rev. *D
AVRH
Value
Typ
Max
Unit
At 1unit operation
0.47
0.62
mA
At stop
0.06
25
μA
At 1unit operation
AVRH=5.5 V
1.1
1.96
mA
At stop
0.06
4
μA
Conditions
Remarks
Page 69 of 117
MB9B110R Series
12.3.2 Pin Characteristics
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
H level input
voltage
(hysteresis
input)
VIHS
L level input
voltage
(hysteresis
input)
VILS
Pin name
CMOS
hysteresis
input pin,
MD0, MD1
5 V tolerant
input pin
CMOS
hysteresis
input pin,
MD0, MD1
5 V tolerant
input pin
4 mA type
H level
output voltage
VOH
12 mA type
P80, P81
Document Number: 002-05622 Rev. *D
Conditions
Min
Value
Typ
Max
Unit
-
VCC × 0.8
-
VCC + 0.3
V
-
VCC × 0.8
-
VSS + 5.5
V
-
VSS - 0.3
-
VCC × 0.2
V
-
VSS - 0.3
-
VCC × 0.2
V
VCC - 0.5
-
VCC
V
VCC - 0.5
-
VCC
V
VCC - 0.4
-
VCC
V
VCC ≥ 4.5 V
IOH = - 4 mA
VCC < 4.5 V
IOH = - 2 mA
VCC ≥ 4.5 V
IOH = - 12 mA
VCC < 4.5 V
IOH = - 8 mA
VCC ≥ 4.5 V
IOH = - 20.5 mA
VCC < 4.5 V
IOH = - 13.0 mA
Remarks
Page 70 of 117
MB9B110R Series
Parameter
Symbol
Pin name
4 mA type
L level
output voltage
VOL
12 mA type
P80, P81
Input leak
current
Pull-up
resistance
value
Input
capacitance
IIL
-
RPU
Pull-up pin
CIN
Other than
VCC,
VSS,
AVCC,
AVSS,
AVRH
Document Number: 002-05622 Rev. *D
Conditions
Value
Unit
Min
Typ
Max
VSS
-
0.4
V
VSS
-
0.4
V
VSS
-
0.4
V
-
-5
-
+5
μA
VCC ≥ 4.5 V
25
50
100
VCC < 4.5 V
30
80
200
-
-
5
15
VCC ≥ 4.5 V
IOL = 4 mA
VCC < 4.5 V
IOL = 2 mA
VCC ≥ 4.5 V
IOL = 12 mA
VCC < 4.5 V
IOL = 8 mA
VCC ≥ 4.5 V
IOL = 18.5 mA
VCC < 4.5 V
IOL = 10.5 mA
Remarks
kΩ
pF
Page 71 of 117
MB9B110R Series
12.4 AC Characteristics
12.4.1 Main Clock Input Characteristics
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Input frequency
Input clock cycle
Input clock pulse
width
Input clock rise
time and fall time
Internal operating
clock*1 frequency
Internal operating
clock*1 cycle time
Symbol
Pin
name
fCH
X0
X1
Conditions
Value
Unit
Min
Max
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
PWH/tCYLH
PWL/tCYLH
4
4
4
4
20.83
50
48
20
48
20
250
250
45
55
%
-
-
5
ns
MHz
MHz
Remarks
When crystal oscillator is
connected
When using external
clock
tCF,
tCR
fCM
-
-
-
144
MHz
When using external
clock
When using external
clock
When using external
clock
Master clock
fCC
fCP0
fCP1
fCP2
-
-
-
144
72
72
72
MHz
MHz
MHz
MHz
Base clock (HCLK/FCLK)
APB0 bus clock*2
APB1 bus clock*2
APB2 bus clock*2
tCYCC
tCYCP0
tCYCP1
tCYCP2
-
-
6.94
13.8
13.8
13.8
-
ns
ns
ns
ns
Base clock (HCLK/FCLK)
APB0 bus clock*2
APB1 bus clock*2
APB2 bus clock*2
tCYLH
-
ns
*1: For more information about each internal operating clock, see "CHAPTER 2-1: Clock" in "FM3 Family PERIPHERAL
MANUAL".
*2: For about each APB bus which each peripheral is connected to, see "8. Block Diagram" in this data sheet.
X0
Document Number: 002-05622 Rev. *D
Page 72 of 117
MB9B110R Series
12.4.2 Sub Clock Input Characteristics
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
Input frequency
1/ tCYLL
Input clock cycle
Input clock pulse
width
tCYLL
Pin
name
X0A
X1A
-
Conditions
Value
Unit
Remarks
Min
Typ
Max
-
-
32.768
-
kHz
-
32
-
100
kHz
When crystal oscillator is
connected
When using external clock
PWH/tCYLL
PWL/tCYLL
10
-
31.25
μs
When using external clock
45
-
55
%
When using external clock
X0A
12.4.3 Internal CR Oscillation Characteristics
High-speed Internal CR
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Clock frequency
Frequency stability
time
Symbol
fCRH
Value
Conditions
Min
Typ
Max
TA = + 25°C
3.96
4
4.04
TA = 0°C to + 70°C
TA = - 40°C to + 85°C
3.84
3.8
4
4
4.16
4.2
TA = - 40°C to + 85°C
3
4
5
-
-
-
90
tCRWT
Unit
MHz
Remarks
When trimming*1
When not trimming
μs
*2
*1: In the case of using the values in CR trimming area of Flash memory at shipment for frequency trimming.
*2: Frequency stable time is time to stable of the frequency of the High-speed CR clock after the trim value is set.
After setting the trim value, the period when the frequency stability time passes can use the High-speed CR clock as a source
clock.
Low-speed Internal CR
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Clock frequency
Symbol
Conditions
fCRL
-
Document Number: 002-05622 Rev. *D
Value
Min
Typ
Max
50
100
150
Unit
Remarks
kHz
Page 73 of 117
MB9B110R Series
12.4.4 Operating Conditions of Main PLL (In the case of using main clock for input of PLL)
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
Value
Min
Typ
Max
PLL oscillation stabilization wait time*1
tLOCK
100
(LOCK UP time)
PLL input clock frequency
fPLLI
4
PLL multiple rate
13
PLL macro oscillation clock frequency
fPLLO
200
Main PLL clock frequency*2
fCLKPLL
*1: Time from when the PLL starts operating until the oscillation stabilizes.
Unit
-
μs
16
75
300
144
MHz
multiple
MHz
MHz
Remarks
*2: For more information about Main PLL clock (CLKPLL), see "CHAPTER 2-1: Clock" in "FM3 Family PERIPHERAL MANUAL".
12.4.5 Operating Conditions of Main PLL (In the case of using high-speed internal CR)
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
Value
Min
Typ
Max
PLL oscillation stabilization wait time*1
tLOCK
100
(LOCK UP time)
PLL input clock frequency
fPLLI
4
PLL multiple rate
13
PLL macro oscillation clock frequency
fPLLO
200
Main PLL clock frequency*2
fCLKPLL
*1: Time from when the PLL starts operating until the oscillation stabilizes.
Unit
-
μs
16
75
300
144
MHz
multiple
MHz
MHz
Remarks
*2: For more information about Main PLL clock (CLKPLL), see "CHAPTER 2-1: Clock" in "FM3 Family PERIPHERAL MANUAL".
Main PLL connection
Main clock (CLKMO)
High-speed CR clock (CLKHC)
K
divider
PLL input
clock
Main
PLL
PLL macro
oscillation clock M
divider
Main PLL
clock
(CLKPLL)
N
divider
Document Number: 002-05622 Rev. *D
Page 74 of 117
MB9B110R Series
12.4.6 Reset Input Characteristics
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
Pin
name
Conditions
tINITX
INITX
-
Reset input time
Value
Min
Max
500
-
Unit
Remarks
ns
12.4.7 Power-on Reset Timing
(VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
Power supply shut down time
tOFF
Pin name
Value
Conditions
-
Min
Typ
Max
50
-
-
Unit
Remarks
ms
*1
Power ramp rate
dV/dt
Vcc: 0.2 V to 2.70 V
0.8
1000
mV/μs *2
VCC
Time until releasing
tPRT
0.57
0.76
ms
Power-on reset
*1: VCC must be held below 0.2 V for minimum period of tOFF. Improper initialization may occur if this condition is not met.
*2: This dV/dt characteristic is applied at the power-on of cold start (tOFF>50 ms).
Note:
− If tOFF cannot be satisfied designs must assert external reset(INITX) at power-up and at any brownout event per “12. 4. 6.Reset
Input Characteristics”.
2.7V
VCC
VDH
0.2V
dV/dt
0.2V
tPRT
Internal RST
CPU Operation
RST Active
0.2V
tOFF
release
start
Glossary
VDH: detection voltage of Low Voltage detection reset. See “12.6.Low-voltage Detection Characteristics”
Document Number: 002-05622 Rev. *D
Page 75 of 117
MB9B110R Series
12.4.8 External Bus Timing
External bus clock output characteristics
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Output frequency
Symbol
Pin name
Conditions
tCYCLE
MCLKOUT*1
VCC ≥ 4.5 V
VCC < 4.5 V
Value
Min
Max
-
50*2
32*3
Unit
MHz
MHz
*1: External bus clock (MCLKOUT) is divided clock of HCLK.
For more information about setting of clock divider, see "CHPATER 12: External Bus Interface" in "FM3 Family PERIPHERAL
MANUAL".
When external bus clock is not output, this characteristic does not give any effect on external bus operation.
*2: When AHB bus clock frequency is more than 100 MHz, the divider setting for MCLKOUT must be more than 4.
*3: When AHB bus clock frequency is more than 64 MHz, the divider setting for MCLKOUT must be more than 4.
MCLKOUT
External bus signal input/output characteristics
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Signal input characteristics
Signal output characteristics
Symbol
Conditions
VIH
VIL
-
VOH
VOL
Input signal
VIH
VIL
VIH
VIL
Output signal
VOH
VOL
VOH
VOL
Document Number: 002-05622 Rev. *D
Value
Unit
0.8 × VCC
V
0.2 × VCC
V
0.8 × VCC
V
0.2 × VCC
V
Remarks
Page 76 of 117
MB9B110R Series
Separate Bus Access Asynchronous SRAM Mode
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
MOEX
Min pulse width
MCSX ↓ → Address
output delay time
MOEX ↑ →
Address hold time
MCSX ↓ →
MOEX ↓ delay time
MOEX ↑ →
MCSX ↑ time
MCSX ↓ →
MDQM ↓ delay time
Data set up →
MOEX ↑ time
MOEX ↑ →
Data hold time
MWEX
Min pulse width
MWEX ↑ → Address
output delay time
MCSX ↓ →
MWEX ↓ delay time
MWEX ↑ →
MCSX ↑ delay time
MCSX ↓→
MDQM ↓ delay time
MCSX ↓→
Data output time
MWEX ↑ →
Data hold time
Symbol
Pin name
tOEW
MOEX
tCSL – AV
tOEH - AX
tCSL - OEL
tOEH - CSH
tCSL - RDQML
tDS - OE
tDH - OE
MCSX[7:0]
MAD[24:0]
MOEX
MAD[24:0]
MOEX
MCSX[7:0]
MCSX
MDQM[1:0]
MOEX
MADATA[15:0]
MOEX
MADATA[15:0]
tWEW
MWEX
tWEH - AX
MWEX
MAD[24:0]
tCSL - WEL
tWEH - CSH
tCSL-WDQML
tCSL - DV
tWEH - DX
MWEX
MCSX[7:0]
MCSX
MDQM[1:0]
MCSX
MADATA[15:0]
MWEX
MADATA[15:0]
Conditions
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
Value
Min
Max
MCLK×n-3
-
-9
-12
+9
+12
MCLK×m+9
MCLK×m+12
MCLK×m+9
MCLK×m+12
MCLK×m+9
0
MCLK×m-9
MCLK×m-12
0
MCLK×m+12
Unit
ns
ns
ns
ns
ns
MCLK×m-9
MCLK×m-12
20
38
MCLK×m+9
MCLK×m+12
-
0
-
ns
MCLK×n-3
-
ns
0
MCLK×n-9
MCLK×n-12
0
MCLK×n-9
MCLK×n-12
MCLK-9
MCLK-12
0
MCLK×m+9
MCLK×m+12
MCLK×n+9
MCLK×n+12
MCLK×m+9
MCLK×m+12
MCLK×n+9
MCLK×n+12
MCLK+9
MCLK+12
MCLK×m+9
MCLK×m+12
ns
ns
ns
ns
ns
ns
ns
ns
Note:
− When the external load capacitance = 30 pF. (m = 0 to 15, n = 1 to 16)
Document Number: 002-05622 Rev. *D
Page 77 of 117
MB9B110R Series
tCYCLE
MCLK
tOEH-CSH
tWEH-CSH
MCSX[7:0]
tCSL-AV
MAD[24:0]
tOEH-AX
Address
tWEH-AX
tCSL-AV
Address
tCSL-OEL
MOEX
tOEW
tCSL-WDQML
tCSL-RDQML
MDQM[1:0]
MWEX
MADATA[15:0]
tCSL-WEL
tWEW
tDS-OE
tDH-OE
RD
tWEH-DX
WD
Invalid
tCSL-DV
Document Number: 002-05622 Rev. *D
Page 78 of 117
MB9B110R Series
Separate Bus Access Synchronous SRAM Mode
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Address delay time
Symbol
Pin name
Conditions
tAV
MCLK
MAD[24:0]
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
tCSL
MCLK
MCSX[7:0]
MCSX delay time
tCSH
tREL
MCLK
MOEX
MOEX delay time
tREH
Data set up →
MCLK ↑ time
MCLK ↑ →
Data hold time
MCLK
MADATA[15:0]
MCLK
MADATA[15:0]
tDS
tDH
tWEL
MCLK
MWEX
MWEX delay time
tWEH
MDQM[1:0]
delay time
MCLK ↑ →
Data output time
MCLK ↑ →
Data hold time
tDQML
MCLK
MDQM[1:0]
tDQMH
MCLK,
MADATA[15:0]
MCLK
MADATA[15:0]
tODS
tOD
Min
1
1
1
1
1
Value
Max
9
12
9
12
9
12
9
12
9
12
Unit
ns
ns
ns
ns
ns
19
37
-
ns
0
-
ns
1
1
1
1
MCLK+1
1
9
12
9
12
9
12
9
12
MCLK+18
MCLK+24
18
24
ns
ns
ns
ns
ns
ns
Note:
− When the external load capacitance = 30 pF.
tCYCLE
MCLK
tCSL
tCSH
MCSX[7:0]
tAV
MAD[24:0]
tAV
Address
Address
tREL
tREH
tDQML
tDQMH
MOEX
tDQML
tDQMH
tWEL
tWEH
MDQM[1:0]
MWEX
MADATA[15:0]
tDS
tDH
RD
tOD
WD
Invalid
tODS
Document Number: 002-05622 Rev. *D
Page 79 of 117
MB9B110R Series
Multiplexed Bus Access Asynchronous SRAM Mode
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
Multiplexed
address delay time
tALE-CHMADV
Multiplexed
address hold time
tCHMADH
Pin name
Conditions
MALE
MADATA[15:0]
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
Min
0
MCLK×n+0
MCLK×n+0
Value
Max
10
20
MCLK×n+10
MCLK×n+20
Unit
ns
ns
Note:
− When the external load capacitance = 30 pF. (m = 0 to 15, n = 1 to 16)
MCLK
MCSX[7:0]
MALE
MAD [24:0]
MOEX
MDQM [1:0]
MWEX
MADATA[15:0]
Document Number: 002-05622 Rev. *D
Page 80 of 117
MB9B110R Series
Multiplexed Bus Access Synchronous SRAM Mode
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
tCHAL
MALE delay time
tCHAH
MCLK ↑ →
Multiplexed
Address delay time
tCHMADV
MCLK ↑ →
Multiplexed
Data output time
tCHMADX
Pin name
Conditions
MCLK
ALE
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
MCLK
MADATA[15:0]
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
Value
Min
Max
Unit
9
12
9
12
ns
ns
ns
ns
1
tOD
ns
1
tOD
ns
1
1
Remarks
Note:
− When the external load capacitance = 30 pF
MCLK
MCSX[7:0]
MALE
MAD [24:0]
MOEX
MDQM [1:0]
MWEX
MADATA[15:0]
Document Number: 002-05622 Rev. *D
Page 81 of 117
MB9B110R Series
NAND Flash Mode
(VCC = 2.7V to 5.5V, VSS = 0V, TA = -40°C to +85°C)
Parameter
MNREX
Min pulse width
Data setup →
MNREX ↑ time
MNREX ↑ →
Data hold time
MNALE ↑ →
MNWEX delay time
MNALE ↓ →
MNWEX delay time
MNCLE ↑ →
MNWEX delay time
MNWEX ↑ →
MNCLE delay time
MNWEX
Min pulse width
MNWEX ↓ →
Data delay time
MNWEX ↑ →
Data hold time
Symbol
Pin name
tNREW
MNREX
tDS – NRE
tDH – NRE
tALEH - NWEL
tALEL - NWEL
tCLEH - NWEL
tNWEH - CLEL
tNWEW
tNWEL – DV
tNWEH – DX
MNREX
MADATA[15:0]
MNREX
MADATA[15:0]
MNALE
MNWEX
MNALE
MNWEX
MNCLE
MNWEX
MNCLE
MNWEX
MNWEX
MNWEX
MADATA[15:0]
MNWEX
MADATA[15:0]
Conditions
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
Value
Unit
Min
Max
MCLK×n-3
-
ns
20
38
-
ns
0
-
ns
MCLK×m-9
MCLK×m-12
MCLK×m-9
MCLK×m-12
MCLK×m-9
MCLK×m-12
MCLK×m+9
MCLK×m+12
MCLK×m+9
MCLK×m+12
MCLK×m+9
MCLK×m+12
MCLK×m+9
MCLK×m+12
0
MCLK×n-3
-
-9
-12
+9
+12
MCLK×m+9
MCLK×m+12
0
ns
ns
ns
ns
ns
ns
ns
Note:
− When the external load capacitance = 30 pF. (m=0 to 15, n=1 to 16)
NAND Flash Read
MCLK
MNREX
MADATA[15:0]
Read
Document Number: 002-05622 Rev. *D
Page 82 of 117
MB9B110R Series
NAND Flash Address Write
MCLK
MNALE
MNCLE
MNWEX
MADATA[15:0]
Write
NAND Flash Command Write
MCLK
MNALE
MNCLE
MNWEX
MADATA[15:0]
Document Number: 002-05622 Rev. *D
Write
Page 83 of 117
MB9B110R Series
External Ready Input Timing
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
Pin name
Conditions
tRDYI
MCLK
MRDY
VCC ≥ 4.5 V
19
VCC < 4.5 V
37
MCLK ↑
MRDY input
setup time
Min
Value
Max
-
Unit
Remarks
ns
When RDY is input
···
MCLK
Original
Over 2cycle
MOEX
MWEX
tRDYI
MRDY
When RDY is released
MCLK
··· ···
2 cycle
Extended
MOEX
tRDYI
MWEX
0.5×VCC
MRDY
Document Number: 002-05622 Rev. *D
Page 84 of 117
MB9B110R Series
12.4.9 Base Timer Input Timing
Timer input timing
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Input pulse width
Symbol
Pin name
Conditions
tTIWH
tTIWL
TIOAn/TIOBn
(when using as
ECK, TIN)
-
tTIWH
ECK
VIHS
Value
Min
Max
2tCYCP
-
Unit
Remarks
ns
tTIWL
VIHS
TIN
VILS
VILS
Trigger input timing
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Input pulse width
Symbol
Pin name
Conditions
tTRGH
tTRGL
TIOAn/TIOBn
(when using as
TGIN)
-
tTRGH
TGIN
VIHS
Value
Min
Max
2tCYCP
-
Unit
Remarks
ns
tTRGL
VIHS
VILS
VILS
Note:
− tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Base Timer is connected to, see "8 Block Diagram" in this data sheet.
Document Number: 002-05622 Rev. *D
Page 85 of 117
MB9B110R Series
12.4.10 CSIO/UART Timing
CSIO (SPI = 0, SCINV = 0)
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
Baud rate
Serial clock cycle time
tSCYC
SCK ↓ → SOT delay time
tSLOVI
SIN → SCK ↑ setup time
tIVSHI
SCK ↑ → SIN hold time
tSHIXI
Serial clock L pulse width
Serial clock H pulse width
tSLSH
tSHSL
SCK ↓ → SOT delay time
tSLOVE
SIN → SCK ↑ setup time
tIVSHE
SCK ↑ → SIN hold time
tSHIXE
-
SCK fall time
SCK rise time
tF
tR
Pin
name
SCKx
SCKx
SOTx
SCKx
SINx
SCKx
SINx
SCKx
SCKx
SCKx
SOTx
SCKx
SINx
SCKx
SINx
SCKx
SCKx
Conditions
-
VCC < 4.5 V
Min
Max
8
4tCYCP
-
VCC ≥ 4.5 V
Min
Max
8
4tCYCP
-
Unit
Mbps
ns
-30
+30
- 20
+ 20
ns
50
-
30
-
ns
0
-
0
-
ns
2tCYCP - 10
tCYCP + 10
-
2tCYCP - 10
tCYCP + 10
-
ns
ns
-
50
-
30
ns
10
-
10
-
ns
20
-
20
-
ns
-
5
5
-
5
5
ns
ns
Master mode
Slave mode
Notes:
− The above characteristics apply to CLK synchronous mode.
− tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function Serial is connected to, see "8 Block Diagram" in this data sheet.
− These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
− When the external load capacitance = 30 pF.
Document Number: 002-05622 Rev. *D
Page 86 of 117
MB9B110R Series
tSCYC
VOH
SCK
VOL
VOL
tSLOVI
VOH
SOT
VOL
tIVSHI
SIN
tSHIXI
VIH
VIH
VIL
VIL
Master mode
tSLSH
SCK
tSHSL
VIH
VIH
tF
VIL
VIL
VIH
tR
tSLOVE
SOT
VOH
VOL
tIVSHE
SIN
VIH
VIL
tSHIXE
VIH
VIL
Slave mode
Document Number: 002-05622 Rev. *D
Page 87 of 117
MB9B110R Series
CSIO (SPI = 0, SCINV = 1)
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
Pin name
Conditions
-
SCKx
SCKx
SOTx
SCKx
SINx
SCKx
SINx
SCKx
SCKx
SCKx
SOTx
SCKx
SINx
SCKx
SINx
SCKx
SCKx
-
Baud rate
Serial clock cycle time
tSCYC
SCK ↑ → SOT delay time
tSHOVI
SIN → SCK ↓ setup time
tIVSLI
SCK ↓ → SIN hold time
tSLIXI
Serial clock L pulse width
Serial clock H pulse width
tSLSH
tSHSL
SCK ↑ → SOT delay time
tSHOVE
SIN → SCK ↓ setup time
tIVSLE
SCK ↓ → SIN hold time
tSLIXE
SCK fall time
SCK rise time
tF
tR
VCC < 4.5 V
VCC ≥ 4.5 V
Min
Max
Min
Max
-
-
4tCYCP
8
-
4tCYCP
8
-
Mbps
ns
-30
+30
- 20
+ 20
ns
50
-
30
-
ns
0
-
0
-
ns
2tCYCP - 10
tCYCP + 10
-
2tCYCP - 10
tCYCP + 10
-
ns
ns
-
50
-
30
ns
10
-
10
-
ns
20
-
20
-
ns
-
5
5
-
5
5
ns
ns
Master
mode
Slave mode
Unit
Notes:
− The above characteristics apply to CLK synchronous mode.
− tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function Serial is connected to, see "8 Block Diagram" in this data sheet.
− These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
− When the external load capacitance = 30 pF.
Document Number: 002-05622 Rev. *D
Page 88 of 117
MB9B110R Series
tSCYC
SCK
VOH
VOH
VOL
tSHOVI
VOH
SOT
VOL
tIVSLI
SIN
VIH
tSLIXI
VIH
VIL
VIL
Master mode
tSHSL
SCK
tSLSH
VIH
VIH
VIL
tR
tF
VIL
VIL
tSHOVE
SOT
VOH
VOL
tIVSLE
SIN
VIH
VIL
tSLIXE
VIH
VIL
Slave mode
Document Number: 002-05622 Rev. *D
Page 89 of 117
MB9B110R Series
CSIO (SPI = 1, SCINV = 0)
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
Pin name
Conditions
-
-
-
Serial clock cycle time
tSCYC
SCK ↑ → SOT delay time
tSHOVI
SIN → SCK ↓ setup time
tIVSLI
SCK ↓→ SIN hold time
tSLIXI
SOT → SCK ↓ delay time
tSOVLI
Serial clock L pulse width
Serial clock H pulse width
tSLSH
tSHSL
SCK ↑ → SOT delay time
tSHOVE
SIN → SCK ↓ setup time
tIVSLE
SCK ↓→ SIN hold time
tSLIXE
SCKx
SCKx
SOTx
SCKx
SINx
SCKx
SINx
SCKx
SOTx
SCKx
SCKx
SCKx
SOTx
SCKx
SINx
SCKx
SINx
SCKx
SCKx
Baud rate
SCK fall time
SCK rise time
tF
tR
VCC < 4.5 V
VCC ≥ 4.5 V
Min
Max
Min
Max
-
8
-
8
Mbps
4tCYCP
-
4tCYCP
-
ns
-30
+30
- 20
+ 20
ns
50
-
30
-
ns
0
-
0
-
ns
2tCYCP - 30
-
2tCYCP - 30
-
ns
2tCYCP - 10
tCYCP + 10
-
2tCYCP - 10
tCYCP + 10
-
ns
ns
-
50
-
30
ns
10
-
10
-
ns
20
-
20
-
ns
-
5
5
-
5
5
ns
ns
Master mode
Slave mode
Unit
Notes:
− The above characteristics apply to CLK synchronous mode.
− tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function Serial is connected to, see "8 Block Diagram" in this data sheet.
− These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
− When the external load capacitance = 30 pF.
Document Number: 002-05622 Rev. *D
Page 90 of 117
MB9B110R Series
tSCYC
VOH
SCK
VOL
SOT
VOH
VOL
VOH
VOL
tIVSLI
tSLIXI
VIH
VIL
SIN
VOL
tSHOVI
tSOVLI
VIH
VIL
Master mode
tSLSH
SCK
VIH
tR
VOH
VOL
tIVSLE
SIN
VIL
tF
*
SOT
VIL
tSHSL
VIH
VIH
tSHOVE
VOH
VOL
tSLIXE
VIH
VIL
VIH
VIL
Slave mode
*: Changes when writing to TDR register
Document Number: 002-05622 Rev. *D
Page 91 of 117
MB9B110R Series
CSIO (SPI = 1, SCINV = 1)
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
VCC < 4.5 V
VCC ≥ 4.5 V
Min
Max
Min
Max
-
8
-
8
Mbps
SCKx
4tCYCP
-
4tCYCP
-
ns
SCKx
SOTx
-30
+30
- 20
+ 20
ns
50
-
30
-
ns
0
-
0
-
ns
2tCYCP - 30
-
2tCYCP - 30
-
ns
2tCYCP - 10
tCYCP + 10
-
2tCYCP - 10
tCYCP + 10
-
ns
ns
-
50
-
30
ns
10
-
10
-
ns
20
-
20
-
ns
-
5
5
-
5
5
ns
ns
Symbol
Pin name
Conditions
-
-
-
Serial clock cycle time
tSCYC
SCK ↓ → SOT delay time
tSLOVI
SIN → SCK ↑ setup time
tIVSHI
SCK ↑ → SIN hold time
tSHIXI
SOT → SCK ↑ delay time
tSOVHI
Serial clock L pulse width
Serial clock H pulse width
tSLSH
tSHSL
SCK ↓ → SOT delay time
tSLOVE
SIN → SCK ↑ setup time
tIVSHE
SCK ↑ → SIN hold time
tSHIXE
Baud rate
SCK fall time
SCK rise time
tF
tR
SCKx
SINx
SCKx
SINx
SCKx
SOTx
SCKx
SCKx
SCKx
SOTx
SCKx
SINx
SCKx
SINx
SCKx
SCKx
Master mode
Slave mode
Unit
Notes:
− The above characteristics apply to CLK synchronous mode.
− tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function Serial is connected to, see "8 Block Diagram" in this data sheet.
− These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
− When the external load capacitance = 30 pF.
Document Number: 002-05622 Rev. *D
Page 92 of 117
MB9B110R Series
tSCYC
VOH
SCK
VOH
VOL
tSOVHI
tSLOVI
VOH
VOL
SOT
VOH
VOL
tSHIXI
tIVSHI
VIH
VIL
SIN
VIH
VIL
Master mode
tR
tF
tSHSL
SCK
VIH
VIH
VIL
tSLSH
VIL
VIL
tSLOVE
VOH
VOL
SOT
VOH
VOL
tIVSHE
tSHIXE
VIH
VIL
SIN
VIH
VIL
Slave mode
UART external clock input (EXT = 1)
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
Serial clock L pulse width
Serial clock H pulse width
SCK fall time
SCK rise time
Conditions
tSLSH
tSHSL
tF
tR
CL = 30 pF
Value
Min
tCYCP + 10
tCYCP + 10
-
tR
Document Number: 002-05622 Rev. *D
VIL
Remarks
ns
ns
ns
ns
tF
tSHSL
SCK
Unit
Max
5
5
VIH
tSLSH
VIH
VIL
VIL
Page 93 of 117
MB9B110R Series
12.4.11 External Input Timing
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
Pin name
Conditions
Value
Min
Max
Unit
ADTG
Input pulse width
tINH,
tINL
FRCKx
ICxx
DTTIxX
INTxx,
NMIX
-
2tCYCP*
-
ns
Except
Timer mode,
Stop mode
Timer mode,
Stop mode
2tCYCP*
-
ns
2tCYCP + 100*
-
ns
500
-
ns
Remarks
A/D converter trigger
input
Free-run timer input clock
Input capture
Wave form generator
External interrupt
NMI
*: tCYCP indicates the APB bus clock cycle time.
About the APB bus number which A/D converter, Multi-function Timer, External interrupt is connected to, see "8.Block Diagram"
in this data sheet.
Document Number: 002-05622 Rev. *D
Page 94 of 117
MB9B110R Series
12.4.12 Quadrature Position/Revolution Counter timing
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
Value
Conditions
AIN pin H width
tAHL
AIN pin L width
tALL
BIN pin H width
tBHL
BIN pin L width
tBLL
BIN rise time from
tAUBU
AIN pin H level
AIN fall time from
tBUAD
BIN pin H level
BIN fall time from
tADBD
AIN pin L level
AIN rise time from
tBDAU
BIN pin L level
AIN rise time from
tBUAU
BIN pin H level
BIN fall time from
tAUBD
AIN pin H level
AIN fall time from
tBDAD
BIN pin L level
BIN rise time from
tADBU
AIN pin L level
ZIN pin H width
tZHL
ZIN pin L width
tZLL
AIN/BIN rise and fall time
tZABE
from determined ZIN level
Determined ZIN level from
tABEZ
AIN/BIN rise and fall time
*: tCYCP indicates the APB bus clock cycle time.
Min
Max
2tCYCP*
-
Unit
PC_Mode2 or PC_Mode3
PC_Mode2 or PC_Mode3
PC_Mode2 or PC_Mode3
PC_Mode2 or PC_Mode3
PC_Mode2 or PC_Mode3
ns
PC_Mode2 or PC_Mode3
PC_Mode2 or PC_Mode3
PC_Mode2 or PC_Mode3
QCR:CGSC=0
QCR:CGSC=0
QCR:CGSC=1
QCR:CGSC=1
About the APB bus number which Quadrature Position/Revolution Counter is connected to, see "8.Block Diagram" in this data
sheet.
tALL
tAHL
AIN
tAUBU
tADBD
tBUAD
tBDAU
BIN
tBHL
Document Number: 002-05622 Rev. *D
tBLL
Page 95 of 117
MB9B110R Series
tBLL
tBHL
BIN
tBUAU
tBDAD
tAUBD
tADBU
AIN
tAHL
tALL
ZIN
ZIN
AIN/BIN
Document Number: 002-05622 Rev. *D
Page 96 of 117
MB9B110R Series
12.4.13 I2C Timing
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
SCL clock frequency
(Repeated) START
condition hold time
SDA ↓ → SCL ↓
SCLclock L width
SCLclock H width
(Repeated) START setup
time
SCL ↑ → SDA ↓
Data hold time
SCL ↓ → SDA ↓ ↑
Data setup time
SDA ↓ ↑ → SCL ↑
STOP condition setup time
SCL ↑ → SDA ↑
Bus free time between
STOP condition and
START condition
Conditions
Standard-mode
Fast-mode
Unit
fSCL
Min
0
Max
100
Min
0
Max
400
tHDSTA
4.0
-
0.6
-
μs
tLOW
tHIGH
4.7
4.0
-
1.3
0.6
-
μs
μs
4.7
-
0.6
-
μs
0
3.45*2
0
0.9*3
μs
tSUDAT
250
-
100
-
ns
tSUSTO
4.0
-
0.6
-
μs
tBUF
4.7
-
1.3
-
μs
tSUSTA
tHDDAT
CL = 30 pF,
R = (Vp/IOL)*1
8 MHz ≤
2 tCYCP*4
2 tCYCP*4
tCYCP ≤ 40 MHz
40 MHz <
Noise filter
tSP
3 tCYCP*4
3 tCYCP*4
tCYCP ≤ 60 MHz
60 MHz <
4 tCYCP*4
4 tCYCP*4
tCYCP ≤ 72 MHz
*1: R and C represent the pull-up resistance and load capacitance of the SCL and SDA lines, respectively.
Remarks
kHz
ns
*5
ns
*5
ns
*5
Vp indicates the power supply voltage of the pull-up resistance and IOL indicates VOL guaranteed current.
*2: The maximum tHDDAT must satisfy that it doesn't extend at least L period (t LOW) of device's SCL signal.
*3: Fast-mode I2C bus device can be used on Standard-mode I2C bus system as long as the device satisfies the requirement of
tSUDAT ≥ 250 ns.
*4: tCYCP is the APB bus clock cycle time.
About the APB bus number that I2C is connected to, see "8 Block Diagram" in this data sheet.
To use Standard-mode, set the APB bus clock at 2 MHz or more.
To use Fast-mode, set the APB bus clock at 8 MHz or more.
*5: The number of the steps of the noise filter can be changed by register settings.
Change the number of the noise filter steps according to APB2 bus clock frequency.
SDA
SCL
Document Number: 002-05622 Rev. *D
Page 97 of 117
MB9B110R Series
12.4.14 ETM Timing
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Data hold
TRACECLK
frequency
Symbol
Pin name
Conditions
tETMH
TRACECLK
TRACED[3:0]
1/ tTRACE
TRACECLK
TRACECLK
cycle time
tTRACE
Value
Unit
Min
Max
VCC ≥ 4.5 V
2
9
VCC < 4.5 V
2
15
VCC ≥ 4.5 V
-
50
MHz
VCC < 4.5 V
-
32
MHz
VCC ≥ 4.5 V
20
-
ns
VCC < 4.5 V
31.25
-
ns
Remarks
ns
Note:
− When the external load capacitance = 30 pF.
HCLK
TRACECLK
TRACED[3:0]
Document Number: 002-05622 Rev. *D
Page 98 of 117
MB9B110R Series
12.4.15 JTAG Timing
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
Pin name
TMS, TDI setup time
tJTAGS
TCK,
TMS, TDI
TMS, TDI hold time
tJTAGH
TCK,
TMS, TDI
TDO delay time
tJTAGD
TCK,
TDO
Conditions
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
Value
Unit
Min
Max
15
-
ns
15
-
ns
-
25
-
45
Remarks
ns
Note:
− When the external load capacitance = 30 pF.
TCK
TMS/TDI
TDO
Document Number: 002-05622 Rev. *D
Page 99 of 117
MB9B110R Series
12.5 12-bit A/D Converter
Electrical Characteristics for the A/D Converter
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
Pin name
Resolution
-
Integral Nonlinearity
Value
Unit
Min
Typ
Max
-
-
-
12
bit
-
-
-
± 4.0
± 4.5
LSB
Differential Nonlinearity
-
-
-
± 2.3
± 2.5
LSB
Zero transition voltage
VZT
ANxx
-
± 10
± 15
mV
Full-scale transition
voltage
VFST
ANxx
-
AVRH ± 10
AVRH ± 15
mV
Conversion time
-
-
Sampling time
tS
-
1.0*1
1.2*1
*2
*2
-
-
Compare clock cycle*3
tCCK
-
50
-
2000
ns
State transition time to
operation permission
tSTT
-
-
-
1.0
μs
Analog input capacity
CAIN
-
-
-
12.9
pF
Analog input resistance
RAIN
-
-
-
2
3.8
kΩ
Interchannel disparity
-
-
-
-
4
LSB
Analog port input leak
current
-
ANxx
-
-
5
μA
Analog input voltage
-
ANxx
AVSS
-
AVRH
V
Reference voltage
-
AVRH
2.7
-
AVCC
V
μs
ns
Remarks
AVRH = 2.7 V to 5.5 V
AVCC ≥ 4.5 V
AVCC < 4.5 V
AVCC ≥ 4.5 V
AVCC < 4.5 V
AVCC ≥ 4.5 V
AVCC < 4.5 V
AVCC ≥ 4.5 V
AVCC < 4.5 V
*1: Conversion time is the value of sampling time (tS) + compare time (tC).
The condition of the minimum conversion time is the following.
AVCC ≥ 4.5 V, HCLK=120 Hz
sampling time: 300 ns, compare time: 700 ns
AVCC < 4.5 V, HCLK=120 Hz
sampling time: 500 ns, compare time: 700 ns
Ensure that it satisfies the value of sampling time (tS) and compare clock cycle (tCCK).
For setting*4 of sampling time and compare clock cycle, see "CHAPTER 1-1: 12-bit A/D Converter" in "FM3 Family
PERIPHERAL MANUAL Analog Macro Part".
A/D Converter register is set at APB bus clock timing. Sampling and compare clock is set at Base clock (HCLK).
About the APB bus number which the A/D Converter is connected to, see "8 Block Diagram" in this data sheet.
*2: A necessary sampling time changes by external impedance.
Ensure that it set the sampling time to satisfy (Equation 1).
*3: Compare time (tC) is the value of (Equation 2).
Document Number: 002-05622 Rev. *D
Page 100 of 117
MB9B110R Series
ANxx
REXT
Analog input pin
Comparator
RAIN
Analog signal
source
CAIN
(Equation 1) tS ≥ ( RAIN + REXT ) × CAIN × 9
tS:
Sampling time
RAIN:
Input resistance of A/D = 2 kΩ at 4.5 V < AVCC < 5.5 V
Input resistance of A/D = 3.8 kΩ at 2.7 V < AVCC < 4.5 V
CAIN:
Input capacity of A/D = 12.9 pF at 2.7 V < AVCC < 5.5 V
REXT:
Output impedance of external circuit
(Equation 2) tC = tCCK × 14
tC:
Compare time
tCCK:
Compare clock cycle
Document Number: 002-05622 Rev. *D
Page 101 of 117
MB9B110R Series
Definition of 12-bit A/D Converter Terms
Resolution:
Analog variation that is recognized by an A/D converter.
Integral Nonlinearity:
Deviation of the line between the zero-transition point
(0b000000000000 ←→ 0b000000000001) and the full-scale transition point
(0b111111111110 ←→ 0b111111111111) from the actual conversion characteristics.
Differential Nonlinearity:
Deviation from the ideal value of the input voltage that is required to change the output code by 1 LSB.
Integral Nonlinearity
0xFFF
Actual conversion
characteristics
0xFFE
Actual conversion
characteristics
0x(N+1)
{1 LSB(N-1) + VZT}
VFST
VNT
0x004
(Actually-measured
value)
0x003
Actual conversion
characteristics
Ideal characteristics
0x002
0x001
(Actuallymeasured
value)
Digital output
Digital output
0xFFD
Differential Nonlinearity
Ideal characteristics
0xN
V(N+1)T
0x(N-1)
VNT
(Actually-measured
value)
0x(N-2)
VZT (Actually-measured value)
AVSS
Actual conversion characteristics
AVRH
AVSS
AVRH
Analog input
Integral Nonlinearity of digital output N =
Differential Nonlinearity of digital output N =
1LSB =
N:
VZT:
VFST:
VNT:
(Actually-measured
value)
Analog input
VNT - {1LSB × (N - 1) + VZT}
1LSB
V(N + 1) T - VNT
1LSB
[LSB]
- 1 [LSB]
VFST - VZT
4094
A/D converter digital output value.
Voltage at which the digital output changes from 0x000 to 0x001.
Voltage at which the digital output changes from 0xFFE to 0xFFF.
Voltage at which the digital output changes from 0x(N − 1) to 0xN.
Document Number: 002-05622 Rev. *D
Page 102 of 117
MB9B110R Series
12.6 Low-Voltage Detection Characteristics
12.6.1 Low-Voltage Detection Reset
(TA = - 40°C to + 85°C)
Parameter
Symbol
Conditions
Detected voltage
VDL
Released voltage
VDH
Value
Unit
Remarks
Min
Typ
Max
-
2.25
2.45
2.65
V
When voltage drops
-
2.30
2.50
2.70
V
When voltage rises
12.6.2 Interrupt of Low-Voltage Detection
(TA = - 40°C to + 85°C)
Parameter
Symbol
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
LVD stabilization
wait time
tLVDW
Conditions
SVHI = 0000
SVHI = 0001
SVHI = 0010
SVHI = 0011
SVHI = 0100
SVHI = 0111
SVHI = 1000
SVHI = 1001
-
Value
Unit
Min
Typ
Max
2.58
2.67
2.76
2.85
2.94
3.04
3.31
3.40
3.40
3.50
3.68
3.77
3.77
3.86
3.86
3.96
2.8
2.9
3.0
3.1
3.2
3.3
3.6
3.7
3.7
3.8
4.0
4.1
4.1
4.2
4.2
4.3
3.02
3.13
3.24
3.34
3.45
3.56
3.88
3.99
3.99
4.10
4.32
4.42
4.42
4.53
4.53
4.64
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
-
-
4032 × tCYCP*
μs
Remarks
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
*: tCYCP indicates the APB2 bus clock cycle time.
Document Number: 002-05622 Rev. *D
Page 103 of 117
MB9B110R Series
12.7 MainFlash Memory Write/Erase Characteristics
12.7.1 Write / Erase time
(VCC = 2.7V to 5.5V, TA = - 40°C to + 85°C)
Value
Parameter
Sector erase time
Typ*
Max*
Large Sector
0.7
3.7
Small Sector
0.3
1.1
Half word (16-bit)
write time
Unit
s
Remarks
Includes write time prior to internal
erase
Not including system-level overhead
time
Includes write time prior to internal
Chip erase time
8
38.4
s
erase
*: The typical value is immediately after shipment, the maximum value is guarantee value under 100,000 cycle of erase/write.
12
384
μs
12.7.2 Erase/write cycles and data hold time
Erase/write cycles (cycle)
Data hold time (year)
1,000
20*
10,000
10*
100,000
5*
Remarks
*: At average + 85°C
12.8 WorkFlash Memory Write/Erase Characteristics
12.8.1 Write / Erase time
(VCC = 2.7V to 5.5V, TA = - 40°C to + 85°C)
Parameter
Value
Typ*
Max*
Sector erase time
0.3
1.5
Half word (16-bit)
write time
20
Unit
s
Remarks
Includes write time prior to internal
erase
Not including system-level overhead
time
Includes write time prior to internal
Chip erase time
1.2
6
s
erase
*: The typical value is immediately after shipment, the maximum value is guarantee value under 10,000 cycle of erase/write.
384
μs
12.8.2 Erase/write cycles and data hold time
Erase/write cycles (cycle)
Data hold time (year)
1,000
20*
10,000
10*
Remarks
*: At average + 85°C
Document Number: 002-05622 Rev. *D
Page 104 of 117
MB9B110R Series
12.9 Return Time from Low-Power Consumption Mode
12.9.1 Return Factor: Interrupt
The return time from Low-Power consumption mode is indicated as follows. It is from receiving the return factor to starting the
program operation.
Return Count Time
(VCC = 2.7V to 5.5V, TA = - 40°C to + 85°C
Parameter
Symbol
Sleep mode
High-speed CR Timer mode,
Main Timer mode,
PLL Timer mode
Value
Typ
Max*
tCYCC
Unit
ns
40
80
μs
453
737
μs
Sub Timer mode
453
737
μs
Stop mode
453
737
μs
Low-speed CR Timer mode
tICNT
Remarks
*: The maximum value depends on the accuracy of built-in CR.
Operation example of return from Low-Power consumption mode (by external interrupt*)
External
interrupt
Interrupt factor
accept
Active
tICNT
CPU
Operation
Interrupt factor
clear by CPU
Start
*: External interrupt is set to detecting fall edge.
Document Number: 002-05622 Rev. *D
Page 105 of 117
MB9B110R Series
Operation example of return from Low-Power consumption mode (by internal resource interrupt*)
Internal
resource
interrupt
Interrupt factor
accept
Active
tICNT
CPU
Operation
Interrupt factor
clear by CPU
Start
*: Internal resource interrupt is not included in return factor by the kind of Low-Power consumption mode.
Notes:
− The return factor is different in each Low-Power consumption modes.
See "CHAPTER 6: Low Power Consumption Mode and Operations of Standby Modes" in "FM3 Family PERIPHERAL MANUAL"
about the return factor from Low-Power consumption mode.
− When interrupt recoveries, the operation mode that CPU recoveries depends on the state before the Low-Power consumption
mode transition. See "CHAPTER 6: Low Power Consumption Mode" in "FM3 Family PERIPHERAL MANUAL".
Document Number: 002-05622 Rev. *D
Page 106 of 117
MB9B110R Series
12.9.2 Return Factor: Reset
The return time from Low-Power consumption mode is indicated as follows. It is from releasing reset to starting the program
operation.
Return Count Time
(VCC = 2.7V to 5.5V, TA = - 40°C to + 85°C)
Parameter
Symbol
Value
Unit
Typ
Max*
321
461
μs
321
461
μs
441
701
μs
Sub Timer mode
441
701
μs
Stop mode
441
701
μs
Sleep mode
High-speed CR Timer mode,
Main Timer mode,
PLL Timer mode
Low-speed CR Timer mode
tRCNT
Remarks
*: The maximum value depends on the accuracy of built-in CR.
Operation example of return from Low-Power consumption mode (by INITX)
INITX
Internal reset
Reset active
Release
tRCNT
CPU
Operation
Document Number: 002-05622 Rev. *D
Start
Page 107 of 117
MB9B110R Series
Operation example of return from low power consumption mode (by internal resource reset*)
Internal
resource
reset
Internal reset
Reset active
Release
tRCNT
CPU
Operation
Start
*: Internal resource reset is not included in return factor by the kind of Low-Power consumption mode.
Notes:
− The return factor is different in each Low-Power consumption modes.
See "CHAPTER 6: Low Power Consumption Mode and Operations of Standby Modes" in "FM3 Family PERIPHERAL
MANUAL".
− When interrupt recoveries, the operation mode that CPU recoveries depends on the state before the Low-Power consumption
mode transition. See "CHAPTER 6: Low Power Consumption Mode" in "FM3 Family PERIPHERAL MANUAL".
− The time during the power-on reset/low-voltage detection reset is excluded. See "(6) Power-on Reset Timing" in "4. AC
Characteristics" in "12 Electrical Characteristics" for the detail on the time during the power-on reset/low -voltage detection reset.
− When in recovery from reset, CPU changes to the High-speed CR Run mode. When using the main clock or the PLL clock, it is
necessary to add the main clock oscillation stabilization wait time or the Main PLL clock stabilization wait time.
− The internal resource reset means the watchdog reset and the CSV reset.
Document Number: 002-05622 Rev. *D
Page 108 of 117
MB9B110R Series
13. Ordering Information
On-chip
Flash
memory
On-chip
SRAM
MB9BF112NPQC-G-JNE2
Main: 128 Kbyte
Work: 32 Kbyte
16 Kbyte
MB9BF114NPQC-G-JNE2
Main: 256 Kbyte
Work: 32 Kbyte
32 Kbyte
MB9BF115NPQC-G-JNE2
Main: 384 Kbyte
Work: 32 Kbyte
48 Kbyte
MB9BF116NPQC-G-JNE2
Main: 512 Kbyte
Work: 32 Kbyte
64 Kbyte
MB9BF112NPMC-G-JNE2
Main: 128 Kbyte
Work: 32 Kbyte
16 Kbyte
MB9BF114NPMC-G-JNE2
Main: 256 Kbyte
Work: 32 Kbyte
32 Kbyte
MB9BF115NPMC-G-JNE2
Main: 384 Kbyte
Work: 32 Kbyte
48 Kbyte
MB9BF116NPMC-G-JNE2
Main: 512 Kbyte
Work: 32 Kbyte
64 Kbyte
MB9BF112RPMC-G-JNE2
Main: 128 Kbyte
Work: 32 Kbyte
16 Kbyte
MB9BF114RPMC-G-JNE2
Main: 256 Kbyte
Work: 32 Kbyte
32 Kbyte
MB9BF115RPMC-G-JNE2
Main: 384 Kbyte
Work: 32 Kbyte
48 Kbyte
MB9BF116RPMC-G-JNE2
Main: 512 Kbyte
Work: 32 Kbyte
64 Kbyte
MB9BF112NBGL-GE1
Main: 128 Kbyte
Work: 32 Kbyte
16 Kbyte
MB9BF114NBGL-GE1
Main: 256 Kbyte
Work: 32 Kbyte
32 Kbyte
MB9BF115NBGL-GE1
Main: 384 Kbyte
Work: 32 Kbyte
48 Kbyte
MB9BF116NBGL-GE1
Main: 512 Kbyte
Work: 32 Kbyte
64 Kbyte
Part number
Document Number: 002-05622 Rev. *D
Package
Packing
Plastic QFP
100-pin (0.65 mm pitch),
(PQH100)
Plastic LQFP
100-pin (0.5 mm pitch),
(LQI100)
Tray
Plastic LQFP
120-pin (0.5 mm pitch),
(LQM120)
Plastic FBGA
112-pin (0.8 mm pitch),
(LBC112)
Page 109 of 117
MB9B110R Series
14. Package Dimensions
Package Type
Package Code
LQFP 100
LQI100
D
D1
75
4
D
5 7
51
D1
51
50
76
4
5 7
75
50
76
E1 E
5 4
7
E1 E
5 4
7
3
6
26
100
1
26
25
1
25
2 5 7
e
100
BOTTOM VIEW
0.1 0 C A-B D
3
0.2 0 C A-B D
b
TOP VIEW
8
0.0 8
C A-B
D
2
A
9
A
SEAT ING
PLA NE
A'
0.25
L1
0.0 8 C
c
A1
b
10
SECTION A-A'
L
SIDE VIEW
SYMBOL
DETAIL A
DIMENSIONS
MIN.
NOM. MAX.
1.70
A
A1
0.05
b
0.15
0.15
0.27
c
0.09
0.20
D
16.00 BSC
D1
14.00 BSC
e
0.50 BSC
E
16.00 BSC
E1
14.00 BSC
L
0.45
0.60
0.75
L1
0.30
0.50
0.70
NOTES :
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. DATUM PLANE H IS LOCATED AT THE BOTTOM OF THE MOLD PARTING
LINE COINCIDENT WITH WHERE THE LEAD EXITS THE BODY.
3. DATUMS A-B AND D TO BE DETERMINED AT DATUM PLANE H.
4. TO BE DETERMINED AT SEATING PLANE C.
5. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION.
ALLOWABLE PROTRUSION IS 0.25mm PRE SIDE.
DIMENSIONS D1 AND E1 INCLUDE MOLD MISMATCH AND ARE DETERMINED
AT DATUM PLANE H.
6. DETAILS OF PIN 1 IDENTIFIER ARE OPTIONAL BUT MUST BE LOCATED
WITHIN THE ZONE INDICATED.
7. REGARDLESS OF THE RELATIVE SIZE OF THE UPPER AND LOWER BODY
SECTIONS. DIMENSIONS D1 AND E1 ARE DETERMINED AT THE LARGEST
FEATURE OF THE BODY EXCLUSIVE OF MOLD FLASH AND GATE BURRS.
BUT INCLUDING ANY MISMATCH BETWEEN THE UPPER AND LOWER
SECTIONS OF THE MOLDER BODY.
8. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. THE DAMBAR
PROTRUSION (S) SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED b
MAXIMUM BY MORE THAN 0.08mm. DAMBAR CANNOT BE LOCATED ON
THE LOWER RADIUS OR THE LEAD FOOT.
9. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD
BETWEEN 0.10mm AND 0.25mm FROM THE LEAD TIP.
10. A1 IS DEFINED AS THE DISTANCE FROM THE SEATING PLANE TO
THE LOWEST POINT OF THE PACKAGE BODY.
PACKAGE OUTLINE, 100 LEAD LQFP
14.0X14.0X1.7 MM LQI100 REV*A
Document Number: 002-05622 Rev. *D
002-11500 *A
Page 110 of 117
MB9B110R Series
Package Type
Package Code
LQFP 120
LQM120
4
D
5 7
D1
90
61
91
61
60
90
91
60
E1
E
4
5
7
3
6
31
120
1
30
e
31
30
2 5 7
1
0.10 C A-B D
3
b
0.20 C A-B D
0.08
C A-B
D
BOTTOM VIEW
8
TOP VIEW
2
A
9
c
A
A'
0.08 C
SEATI NG
PLA NE
0.25
A1
10
b
SEC TION A -A'
L
SIDE VIEW
SYMBOL
DIMENSIONS
MIN. NOM. MAX.
A
A1
1 . 70
0.05
0.15
b
0.17
c
0.115
0.22
D
18.00 BSC
D1
16.00 BSC
e
0.50 BSC
E
18.00 BSC
E1
L
0.27
0.195
16.00 BSC
0.45
0
0.60
0.75
8
PACKAGE OUTLINE, 120 LEAD LQFP
18.0X18.0X1.7 MM LQM120 REV**
Document Number: 002-05622 Rev. *D
002-16172 **
Page 111 of 117
MB9B110R Series
Package Type
Package Code
QFP 100
PQH100
D
D1
4
5 7
80
51
81
51
50
80
50
81
31
100
E1 E
5
7
6
3
4
31
100
1
30
e
3
0.40 C A-B D
30
2 5 7
1
0.20 C A-B D
b
0.13
C A-B
D
BOTTOM VIEW
8
TOP VIEW
2
9
A
A'
SEATING
PLANE
L2
c
10
b
0.10 C
SECTION A-A'
DETAIL A
SIDE VIEW
SYMBOL
DIMENSIONS
MIN.
NOM. MAX.
A1
0.05
0.45
b
0.27
c
0.11
A
3.35
0.32
0.23
D
23.90 BSC
D1
20.00 BSC
e
0.65 BSC
E
17.90 BSC
E1
14.00 BSC
0
L
0.37
0.73
8
0.88
L1
1.95 REF
L2
0.25 BSC
1.03
PACKAGE OUTLINE, 100 LEAD QFP
20.00X14.00X3.35 MM PQH100 REV**
Document Number: 002-05622 Rev. *D
002-15156 **
Page 112 of 117
MB9B110R Series
Package Type
Package Code
FBGA 112
LBC112
A
0.20 C
11
2X
10
9
6
8
7
6
5
4
3
2
1
L
PIN A1
CORNER
INDEX MARK
K
J
H
G
F
E
D
7
C
B
A
6
B
0.20 C
TOP VIEW
2X
BOTTOM VIEW
DETAIL A
5
112x φb
C
0.10 C
DETAIL A
0.08
C A B
SIDE VIEW
NOTES:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
DIMENSIONS
SYMBOL
MIN.
NOM.
MAX.
2. SOLDER BALL POSITION DESIGNATIO
N PER JEP95, SECTION 3, SPP-020.
A
-
-
1.45
3. "e" REPRESENTS THE SOLDER BALL GRID PITCH.
A1
0.25
0.35
0.45
4. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION.
D
10.00 BSC
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION.
E
10.00 BSC
N IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIX
D1
8.00 BSC
E1
8.00 BSC
MD
11
N
112
0.35
0.45
eD
0.80 BSC
eE
0.80 BSC
SD
0.00
SE
5. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A
PLANE PARALLEL TO DATUM C.
11
ME
b
SIZE MD X ME.
0.00
6. "SD" AND "SE" ARE MEASUREDWITH RESPECT TO DATUMS A AND B AND
DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW.
0.55
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW,
"SD" OR "SE" = 0.
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW,
"SD" = eD/2 AND "SE" = eE/2.
7. A1 CORNER TO BE IDENTIFIED BY
CHAMFER, LASER OR INK MARK
METALIZED MARK, INDENTATION OR OTHER MEANS.
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED SOLDER
BALLS.
PACKAGE OUTLINE, 112 BALL FBGA
10.00X10.00X1.45 MM LBC112 REV**
Document Number: 002-05622 Rev. *D
002-13225 **
Page 113 of 117
MB9B110R Series
15. Major Changes
Spansion Publication Number: DS706-00028
Page
Section
Change Results
Revision 2.0
5
FEATURES
External Interrupt Controller
Unit
ELECTRICAL
CHARACTERISTICS
101
5. 12-bit A/D Converter
Electrical Characteristics for the
A/D Converter
ORDERING INFORMATION
106
Revision 2.1
Revision 3.0
Features
2
External Bus Interface
9
Packages
List of Pin Functions
27, 28
· List of pin numbers
47, 49
I/O Circuit Type
47, 48
I/O Circuit Type
54
Handling Devices
54
55
56
57
58, 59
Handling Devices
Crystal oscillator circuit
Handling Devices
C Pin
Block Diagram
Memory Map
· Memory map(1)
Memory Map
· Memory map(2)(3)
66, 67
Electrical Characteristics
1. Absolute Maximum Ratings
68
Electrical Characteristics
2. Recommended Operation
Conditions
69, 70
Electrical Characteristics
3. DC Characteristics
(1) Current rating
73
74
Electrical Characteristics
4. AC Characteristics
(1) Main Clock Input
Characteristics
Electrical Characteristics
4. AC Characteristics
(3) Built-in CR Oscillation
Characteristics
Document Number: 002-05622 Rev. *D
Corrected the external interrupt input pin.
Corrected the value of "Compare clock cycle".
Max: 10000 → 2000
Corrected the part number.
Company name and layout design change
Added the description of Maximum area size
Deleted the description of ES
Modified I/O circuit type of P63 to P68
Added the description of I2C to the type of E, F and I
Added about +B input
Added " Stabilizing power supply voltage"
Added the following description
"Evaluate oscillation of your using crystal oscillator by your mount
board."
Changed the description
Modified the block diagram
Modified the area of "External Device Area"
Added the summary of Flash memory sector and the note
· Added the Clamp maximum current
· Added the output current of P80 and P81
· Added about +B input
· Modified the minimum value of Analog reference voltage
· Added Smoothing capacitor
· Added the note about less than the minimum power supply voltage
· Changed the table format
· Added Main TIMER mode current
· Added Flash Memory Current
· Moved A/D Converter Current
· Modified the unit of low voltage detection circuit (LVD) power supply
current
Added Master clock at Internal operating clock frequency
Added Frequency stability time at Built-in high-speed CR
Page 114 of 117
MB9B110R Series
Page
75
76
78-80
88-95
102
Section
Electrical Characteristics
4. AC Characteristics
(4-1) Operating Conditions of
Main PLL
(4-2) Operating Conditions of
Main PLL
Electrical Characteristics
4. AC Characteristics
(6) Power-on Reset Timing
Electrical Characteristics
4. AC Characteristics
(7) External Bus Timing
Electrical Characteristics
4. AC Characteristics
(8) CSIO/UART Timing
Electrical Characteristics
5. 12bit A/D Converter
Change Results
· Added Main PLL clock frequency
· Added the figure of Main PLL connection
· Added Time until releasing Power-on reset
· Changed the figure of timing
Modified Data output time
· Modified from UART Timing to CSIO/UART Timing
· Changed from Internal shift clock operation to Master mode
· Changed from External shift clock operation to Slave mode
· Added the typical value of Integral Nonlinearity, Differential Nonlinearity,
Zero transition voltage and Full-scale transition voltage
· Modified Stage transition time to operation permission
· Modified the minimum value of Reference voltage
Electrical Characteristics
7. Low-voltage Detection
105
Modified LVD stabilization wait time
Characteristics
(2) Interrupt of Low-voltage
Detection
Electrical Characteristics
8. WorkFlash Memory Write/Erase · Modified sector erase time
106
· Modified half word(16-bit) write time
Characteristics
(1) Write / Erase time
Electrical Characteristics
107-11
Added Return Time from Low-Power Consumption Mode
9. Return Time from Low-Power
0
Consumption Mode
111
Change to full part number
Ordering Information
112-115 Package Dimensions
Deleted FPT-100P-M20 and FPT-120P-M21
NOTE: Please see “Document History” about later revised information.
Document Number: 002-05622 Rev. *D
Page 115 of 117
MB9B110R Series
Document History
Document Title: MB9B110R Series 32-bit Arm® Cortex®-M3 FM3 Microcontroller
Document Number: 002-05622
Revision
ECN
**
-
Orig. of
Submission
Change
Date
TOYO
03/13/2015
Description of Change
Migrated to Cypress and assigned document number 002-05622.
No change to document contents or format.
Changed package code as below.
FPT-100P-M23 to LQI100-02
FPT-120P-M37 to LQM120-02
FPT-100P-M36 to PQH100
BGA-112P-M04 to LBC112
*A
5175344
TOYO
03/17/2016
P.19 Modified I/O circuit type of MD0
P.43 Added the note of JTAG pins.
P.56 Modified X1A of block diagram.
P.75 Modified max value of PLL macro oscillation clock frequency to 144MHz.
P.111-114 Changed package Dimensions.
*B
5314949
TOYO
06/21/2016
P.110 Modified part number.
“Modified RTC description in “Features, Real-Time Clock(RTC)”
Changed starting count value from 01 to 00. Deleted “second , or day of the week”
in the Interrupt function (Page 2)
Updated “12.4.7 Power-On Reset Timing”. Changed parameter from “Power Supply
rising time(tVCCR)[ms]” to “Power ramp rate(dV/dt)[mV/us]” and added some
*C
5666809
YSKA
03/21/2017
comments (Page 75)
Updated Package code as follows (Page 8-12, 67, 109)
LQI100-02 -> LQI100,
LQM120-02 -> LQM120
Updated “14. Package dimensions” (Page 110-113)
Modified typo in “13. Ordering Information” (Page 109)
Added the Baud rate spec in “12.4.10 CSIO/UART Timing”.(Page 86, 88, 90, 92)
*D
6064714
HUAL
Document Number: 002-05622 Rev. *D
02/09/2018
Updated the Sales information and legal
Page 116 of 117
MB9B110R Series
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the
office closest to you, visit us at Cypress Locations.
PSoC® Solutions
Products
Arm® Cortex® Microcontrollers
Automotive
Clocks & Buffers
Interface
Internet of Things
Memory
cypress.com/arm
cypress.com/automotive
cypress.com/clocks
cypress.com/interface
cypress.com/iot
cypress.com/memory
Microcontrollers
cypress.com/mcu
PSoC
cypress.com/psoc
Power Management ICs
cypress.com/pmic
Touch Sensing
USB Controllers
Wireless Connectivity
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 MCU
Cypress Developer Community
Community | Projects | Videos | Blogs | Training | Components
Technical Support
cypress.com/support
cypress.com/touch
cypress.com/usb
cypress.com/wireless
Arm and Cortex are registered trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
All other trademarks or registered trademarks referenced herein are the property of their respective owners.
© Cypress Semiconductor Corporation, 2012-2018. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC (“Cypress”). This document,
including any software or firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or
other intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software,
then Cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in sour ce
code form, to modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form
externally to end users (either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress’s patents that are
infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction,
modification, translation, or compilation of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computing
device can be absolutely secure. Therefore, despite security measures implemented in Cypress hardware or software products, Cypress does not assume any liability arising out of any security
breach, such as unauthorized access to or use of a Cypress product. In addition, the products described in these materials may contain design defects or errors known as errata which may cause
the product to deviate from published specifications. To the extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not
assume any liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or
programming code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application
made of this information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of
weapons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or
hazardous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage (“Unintended Uses”). A critical component is
any component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable,
in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from or r elated to all Unintended Uses of Cypress products. You shall indemnify
and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress
products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 002-05622 Rev. *D
February 9, 2018
Page 117 of 117