Product Folder Sample & Buy Support & Community Tools & Software Technical Documents LMP8480, LMP8481 SNVS829C – MARCH 1999 – REVISED SEPTEMBER 2015 LMP848x Precision 76-V High-Side Current Sense Amplifiers With Voltage Output 1 Features 3 Description • • • • • • • • • • • • • • • The LMP8480 and LMP8481 are precision high-side current sense amplifiers that amplify a small differential voltage developed across a current sense resistor in the presence of high input common-mode voltages. These amplifiers are designed for bidirectional (LMP8481) or unidirectional (LMP8480) current applications and will accept input signals with common-mode voltage range from 4 V to 76 V with a bandwidth of 270 kHz. Since the operating power supply range overlaps the input common-mode voltage range, the LMP848x can be powered by the same voltage that is being monitored. This benefit eliminates the need for an intermediate supply voltage to be routed to the point of load where the current is being monitored, resulting in reduced component count and board space. 1 Typical Values, TA = 25°C Bidirectional or Unidirectional Sensing Common Mode Voltage Range 4.0 V to 76 V Supply Voltage Range 4.5 V to 76 V Fixed Gains 20, 60 and 100 V/V Gain Accuracy ±0.1% Offset ±80 µV Bandwidth (–3dB) 270 kHz Quiescent Current < 100 µA Buffered High-Current Output > 5 mA Input Bias Current 7 µA PSRR (DC) 122 dB CMRR (DC) 124 dB Temperature Range –40°C to 125°C 8-Pin VSSOP Package 2 Applications • • • • • • • High-Side Current Sense Vehicle Current Measurement Telecommunications Motor Controls Laser or LED Drivers Energy Management Solar Panel Monitoring Typical Application Schematic The LMP848x family consists of fixed gains of 20, 60 and 100 for applications that demand high accuracy over temperature. The low-input offset voltage allows the use of smaller sense resistors without sacrificing system error. The wide operating temperature range of –40°C to 125°C makes the LMP848x an ideal choice for automotive, telecommunications, industrial, and consumer applications. The LMP8480 and LMP8481 are pin-for-pin replacements for the MAX4080 and MAX4081, offering improved offset voltage, wider reference adjust range and higher output drive capabilities. The LMP8480 and LMP8481 are available in a 8-pin VSSOP package. Device Information(1) PACKAGE BODY SIZE (NOM) LMP8480 PART NUMBER VSSOP (8) 3.00 mm x 3.00 mm LMP8481 VSSOP (8) 3.00 mm x 3.00 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA. LMP8480, LMP8481 SNVS829C – MARCH 1999 – REVISED SEPTEMBER 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Device Comparison Table..................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 3 4 7.1 7.2 7.3 7.4 7.5 7.6 4 4 4 4 5 7 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Typical Characteristics .............................................. Detailed Description ............................................ 10 8.1 Overview ................................................................. 10 8.2 Functional Block Diagrams ..................................... 11 8.3 Feature Description................................................. 12 8.4 Device Functional Modes........................................ 17 9 Application and Implementation ........................ 18 9.1 Application Information............................................ 18 9.2 Typical Applications ................................................ 18 10 Power Supply Recommendations ..................... 21 10.1 Power Supply Decoupling ..................................... 21 11 Layout................................................................... 21 11.1 Layout Guidelines ................................................. 21 11.2 Layout Example .................................................... 21 12 Device and Documentation Support ................. 22 12.1 12.2 12.3 12.4 12.5 12.6 Device Support .................................................... Related Links ........................................................ Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 22 22 22 22 22 22 13 Mechanical, Packaging, and Orderable Information ........................................................... 22 4 Revision History Changes from Revision B (December 2014) to Revision C Page • Deleted WSON package option for LMP8480 and LMP8481 ............................................................................................... 1 • Deleted -F version (50x gain) for LMP8480 and LMP8481.................................................................................................... 3 • Deleted WSON package options for LMP8480 and LMP8481 ............................................................................................. 3 Changes from Revision A (August 2012) to Revision B • 2 Page Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1 Submit Documentation Feedback Copyright © 1999–2015, Texas Instruments Incorporated Product Folder Links: LMP8480 LMP8481 LMP8480, LMP8481 www.ti.com SNVS829C – MARCH 1999 – REVISED SEPTEMBER 2015 5 Device Comparison Table DEVICE NAME GAIN POLARITY LMP8480-T x20 Unidirectional LMP8480-S x60 Unidirectional LMP8480-H x100 Unidirectional LMP8481-T x20 Bidirectional or Unidirectional LMP8481-S x60 Bidirectional or Unidirectional LMP8481-H x100 Bidirectional or Unidirectional 6 Pin Configuration and Functions LMP8481 VSSOP PACKAGE 8 PINS (TOP VIEW) LMP8480 VSSOP PACKAGE 8 PINS (TOP VIEW) Pin Functions PIN NAME NO. RSP 1 VCC NC I/O DESCRIPTION I Positive current sense input 2 P Positive supply voltage 3 — No Connection – Not internally Connected. GND 4 P Ground VOUT 5 O Output NC or REFA 6 I LMP8480: No Connection LMP8481: Reference Voltage “B” Input NC or REFB 7 I LMP8480: No Connection LMP8481: Reference Voltage “A” Input RSN 8 I Negative current sense input Copyright © 1999–2015, Texas Instruments Incorporated Product Folder Links: LMP8480 LMP8481 Submit Documentation Feedback 3 LMP8480, LMP8481 SNVS829C – MARCH 1999 – REVISED SEPTEMBER 2015 www.ti.com 7 Specifications 7.1 Absolute Maximum Ratings (1) (2) Over operating free-air temperature range (unless otherwise noted) (3) Supply Voltage (VCC to GND) RSP or RSN to GND VOUT to GND MIN MAX UNIT –0.3 85 V –0.3 85 V –0.3 to the lesser of (VCC + 0.3) or +20 –0.3 Applied to both VREF Pins tied together V 12 V –0.3 6 V –85 85 V Current into output pin –20 (4) 20 mA Current into any other pins –5 (4) 5 mA Operating Temperature –40 125 °C Junction Temperature -40 150 °C Storage temperature –65 150 °C VREF Pins (LMP8481 Only) Other VREF pin tied to ground Differential Input Voltage (1) (2) (3) (4) The maximum power dissipation must be derated at elevated temperatures and is dictated by TJ(MAX), θJA, and the ambient temperature, TA. The maximum allowable power dissipation PDMAX = (TJ(MAX) –TA)/ θJA or the number given in Absolute Maximum Ratings, whichever is lower. If Military/Aerospace specified devices are required, contact the Texas Instruments Sales Office/ Distributors for availability and specifications. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods my affect device reliability. When the input voltage (VIN) at any pin exceeds power supplies (VIN < GND or VIN > VS ), the current at that pin must not exceed 5 mA, and the voltage (VIN) has to be within the Absolute Maximum Ratings for that pin. The 20-mA package input current rating limits the number of pins that can safely exceed the power supplies with current flow to four pins. 7.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000 Charged-device model (CDM), per JEDEC specification JESD22C101 (2) ±750 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Conditions Expected normal operating conditions over free-air temperature range (unless otherwise noted) (1) Supply Voltage (VCC) Common Mode Voltage Reference Input (LMP8481 Only) (1) MIN MAX 4.5 76 UNIT V 4.0 76 V VREFA and VREFB tied together –0.3 to the lesser of (VCC – 1.5) or +6 V Single VREF pin with other VREF pin grounded –0.3 or +12 where the average of the two VREF pins is less than the lesser of (VCC – 1.5) or +6 V Exceeding the Recommended Operating Conditions for extended periods of time may effect device reliability or cause parametric shifts. 7.4 Thermal Information LMP8480, LMP8481 THERMAL METRIC (1) DGK NCQ UNIT 70 °C/W 8 PINS RθJA (1) 4 Junction-to-ambient thermal resistance 185 For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 1999–2015, Texas Instruments Incorporated Product Folder Links: LMP8480 LMP8481 LMP8480, LMP8481 www.ti.com SNVS829C – MARCH 1999 – REVISED SEPTEMBER 2015 7.5 Electrical Characteristics Unless otherwise specified, all limits specified for at TA = 25°C, VCC = 4.5 V to 76 V, 4.5V VCM 76 V, RL = 100 k, VSENSE = (VRSP – VRSN) = 0 V. (1) PARAMETER VOS Input Offset Voltage (RTI) TCVOS Input Offset Voltage Drift (4) Input Bias Current TEST CONDITIONS VCC = VRSP = 48 V, ΔV = 100 mV MIN (2) TA = 25°C TYP (3) MAX (2) ±80 ±265 –40°C ≤ TA ≤ 125°C ±900 ±6 (5) VCC = VRSP = 76 V, Per Input IB Input Leakage Current VSENSE(MA X) 2 -T Version, –40°C ≤ TA ≤ 125°C 667 -F Version, –40°C ≤ TA ≤ 125°C 267 -S Version, –40°C ≤ TA ≤ 125°C 222 -H Version, –40°C ≤ TA ≤ 125°C 133 20 -T Version, –40°C ≤ TA ≤ 125°C 19.8 -S Version Gain 59.5 -H Version 99.2 DC Power Supply Rejection Ratio ±0.6% –40°C ≤ TA ≤ 125°C ±0.8% VRSP = 48 V, VCC = 4.5 to 76 V, –40°C ≤ TA ≤ 125°C 122 V = 48 V, VRSP = 4.5 to 76 V, –40°C ≤ TA DC CMRR DC Common Mode Rejection Ratio CC ≤ 125°C dB 100 VCC = 48 V, VRSP = 4.5 to 76 V 124 dB 100 VCC = 48 V, VRSP = 4 to 76 V 124 CMVR Input Common Mode Voltage Range CMRR > 100 dB, –40°C ≤ TA ≤ 125°C ROUT Output Resistance / Load Regulation VSENSE = 100 mV 0.1 VOMAX Maximum Output Voltage (Headroom) (VOMAX = VCC – VOUT) VCC = 4.5 V, VRSP = 48 V, VSENSE = +1 V, IOUT (sourcing) 500 μA 230 (1) (2) (3) (4) (5) (6) V/V 100.8 TA = 25°C VRSP = 48 V, VCC = 4.5 to 76 V DC PSRR 60.5 100 -H Version, –40°C ≤ TA ≤ 125°C VCC = VRSP = 48 V 20.2 60 -S Version, –40°C ≤ TA ≤ 125°C Gain Error μA mV -T Version AV μA 0.01 VCC = 0, VRSP = 86 V, Both inputs together, –40°C ≤ TA ≤ 125°C VCC = 16 µV°C 12 VCC = 0, VRSP = 86 V, Both inputs together Differential Input Voltage Across Sense Resistor (6) µV 6.3 VCC = VRSP = 76 V, Per Input, –40°C ≤ TA ≤ 125°C ILEAK UNIT 4 dB 76 V 500 mV Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ > TA. All limits are specified by testing, design, or statistical analysis. Typical values represent the most likely parametric norm at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped production material. Offset voltage temperature drift is determined by dividing the change in VOS at the temperature extremes by the total temperature change. Positive Bias Current corresponds to current flowing into the device. This parameter is specified by design and/or characterization and is not tested in production. Copyright © 1999–2015, Texas Instruments Incorporated Product Folder Links: LMP8480 LMP8481 Submit Documentation Feedback 5 LMP8480, LMP8481 SNVS829C – MARCH 1999 – REVISED SEPTEMBER 2015 www.ti.com Electrical Characteristics (continued) Unless otherwise specified, all limits specified for at TA = 25°C, VCC = 4.5 V to 76 V, 4.5V VCM 76 V, RL = 100 k, VSENSE = (VRSP – VRSN) = 0 V.(1) PARAMETER MIN (2) TEST CONDITIONS VCC = VRSP = 48 V, VSENSE = –1 V, IOUT (sinking) = 10 µA TYP (3) Minimum Output Voltage 15 VCC = VRSP = 4.5 V, VSENSE = –1 V, IOUT (sinking) = 10 µA 3 VCC = VRSP = 48 V, VSENSE = –1 V, IOUT (sinking) = 100 µA 18 mV VCC = VRSP = 48 V, VSENSE = –1 V, IOUT (sinking) = 100 µA, –40°C ≤ TA ≤ 125°C 18 12 Output voltage with load VCC = 28 V, VRSP=28 V, VSENSE= 600 mV, I OUT (sourcing) = 500 µA VOLREG Output Load Regulation VCC = 20, VRSP = 16, VOUT = 12, ΔIL = 200 na to 8 mA ICC Supply Current VOUT = 2 V, RL = 10 M, VCC = VRSP = 76 V, –40°C ≤ TA ≤ 125°C BW –3 dB Bandwidth RL = 10 M, CL = 20 pF SR Slew rate (7) VSENSE from 10 mV to 80 mV, RL = 10 M, CL = 20 pF eni Input Referred Voltage Noise f = 1 kHz tSETTLE Output Settling Time to 1% of Final VSENSE = 10 mV to 100 mV and 100 mV to Value 10 mV tPU Power-up Time tRECOVERY CLOAD V 0.001% VOUT = 2 V, RL = 10 M, VCC = VRSP = 76 V 6 55 VCC = VRSP = 4.5 V, VSENSE = –1 V, IOUT (sinking) = 100 µA VOLOAD (7) UNIT 3 VCC = VRSP = 48 V, VSENSE = –1 V, IOUT (sinking) = 10 µA, –40°C ≤ TA ≤ 125°C VOMIN MAX (2) 88 155 µA 270 kHz 1 V/µs 95 nV/√Hz 20 µs VCC = VRSP = 48 V, VSENSE = 100 mV, output to 1% of final value 50 µs Saturation Recovery Time Output settles to 1% of final value, the device will not experience phase reversal when overdriven. 50 µs Max Output Capacitance Load No sustained oscillations 500 pF The number specified is the average of rising and falling slew rates and measured at 90% to 10%. Submit Documentation Feedback Copyright © 1999–2015, Texas Instruments Incorporated Product Folder Links: LMP8480 LMP8481 LMP8480, LMP8481 www.ti.com SNVS829C – MARCH 1999 – REVISED SEPTEMBER 2015 7.6 Typical Characteristics Unless otherwise specified, TA = 25°C, VCC = 4.5 V to 76 V, 4.5 V < VCM < 76 V, RL = 100k, VSENSE = (VRSP – VRSN ) = 0 V, for all gain options. Figure 1. Offset Voltage Histogram Figure 2. Typical Offset Voltage vs Temperature Figure 3. Typical Gain Accuracy vs Temperature Figure 4. Typical Gain Accuracy vs Supply Voltage Figure 5. Typical Offset Voltage vs Supply Voltage Figure 6. AC Common-Mode Rejection Ratio vs Frequency Copyright © 1999–2015, Texas Instruments Incorporated Product Folder Links: LMP8480 LMP8481 Submit Documentation Feedback 7 LMP8480, LMP8481 SNVS829C – MARCH 1999 – REVISED SEPTEMBER 2015 www.ti.com Typical Characteristics (continued) Unless otherwise specified, TA = 25°C, VCC = 4.5 V to 76 V, 4.5 V < VCM < 76 V, RL = 100k, VSENSE = (VRSP – VRSN ) = 0 V, for all gain options. 8 Figure 7. AC Power Supply Rejection Ratio vs Frequency Figure 8. Small Signal Gain vs Frequency Figure 9. Large Signal Pulse Response Figure 10. Small Signal Pulse Response Figure 11. Supply Current vs Supply Voltage Figure 12. Supply Current vs Temperature Submit Documentation Feedback Copyright © 1999–2015, Texas Instruments Incorporated Product Folder Links: LMP8480 LMP8481 LMP8480, LMP8481 www.ti.com SNVS829C – MARCH 1999 – REVISED SEPTEMBER 2015 Typical Characteristics (continued) Unless otherwise specified, TA = 25°C, VCC = 4.5 V to 76 V, 4.5 V < VCM < 76 V, RL = 100k, VSENSE = (VRSP – VRSN ) = 0 V, for all gain options. Figure 13. Saturated Output Sourcing Current at 4.5 V Figure 14. Saturated Output Sinking Current at 4.5 V Figure 15. Saturated Output Sourcing Current at 12 V Figure 16. Saturated Output Current Sinking at 12 V Copyright © 1999–2015, Texas Instruments Incorporated Product Folder Links: LMP8480 LMP8481 Submit Documentation Feedback 9 LMP8480, LMP8481 SNVS829C – MARCH 1999 – REVISED SEPTEMBER 2015 www.ti.com 8 Detailed Description 8.1 Overview The LMP8480 and LMP8481 are single-supply, high-side current sense amplifiers with available fixed gains of x20, x60 and x100. The power supply range is 4.5 V to 76 V, while the common-mode input voltage range is capable of 4.0-V to 76-V operation. The supply voltage and common-mode range are completely independent of each other. This makes the LMP848x supply voltage extremely flexible, as the LMP848x's supply voltage can be greater than, equal to, or less than the load source voltage, and allowing the device to be powered from the system supply or the load supply voltage. The LMP8480 and LMP8481 supply voltage does not have to be larger than the load source voltage. A 76-V load source voltage with a 5-V supply voltage is perfectly acceptable. 8.1.1 Theory of Operation The LMP8480 and LMP8481 are comprised of two main stages. The first stage is a differential input current to voltage converter, followed by a differential voltage amplifier and level-shifting output stage. Also present is an internal 14 Volt Low-Dropout Regulator (LDO) to power the amplifiers and output stage, as well as a reference divider resistor string to allow the setting of the reference level. As seen in Figure 18, the current flowing through RSENSE develops a voltage drop called VSENSE. The voltage across the sense resistor, VSENSE, is then applied to the input RSP and RSN pins of the amplifier. Internally, the voltage on each input pin is converted to a current by the internal precision thin-film input resistors RGP and RGN. A second set of much higher value VCM sense resistors between the inputs provide a sample of the input common-mode voltage for internal use by the differential amplifier. VSENSE is applied to the differential amplifier through RGP and RGN. These resistors change the input voltage to a differential current. The differential amplifier then servos the resistor currents through the MOSFETs to maintain a zero balance across the differential amplifier inputs. With no input signal present, the currents in RGP and RGN are equal. When a signal is applied to VSENSE, the current through RGP and RGN are imbalanced and are no longer equal. The amplifier then servos the MOSFETS to correct this current imbalance, and the extra current required to balance the input currents is then reflected down into the two lower 400-kΩ “tail” resistors. The difference in the currents into the tail resistors is therefore proportional to the amplitude and polarity of VSENSE. The tail resistors, being larger than the input resistors for the same current, then provide voltage gain by changing the current into a proportionally larger voltage. The gain of the first stage is then set by the tail resistor value divided by RG value. The differential amplifier stage then samples the voltage difference across the two 400-kΩ tail resistors and also applies a further gain-of-five and output level-shifting according to the applied reference voltage (VREF). The resulting output of the amplifier will be equal to the differential input voltage times the gain of the device, plus any voltage value applied to the two VREF pins. The resistor values in the schematic are ideal values for clarity and understanding. Table 1 shows the actual values used that account for parallel combinations and loading. This table can be used for calculating the effects of any additional external resistance. The LMP8480 is identical to the LMP8481, except that both the VREF pins are grounded internally. Table 1. Actual Internal Resistor Values Gain Option 10 RGP and RGN (each) RVCMSENSE (each) RTAIL (each) Differential Amp FB (each) VREFx Resistors (each) 20x 98.38 k 491.9 k 393.52 k 1967.6 k 98.38 k 60x 32.793 k 172.165 k 393.52 k 1967.6 k 98.38 k 100x 19.676 k 98.38 k 393.52 k 1967.6 k 98.38 k Submit Documentation Feedback Copyright © 1999–2015, Texas Instruments Incorporated Product Folder Links: LMP8480 LMP8481 LMP8480, LMP8481 www.ti.com SNVS829C – MARCH 1999 – REVISED SEPTEMBER 2015 8.2 Functional Block Diagrams RSN RSP LMP8480 VSENSE VCM SENSE RGP VCC Difference Amplifier (x5) Internal 14V LDO Regulator RGN 2 M: - + + VOUT 100 k: V to I Converter 1.95 M: 100 k: 400 k: 400 k: GND Figure 17. LMP8480 Block Diagram RSN RSP LMP8481 VSENSE RGP VCC Internal 14V LDO Regulator VCM SENSE + Difference Amplifier (x5) RGN 2 M: - + VOUT 100 k: V to I Converter VREFA 1.95 M: 100 k: 400 k: 400 k: VREFB GND Figure 18. LMP8481 Block Diagram Copyright © 1999–2015, Texas Instruments Incorporated Product Folder Links: LMP8480 LMP8481 Submit Documentation Feedback 11 LMP8480, LMP8481 SNVS829C – MARCH 1999 – REVISED SEPTEMBER 2015 www.ti.com 8.3 Feature Description 8.3.1 Basic Connections Figure 19 through Figure 22 show the basic connections for seveal different configurations. +4.0V to +76V ISENSE VCC = +4.5V to +76V To Load RSENSE CBYPASS 0.1PF VCC RSN VSENSE OUTPUT LMP8480 VOUT RSP GND Figure 19. LMP8480 Basic Connections (Unidirectional) Figure 19 shows the basic connections for the LMP8480 for Unidirectional applications. The output will be at zero with zero sense voltage. +4.0V to +76V ISENSE VCC = +4.5V to +76V To Load RSENSE CBYPASS 0.1PF VCC RSN VSENSE OUTPUT LMP8481 VOUT REFA RSP REFB GND VREF INPUT Figure 20. LMP8481 Basic Connections for External 1:1 VREF Input (Bidirectional) Figure 20 shows the basic connections for the LMP8481 for Bidirectional applications using an external reference input. At zero input voltage, the output will be at the applied reference voltage (VREF), moving positive or negative from the zero reference point. +4.0V to +76V ISENSE VCC = +4.5V to +76V To Load RSENSE CBYPASS 0.1PF VCC RSN VSENSE OUTPUT LMP8481 VOUT REFA RSP REFB GND VREF or VCC Figure 21. LMP8481 Basic Connections for Mid-Bias (VREF/2) Input (Bidirectional) 12 Submit Documentation Feedback Copyright © 1999–2015, Texas Instruments Incorporated Product Folder Links: LMP8480 LMP8481 LMP8480, LMP8481 www.ti.com SNVS829C – MARCH 1999 – REVISED SEPTEMBER 2015 Feature Description (continued) Figure 21 shows the basic connections for the LMP8481 for Bidirectional applications centering the output at one-half the applied VREF or VCC voltage. If VREFA is connected to VCC, then the output "zero" point will be VCC/2. If VREFA is connected to the ADC VREF line, then the "zero" output will be at mid-scale for the ADC. ISENSE +4.0V to +76V VCC = +4.5V to +76V To Load RSENSE CBYPASS 0.1PF VCC RSN VSENSE LMP8481 VOUT OUTPUT REFA RSP REFB GND Figure 22. LMP8481 Connections for Unidirectional Configuration (Equivalent to LMP8480 Unidirectional) Figure 22 shows the how to connect the LMP8481 for Bidirectional applications, thus making it equivalent to the LMP8480 in Figure 19. 8.3.2 Selection of the Sense Resistor The accuracy of the current measurement depends heavily on the accuracy of the shunt resistor RSENSE. Its value depends on the application and is a compromise between small-signal accuracy, maximum permissible voltage drop and allowable power dissipation in the current measurement circuit. The use of a “4-terminal” or “Kelvin” sense resistor is highly recommended. See the Layout Guidelines. For best results, the value of the resistor is calculated from the maximum expected load current ILMAX and the expected maximum output swing VOUTMAX, plus a few percent of headroom. See the Maximum Output Voltage section for details about the maximum output voltage limits. High values of RSENSE provide better accuracy at lower currents by minimizing the effects of amplifier offset. Low values of RSENSE minimize load voltage loss, but at the expense of accuracy at low currents. A compromise between low current accuracy and load circuit losses must generally be made. The maximum VSENSE voltage that must be generated across the RSENSE resistor will be: VSENSE = VOUTMAX / AV (1) NOTE The maximum VSENSE voltage should be no more than 667 mV. From this maximum VSENSE voltage, the RSENSE value can be calculated from: RSENSE = VSENSE / ILMAX (2) Take care not exceed the maximum power dissipation of the resistor. The maximum sense resistor power dissipation will be: PRSENSE = VSENSE × ILMAX (3) TI recommends using a 2-3x minimum safety margin in selecting the power rating of the resistor. 8.3.3 Using PCB Traces as Sense Resistors While it may be tempting to use a known length of PCB trace resistance as a sense resistor, it is not recommended. The temperature coefficient of copper is typically 3300-4000 ppm/°K, which can vary over PCB process variations and require measurement correction (possibly requiring ambient temperature measurements). Copyright © 1999–2015, Texas Instruments Incorporated Product Folder Links: LMP8480 LMP8481 Submit Documentation Feedback 13 LMP8480, LMP8481 SNVS829C – MARCH 1999 – REVISED SEPTEMBER 2015 www.ti.com Feature Description (continued) A typical surface mount sense resistor tempco is in the 50 ppm to 500 ppm/°C range offering more measurement consistency and accuracy over the copper trace. Special low-tempco resistors are available in the 0.1 to 50 ppm range, but at a higher cost. 8.3.4 VREFA and VREFB Pins (LMP8481 Only) The voltage applied to the VREFA and VREFB pins controls the output zero reference level. Depending on how the pins are configured, the output reference level can be set to GND, or VCC/2, or external VREF/2, or the average of two different input references. The reference inputs consist of a pair of divider resistors with equal values to a common summing point, VREF' as shown in Figure 23. Assuming VSENSE is zero, the output will be at the same value as VREF'. Figure 23. VREF Input Resistor Network VREF' is the voltage at the resistor tap-point that will be directly applied to the output as an offset. With the two VREF inputs tied together, the output zero voltage will have a 1:1 ratio relationship with VREF. VOUT = ( (VRSP – VRSN) ×Av ) + VREF’ (4) Where: VREF’ = VREFA = VREFB (Equal Inputs) (5) VREF’ = ( VREFA + VREFB ) / 2 (Different Inputs) (6) or: 8.3.4.1 One-to-One (1:1) Reference Input To directly set the reference level, the two inputs are connected to the external reference voltage. The applied VREF will be reflected 1:1 on the output. Figure 24. Applying 1:1 Direct Reference Voltage 14 Submit Documentation Feedback Copyright © 1999–2015, Texas Instruments Incorporated Product Folder Links: LMP8480 LMP8481 LMP8480, LMP8481 www.ti.com SNVS829C – MARCH 1999 – REVISED SEPTEMBER 2015 Feature Description (continued) 8.3.4.2 Setting Output to One-Half VCC or external VREF For mid-range operation VREFB should be tied to ground and VREFA can be tied to VCC or an external A/D reference voltage. The output will be set to one-half the reference voltage. For example, a 5-V reference would result in a 2.5-V output “zero” reference. Figure 25. Applying a Divided Reference Voltage VREF’ = (VREFA – VREFB) / 2 (7) When the reference pins are biased at different voltages, the output will be referenced to the average of the two applied voltages. The reference pins should always be driven from clean, stable sources, such as A/D reference lines or clean supply lines. Any noise or drifts on the reference inputs are directly reflected in the output. Take care if the power supply is used as the reference source so as to not introduce supply noise, drift or sags into the measurement. It is possible to set different resistor divider ratios by adding external resistors in series with the internal 100-K resistors, though the temperature coefficient (tempco) of the external resistors may not tightly track the internal resistors and there will be slight errors over temperature. The LMP8480 is identical to the LMP8481, except that both the VREF pins are grounded internally. The LMP8481 can replace the LMP8480 if both VREF pins are grounded. 8.3.5 Reference Input Voltage Limits (LMP8481 Only) The maximum voltage on either reference input pin is limited to VCC or 12 V, whichever is less. The average voltage on the two VREF pins, and thus the actual output reference voltage level, is limited to a maximum of 1.5 V below VCC, or 6 V, whichever is less. Beware that supply voltages of less than 7.5 V will have a diminishing VREF maximum. Both VREFA and VREFB may both be grounded to provide a ground referenced output (thus functionally duplicating the LMP8480). It should be noted that there can be a dynamic error in the VREF to output level matching of up to 100 µV/V. Normally this is not an issue for fixed references, but if the reference voltage is dynamically adjusted during operation, this error needs to be taken into account during calibration routines. This error will vary in both amplitude and polarity part-to-part, but the slope will generally be linear. 8.3.6 Low-Side Current Sensing The LMP8480 and LMP8481 are not recommended for low-side current sensing at ground level. The voltage on either input pin must be a minimum of 4.0 V above the ground pin for proper operation. The output level may not be valid for common-mode voltages below 4 V. This should be taken into consideration for monitoring or feedback applications where the load-supply voltage may dip below 4 V or be switched completely off. Copyright © 1999–2015, Texas Instruments Incorporated Product Folder Links: LMP8480 LMP8481 Submit Documentation Feedback 15 LMP8480, LMP8481 SNVS829C – MARCH 1999 – REVISED SEPTEMBER 2015 www.ti.com Feature Description (continued) 8.3.7 Input Series Resistance Because the input stage uses precision resistors to convert the voltage on the input pin to a current, any resistance added in series with the input pins will change the gain. If a resistance is added in series with an input, the gain of that input will not track that of the other input, causing a constant gain error. TI does not recommend using external resistances to alter the gain, as external resistors will not have the same thermal matching as the internal thin film resistors. If resistors are purposely added for filtering, resistance should be added equally to both inputs and the user should be aware that the gain will change slightly. See the end of the Theory of Operation section for the internal resistor values. External resistances should be kept below 10 ohms. 8.3.8 Minimum Output Voltage The amplifier output cannot swing to exactly 0 V. There will always be a minimum output voltage set by the output transistor saturation and input offset errors. This will create a minimum output swing around the zero current reading due to the output saturation. The user should be aware of this when designing any servo loops or data acquisition systems that may assume 0 V = 0 A. If a true zero is required, the LMP8481 should be used with a VREF set slightly above ground (> 50 mV). See the Swinging Output Below Ground section for a possible solution to this issue. 8.3.9 Swinging Output Below Ground If a negative supply is available, a pulldown resistor can be added from the output to the negative voltage to allow the output to swing a few millivolts below ground. This will now allow the ADC to resolve true zero and recover codes that would normally be lost to the negative output saturation limit. Figure 26. Output Pulldown Resistor Example A minimum of 50 µA should be sourced (“pulled”) from the output to a negative voltage. The pulldown resistor can be calculated from: RPD = –VS/50 µA (8) For example, if a –5-V supply is available, a pulldown resistor of 5 V/50 µA = 100 kΩ should be used. This will allow the output to swing to about 10 mV below ground. This technique may also reduce the maximum positive swing voltage. Do not forget to include the parallel loading effects of the pulldown any output load. TI recommends not to exceed –100 mV on the output. Source currents greater than 100 µA should be avoided to prevent self-heating at high-supply voltages. Pulldown resistor values should not be so low as to heavily load the output during positive output excursions. This mode of operation is not directly specified and is not ensured. 16 Submit Documentation Feedback Copyright © 1999–2015, Texas Instruments Incorporated Product Folder Links: LMP8480 LMP8481 LMP8480, LMP8481 www.ti.com SNVS829C – MARCH 1999 – REVISED SEPTEMBER 2015 Feature Description (continued) 8.3.10 Maximum Output Voltage The LMP8481 has an internal precision 14-V low-dropout regulator which limits the maximum amplifier output swing to about 250 mV below VCC or 13.7 V (whichever is less). This effectively clamps the maximum output to slightly less than 13.7 V even with a VCC greater than 14 V. See Typical Application With Resistive Divider for more information. 8.4 Device Functional Modes 8.4.1 Unidirectional vs Bidirectional Operation Unidirectional operation is where the load current only flows in one direction (VSENSE is always positive). Application examples would be PA monitoring, non-inductive load monitoring and laser or LED drivers. This allows the output zero reference to be true zero volts on the output. The LMP8480 is designed for unidirectional applications where the setting of VREF is not required. See the Unidirectional Application With LMP8480 for more details. Bidirectional operation is where the load current can flow in both directions (VSENSE can be positive or negative). Application examples would be battery-charging or regenerative motor monitoring. The LMP8481 is designed for bidirectional applications and has a pair of VREF pins to allow the setting of the output zero reference level (VREF). See the Unidirectional Application With LMP8480 section for more details. Copyright © 1999–2015, Texas Instruments Incorporated Product Folder Links: LMP8480 LMP8481 Submit Documentation Feedback 17 LMP8480, LMP8481 SNVS829C – MARCH 1999 – REVISED SEPTEMBER 2015 www.ti.com 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information The LMP848x amplifies the voltage developed across a current-sensing resistor when current passes through it. Flexible offset inputs allow adjusting the functionality of the output for multiple configurations, as discussed throughout this section. 9.1.1 Input Common-Mode and Differential Voltage Range The input common-mode range, where “common-mode range” is defined as the voltage from ground to the voltage on RSP input, should be in the range of 4.0 V to 76 V. Operation below 4.0 V on either input pin will introduce severe gain error and nonlinearities. The maximum differential voltage (defined as the voltage difference between RSP and RSN) should be 667 mV or less. The theoretical maximum input is 700 mV (14 V / 20). Taking the inputs below 4 V will not damage the device, but the output conditions during this time are not predictable and are not ensured. If the load voltage (Vcm) is expected to fall below 4 V as part of normal operation, preparations must be made for invalid output levels during this time. 9.2 Typical Applications 9.2.1 Unidirectional Application With LMP8480 Figure 27. Unidirectional Application with LMP8480 9.2.1.1 Design Requirements The LMP8480 is designed for unidirectional current sense applications. The output of the amplifier will be equal to the differential input voltage times the fixed device gain. 9.2.1.2 Detailed Design Procedure The output voltage can be calculated from: VOUT = ( (VRSP – VRSN) × Av ) 18 Submit Documentation Feedback (9) Copyright © 1999–2015, Texas Instruments Incorporated Product Folder Links: LMP8480 LMP8481 LMP8480, LMP8481 www.ti.com SNVS829C – MARCH 1999 – REVISED SEPTEMBER 2015 Typical Applications (continued) It should be noted that the minimum “zero” reading will be limited by the lower output swing and input offset. The LMP8480 is functionally identical to the LMP8481, but with the VREFA and VREFB nodes grounded internally. The LMP8481 can replace the LMP8480 if both the VREF inputs (pins 6 and 7) are grounded. 9.2.1.3 Application Curve Figure 28. Unidirectional Transfer Function for Gain-of-20 Option 9.2.2 Bidirectional Current Sensing Using LMP8481 Figure 29. Bidirectional Current Sensing Using LMP8481 9.2.2.1 Design Requirements Bidirectional operation is required where the measured load current can be positive or negative. Because VSENSE can be positive or negative, and the output cannot swing negative, the “zero” output level must be level-shifted above ground to a known zero reference point. The LMP8481 allows for the setting this reference point. 9.2.2.2 Detailed Design Procedure The VREFA and VREFB pins set the zero reference point. The output “zero” reference point is set by applying a voltage to the REFA and/or REFB pins. See the Unidirectional Application With LMP8480 section. VREFA and VREFB Pins (LMP8481 Only) shows the output transfer function with a 1.2-V reference applied to the Gain-of-20 option. Copyright © 1999–2015, Texas Instruments Incorporated Product Folder Links: LMP8480 LMP8481 Submit Documentation Feedback 19 LMP8480, LMP8481 SNVS829C – MARCH 1999 – REVISED SEPTEMBER 2015 www.ti.com Typical Applications (continued) 9.2.2.3 Application Curve Figure 30. Bidirectional Transfer Function Using 1.2-V Reference Voltage 9.2.3 Typical Application With Resistive Divider Take care if the output is driving an A/D input with a maximum A/D maximum input voltage lower than the amplifier supply voltage, as the output can swing higher than the planned load maximum due to input transients or shorts on the load and overload or possibly damage the A/D input. A resistive attenuator, as shown in Figure 31, can be used to match the maximum swing to the input range of the A/D. Figure 31. Typical Application With Resistive Divider Example 20 Submit Documentation Feedback Copyright © 1999–2015, Texas Instruments Incorporated Product Folder Links: LMP8480 LMP8481 LMP8480, LMP8481 www.ti.com SNVS829C – MARCH 1999 – REVISED SEPTEMBER 2015 10 Power Supply Recommendations 10.1 Power Supply Decoupling In order to decouple the LMP848x from AC noise on the power supply, TI recommends using a 0.1-μF bypass capacitor between the VCC and GND pins. This capacitor should be placed as close as possible to the supply pins. In some cases, an additional 10-μF bypass capacitor may further reduce the supply noise. Do not forget that these bypass capacitors must be rated for the full supply and / or load source voltage. TI recommends that the working voltage of the capacitor (WVDC) should be at least two times the maximum expected circuit voltage. 11 Layout 11.1 Layout Guidelines The traces leading to and from the sense resistor can be significant error sources. With small value sense resistors (< 100 mΩ), any trace resistance shared with the load current can cause significant errors. The amplifier inputs should be directly connected to the sense resistor pads using “Kelvin” or “4-wire” connection techniques. The traces should be one continuous piece of copper from the sense resistor pad to the amplifier input pin pad, and ideally on the same copper layer with minimal vias or connectors. This can be important around the sense resistor if it is generating any significant heat gradients. To minimize noise pickup and thermal errors, the input traces should be treated as a differential signal pair and routed tightly together with a direct path to the input pins. The input traces should be run away from noise sources, such as digital lines, switching supplies or motor drive lines. Remember that these traces can contain high voltage, and should have the appropriate trace routing clearances. Since the sense traces only carry the amplifier bias current (about 7 µA at room temperature), the connecting input traces can be thinner, signal level traces. Excessive Resistance in the trace should also be avoided. The paths of the traces should be identical, including connectors and vias, so that these errors will be equal and cancel. The sense resistor will heat up as the load increases. As the resistor heats up, the resistance generally goes up, which will cause a change in the readings The sense resistor should have as much heatsinking as possible to remove this heat through the use of heatsinks or large copper areas coupled to the resistor pads. A reading drifting over time after turn-on can usually be traced back to sense resistor heating. 11.2 Layout Example Figure 32. “Kelvin” or “4–wire” Connection to the Sense Resistor Copyright © 1999–2015, Texas Instruments Incorporated Product Folder Links: LMP8480 LMP8481 Submit Documentation Feedback 21 LMP8480, LMP8481 SNVS829C – MARCH 1999 – REVISED SEPTEMBER 2015 www.ti.com 12 Device and Documentation Support 12.1 Device Support 12.1.1 Development Support LMP8480/1 PSPICE Model, SNVM046 LMP8480/1 TINA Reference Design, SNVM048 TINA-TI SPICE-Based Analog Simulation Program, http://www.ti.com/tool/tina-ti LMP8480/1 Evaluation Boards, product pages LMP8480/1 Evaluation Board Manual, SNOU031 12.2 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 2. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY LMP8480 Click here Click here Click here Click here Click here LMP8481 Click here Click here Click here Click here Click here 12.3 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 12.4 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 12.5 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 12.6 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 22 Submit Documentation Feedback Copyright © 1999–2015, Texas Instruments Incorporated Product Folder Links: LMP8480 LMP8481 PACKAGE OPTION ADDENDUM www.ti.com 23-Sep-2015 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) LMP8480MM-T/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 AV8A LMP8480MME-S/NOPB ACTIVE VSSOP DGK 8 250 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 AY8A LMP8480MME-T/NOPB ACTIVE VSSOP DGK 8 250 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 AV8A LMP8480MMX-S/NOPB ACTIVE VSSOP DGK 8 3500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 AY8A LMP8480MMX-T/NOPB ACTIVE VSSOP DGK 8 3500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 AV8A LMP8481MM-H/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 AH9A LMP8481MM-S/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 AA9A LMP8481MM-T/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 AT9A LMP8481MME-H/NOPB ACTIVE VSSOP DGK 8 250 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 AH9A LMP8481MME-S/NOPB ACTIVE VSSOP DGK 8 250 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 AA9A LMP8481MME-T/NOPB ACTIVE VSSOP DGK 8 250 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 AT9A LMP8481MMX-H/NOPB ACTIVE VSSOP DGK 8 3500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 AH9A LMP8481MMX-S/NOPB ACTIVE VSSOP DGK 8 3500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 AA9A LMP8481MMX-T/NOPB ACTIVE VSSOP DGK 8 3500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 AT9A (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 23-Sep-2015 (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2015 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LMP8480MM-T/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LMP8480MME-S/NOPB VSSOP DGK 8 250 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LMP8480MME-T/NOPB VSSOP DGK 8 250 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LMP8480MMX-S/NOPB VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LMP8480MMX-T/NOPB VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LMP8481MM-H/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LMP8481MM-S/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LMP8481MM-T/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LMP8481MME-H/NOPB VSSOP DGK 8 250 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LMP8481MME-S/NOPB VSSOP DGK 8 250 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LMP8481MME-T/NOPB VSSOP DGK 8 250 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LMP8481MMX-H/NOPB VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LMP8481MMX-S/NOPB VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LMP8481MMX-T/NOPB VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2015 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMP8480MM-T/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 LMP8480MME-S/NOPB VSSOP DGK 8 250 210.0 185.0 35.0 LMP8480MME-T/NOPB VSSOP DGK 8 250 210.0 185.0 35.0 LMP8480MMX-S/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0 LMP8480MMX-T/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0 LMP8481MM-H/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 LMP8481MM-S/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 LMP8481MM-T/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 LMP8481MME-H/NOPB VSSOP DGK 8 250 210.0 185.0 35.0 LMP8481MME-S/NOPB VSSOP DGK 8 250 210.0 185.0 35.0 LMP8481MME-T/NOPB VSSOP DGK 8 250 210.0 185.0 35.0 LMP8481MMX-H/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0 LMP8481MMX-S/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0 LMP8481MMX-T/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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