TI1 AMC1303E0510 Small, high-precision, reinforced isolated delta-sigma modulators with internal clock Datasheet

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AMC1303E0510, AMC1303M0510, AMC1303E0520, AMC1303M0520
AMC1303E2510, AMC1303M2510, AMC1303E2520, AMC1303M2520
SBAS771 – JUNE 2017
AMC1303x Small, High-Precision,
Reinforced Isolated Delta-Sigma Modulators with Internal Clock
1 Features
3 Description
•
The AMC1303 (AMC1303x0510, AMC1303x0520,
AMC1303x2510, and AMC1303x2520) is a family of
precision, delta-sigma (ΔΣ) modulators with the
output separated from the input circuitry by a
capacitive double isolation barrier that is highly
resistant to magnetic interference. This barrier is
certified to provide reinforced isolation of up to 7000
VPK according to the DIN V VDE V 0884-11 and
UL1577 standards. Used in conjunction with isolated
power supplies, this isolated modulator separates
parts of the system that operate on different commonmode voltage levels and protects lower-voltage parts
from damage.
1
•
•
•
•
•
Pin-Compatible Family Optimized for ShuntResistor-Based Current Measurements:
– ±50-mV or ±250-mV Input Voltage Ranges
– Manchester Coded or Uncoded Bistream
Options
– 10-MHz and 20-MHz Clock Options
Excellent DC Performance:
– Offset Error: ±100 µV (max)
– Offset Drift: ±1 µV/°C (max)
– Gain Error: ±0.2% (max)
– Gain Drift: ±40 ppm/°C (max)
Transient Immunity: 100 kV/µs (typ)
System-Level Diagnostic Features
Safety-Related Certifications:
– 7000-VPK Reinforced Isolation per DIN V VDE
V 0884-11 (VDE V 0884-11): 2017-01
– 5000-VRMS Isolation for 1 Minute per UL1577
– CAN/CSA No. 5A-Component Acceptance
Service Notice, IEC 60950-1, and IEC 60065
End Equipment Standards
Fully Specified Over the Extended Industrial
Temperature Range: –40°C to +125°C
2 Applications
•
Shunt-Resistor-Based Current Sensing and
Isolated Voltage Measurement in:
– Industrial Motor Drives
– Photovoltaic Inverters
– Uninterruptible and Isolated Power Supplies
– Power Factor Correction Circuits
The input of the AMC1303 is optimized for direct
connection to shunt resistors or other low voltagelevel signal sources. The ±50-mV input voltage range
option allows significant reduction of the power
dissipation through the shunt. The output bit-stream
of the AMC1303 is synchronized to the internally
generated clock and is Manchester coded
(AMC1303Ex) or uncoded (AMC1303Mx). By using
an integrated digital filter (such as those in the
TMS320F2807x or TMS320F2837x microcontroller
families) to decimate the bitstream, the device can
achieve 16 bits of resolution with a dynamic range of
85 dB at an effective output data rate of 78 kSPS.
The bitstream output of the Manchester coded
AMC1303Ex versions supports single-wire data and
clock transfer without having to consider the setup
and hold time requirements of the receiving device.
Device Information
PART NUMBER
AMC1303x
PACKAGE
SOIC (8)
(1)
BODY SIZE (NOM)
5.85 mm × 7.50 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Simplified Schematic
Floating
Power Supply
HV+
AMC1303Mx
DVDD
AVDD
AGND
RSHUNT
AINN
AINP
Reinforced Isolation
3.3 V or 5.0 V
DGND
3.0 V, 3.3 V, or 5.0 V
TMS320F28x7x
DOUT
SD-Dx
CLKOUT
SD-Cx
Note: no CLKOUT connection using AMC1303Ex,
pin 7 to be connected to DGND in this case
HV-
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
AMC1303E0510, AMC1303M0510, AMC1303E0520, AMC1303M0520
AMC1303E2510, AMC1303M2510, AMC1303E2520, AMC1303M2520
SBAS771 – JUNE 2017
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configurations and Functions .......................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
7.12
8
8.2 Functional Block Diagram ....................................... 17
8.3 Feature Description................................................. 18
8.4 Device Functional Modes........................................ 22
1
1
1
2
3
3
4
9
Application and Implementation ........................ 23
9.1 Application Information............................................ 23
9.2 Typical Applications ................................................ 24
10 Power Supply Recommendations ..................... 29
11 Layout................................................................... 30
Absolute Maximum Ratings ...................................... 4
ESD Ratings.............................................................. 4
Recommended Operating Conditions....................... 4
Thermal Information .................................................. 4
Power Ratings........................................................... 4
Insulation Specifications............................................ 5
Safety-Related Certifications..................................... 6
Safety Limiting Values .............................................. 6
Electrical Characteristics: AMC1303x25x ................. 7
Switching Characteristics ........................................ 9
Insulation Characteristics Curves ........................ 10
Typical Characteristics .......................................... 11
11.1 Layout Guidelines ................................................. 30
11.2 Layout Example .................................................... 30
12 Device and Documentation Support ................. 31
12.1
12.2
12.3
12.4
12.5
12.6
12.7
12.8
Device Support......................................................
Documentation Support ........................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
31
31
31
31
31
32
32
32
13 Mechanical, Packaging, and Orderable
Information ........................................................... 32
Detailed Description ............................................ 17
8.1 Overview ................................................................. 17
4 Revision History
2
DATE
REVISION
NOTES
June 2017
*
Initial release.
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5 Device Comparison Table
PART NUMBER
INPUT VOLTAGE RANGE
DIFFERENTIAL INPUT
RESISTANCE
DIGITAL OUTPUT
INTERFACE
AMC1303E0510
±50 mV
4.9 kΩ
Manchester coded CMOS
AMC1303E2510
±250 mV
22 kΩ
Manchester coded CMOS
AMC1303M0510
±50 mV
4.9 kΩ
Uncoded CMOS
AMC1303M2510
±250 mV
22 kΩ
Uncoded CMOS
AMC1303E0520
±50 mV
4.9 kΩ
Manchester coded CMOS
AMC1303E2520
±250 mV
22 kΩ
Manchester coded CMOS
AMC1303M0520
±50 mV
4.9 kΩ
Uncoded CMOS
AMC1303M2520
±250 mV
22 kΩ
Uncoded CMOS
INTERNAL CLOCK
FREQUENCY
10 MHz
20 MHz
6 Pin Configurations and Functions
AMC1303Mx: DWV Package
8-Pin SOIC
Top View
AMC1303Ex: DWV Package
8-Pin SOIC
Top View
AVDD
1
8
DVDD
AINP
2
7
AINN
3
AGND
4
AVDD
1
8
DVDD
CLKOUT
AINP
2
7
DGND
6
DOUT
AINN
3
6
DOUT
5
DGND
AGND
4
5
DGND
Pin Functions
NAME
AMC1303Mx
AMC1303Ex
I/O
AGND
4
4
—
AINN
3
3
I
Inverting analog input
AINP
2
2
I
Noninverting analog input
AVDD
1
1
—
Analog (high-side) power supply, 3.0 V to 5.5 V.
See the Power Supply Recommendations section for decoupling recommendations.
CLKOUT
7
—
O
Modulator clock output, 10 MHz (on AMC1303Mxx10) or 20 MHz (on AMC1303Mxx20)
nominal
DGND
5
5
—
Digital (controller-side) ground reference
DGND
—
7
—
Connect this pin to the controller-side ground for AMC1303Ex derivates
DOUT
6
6
O
Modulator bitstream output. This pin is a Manchester coded output for the AMC1303Ex
derivates.
DVDD
8
8
—
Digital (controller-side) power supply, 2.7 V to 5.5 V.
See the Power Supply Recommendations section for decoupling recommendations.
Copyright © 2017, Texas Instruments Incorporated
DESCRIPTION
Analog (high-side) ground reference
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7 Specifications
7.1 Absolute Maximum Ratings (1)
Supply voltage, AVDD to AGND or DVDD to DGND
Analog input voltage at AINP, AINN
Digital output voltage at DOUT, CLKOUT
Input current to any pin except supply pins
MIN
MAX
UNIT
–0.3
6.5
V
AGND – 6
AVDD + 0.5
V
DGND – 0.5
DVDD + 0.5
V
–10
Junction temperature, TJ
Storage temperature, Tstg
(1)
–65
10
mA
150
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating ambient temperature range (unless otherwise noted)
MIN
NOM
MAX
AVDD
Analog (high-side) supply voltage (AVDD to AGND)
3.0
5.0
5.5
UNIT
V
DVDD
Digital (controller-side) supply voltage (DVDD to DGND)
2.7
3.3
5.5
V
TA
Operating ambient temperature
–40
125
°C
7.4 Thermal Information
AMC1303x
THERMAL METRIC (1)
DWV (SOIC)
UNIT
8 PINS
RθJA
112.2
°C/W
RθJC(top) Junction-to-case (top) thermal resistance
47.6
°C/W
RθJB
Junction-to-board thermal resistance
60.0
°C/W
ψJT
Junction-to-top characterization parameter
23.1
°C/W
ψJB
Junction-to-board characterization parameter
60.0
°C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance
N/A
°C/W
(1)
Junction-to-ambient thermal resistance
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Power Ratings
PARAMETER
PD
Maximum power dissipation
(both sides)
PD1
Maximum power dissipation
(high-side supply)
PD2
Maximum power dissipation
(low-side supply)
4
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TEST CONDITIONS
MIN
TYP
MAX
AMC1303Exxx20, AVDD = DVDD = 5.5 V
89.65
AMC1303Mxxx20, AVDD = DVDD = 5.5 V
93.50
AMC1303xxx20, AVDD = 5.5 V
53.90
AMC1303Exxx20, DVDD = 5.5 V
35.75
AMC1303Mxxx20, DVDD = 5.5 V
39.60
UNIT
mW
mW
mW
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7.6 Insulation Specifications
over operating ambient temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VALUE
UNIT
GENERAL
CLR
External clearance (1)
Shortest pin-to-pin distance through air
≥9
mm
CPG
External creepage (1)
Shortest pin-to-pin distance across the package surface
≥9
mm
DTI
Distance through insulation
Minimum internal gap (internal clearance) of the double insulation
(2 × 0.0105 mm)
≥ 0.021
mm
CTI
Comparative tracking index
DIN EN 60112 (VDE 0303-11); IEC 60112
≥ 600
V
Material group
According to IEC 60664-1
Overvoltage category
per IEC 60664-1
I
Rated mains voltage ≤ 300 VRMS
I-IV
Rated mains voltage ≤ 600 VRMS
I-IV
Rated mains voltage ≤ 1000 VRMS
I-III
DIN V VDE V 0884-11 (VDE V 0884-11): 2017-01 (2)
VIORM
Maximum repetitive peak
isolation voltage
VIOWM
At ac voltage (bipolar)
2121
VPK
Maximum-rated isolation
working voltage
At ac voltage (sine wave)
1500
VRMS
At dc voltage
2121
VDC
VIOTM
Maximum transient isolation
voltage
VTEST = VIOTM, t = 60 s (qualification test)
7000
VTEST = 1.2 × VIOTM, t = 1 s (100% production test)
8400
VIOSM
Maximum surge isolation
voltage (3)
Test method per IEC 60065, 1.2-μs, 50-μs waveform,
VTEST = 1.6 × VIOSM = 12800 VPK (qualification)
8000
Apparent charge (4)
qpd
Barrier capacitance,
input to output (5)
CIO
Insulation resistance,
input to output (5)
RIO
Method a, after input/output safety test subgroup 2 / 3,
Vini = VIOTM, tini = 60 s, Vpd(m) = 1.2 × VIORM = 2545 VPK, tm = 10 s
≤5
Method a, after environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s, Vpd(m) = 1.6 × VIORM = 3394 VPK, tm = 10 s
≤5
Method b1, at routine test (100% production) and type test,
Vini = VIOTM, tini = 1 s, Vpd(m) = 1.875 × VIORM = 3977 VPK, tm = 1 s
≤5
VIO = 0.5 VPP at 1 MHz
~1
VPK
VPK
pC
pF
VIO = 500 V at TA = 25°C
12
> 10
Ω
VIO = 500 V at 100°C ≤ TA ≤ 125°C
> 1011
Ω
9
Ω
VIO = 500 V at TS = 150°C
> 10
Pollution degree
2
Climatic category
40/125/21
UL1577
VISO
(1)
(2)
(3)
(4)
(5)
Withstand isolation voltage
VTEST = VISO = 5000 VRMS or 7000 VDC, t = 60 s (qualification),
VTEST = 1.2 × VISO = 6000 VRMS, t = 1 s (100% production test)
5000
VRMS
Apply creepage and clearance requirements according to the specific equipment isolation standards of an application. Care must be
taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed
circuit board (PCB) do not reduce this distance. Creepage and clearance on a PCB become equal in certain cases. Techniques such as
inserting grooves and ribs on the PCB are used to help increase these specifications.
This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by
means of suitable protective circuits.
Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
Apparent charge is electrical discharge caused by a partial discharge (pd).
All pins on each side of the barrier are tied together, creating a two-pin device.
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7.7 Safety-Related Certifications
VDE
UL
Certified according to DIN V VDE V 0884-11 (VDE V 0884-11):
2017-01, DIN EN 60950-1 (VDE 0805 Teil 1): 2014-08, and
DIN EN 60065 (VDE 0860): 2005-11
Recognized under 1577 component recognition and
CSA component acceptance NO 5 programs
Reinforced insulation
Single protection
Certificate number: 40040142
File number: E181974
7.8 Safety Limiting Values
Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output (I/O) circuitry.
A failure of the I/O may allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to
overheat the die and damage the isolation barrier, potentially leading to secondary system failures.
PARAMETER
IS
Safety input, output, or supply current,
see Figure 3
PS
Safety input, output, or total power,
see Figure 4
TS
Maximum safety temperature
(1)
TEST CONDITIONS
MIN
TYP
MAX
θJA = 112.2°C/W, VDD1 = VDD2 = 5.5 V,
TJ = 150°C, TA = 25°C
202.5
θJA = 112.2°C/W, VDD1 = VDD2 = 3.6 V,
TJ = 150°C, TA = 25°C
309.4
θJA = 112.2°C/W, TJ = 150°C, TA = 25°C
1114 (1)
UNIT
mA
150
mW
°C
Input, output, or the sum of input and output power must not exceed this value.
The maximum safety temperature is the maximum junction temperature specified for the device. The power
dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines
the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Information table is that
of a device installed on a high-K test board for leaded surface-mount packages. The power is the recommended
maximum input voltage times the current. The junction temperature is then the ambient temperature plus the
power times the junction-to-air thermal resistance.
6
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7.9 Electrical Characteristics: AMC1303x25x
minimum and maximum specifications apply from TA = –40°C to +125°C, AVDD = 3.0 V to 5.5 V, DVDD = 2.7 V to 5.5 V,
AINP = –250 mV to 250 mV, AINN = AGND, and sinc3 filter with OSR = 256 (unless otherwise noted); typical specifications
are at TA = 25°C, AVDD = 5 V, and DVDD = 3.3 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG INPUTS
VClipping
Differential input voltage before clipping
output
VIN = AINP – AINN
FSR
Specified linear differential full-scale
VIN = AINP – AINN
–250
250
Absolute common-mode input voltage (1)
(AINP + AINN) / 2 to AGND
–2
AVDD
V
VCM
Operating common-mode input voltage
(AINP + AINN) / 2 to AGND
–0.16
AVDD – 2.1
V
VCMov
Common-mode overvoltage detection level
(AINP + AINN) / 2 to AGND
AVDD – 2
±320
Hysteresis of common-mode overvoltage
detection level
CIN
Single-ended input capacitance
CIND
Differential input capacitance
RIN
Single-ended input resistance
RIND
Differential input resistance
IIB
Input bias current
IIO
Input offset current
CMTI
Common-mode transient immunity
CMRR
PSRR
Common-mode rejection ratio
Power-supply rejection ratio
Input bandwidth (2)
BW
AINN = AGND
AINN = AGND
mV
V
90
mV
2
pF
1
pF
19
kΩ
22
AINP = AINN = AGND, IIB = IIBP + IIBN
–82
50
mV
–60
kΩ
–48
µA
±5
nA
100
kV/µs
AINP = AINN, fIN = 0 Hz,
VCM min ≤ VIN ≤ VCM max
–98
AINP = AINN, fIN from 0.1 Hz to 50 kHz,
VCM min ≤ VIN ≤ VCM max
–98
AINP = AINN = AGND, 3.0 V ≤ AVDD ≤ 5.5 V,
at dc
–97
AINP = AINN = AGND, 3.0 V ≤ AVDD ≤ 5.5 V,
10-kHz, 100-mV ripple
–94.5
dB
dB
AMC1303x2510
510
AMC1303x2520
900
kHz
DC ACCURACY
DNL
Differential nonlinearity
Resolution: 16 bits
–0.99
0.99
LSB
INL
Integral nonlinearity (3)
Resolution: 16 bits
–4
±1
4
LSB
EO
Offset error
Initial, at TA = 25°C, AINP = AINN = AGND
–100
±4.5
100
TCEO
Offset error thermal drift (4)
–1
±0.15
1
EG
Gain error
–0.2%
–0.005%
0.2%
TCEG
Gain error thermal drift (5)
–40
±20
40
Initial, at TA = 25°C
µV
μV/°C
ppm/°C
AC ACCURACY
SNR
Signal-to-noise ratio
THD
Total harmonic distortion
SFDR
Spurious-free dynamic range
(1)
(2)
(3)
(4)
(5)
AMC1303x2510, fIN = 35 Hz
85
87
AMC1303x2520, fIN = 35 Hz
84.5
86.5
dB
AMC1303x2510, fIN = 35 Hz
–97
–86
AMC1303x2520, fIN = 35 Hz
–101
–86
fIN = 35 Hz
98
dB
dB
Steady-state voltage supported by the device in case of a system failure. See the specified common-mode input voltage VCM for normal
operation. Observe analog input voltage range as specified in the Absolute Maximum Ratings table.
This parameter is the –3-dB, second-order, roll-off frequency of the integrated differential input amplifier to consider for antialiasing filter
designs.
Integral nonlinearity is defined as the maximum deviation from a straight line passing through the end-points of the ideal ADC transfer
function expressed as number of LSBs or as a percent of the specified linear full-scale range FSR.
value MAX value MIN
TempRange
.
§ value MAX value MIN
TCE G ( ppm ) ¨¨
© value u TempRange
Gain error drift is calculated using the box method as described by the following equation:
Offset error drift is calculated using the box method as described by the following equation:
Copyright © 2017, Texas Instruments Incorporated
TCE O
·
¸¸ u 10 6
¹
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Electrical Characteristics: AMC1303x25x (continued)
minimum and maximum specifications apply from TA = –40°C to +125°C, AVDD = 3.0 V to 5.5 V, DVDD = 2.7 V to 5.5 V,
AINP = –250 mV to 250 mV, AINN = AGND, and sinc3 filter with OSR = 256 (unless otherwise noted); typical specifications
are at TA = 25°C, AVDD = 5 V, and DVDD = 3.3 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DIGITAL OUTPUTS (CMOS LOGIC)
CLOAD
Output load capacitance
VOH
High-level output voltage
VOL
Low-level output voltage
30
IOH = –20 µA
DVDD – 0.1
IOH = –4 mA
DVDD – 0.4
pF
V
IOL = 20 µA
0.1
IOL = 4 mA
0.4
V
POWER SUPPLY
IAVDD
IDVDD
8
High-side supply current
Controller-side supply current
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AMC1303x2510, 3.0 V ≤ AVDD ≤ 3.6 V
5.4
7.3
AMC1303x2510, 4.5 V ≤ AVDD ≤ 5.5 V
6.0
8.0
AMC1303x2520, 3.0 V ≤ AVDD ≤ 3.6 V
6.3
8.5
AMC1303x2520, 4.5 V ≤ AVDD ≤ 5.5 V
7.2
9.8
AMC1303E2510, 2.7 V ≤ DVDD ≤ 3.6 V,
CLOAD = 15 pF
3.3
4.5
AMC1303E2510, 4.5 V ≤ DVDD ≤ 5.5 V,
CLOAD = 15 pF
3.6
5.0
AMC1303M2510, 2.7 V ≤ DVDD ≤ 3.6 V,
CLOAD = 15 pF
3.5
4.7
AMC1303M2510, 4.5 V ≤ DVDD ≤ 5.5 V,
CLOAD = 15 pF
3.9
5.4
AMC1303E2520, 2.7 V ≤ DVDD ≤ 3.6 V,
CLOAD = 15 pF
4.1
5.5
AMC1303E2520, 4.5 V ≤ DVDD ≤ 5.5 V,
CLOAD = 15 pF
4.7
6.5
AMC1303M2520, 2.7 V ≤ DVDD ≤ 3.6 V,
CLOAD = 15 pF
4.6
6.0
AMC1303M2520, 4.5 V ≤ DVDD ≤ 5.5 V,
CLOAD = 15 pF
5.4
7.2
mA
mA
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7.10 Switching Characteristics
over operating ambient temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
AMC1303Mxx10
9.6
10
10.4
AMC1303Mxx20
19.2
20
20.8
45%
50%
55%
fCLK
Internal clock frequency,
on the CLKOUT pin of the AMC1303Mx
only
Duty
Cycle
Internal clock duty cycle (1),
on the CLKOUT pin of the AMC1303Mx
only
th
DOUT hold time after rising edge of
CLKOUT
AMC1303Mx, CLOAD = 15 pF
td
DOUT delay time after rising edge of
CLKOUT
AMC1303Mx, CLOAD = 15 pF
tr
DOUT, CLKOUT rise time
tf
DOUT, CLKOUT fall time
tASTART
(1)
Analog startup time
7
UNIT
MHz
ns
15
10% to 90%, 2.7 V ≤ DVDD ≤ 3.6 V,
CLOAD = 15 pF
0.8
3.5
10% to 90%, 4.5 V ≤ DVDD ≤ 5.5 V,
CLOAD = 15 pF
1.8
3.9
90% to 10%, 2.7 V ≤ DVDD ≤ 3.6 V,
CLOAD = 15 pF
0.8
3.5
90% to 10%, 4.5 V ≤ DVDD ≤ 5.5 V,
CLOAD = 15 pF
1.8
3.9
AVDD step to 3.0 V with DVDD ≥ 2.7 V
0.5
ns
ns
ns
ms
Duty cycle values are specified by design.
CLKOUT
(AMC1303Mx)
th
tr / tf
td
DOUT
(AMC1303Mx)
DOUT
(AMC1303Ex)
Figure 1. AMC1303Mx Digital Interface Timing
AVDD
DVDD
tASTART
tASTART
2 cycles
256 cycles
CLKOUT
(AMC1303Mx)
µ1¶
...
...
DOUT
Bitream not valid
Valid bitstream
µ0¶
Bitream not valid
...
Valid bitstream
µ1¶
Figure 2. Digital Interface Startup Timing
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7.11
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Insulation Characteristics Curves
1200
500
AVDD = DVDD = 3.6 V
AVDD = DVDD = 5.5 V
1100
1000
400
900
PS (mW)
IS (mA)
800
300
200
700
600
500
400
300
100
200
100
0
0
0
50
100
TA (°C)
150
0
200
Figure 3. Thermal Derating Curve for Safety-Limiting
Current per VDE
100
TA (°C)
200
D002
Safety Margin Zone: 1800 VRMS , 254 Years
Operating Zone: 1500 VRMS , 135 Years
TDDB Line (<1 PPM Fail Rate)
1E+10
1E+9
150
Figure 4. Thermal Derating Curve for Safety-Limiting
Power per VDE
1E+11
Time to Fail (sec)
50
D001
87.5%
1E+8
1E+7
1E+6
1E+5
1E+4
1E+3
20%
1E+2
9000
9500
8500
8000
7500
7000
6500
6000
5500
5000
4500
4000
3500
3000
2500
2000
1500
500
1000
1E+1
Stress Voltage (V RMS)
TA up to 150°C, stress-voltage frequency = 60 Hz,
isolation working voltage = 1500 VRMS, operating lifetime = 135 years
Figure 5. Reinforced Isolation Capacitor Lifetime Projection
10
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7.12 Typical Characteristics
at TA = 25°C, AVDD = 5 V, DVDD = 3.3 V, AINP = –50 mV to 50 mV (AMC1303x05x) or –250 mV to 250 mV
(AMC1303x25x), AINN = AGND, and sinc3 filter with OSR = 256 (unless otherwise noted)
4
3.3
3.5
3.25
3.2
VCMov (V)
VCM (V)
3
2.5
2
1.5
3.1
3.05
3
1
2.95
0.5
3
3.5
4
4.5
AVDD (V)
5
2.9
-40
5.5
-10
5
20 35 50 65
Temperature (qC)
80
95
110 125
D004
Figure 7. Common-Mode Overvoltage Detection Level vs
Temperature
60
0
40
-20
20
CMRR (dB)
-40
0
-20
-60
-80
-40
-100
-60
-80
-0.5
-25
D003
Figure 6. Maximum Operating Common-Mode Input Voltage
vs High-Side Supply Voltage
IIB (PA)
3.15
0
0.5
1
1.5
VCM (V)
2
2.5
3
-120
0.1
3.5
1
D005
AMC1303x25x
10
fIN (kHz)
100
1000
D006
AMC1303x25x
Figure 8. Input Bias Current vs
Common-Mode Input Voltage
Figure 9. Common-Mode Rejection Ratio vs
Input Signal Frequency
0
4
3.5
-20
3
INL (|LSB|)
PSRR (dB)
-40
-60
-80
2.5
2
1.5
1
-100
-120
0.1
0.5
1
10
100
Ripple Frequency (kHz)
AMC1303x25x
Figure 10. Power-Supply Rejection Ratio vs
Ripple Frequency
Copyright © 2017, Texas Instruments Incorporated
1000
D012
0
-40
-25
-10
5
20 35 50 65
Temperature (°C)
80
95
110 125
D034
AMC1303x25x
Figure 11. Integral Nonlinearity vs Temperature
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Typical Characteristics (continued)
100
100
75
75
50
50
25
25
EO (PV)
EO (µV)
at TA = 25°C, AVDD = 5 V, DVDD = 3.3 V, AINP = –50 mV to 50 mV (AMC1303x05x) or –250 mV to 250 mV
(AMC1303x25x), AINN = AGND, and sinc3 filter with OSR = 256 (unless otherwise noted)
0
0
-25
-25
-50
-50
-75
-75
-100
-40
-100
3
3.5
4
4.5
AVDD (V)
5
Device 1
Device 2
Device 3
5.5
-25
-10
5
D008
AMC1303x25x
20 35 50 65
Temperature (°C)
80
95
110 125
D009
AMC1303x25x
Figure 12. Offset Error vs High-Side Supply Voltage
Figure 13. Offset Error vs Temperature
0.3
0.2
0.15
0.2
0.1
0.1
EG (%)
EG (%)
0.05
0
-0.05
0
-0.1
-0.1
-0.2
-0.15
-0.3
-40
-0.2
3
3.5
4
4.5
AVDD (V)
5
5.5
-25
-10
5
D010
AMC1303x25x
Figure 14. Gain Error vs High-Side Supply Voltage
95
110 125
D011
Figure 15. Gain Error vs Temperature
90
AMC1303x2510
AMC1303x2520
89
88
88
87
87
86
85
86
85
84
84
83
83
82
3
3.5
4
4.5
AVDD (V)
5
5.5
D013
Capture time = 105 ms
Figure 16. Signal-to-Noise Ratio vs High-Side Supply
Voltage
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AMC1303x2520
89
SNR (dB)
SNR (dB)
80
AMC1303x25x
90
12
20 35 50 65
Temperature (qC)
82
-40
-25
-10
5
20 35 50 65
Temperature (qC)
80
95
110 125
D014
Capture time = 105 ms
Figure 17. Signal-to-Noise Ratio vs Temperature
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Typical Characteristics (continued)
at TA = 25°C, AVDD = 5 V, DVDD = 3.3 V, AINP = –50 mV to 50 mV (AMC1303x05x) or –250 mV to 250 mV
(AMC1303x25x), AINN = AGND, and sinc3 filter with OSR = 256 (unless otherwise noted)
100
100
AMC1303x2510
AMC1303x2520
90
90
85
85
80
80
75
70
75
70
65
65
60
60
55
55
50
0.01
AMC1303x2510
AMC1303x2520
95
SNR (dB)
SNR (dB)
95
50
0.1
1
10
fIN (kHz)
0
50
100
Capture time = 105 ms
350
400
450
500
D016
Figure 19. Signal-to-Noise Ratio vs Input Signal Amplitude
-75
-75
AMC1303x2510
AMC1303x2520
-80
-85
-85
-90
-90
-95
-100
-95
-100
-105
-105
-110
-110
-115
3
3.25
3.5
3.75
4
4.25 4.5
AVDD (V)
4.75
5
5.25
AMC1303x2510
AMC1303x2520
-80
THD (dB)
THD (dB)
200 250 300
VIN (mVpp)
Capture time = 105 ms
Figure 18. Signal-to-Noise Ratio vs Input Signal Frequency
-115
-40
5.5
-25
-10
20 35 50 65
Temperature (°C)
80
95
110 125
D018
Capture time = 839 ms
Figure 20. Total Harmonic Distortion vs
High-Side Supply Voltage
Figure 21. Total Harmonic Distortion vs Temperature
-75
-75
AMC1303x2510
AMC1303x2520
-80
AMC1303x2510
AMC1303x2520
-80
-85
-90
-90
THD (dB)
-85
-95
-100
-95
-100
-105
-105
-110
-110
-115
0.01
5
D017
Capture time = 839 ms
THD (dB)
150
D015
-115
0.1
1
fIN (kHz)
Capture time = 839 ms
Figure 22. Total Harmonic Distortion vs
Input Signal Frequency
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10
D019
0
50
100
150
200 250 300
VIN (mVpp)
350
400
450
500
D020
Capture time = 839 ms
Figure 23. Total Harmonic Distortion vs
Input Signal Amplitude
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Typical Characteristics (continued)
110
110
100
100
90
90
SFDR (dB)
SFDR (dB)
at TA = 25°C, AVDD = 5 V, DVDD = 3.3 V, AINP = –50 mV to 50 mV (AMC1303x05x) or –250 mV to 250 mV
(AMC1303x25x), AINN = AGND, and sinc3 filter with OSR = 256 (unless otherwise noted)
80
80
70
70
60
60
50
-40
50
3
3.5
4
4.5
AVDD (V)
5
5.5
AMC1303x25x, capture time = 105 ms
100
100
90
90
SFDR (dB)
SFDR (dB)
110
80
20 35 50 65
Temperature (qC)
80
95
110 125
D022
80
70
70
60
60
50
0.1
1
10
0
50
100
150
D023
AMC1303x25x, capture time = 105 ms
200 250 300
VIN (mVpp)
350
400
450
500
D024
AMC1303x25x, capture time = 105 ms
Figure 26. Spurious-Free Dynamic Range vs
Input Signal Frequency
Figure 27. Spurious-Free Dynamic Range vs
Input Signal Amplitude
0
0
-20
-20
-40
-40
Magnitude (dB)
Magnitude (dB)
5
Figure 25. Spurious-Free Dynamic Range vs Temperature
110
fIN (kHz)
-60
-80
-100
-60
-80
-100
-120
-120
-140
-140
-160
-160
0
5
10
Frequency (kHz)
15
20
D025
AMC1303x2510, capture time = 839 ms, VIN = 500 mVPP
Figure 28. Frequency Spectrum with 35-Hz Input Signal
14
-10
AMC1303x25x, capture time = 105 ms
Figure 24. Spurious-Free Dynamic Range vs
High-Side Supply Voltage
50
0.01
-25
D021
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0
5
10
Frequency (kHz)
15
20
D026
AMC1303x2520, capture time = 839 ms, VIN = 500 mVPP
Figure 29. Frequency Spectrum with 35-Hz Input Signal
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Typical Characteristics (continued)
at TA = 25°C, AVDD = 5 V, DVDD = 3.3 V, AINP = –50 mV to 50 mV (AMC1303x05x) or –250 mV to 250 mV
(AMC1303x25x), AINN = AGND, and sinc3 filter with OSR = 256 (unless otherwise noted)
10.5
10.5
AMC1303x2520
AMC1303x2510
10
9
9
8.5
8.5
8
7.5
7
6.5
8
7.5
7
6.5
6
6
5.5
5.5
5
5
4.5
3
3.5
4
4.5
AVDD (V)
5
4.5
-40
5.5
-10
5
20 35 50 65
Temperature (°C)
80
95
110 125
D028
Figure 31. High-Side Supply Current vs Temperature
8
8
AMC1303Mx2520
AMC1303Ex2520
AMC1303Mx2510
AMC1303Ex2510
7.5
7
6.5
AMC1303Mx520
AMC1303Ex520
AMC1303Mx510
AMC1303Ex510
7.5
7
6.5
6
IDVDD (mA)
6
5.5
5
4.5
5.5
5
4.5
4
4
3.5
3.5
3
3
2.5
2.5
2
2.7
-25
D027
Figure 30. High-Side Supply Current vs
High-Side Supply Voltage
IDVDD (mA)
AMC1303x2520, AVDD = 5 V
AMC1303x2520, AVDD = 3.3 V
AMC1303x2510, AVDD = 5 V
AMC1303x2510, AVDD = 3.3 V
10
9.5
IAVDD (mA)
IAVDD (mA)
9.5
3.1
3.5
3.9
4.3
DVDD (V)
4.7
5.1
2
-40
5.5
-25
-10
5
D029
20 35 50 65
Temperature (qC)
80
95
110 125
D030
DVDD = 3.3 V
Figure 32. Controller-Side Supply Current vs
Controller-Side Supply Voltage
Figure 33. Controller-Side Supply Current vs Temperature
8
10.4
AMC1303Mx520
AMC1303Ex520
AMC1303Mx510
AMC1303Ex510
7.5
7
6.5
10.3
10.2
fCLK (MHz)
IDVDD (mA)
6
5.5
5
4.5
4
3.5
10
9.9
9.8
3
9.7
2.5
2
-40
10.1
-25
-10
5
20 35 50 65
Temperature (qC)
80
95
110 125
D031
DVDD = 5 V
Figure 34. Controller-Side Supply Current vs Temperature
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9.6
-40
-25
-10
5
20 35 50 65
Temperature (qC)
80
95
110 125
D032
AMC1303Mxx10
Figure 35. Output Clock Frequency vs Temperature
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Typical Characteristics (continued)
at TA = 25°C, AVDD = 5 V, DVDD = 3.3 V, AINP = –50 mV to 50 mV (AMC1303x05x) or –250 mV to 250 mV
(AMC1303x25x), AINN = AGND, and sinc3 filter with OSR = 256 (unless otherwise noted)
20.8
20.6
fCLK (MHz)
20.4
20.2
20
19.8
19.6
19.4
19.2
-40
-25
-10
5
20 35 50 65
Temperature (qC)
80
95
110 125
D033
AMC1303Mxx20
Figure 36. Output Clock Frequency vs Temperature
16
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8 Detailed Description
8.1 Overview
The analog input stage of the AMC1303 is a fully differential amplifier feeding the switched-capacitor input of a
second-order, delta-sigma (ΔΣ) modulator stage that digitizes the input signal into a 1-bit output stream. The
isolated data output DOUT of the converter provides a stream of digital ones and zeros that is synchronous to
the internally-generated clock at the CLKOUT pin (active on AMC1303Mx derivates only) with a frequency as
specified in the Switching Characteristics table. The time average of this serial bit-stream output is proportional to
the analog input voltage.
The Functional Block Diagram section shows a detailed block diagram of the AMC1303. The analog input range
is tailored to directly accommodate a voltage drop across a shunt resistor used for current sensing. The SiO2based capacitive isolation barrier supports a high level of magnetic field immunity as described in the application
report ISO72x Digital Isolator Magnetic-Field Immunity (SLLA181A), available for download at www.ti.com. The
extended clock frequency of 20 MHz on the AMC1303xxx20 supports faster control loops and higher
performance levels compared to the other solutions available on the market.
8.2 Functional Block Diagram
DVDD
AVDD
û -Modulator
VCM / AVDD
Diagnostic
AMC1303x
AGND
Clock Generator
Bandgap
Reference
Receiver
AINN
Interface
Receiver
AINP
Manchester Coding
(AMC1303Ex only)
Isolation
Barrier
DOUT
CLKOUT
(AMC1303Mx only)
DGND
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8.3 Feature Description
8.3.1 Analog Input
The AMC1303 incorporates a front-end circuitry that contains a differential amplifier and sampling stage, followed
by a ΔΣ modulator. The gain of the differential amplifier is set by internal precision resistors to a factor of 4 for
devices with a specified input voltage range of ±250 mV (for the AMC1303x25x), or to a factor of 20 in devices
with a ±50-mV input voltage range (for the AMC1303x05x), resulting in a differential input resistance of 4.9 kΩ
(for the AMC1303x05x) or 22 kΩ (for the AMC1303x25x).
For reduced offset and offset drift, the differential amplifier is chopper-stabilized with the switching frequency set
at fCLK / 32. Figure 37 shows that the switching frequency generates a spur.
0
-20
Magnitude (dB)
-40
-60
-80
-100
-120
-140
-160
0.1
1
10
100
Frequency (kHz)
1000
10000
D007
AMC1303xxx20, sinc3 filter, OSR = 2, fIN = 1 kHz
Figure 37. Quantization Noise Shaping
Consider the input resistance of the AMC1303 in designs with high-impedance signal sources that can cause
degradation of gain and offset specifications. The importance of this effect, however, depends on the desired
system performance. Additionally, the input bias current caused by the internal common-mode voltage at the
output of the differential amplifier causes an offset that is dependent on the actual amplitude of the input signal.
See the Isolated Voltage Sensing section for more details on reducing these effects.
There are two restrictions on the analog input signals (AINP and AINN). First, if the input voltage exceeds the
range AGND – 6 V to AVDD + 0.5 V, the input current must be limited to 10 mA because the device input
electrostatic discharge (ESD) diodes turn on. In addition, the linearity and noise performance of the device are
ensured only when the differential analog input voltage remains within the specified linear full-scale range (FSR),
that is ±250 mV (for the AMC1303x25x) or ±50 mV (for the AMC1303x05x), and within the specified input
common-mode voltage range.
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Feature Description (continued)
8.3.2 Modulator
The modulator implemented in the AMC1303 (such as the one conceptualized in Figure 38) is a second-order,
switched-capacitor, feed-forward ΔΣ modulator. The analog input voltage VIN and the output V5 of the 1-bit
digital-to-analog converter (DAC) are subtracted, providing an analog voltage V1 at the input of the first integrator
stage. The output of the first integrator feeds the input of the second integrator stage, resulting in output voltage
V3 that is subtracted from the input signal VIN and the output of the first integrator V2. Depending on the polarity
of the resulting voltage V4, the output of the comparator is changed. In this case, the 1-bit DAC responds on the
next clock pulse by changing its analog output voltage V5, causing the integrators to progress in the opposite
direction and forcing the value of the integrator output to track the average value of the input.
fCLKIN
V1
V2
Integrator 1
VIN
V3
V4
Integrator 2
CMP
0V
V5
DAC
Figure 38. Block Diagram of a Second-Order Modulator
The modulator shifts the quantization noise to high frequencies; see Figure 37. Therefore, use a low-pass digital
filter at the output of the device to increase the overall performance. This filter is also used to convert the 1-bit
data stream at a high sampling rate into a higher-bit data word at a lower rate (decimation). TI's microcontroller
families TMS320F2807x and TMS320F2837x offer a suitable programmable, hardwired filter structure called a
sigma-delta filter module (SDFM) optimized for usage with the AMC1303 family. Also, SD24_B converters on the
MSP430F677x microcontrollers offer a path to directly access the integrated sinc-filters, thus offering a systemlevel solution for multichannel, isolated current sensing. An additional option is to use a suitable applicationspecific device, such as the AMC1210 (a four-channel digital sinc-filter). Alternatively, a field-programmable gate
array (FPGA) can be used to implement the filter.
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Feature Description (continued)
8.3.3 Isolation Channel Signal Transmission
The AMC1303 uses an on-off keying (OOK) modulation scheme to transmit the modulator output bitstream
across the capacitive SiO2-based isolation barrier. The transmitter modulates the bitstream at TX IN in Figure 39
with an internally-generated, 480-MHz carrier across the isolation barrier to represent a digital zero and sends a
no signal to represent the digital one. The receiver demodulates the signal after advanced signal conditioning
and produces the output. The symmetrical design of each isolation channel improves the CMTI performance and
reduces the radiated emissions caused by the high-frequency carrier. Figure 39 shows a block diagram of an
isolation channel integrated in the AMC1303.
Transmitter
Receiver
OOK
Modulation
TX IN
TX Signal
Conditioning
SiO2-Based
Capacitive
Reinforced
Isolation
Barrier
RX Signal
Conditioning
Envelope
Detection
RX OUT
Oscillator
Figure 39. Block Diagram of an Isolation Channel
Figure 40 shows the concept of the on-off keying scheme.
TX IN
Carrier signal across
the isolation barrier
RX OUT
Figure 40. OOK-Based Modulation Scheme
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Feature Description (continued)
8.3.4 Digital Output
A differential input signal of 0 V ideally produces a stream of ones and zeros that are high 50% of the time. A
differential input of 250 mV (for the AMC1303x25x) or 50 mV (for the AMC1303x05x) produces a stream of ones
and zeros that are high 89.06% of the time. With 16 bits of resolution on the decimation filter, that percentage
ideally corresponds to code 58368. A differential input of –250 mV (–50 mV for the AMC1303x05x) produces a
stream of ones and zeros that are high 10.94% of the time and ideally results in code 7168 with a 16-bit
resolution decimation filter. These input voltages are also the specified linear ranges of the different AMC1303
versions with performance as specified in this document. If the input voltage value exceeds these ranges, the
output of the modulator shows nonlinear behavior where the quantization noise increases. The output of the
modulator clips with a stream of only zeros with an input less than or equal to –320 mV (–64 mV for the
AMC1303x05x) or with a stream of only ones with an input greater than or equal to 320 mV (64 mV for the
AMC1303x05x). In this case, however, the AMC1303 generates a single 1 (if the input is at negative full-scale) or
0 every 128 clock cycles to indicate proper device function (see the Fail-Safe Output section for more details).
Figure 41 shows the input voltage versus the output modulator signal.
Modulator Output
+FS (Analog Input)
-FS (Analog Input)
Analog Input
Figure 41. Analog Input versus AMC1303 Modulator Output
Equation 1 calculates the density of ones in the output bit-stream for any input voltage value (with the exception
of a full-scale input signal, as described in the Output Behavior in Case of a Full-Scale Input section):
VIN
VClipping
2 u VClipping
(1)
The AMC1303 internally generates the clock signal required for the modulator. This clock is provided externally
at the CLKOUT pin on AMC1303Mx devices only. For more details, see the Switching Characteristics section.
8.3.5 Manchester Coding Feature
The AMC1303Ex offers the IEEE 802.3-compliant Manchester coding feature that generates at least one
transition per bit to support clock signal recovery from the bitstream. A Manchester coded bitstream is free of dc
components. The Manchester coding combines the clock and data information using exclusive or (XOR) logical
operation. Figure 42 shows the resulting bitstream.
Clock
Uncoded
Bitstream
1
0
1
0
1
1
1
0
0
1
1
0
0
0
1
Machester
Coded
Bitstream
Figure 42. Manchester Coded Output of the AMC1303Ex
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8.4 Device Functional Modes
8.4.1 Fail-Safe Output
In the case of a missing high-side supply voltage AVDD, the output of the ΔΣ modulator is not defined and can
cause a system malfunction. In systems with high safety requirements, this behavior is not acceptable.
Therefore, as shown in Figure 2, the AMC1303 implements a fail-safe output function that pulls the DOUT and
CLKOUT outputs (AMC1303Mx only) to a steady-state logic 1 in case of a missing AVDD.
Similarly, as also shown in Figure 43, if the common-mode voltage of the input reaches or exceeds the specified
common-mode overvoltage detection level VCMov as defined in the Electrical Characteristics table, the AMC1303
generates a steady-state bitstream of logic 1's at the DOUT output.
In both cases, the steady-state logic 1 occurs on the DOUT output with a delay of two clock cycles after the
event of either exceeded common-mode input voltage or missing AVDD. Another 256 clock cycles are required
for the CLKOUT pin of the AMC1303Mx to be held at logic 1.
VCM
VCM • 9CMov
VCM < VCMov
VCM < VCMov
256 cycles
CLKOUT
(AMC1303Mx only)
µ1¶
...
4 cycles
4 cycles
DOUT
µ1¶
Valid bitstream
Valid bitstream
Figure 43. Fail-Safe Output of the AMC1303
8.4.2 Output Behavior in Case of a Full-Scale Input
If a full-scale input signal is applied to the AMC1303 (that is, |VIN| ≥ |VClipping|), Figure 44 shows that the device
generates a single one or zero every 128 bits at DOUT, depending on the actual polarity of the signal being
sensed. In this way, differentiating between a missing AVDD and a full-scale input signal is possible on the
system level.
CLKOUT
(AMC1303Mx only)
...
...
VIN ” -320 mV (AMC1303x05x: ” -64 mV)
DOUT
...
...
...
...
VIN • 320 mV (AMC1303x05x: H 64 mV)
DOUT
127 CLK cycles
127 CLK cycles
Figure 44. Overrange Output of the AMC1303
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
9.1.1 Digital Filter Usage
The modulator generates a bit stream that is processed by a digital filter to obtain a digital word similar to a
conversion result of a conventional analog-to-digital converter (ADC). A very simple filter, shown in Equation 2,
built with minimal effort and hardware, is a sinc3-type filter:
H z
§ 1 z OSR
¨¨
1
© 1 z
·
¸¸
¹
3
(2)
This filter provides the best output performance at the lowest hardware size (count of digital gates) for a secondorder modulator. All the characterization in this document is done with a sinc3 filter with an oversampling ratio
(OSR) of 256 and an output word size of 16 bits.
The effective number of bits (ENOB) is often used to compare the performance of ADCs and ΔΣ modulators.
shows the ENOB of the AMC1303 with different oversampling ratios. In this document, Equation 3 calculates this
number from the SNR:
ENOB
SNR 1.76 dB
6.05 dB
(3)
16
14
ENOB (bits)
12
10
8
6
4
sinc3
sinc2
sinc1
2
0
1
10
100
OSR
1000
D040
Figure 45. Measured Effective Number of Bits versus Oversampling Ratio
An example code for implementing a sinc3 filter in an FPGA is discussed in application note Combining ADS1202
with FPGA Digital Filter for Current Measurement in Motor Control Applications, available for download at
www.ti.com.
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9.2 Typical Applications
9.2.1 Frequency Inverter Application
Isolated ΔΣ modulators are widely used in new-generation frequency inverter designs because of their high ac
and dc performance. Frequency inverters are critical parts of industrial motor drives, photovoltaic inverters (string
and central inverters), uninterruptible power supplies (UPS), and other industrial applications.
Figure 46 shows a simplified schematic of the AMC1303Mx in a typical frequency inverter application as used in
industrial motor drives with shunt resistors (RSHUNT) used for current sensing. Depending on the system design,
either all three or only two motor phase currents are sensed.
Motor
DC link
RSHUNT
L1
RSHUNT
L3
RSHUNT
L2
3.3 V
AMC1303Mx
AVDD
AINP
DOUT
AINN
CLKOUT
AGND
3.3 V
3.3 V
3.3 V
AMC1303Mx
AVDD
AVDD
DVDD
AINP
DOUT
AINN
CLKOUT
AGND
3.3 V
TMS320F28x7x
DGND
3.3 V
SD-D1
AVDD
DVDD
SD-C1
AINP
DOUT
SD-D2
AINN
CLKOUT
SD-C2
AGND
DGND
SD-D3
SD-C3
SD-D4
SD-C4
DGND
DVDD
AINP
DOUT
AINN
CLKOUT
AGND
3.3 V
AMC1303Mx
AMC1303Mx
3.3 V
DVDD
DGND
Power Board
Control Board
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Figure 46. Simplified Diagram of the AMC1303Mx in a Frequency Inverter Application
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Typical Applications (continued)
Figure 47 shows how the Manchester coded bitstream output of the AMC1303Ex minimizes the wiring efforts of
the connection between the power and the control board. This bitstream output also allows the clock to be
generated locally on the power board without the having to adjust the propagation delay time of each DOUT
connection to fulfill the setup and hold time requirements of the microcontroller.
Motor
DC link
RSHUNT
L1
RSHUNT
L3
RSHUNT
L2
3.3 V
AMC1303Ex
AVDD
AINP
DOUT
AINN
CLKOUT
AGND
3.3 V
AMC1303Ex
AVDD
3.3 V
3.3 V
AMC1303Ex
AVDD
DVDD
AINP
DOUT
AINN
CLKOUT
AGND
3.3 V
3.3 V
SD-D1
DVDD
AINP
DOUT
AINN
CLKOUT
AGND
TMS320F28x7x
DGND
SD-D2
DGND
SD-D3
SD-D4
DGND
DVDD
AINP
DOUT
AINN
CLKOUT
AGND
3.3 V
AMC1303Ex
AVDD
3.3 V
DVDD
DGND
Power Board
Control Board
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Figure 47. Simplified Diagram of the AMC1303Ex in a Frequency Inverter Application
In both examples shown previously, an additional fourth AMC1303 is used to support isolated voltage sensing of
the dc link. This high voltage is reduced using a resistive divider and is sensed by the device across a smaller
resistor. The value of this resistor can degrade the performance of the measurement, as described in the Isolated
Voltage Sensing section.
9.2.1.1 Design Requirements
Table 1 lists the parameters for the typical application in the Frequency Inverter Application section.
Table 1. Design Requirements
PARAMETER
VALUE
High-side supply voltage
3.3 V or 5 V
Low-side supply voltage
Voltage drop across the shunt for a linear response
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3.3 V or 5 V
AMC1303x25x: ±250 mV (maximum)
AMC1303x05x: ±50 mV (maximum)
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9.2.1.2 Detailed Design Procedure
The high-side power supply (AVDD) for the AMC1303 device is derived from the power supply of the upper gate
driver. Further details are provided in the Power Supply Recommendations section.
The floating ground reference (AGND) is derived from one of the ends of the shunt resistor that is connected to
the negative input of the AMC1303 (AINN). If a four-pin shunt is used, the inputs of the device are connected to
the inner leads and AGND is connected to one of the outer shunt leads.
Use Ohm's Law to calculate the voltage drop across the shunt resistor (VSHUNT) for the desired measured
current: VSHUNT = I × RSHUNT.
Consider the following two restrictions to choose the proper value of the shunt resistor RSHUNT:
• The voltage drop caused by the nominal current range must not exceed the recommended differential input
voltage range: VSHUNT ≤ ±250 mV
• The voltage drop caused by the maximum allowed overcurrent must not exceed the input voltage that causes
a clipping output: |VSHUNT| ≤ |VClipping|
The typically recommended RC filter in front of a ΔΣ modulator to improve signal-to-noise performance of the
signal path is not required for the AMC1303. By design, the input bandwidth of the analog front-end of the device
is limited as specified in the Electrical Characteristics table.
For modulator output bitstream filtering, a device from TI's TMS320F2807x family of low-cost microcontrollers
(MCUs) or TMS320F2837x family of dual-core MCUs is recommended. These families support up to eight
channels of dedicated hardwired filter structures that significantly simplify system level design by offering two
filtering paths per channel: one providing high accuracy results for the control loop and one fast response path
for overcurrent detection.
9.2.1.3 Application Curves
In motor control applications, a very fast response time for overcurrent detection is required. The time for fully
settling the filter in case of a step-signal at the input of the modulator depends on its order; that is, a sinc3 filter
requires three data updates for full settling (with fDATA = fCLK / OSR). Therefore, for overcurrent protection, filter
types other than sinc3 can be a better choice; an alternative is the sinc2 filter. Figure 48 and Figure 49 compare
the settling times of different filter orders.
16
16
14
14
12
12
10
10
ENOB (Bits)
ENOB (Bits)
The delay time of a sinc filter with a continuous signal is half of its settling time.
8
6
4
6
4
sinc3
sinc2
sinc1
2
0
sinc3
sinc2
sinc1
2
0
0
2
4
6
8
10 12 14 16 18 20 22 24 26
Settling Time (µs)
D035
AMC1303xxx20
Figure 48. Measured Effective Number of Bits versus
Settling Time
26
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0
2
4
6
8
10 12 14 16 18 20 22 24 26
Settling Time (µs)
D035
AMC1303xxx10
Figure 49. Measured Effective Number of Bits versus
Settling Time
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9.2.2 Isolated Voltage Sensing
The AMC1303 is optimized for usage in current-sensing applications using low-resistance shunts. However, the
device can also be used in isolated voltage-sensing applications if the effect of the (usually higher) value of the
resistor used in this case is considered. For best performance, TI recommends using the ±250-mV versions of
the device (AMC1303x25xx) for this use case.
Figure 50 shows a simplified circuit typically used in high-voltage-sensing applications. The high value resistors
(R1 and R2) are used as voltage dividers and dominate the current value definition. The resistance of the
sensing resistor R3 is chosen to meet the input voltage range of the AMC1303. This resistor and the differential
input resistance of the AMC1303x25x is 22 kΩ also create a voltage divider that results in an additional gain
error. With the assumption of R1, R2, and RIND having a considerably higher value than R3, the resulting total
gain error can be estimated using Equation 4, with EG being the gain error of the AMC1303.
EGtot = EG +
R3
RIN
(4)
This gain error can be minimized during the initial system-level gain calibration procedure.
High Voltage
Potential
3.3 V
or 5 V
R1
AMC1303x25x
AVDD
R2
R4
AINP
R5
IIB
RIND
200 NŸ
R3
û Modulator
AINN
R4'
R3'
R5'
AGND
VCM = 1.9 V
AGND
Figure 50. Using the AMC1303x25x for Isolated Voltage Sensing
9.2.2.1 Design Requirements
Table 2 lists the parameters for the typical application in the Isolated Voltage Sensing section.
Table 2. Design Requirements
PARAMETER
VALUE
High-side supply voltage
3.3 V or 5 V
Low-side supply voltage
3.3 V or 5 V
Voltage drop across the resistor R3 for a linear response
AMC1303x25x: ±250 mV (maximum)
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9.2.2.2 Detailed Design Procedure
As indicated in Figure 50, the output of the integrated differential amplifier is internally biased to a common-mode
voltage of 1.9 V. This voltage results in a bias current IIB through the resistive network R4 and R5 (or R4' and
R5') used for setting the gain of the amplifier. The value range of this current is specified in the Electrical
Characteristics table. This bias current generates additional offset error that depends on the value of the resistor
R3. Because the value of this bias current depends on the actual common-mode amplitude of the input signal (as
illustrated in Figure 51), the initial system offset calibration does not minimize its effect. Therefore, in systems
with high accuracy requirements, TI recommends using a series resistor at the negative input (AINN) of the
AMC1303 with a value equal to the shunt resistor R3 (that is, R3' = R3 in Figure 50) to eliminate the effect of the
bias current.
This additional series resistor (R3') influences the gain error of the circuit. The effect is calculated using
Equation 5 with R5 = R5' = 50 kΩ and R4 = R4' = 12.5 kΩ for the AMC1303x25x.
E G (%)
R4 ·
§
¨ 1 R4' R3' ¸ u 100%
©
¹
(5)
9.2.2.3 Application Curve
Figure 51 shows the dependency of the input bias current on the common-mode voltage at the input of the
AMC1303x25x.
60
40
IIB (PA)
20
0
-20
-40
-60
-80
-0.5
0
0.5
1
1.5
VCM (V)
2
2.5
3
3.5
D005
AMC1303x25x
Figure 51. Input Current vs Input Common-Mode Voltage
9.2.3 Do's and Don'ts
Do not leave the inputs of the AMC1303 unconnected (floating) when the device is powered up. If both modulator
inputs are left floating, the input bias current drives these inputs to the output common-mode voltage of the
differential amplifier of approximately 1.9 V. If that voltage is above the specified input common-mode range, the
gain of the differential amplifier diminishes and the modulator outputs a bitstream resembling a zero differential
input voltage.
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10 Power Supply Recommendations
In a typical frequency-inverter application, the high-side power supply (AVDD) for the device is directly derived
from the floating power supply of the upper gate driver. For lowest system-level cost, a Zener diode can be used
to limit the voltage to 5 V or 3.3 V (±10%). Alternatively a low-cost low-drop regulator (LDO), for example the
LM317-N, can be used to adjust the supply voltage level and minimize noise on the power supply node. A lowESR decoupling capacitor of 0.1 µF is recommended for filtering this power-supply path. Place this capacitor (C2
in Figure 52) as close as possible to the AVDD pin of the AMC1303 for best performance. Further, an additional
capacitor with a value in the range of 2.2 µF to 10 µF is recommended.
The floating ground reference (AGND) is derived from the end of the shunt resistor, which is connected to the
negative input (AINN) of the device. If a four-pin shunt is used, the device inputs are connected to the inner leads
and AGND is connected to one of the outer leads of the shunt.
For decoupling of the digital power supply on the controller side, TI recommends using a 0.1-µF capacitor
assembled as close to the DVDD pin of the AMC1303 as possible, followed by an additional capacitor in the
range of 2.2 µF to 10 µF.
R1
800
Gate Driver
Z1
1N751A
C1
2.2 F
AMC1303Mx
5.1 V
AVDD
C2
0.1 F
AGND
RSHUNT
To Load
AINN
AINP
3.0 V,
or 3.3 V
or 5.0 V
DVDD
Reinforced Isolation
HV+
Floating
Power Supply
20 V
C4
0.1 F
C5
2.2 F
DGND
DOUT
SD-Dx
CLKOUT
SD-Cx
TMS320F2837x
Gate Driver
Note: no CLKOUT connection using AMC1303Ex,
pin 7 to be connected to DGND in this case
HV-
Copyright © 2017, Texas Instruments Incorporated
Figure 52. Decoupling the AMC1303
Copyright © 2017, Texas Instruments Incorporated
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29
AMC1303E0510, AMC1303M0510, AMC1303E0520, AMC1303M0520
AMC1303E2510, AMC1303M2510, AMC1303E2520, AMC1303M2520
SBAS771 – JUNE 2017
www.ti.com
11 Layout
11.1 Layout Guidelines
Figure 53 shows a layout recommendation detailing the critical placement of the decoupling capacitors (as close
as possible to the AMC1303) and placement of the other components required by the device. For best
performance, place the shunt resistor and the antialiasing filter components as close as possible to the AINP and
AINN inputs of the AMC1303 and keep the layout of both connections symmetrical.
11.2 Layout Example
Clearance area,
to be kept free of any
conductive materials.
Shunt Resistor
To Floating
Power
Supply
RFLT
RFLT
SMD
0603
SMD
0603
2.2 µF
0.1 µF
SMD
0603
SMD
0603
AVDD
CFLT
SMD
0603
1
16
0.1 µF
2.2 µF
SMD
0603
SMD
0603
DVDD
CLKOUT
AINP
To Digital
Filter
(MCU)
AMC1303Mx
AINN
DOUT
AGND
DGND
LEGEND
Note: no CLKOUT connection using AMC1303Ex,
pin 7 to be connected to DGND in this case
Copper Pour and Traces
High-Side Area
Controller-Side Area
Via to Ground Plane
Via to Supply Plane
Copyright © 2017, Texas Instruments Incorporated
Figure 53. Recommended Layout of the AMC1303
30
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Product Folder Links: AMC1303E0510 AMC1303M0510 AMC1303E0520 AMC1303M0520 AMC1303E2510
AMC1303M2510 AMC1303E2520 AMC1303M2520
AMC1303E0510, AMC1303M0510, AMC1303E0520, AMC1303M0520
AMC1303E2510, AMC1303M2510, AMC1303E2520, AMC1303M2520
www.ti.com
SBAS771 – JUNE 2017
12 Device and Documentation Support
12.1 Device Support
12.1.1 Device Nomenclature
12.1.1.1 Isolation Glossary
See the Isolation Glossary, SLLA353.
12.2 Documentation Support
12.2.1 Related Documentation
• AMC1210 Quad Digital Filter for 2nd-Order Delta-Sigma Modulator
• MSP430F677x Polyphase Metering SoCs
• TMS320F2807x Piccolo™ Microcontrollers
• TMS320F2837xD Dual-Core Delfino™ Microcontrollers
• ISO72x Digital Isolator Magnetic-Field Immunity
• Combining ADS1202 with FPGA Digital Filter for Current Measurement in Motor Control Applications
12.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
Table 3. Related Links
PARTS
PRODUCT FOLDER
ORDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
AMC1303E0510
Click here
Click here
Click here
Click here
Click here
AMC1303M0510
Click here
Click here
Click here
Click here
Click here
AMC1303E0520
Click here
Click here
Click here
Click here
Click here
AMC1303M0520
Click here
Click here
Click here
Click here
Click here
AMC1303E2510
Click here
Click here
Click here
Click here
Click here
AMC1303M2510
Click here
Click here
Click here
Click here
Click here
AMC1303E2520
Click here
Click here
Click here
Click here
Click here
AMC1303M2520
Click here
Click here
Click here
Click here
Click here
12.4 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.5 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
Copyright © 2017, Texas Instruments Incorporated
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AMC1303M2510 AMC1303E2520 AMC1303M2520
31
AMC1303E0510, AMC1303M0510, AMC1303E0520, AMC1303M0520
AMC1303E2510, AMC1303M2510, AMC1303E2520, AMC1303M2520
SBAS771 – JUNE 2017
www.ti.com
12.6 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.7 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.8 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
32
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Product Folder Links: AMC1303E0510 AMC1303M0510 AMC1303E0520 AMC1303M0520 AMC1303E2510
AMC1303M2510 AMC1303E2520 AMC1303M2520
PACKAGE OPTION ADDENDUM
www.ti.com
28-Jun-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
AMC1303E0510DWV
PREVIEW
SOIC
DWV
8
64
TBD
Call TI
Call TI
-40 to 125
AMC1303E0510DWVR
PREVIEW
SOIC
DWV
8
1000
TBD
Call TI
Call TI
-40 to 125
AMC1303E0520DWV
PREVIEW
SOIC
DWV
8
64
TBD
Call TI
Call TI
-40 to 125
AMC1303E0520DWVR
PREVIEW
SOIC
DWV
8
1000
TBD
Call TI
Call TI
-40 to 125
AMC1303E2510DWV
ACTIVE
SOIC
DWV
8
64
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
1303E251
AMC1303E2510DWVR
ACTIVE
SOIC
DWV
8
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
1303E251
AMC1303E2520DWV
ACTIVE
SOIC
DWV
8
64
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
1303E252
AMC1303E2520DWVR
ACTIVE
SOIC
DWV
8
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
1303E252
AMC1303M0510DWV
PREVIEW
SOIC
DWV
8
64
TBD
Call TI
Call TI
-40 to 125
AMC1303M0510DWVR
PREVIEW
SOIC
DWV
8
1000
TBD
Call TI
Call TI
-40 to 125
AMC1303M0520DWV
PREVIEW
SOIC
DWV
8
64
TBD
Call TI
Call TI
-40 to 125
AMC1303M0520DWVR
PREVIEW
SOIC
DWV
8
1000
TBD
Call TI
Call TI
-40 to 125
AMC1303M2510DWV
ACTIVE
SOIC
DWV
8
64
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
1303M251
AMC1303M2510DWVR
ACTIVE
SOIC
DWV
8
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
1303M251
AMC1303M2520DWV
ACTIVE
SOIC
DWV
8
64
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
1303M252
AMC1303M2520DWVR
ACTIVE
SOIC
DWV
8
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
1303M252
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
28-Jun-2017
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Jun-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
AMC1303E2510DWVR
SOIC
DWV
8
1000
330.0
16.4
12.05
6.15
3.3
16.0
16.0
Q1
AMC1303E2520DWVR
SOIC
DWV
8
1000
330.0
16.4
12.05
6.15
3.3
16.0
16.0
Q1
AMC1303M2510DWVR
SOIC
DWV
8
1000
330.0
16.4
12.05
6.15
3.3
16.0
16.0
Q1
AMC1303M2520DWVR
SOIC
DWV
8
1000
330.0
16.4
12.05
6.15
3.3
16.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Jun-2017
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
AMC1303E2510DWVR
SOIC
DWV
8
1000
367.0
367.0
38.0
AMC1303E2520DWVR
SOIC
DWV
8
1000
367.0
367.0
38.0
AMC1303M2510DWVR
SOIC
DWV
8
1000
367.0
367.0
38.0
AMC1303M2520DWVR
SOIC
DWV
8
1000
367.0
367.0
38.0
Pack Materials-Page 2
PACKAGE OUTLINE
DWV0008A
SOIC - 2.8 mm max height
SCALE 2.000
SOIC
C
SEATING PLANE
11.5 0.25
TYP
PIN 1 ID
AREA
0.1 C
6X 1.27
8
1
2X
3.81
5.95
5.75
NOTE 3
4
5
0.51
0.31
0.25
C A
8X
A
7.6
7.4
NOTE 4
B
B
2.8 MAX
0.33
TYP
0.13
SEE DETAIL A
(2.286)
0.25
GAGE PLANE
0 -8
0.46
0.36
1.0
0.5
(2)
DETAIL A
TYPICAL
4218796/A 09/2013
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DWV0008A
SOIC - 2.8 mm max height
SOIC
8X (1.8)
SEE DETAILS
SYMM
8X (0.6)
SYMM
6X (1.27)
(10.9)
LAND PATTERN EXAMPLE
9.1 mm NOMINAL CLEARANCE/CREEPAGE
SCALE:6X
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
0.07 MAX
ALL AROUND
METAL
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4218796/A 09/2013
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DWV0008A
SOIC - 2.8 mm max height
SOIC
8X (1.8)
SYMM
8X (0.6)
SYMM
6X (1.27)
(10.9)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
4218796/A 09/2013
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
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