IDT IDT7099S25G High-speed 4k x 9 synchronous dual-port ram Datasheet

HIGH-SPEED
4K x 9 SYNCHRONOUS
DUAL-PORT RAM
IDT7099S
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
• High-speed clock-to-data output times
— Military: 20/25/30ns (max.)
— Commercial: 15/20/25ns (max.)
• Low-power operation
— IDT7099S
Active: 900 mW (typ.)
Standby: 50 mW (typ.)
• Architecture based on Dual-Port RAM cells
— Allows full simultaneous access from both ports
— Independent bit/byte Read and Write inputs for control
functions
• Synchronous operation
— 4ns setup to clock, 1ns hold on all control, data, and
address inputs
— Data input, address, and control registers
— Fast 15ns clock to data out
— 20ns cycle times, 50MHz operation
• Clock enable feature
• Guaranteed data output hold times
• Available in 68-pin PGA, 68-pin PLCC, and 80-pin TQFP
• Military product compliant to MIL-STD-883, Class B
• Industrial temperature range (–40°C to +85°C) is available, tested to military electrical specifications
The IDT7099 is a high-speed 4K x 9 bit synchronous DualPort RAM. The memory array is based on Dual-Port memory
cells to allow simultaneous access from both ports. Registers
on control, data, and address inputs provide low set-up and
hold times. The timing latitude provided by this approach
allow systems to be designed with very short realized cycle
times. With an input data register, this device has been
optimized for applications having unidirectional data flow or
bi-directional data flow in bursts. Changing data direction from
reading to writing normally requires one dead cycle.
These Dual-Ports typically operate on only 900mW of
power at maximum high-speed clock-to-data output times as
fast as 15ns. An automatic power down feature, controlled
by CE, permits the on-chip circuitry of each port to enter a very
low standby power mode.
The IDT7099 is packaged in a 68-pin PGA, 68-pin PLCC,
and a 80-pin TQFP. Military grade product is manufactured in
compliance with the latest revision of MIL-STD-883, Class B,
making it ideally suited to military temperature applications
demanding the highest level of performance and reliability.
FUNCTIONAL BLOCK DIAGRAM
WRITE
LOGIC
SENSE
AMPS
BIT OEL
MEMOR
MEMORY
YARRAY
ARRAY
DECODER DECODER
REG
en
BYTE OEL
CLKL
WRITE
LOGIC
REGISTER
REGISTER
I/O8L
I/O0-7L
I/O8R
I/O0-7R
SENSE
AMPS
BIT OER
REG
en
BYTE OER
CLKR
CLKEN
WL
BYTE R/WL
CLKENR
Write
Control
Logic
BIT R/
Write
Control
Logic
REG
CEL
A0L-A11L
A0R-A11R
WR
BYTE R/WR
BIT R/
REG
CER
3007 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1996 Integrated Device Technology, Inc.
For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.
6.23
OCTOBER 1996
DSC-3007/3
1
IDT7099S
HIGH-SPEED 4K x 9 SYNCHRONOUS DUAL-PORT RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
9
8
7
6
5
4
3
2
CLKEN R
A0R
A1R
A2R
A3R
A4R
A5R
A6R
CLKENL
A5L
A4L
A3L
A2L
A1L
A0L
INDEX
CLKL
CLKR
PIN CONFIGURATIONS (1,2)
68 67 66 65 64 63 62 61
60
20
50
21
49
A7R
A8R
A9R
A10R
A11R
BYTE OER
BIT OER
GND
GND
BYTE R/ WR
BIT R/ WR
N/C
CE L
22
48
CE R
GND
I/O8L
I/O7L
I/O6L
23
47
24
46
25
45
26
44
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
GND
I/O8R
I/O7R
I/O6R
A6L
A7L
A8L
A9L
A10L
A11L
10
BYTE OE L
BIT OEL
VCC
BYTE R/ WL
BIT R/ WL
N/C
16
1
11
59
12
58
13
57
14
56
55
15
54
IDT7099
J68-1
17
18
53
52
68-Pin PLCC
Top View (3)
51
3007 drw 03
N/C
I/O5L
VCC
I/O4L
I/O3L
I/O2L
I/O1L
I/O0L
GND
GND
I/O0R
I/O1R
I/O2R
I/O3R
VCC
I/O4R
I/O5R
19
A
A
0R
51
53
50
A5L
1R
52
55
49
47
44
A0L
45
A1L
42
CLKL
43
CLKENL
40
CLKENR
41
CLKR
38
A1R
39
A0R
36
A3R
37
A2R
57
30
A10L
BIT
OEL
61
28
OEL
60
BYTE
R/ L
W
63
OER
IDT7099
G68-1
VCC
26
62
NC
65
24
W
W
64
67
22
CEL
GND
68
1
A
W
3
5
VCC
4
7
I/O3L
6
9
I/O1L
8
11
GND
10
13
I/O0R
12
15
I/O2R
14
18
VCC
16
NC
21
I/O8R
NC
2
BYTE
R/ R
23
20
I/O8L
I/O6L
GND
CER
66
I/O7L
OER
25
BIT
R/ R
BIT
R/ L
BYTE
27
GND
68-Pin PGA
Top View (3)
A10R
29
BIT
BYTE
A8R
31
A11R
58
A7R
33
A9R
56
59
34
A6R
32
A8L
A11L
A5R
35
A4R
54
A9L
INDEX
46
A2L
A3L
A6L
A7L
48
A4L
GND
19
I/O6R
I/O7R
17
I/O5L
I/O4L
I/O2L
I/O0L
GND
I/O1R
I/O3R
I/O4R
I/O5R
B
C
D
E
F
G
H
J
K
L
3007 drw 02
NOTES:
1. All VCC pins must be connected to power supply.
2. All ground pins must be connected to ground supply.
3. This text does not indicate orientation of the actual
part-marking.
6.23
2
IDT7099S
HIGH-SPEED 4K x 9 SYNCHRONOUS DUAL-PORT RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
CLKEN R
A0R
A1R
A2R
A3R
A4R
A5R
A6R
N/C
CLKENL
N/C
N/C
A5L
A4L
A3L
A2L
A1L
A0L
Reference
CLKL
CLKR
PIN CONFIGURATIONS (CONT'D) (1,2)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
N/C
A6L
A7L
A8L
A9L
A10L
A11L
N/C
14
47
N/C
A7R
A8R
A9R
A10R
A11R
N/C
BYTE OE R
BIT OE R
GND
GND
BYTE R/ W R
BIT R/ W R
N/C
15
46
CE R
16
45
17
44
18
43
19
42
GND
I/O 8R
I/O 7R
I/O 6R
N/C
1
60
2
59
3
58
4
57
5
56
6
55
7
54
8
BYTE OE L
BIT OE L
VCC
BYTE R/ W L
BIT R/ WL
N/C
9
10
11
12
13
CE L
GND
I/O 8L
I/O 7L
I/O 6L
N/C
IDT7099
PN80-1
53
80-Pin TQFP
Top View (3)
50
52
51
49
48
20
41
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
N/C
N/C
I/O5L
VCC
I/O 4L
I/O 3L
I/O2L
I/O1L
I/O 0L
GND
GND
I/O 0R
I/O 1R
I/O2R
I/O3R
VCC
I/O 4R
I/O5R
N/C
N/C
3007 drw 04
NOTES:
1. All VCC pins must be connected to power supply.
2. All ground pins must be connected to ground supply.
3. This text does not indicate the orientaion of the actual part-marking.
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
ABSOLUTE MAXIMUM RATINGS
Symbol
Rating
VTERM(2)
Terminal Voltage
with Respect to
GND
VTERM
(3)
TA
TBIAS
Terminal Voltage
Operating
Temperature
Temperature
Under Bias
TSTG
Storage
Temperature
IOUT
DC Output Current
Commercial
Grade
Ambient
Temperature
GND
VCC
Military
–55°C to +125°C
0V
5.0V ± 10%
Commercial
0°C to +70°C
0V
5.0V ± 10%
(1)
3007 tbl 02
Military
–0.5 to +7.0 –0.5 to +7.0
RECOMMENDED DC OPERATING
CONDITIONS
Unit
V
Symbol
–0.5 to VCC –0.5 to VCC
0 to +70
–55 to +125
Min.
Typ.
Max.
VCC
Supply Voltage
4.5
5.0
5.5
V
V
GND
Supply Voltage
0
0
0
V
°C
VIH
Input High Voltage
2.2
—
6.0 (2)
V
Input Low Voltage
–0.5(1)
—
0.8
VIL
Parameter
–55 to +125 –65 to +135
°C
–55 to +125 –65 to +150
°C
NOTES:
1. VIL > -1.5V for pulse width less than 10ns.
2. VTERM must not exceed Vcc + 0.5V.
mA
CAPACITANCE(1)
50
50
NOTES:
3007 tbl 01
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. VTERM must not exceed Vcc + 0.5V for more than 25% of the cycle time
or 10ns maximum, and is limited to < 20mA for the period of VTERM > Vcc
+ 0.5V.
Unit
V
3007 tbl 03
(TA = +25°C, F = 1.0MHZ) TQFP ONLY
Symbol Parameter
CIN
Input Capacitance
COUT
Output Capacitance
Condition(2)
Max. Unit
VIN = 3dV
9
pF
VOUT = 3dV
10
pF
3007 tbl 04
NOTES:
1. These parameters are determined by device characterization, but are not
production tested.
2. 3dV references the interpolated capacitance when the input and output
switch from 0V to 3V or from 3V to 0V.
6.23
3
IDT7099S
HIGH-SPEED 4K x 9 SYNCHRONOUS DUAL-PORT RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (VCC = 5.0V ± 10%)
IDT7099S
Symbol
Parameter
(1)
Test Condition
Min.
Max.
Unit
VCC = 5.5V, VIN = 0V to VCC
—
10
CE = VIH, VOUT = 0V to VCC
µA
—
10
µA
V
|ILI|
Input Leakage Current
|ILO|
Output Leakage Current
VOL
Output Low Voltage
IOL = 4mA
—
0.4
VOH
Output High Voltage
IOL = –4mA
2.4
—
V
NOTE:
1. Input leakages are undefined at VCC ≤ 2.0V.
3007 tbl 05
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(4) (VCC = 5V ± 10%)
IDT7099S15
IDT7099S20
IDT7099S25
Com'l. Only
Symbol
ICC
ISB1
ISB2
ISB3
ISB4
Parameter
Test Conditions
Version Typ.
Dynamic
CE = VIL
Operating
Outputs Open
Current (Both f = fmAX(1)
Ports Active)
Typ.
Max.
Typ.
Max.
Typ.
Max.
Unit
—
—
170
310
160
290
160
270
mA
180
300
170
290
160
270
—
—
Mil.
—
—
85
140
80
130
80
110
Com’l.
90
140
85
130
80
110
—
—
—
—
150
210
140
200
140
180
160
210
150
200
140
180
—
—
Mil.
—
—
10
20
10
20
10
20
mA
Com’l.
10
15
10
—
10
—
—
Mil.
—
—
145
200
135
190
135
170
mA
155
200
145
190
135
170
—
—
Com’l.
Standby
Current (One
Port—TTL
Level Inputs)
CE'A' = VIL and CE'B' = VIH (3)
Mil.
Active Port
Outputs Open,
f = fmAX(1)
Com’l.
Full Standby
Current (Both
Ports—CMOS
Level Inputs)
Both Ports CER
and CEL ≥ VCC – 0.2V
VIN ≥ VCC – 0.2V
or VIN ≤ 0.2V, f = 0(2)
Full Standby
Current (One
Port—CMOS
Level Inputs)
CE'A'<0.2V and CE'B '> VCC
-0.2V(3), VIN ≥ VCC – 0.2V or
VIN ≤ 0.2V, Active Port
Outputs Open, f = fmAX(1)
Mil Only
Max.
Mil.
Standby
CEL and
Current (Both CER = VIH
Ports—TTL
f = fmAX(1)
Level Inputs)
IDT7099S30
Com’l.
NOTES:
1. At f = fmax, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of the 1/tCLK, using
"AC TEST CONDITIONS" of input levels of GND to 3V.
2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4. Vcc = 5V, TA = 25°C for Typ, and are not production tested. ICC DC = 150mA (Typ).
mA
mA
3007 tbl 06
AC TEST CONDITIONS
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
3ns
Input Timing Reference Levels
1.5V
Output Reference Levels
Output Load
1.5V
Figures 1, 2, and 3
3007 tbl 07
6.23
4
IDT7099S
HIGH-SPEED 4K x 9 SYNCHRONOUS DUAL-PORT RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
8
5V
5V
893Ω
DATAOUT
6
893Ω
∆tCD
(Typical, ns)
DATAOUT
347Ω
30pF
- 10pF is the I/O capacitance
of this device, and 3pF is the
AC Test Load Capacitance
7
347Ω
5pF
5
4
3
2
3007 drw 05
Figure 1. AC Output Test load.
3007 drw 06
1
Figure 2. Output Test Load
(For tCLZ, tCHZ, tOLZ, and tOHZ).
Including scope and jig.
0
-1
20 40 60 80 100 120 140 160 180 200
Capacitance (pF)
3007 drw 07
Figure 3. Typical Output Derating (Lumped Capacitive Load).
AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE RANGE —
(READ AND WRITE CYCLE TIMING)
(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Military: VCC = 5V ± 10%, TA = -55°C to +125°C)
Commercial
7099S15
7099S20
Min. Max. Min. Max.
Military
7099S25
7099S20
7099S30
Symbol
Parameter
tCYC
Clock Cycle Time
tCH
Clock High Time
6
—
8
—
10
—
8
—
10
—
12
—
ns
tCL
Clock Low Time
6
—
8
—
10
—
8
—
10
—
12
—
ns
tCD
Clock High to Output Valid
—
15
—
20
—
25
—
20
—
25
—
30
ns
tS
Registered Signal Set-up Time
4
—
5
—
6
—
5
—
6
—
7
—
ns
tH
Registered Signal Hold Time
1
—
1
—
1
—
2
—
2
—
2
—
ns
20
—
20
—
Min. Max. Min. Max.
7099S25
25
—
20
—
Min. Max. Min. Max.
25
—
30
—
Unit
ns
tDC
Data Output Hold After Clock High
3
—
3
—
3
—
3
—
3
—
3
—
ns
tCKLZ
Clock High to Output Low-Z(1,2)
2
—
2
—
2
—
2
—
2
—
2
—
ns
tCKHZ
Clock High to Output High-Z(1,2)
—
7
—
9
—
12
—
9
—
12
—
15
ns
tOE
Output Enable to Output Valid
—
8
—
10
—
12
—
10
—
12
—
15
ns
0
—
0
—
0
—
0
—
0
—
0
—
ns
—
7
—
9
—
11
—
9
—
11
—
14
ns
tOLZ
Output Enable to Output Low-Z
tOHZ
Output Disable to Output High-Z(1,2)
tSCK
Clock Enable, Disable Set-up Time
4
—
5
—
6
—
5
—
6
—
7
—
ns
tHCK
Clock Enable, Disable Hold Time
2
—
2
—
2
—
3
—
3
—
3
—
ns
—
30
—
35
—
45
—
35
—
45
—
55
ns
(1,2)
Port-to-Port Delay
tCWDD
Write Port Clock High to Read
Data Delay
NOTES:
1. Transition is measured +/-200mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
6.23
3007 tbl 08
5
IDT7099S
HIGH-SPEED 4K x 9 SYNCHRONOUS DUAL-PORT RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CYCLE, EITHER SIDE
tCYC
tCH
CLK
tCL
tSCK
tHCK
tSCK
CLKEN
tS
tH
CE
W
W
BYTE R/
or BIT R/
ADDRESS
An
An + 1
An + 3
tCKHZ(1)
tDC
tCD
DATAOUT
An + 2
Qn
tCKLZ(1)
Qn + 1
Qn + 1
(1)
tOHZ
tOLZ
BYTE OE
or BIT OE
(1)
tOE
NOTE:
1. Transition is measured +/-200mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
3007 drw 08
TIMING WAVEFORM OF WRITE WITH PORT-TO-PORT READ (1,2,3)
CLK "A"
W "A"
R/
ADDR "A"
DATAIN "A"
(4)
NO
MATCH
MATCH
VALID
CLK "B"
W "B"
R/
ADDR "B"
NO
MATCH
MATCH
tCWDD
tCD
DATAOUT "B"
VALID
VALID
tDC
NOTES:
1. CEL = CER = VIL, CLKENL = CLKENR = VIL
2. OE = VIL for the reading port, port 'B'.
3. All timing is the same for left and right ports. Ports "A" may be either the left or right port. Port "B" is opposite from port "A".
4. R/W'A' was active (VIL) during the previous CLK'A', when enabled the write path.
6.23
3007 drw 09
6
IDT7099S
HIGH-SPEED 4K x 9 SYNCHRONOUS DUAL-PORT RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ-TO-WRITE CYCLE NO. 1, CE = VIH (2)
tCYC
tCH
CLK
tCYC
tCL
tCH
tCL
CLKEN
tS
tH
CE
W
W
BYTE R/
or BIT R/
ADDRESS
An
An + 1
DATAIN
An + 2
An + 3
Dn + 2
Dn + 3
(3)
tCD
DATAOUT
tCKLZ
tCKHZ
Qn
(3)
3007 drw 10
TIMING WAVEFORM OF READ-TO-WRITE CYCLE NO. 2, CE = VIL(2)
tCYC
tCH
CLK
tCYC
tCL
tCH
tCL
CLKEN
tS
CE
tH
(1)
W
W
BYTE R/
or BIT R/
ADDRESS
An
(1)
An + 1
An + 1
(1)
Dn + 1
DATAIN
An + 2
Dn + 2
(3)
tCD
DATAOUT
tCKLZ
(3)
tCKHZ
Qn
3007 drw 11
NOTES:
1. During dead cycle, if CE = VIL, then invalid data will be written into array. The An+1 must be rewritten on the following cycle.
2. OE low throughout.
3. Transition is measured +/-200mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
6.23
7
IDT7099S
HIGH-SPEED 4K x 9 SYNCHRONOUS DUAL-PORT RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTIONAL DESCRIPTION
registers without introducing clock skew for very fast interleaved memory applications.
The data inputs are gated to control on-chip noise in bussed
applications. The user must guarantee that the BYTE R/W and
BIT R/W pins are low for at least one clock cycle before any
write is attempted. A High on the CE input for one clock cycle
will power down the internal circuitry to reduce static power
consumption.
The device has separate Bit Write, Byte Write, Bit Enable,
and Byte Enable pins to allow for independent control.
The IDT7099 provides a true synchronous Dual-Port Static
RAM interface. Registered inputs provide very short set-up
and hold times on address, data, and all critical control inputs.
All internal registers are clocked on the rising edge of the clock
signal. An asynchronous output enable is provided to ease
asynchronous bus interfacing.
The internal write pulse width is dependent on the low to
high transitions of the clock signal allowing the shortest
possible realized cycle times. Clock enable inputs are
provided to stall the operation of the address and data input
TRUTH TABLE I – READ/WRITE CONTROL(1)
Inputs
(3)
Synchronous
CLK
Asynchronous
Bit R/W
Byte OE
Outputs
CE
Byte R/W
Bit OE
h
h
h
X
X
High-Z
High-Z
Deselected, Power Down, Data I/O Disabled
h
l
h
X
X
DATAIN
High-Z
Deselected, Power Down, Byte Data Input Enabled
h
h
l
X
X
High-Z
DATAIN
Deselected, Power Down, Bit Data Input Enabled
h
l
l
X
X
DATAIN
DATAIN
Deselected, Power Down, Data Input Enabled
l
l
h
X
L
DATAIN DATAOUT
Write Byte, Read Bit
l
l
h
X
H
DATAIN
Write Byte Only
l
h
l
L
X
l
h
l
H
X
I/O0-7
I/O8
Mode
High-Z
DATAOUT DATAIN
Read Byte, Write Bit
High-Z
DATAIN
Write Bit Only
DATAIN
DATAIN
Write Byte, Write Bit
l
l
l
X
X
l
h
h
L
L
DATAOUT DATAOUT
l
h
h
H
L
High-Z DATAOUT
l
h
h
L
H
l
h
h
H
H
DATAOUT High-Z
High-Z
High-Z
Read Byte, Read Bit
Read Bit Only
Read Byte Only
Data I/O Disabled
3007 tbl 09
(1)
TRUTH TABLE II – CLOCK ENABLE FUNCTION TABLE
Inputs
Operating Mode
CLK(3)
Load "1"
Register Inputs
Register Outputs
CLKEN(2)
ADDR
DATAIN
ADDR
DATAOUT
l
h
h
H
H
Load "0"
l
l
l
L
L
Hold (do nothing)
h
X
X
NC
NC
H
X
X
NC
NC
X
NOTES:
3007 tbl 10
1. 'H' = High voltage level steady state, 'h' = High voltage level one set-up time prior to the low-to-high clock transition, 'L' = Low voltage level steady state
'l' = Low voltage level one set-up time prior to the Low-to-High clock transition, 'X' = Don't care, 'NC' = No change
2. CLKEN = VIL must be clocked in during Power-Up.
3. Control signals are initialted and terminated on the rising edge of the CLK, depending on their input level. When R/W and CE are low, a write cycle is initiated
on the low-to-high transition of the CLK. Termination of a write cycle is done on the next low-to-high transistion of the CLK.
6.23
8
IDT7099S
HIGH-SPEED 4K x 9 SYNCHRONOUS DUAL-PORT RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT
XXXX
A
999
A
A
Device
Type
Power
Speed
Package
Process/
Temperature
Range
Blank
Commercial (0°C to +70°C)
B
Military (–55°C to +125°C)
Compliant to MIL-STD-883, Class C
J
G
PF
68-pin PLCC (J68-1)
68-pin PGA (G68-1)
80-pin TQFP (PN80-1)
15
20
25
30
Commercial Only
S
Standard Power
7099
36K (4K x 9-Bit) Synchronous Dual-Port RAM
Speed in nanoseconds
Military Only
3007 drw 12
6.23
9
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