Cirrus CS43L36 Low-power, high-performance audio dac with class h headphone driver Datasheet

CS43L36
Low-Power, High-Performance Audio DAC with Class H Headphone Drivers
System Features
•
•
•
•
• Integrated fractional-N PLL
— Increases system-clock flexibility for audio processing
Stereo headphone (HP) output with 114-dB dynamic range
— Reference clock sourced from I2S/TDM bit clock
— Class H HP amplifier with four-level automatic or
manual supply adjust
• Bypassable SRCs for maximum flexibility
— –98-dB THD+N into 30  with 10-mW output power • Attenuation, mute, and volume controls for each output
— 2 x 35 mW output power into 30 with 0.018%
• Integrated power management
THD+N
— Digital core operates from either an external 1.2-V
Load detection
supply or LDO from a 1.8-V supply.
— Headphone load detection of 15 or 30 
— Step-down charge pump improves HP efficiency
— Line-level load (3 k) with capacitance detection
— Independent peripheral power-down controls
Headphone insertion/removal detection with WAKE
— Standby operation from VP with all other supplies
powered off
Audio serial port (ASP)
— VP monitor to detect and report brownout conditions
— I2S (two channels) or TDM (up to four channels)
— Low-impedance switching suppresses ground-noise
— Slave or Hybrid-Master Mode (bit-clock slave and
LRCK/FSYNC derived from bit clock)
Applications
— Supports up to 32-bit audio
• Ultrabooks, tablets, and smartphones
— Sample rate support for 8 to 192 kHz
• Digital headsets
— I2C control with interrupt output
VA
DIGLDO_PDN
CS43L36
Analog Core
PLL
Clock
Gen
ASP_SCLK
ASP_SDIN
ASP_LRCK
/FSYNC
HS3
HS3_REF
VL
VD_FILT
LDO
with
Bypass
VP
POR
LDO VP_CP
VCP
Step -Down
+VCP_FILT
Inverting
–VCP_FILT
Digital
Core
MCLK
SRC
Digital Audio
Input
SRC
Interpolator
and
Volume
Control
Interpolator
and
Volume
Control
HPSENSA *
+VCP_FILT
Multibit 
Modulator
DAC
–
HPOUTA
+
–VCP_FILT
HPSENSB *
+VCP_FILT
Multibit 
Modulator
DAC
–
HPOUTB
+
–VCP_FILT
Pseudodifferential
Input
Headset
Impedance
Detect and
Switches
* WLCSP
package only
I 2C Slave
TIP_SENSE
Headphone Detect
INT
http://www.cirrus.com
WAKE
AD0 AD1 SDA SCL
Copyright  Cirrus Logic, Inc. 2014–2018
(All Rights Reserved)
DS1081F3
JAN ’18
CS43L36
General Description
The CS43L36 is a low-power, high dynamic-range, stereo audio DAC with integrated I2S/I2C/TDM interfaces designed for
portable applications. The CS43L36 features support for up to 32-bit audio inputs and includes bypassable SRCs.
The bypassable fractional-N PLL sourced from the ASP SCLK allows for maximum flexibility in any system.
There is independent attenuation on each input along with volume adjustment and mute control.
The CS43L36 is available in 49-ball WLCSP package and a 40-pin QFN package, both supporting an extended
commercial operational temperature range of –40°C to +85°C.
DS1081F3
2
CS43L36
Table of Contents
1 Pin Assignments and Descriptions . . . . . . . . . . . . . . . . . . . . . . 4
1.1 WLCSP Pin Out (Through-Package View) . . . . . . . . . . . . . . 4
1.2 QFN Pin Out (Through-Package View) . . . . . . . . . . . . . . . . . 5
1.3 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.4 Electrostatic Discharge (ESD) Protection Circuitry . . . . . . . . 7
2 Typical Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1 Electromagnetic Compatibility (EMC) Circuitry . . . . . . . . . . 11
3 Characteristics and Specifications . . . . . . . . . . . . . . . . . . . . . 12
Table 3-1. Parameter Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Table 3-2. Recommended Operating Conditions . . . . . . . . . . . . . . . . .12
Table 3-3. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . .12
Table 3-4. Combined DAC Digital, On-Chip Analog, and HPOUTx
Filter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Table 3-5. DAC High-Pass Filter (HPF) Characteristics . . . . . . . . . . . .13
Table 3-6. SDIN to HPOUTx with SRC-Enabled Datapath
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Table 3-7. Serial Data In-to-HPOUTx Characteristics . . . . . . . . . . . . . .14
Table 3-8. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Table 3-9. Power-Supply Rejection Ratio (PSRR) Characteristics . . . .15
Table 3-10. Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Table 3-11. Register Field Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Table 3-12. Digital Audio Interface Timing Characteristics . . . . . . . . . .17
Table 3-13. I2C Slave Port Characteristics . . . . . . . . . . . . . . . . . . . . . .17
Table 3-14. Digital Interface Specifications and Characteristics . . . . . .19
4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.1 Digital Volume Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.2 Analog Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.3 Class H Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.4 Clocking Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.5 Audio Serial Port (ASP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.6 Sample-Rate Converters (SRCs) . . . . . . . . . . . . . . . . . . . . 40
4.7 Headset Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.8 Plug Presence Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.9 Power-Supply Considerations . . . . . . . . . . . . . . . . . . . . . . . 43
4.10 Control-Port Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.11 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.12 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
5 System Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
5.1 Power-Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
5.2 Power-Down Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
5.3 Page 0x30 Read Sequence . . . . . . . . . . . . . . . . . . . . . . . . 51
5.4 PLL Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
5.5 VD_FILT/VL ESD Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
6 Register Quick Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6.1 Global Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6.2 Power-Down and Headset-Detect Registers . . . . . . . . . . . . 53
6.3 Clocking Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
6.4 Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
6.5 Fractional-N PLL Registers . . . . . . . . . . . . . . . . . . . . . . . . . 55
6.6 HP Load Detect Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 56
6.7 Headset Interface Registers . . . . . . . . . . . . . . . . . . . . . . . . 56
6.8 DAC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.9 HP Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.10 Class H Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.11 Mixer Volume Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.12 AudioPort Interface Registers . . . . . . . . . . . . . . . . . . . . . . 58
6.13 SRC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
6.14 Serial Port Receive Registers . . . . . . . . . . . . . . . . . . . . . . 58
6.15 ID Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
7 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
7.1 Global Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
7.2 Power Down and Headset Detects . . . . . . . . . . . . . . . . . . . 62
7.3 Clocking Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
7.4 Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
7.5 Fractional-N PLL Registers . . . . . . . . . . . . . . . . . . . . . . . . . 71
7.6 HP Load-Detect Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 73
DS1081F3
7.7 Headset Interface Registers . . . . . . . . . . . . . . . . . . . . . . . . . 73
7.8 DAC Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
7.9 HP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
7.10 Class H Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
7.11 Volume Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
7.12 AudioPort Interface Registers . . . . . . . . . . . . . . . . . . . . . . 77
7.13 SRC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
7.14 Serial Port Receive Registers . . . . . . . . . . . . . . . . . . . . . . 78
7.15 ID Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
8 PCB Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
8.1 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
8.2 Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
8.3 QFN Thermal Pad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
9 Plots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
9.1 Digital Filter Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
10 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
10.1 WLCSP Package Dimensions . . . . . . . . . . . . . . . . . . . . . . 86
10.2 QFN Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . 87
11 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
12 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
13 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
14 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
3
CS43L36
1 Pin Assignments and Descriptions
1 Pin Assignments and Descriptions
This section shows pin assignments and describes pin functions.
1.1 WLCSP Pin Out (Through-Package View)
A1
A2
A3
A4
A5
A6
A7
SDA
SCL
VL
TSTO
ASP_SDIN
TSTO
VD_FILT
B1
B2
B3
B4
B5
B6
B7
VA
AD1
GNDL
ASP_SCLK
ASP_LRCK/
FSYNC
GNDD
INT
C1
C2
C3
C4
C5
C6
C7
FILT+
GNDA
AD0
VL_SEL
RESET
WAKE
TSTI
D1
D2
D3
D4
D5
D6
D7
TSTI
TSTI
TSTI
DIGLDO_PDN
HPSENSA
VCP
VP
E1
E2
E3
E4
E5
E6
E7
TSTI
TSTI
TSTO
TIP_SENSE
HPOUTA
+VCP_FILT
FLYP
F1
F2
F3
F4
F5
F6
F7
TSTI
TSTI
TSTO
TSTO
HPSENSB
GNDCP
FLYC
G1
G2
G3
G4
G5
G6
G7
GNDHS
HS3
TSTI
HS3_REF
HPOUTB
–VCP_FILT
FLYN
Headphone
Digital I/O
Charge
Pump
Power
General
Ground
Test
Figure 1-1. WLCSP Pin Diagram (Through-Package View)
DS1081F3
4
CS43L36
1.2 QFN Pin Out (Through-Package View)
VL_SEL
VD_FILT
GNDD
TSTO
ASP_SDIN
ASP_LRCK/FSYNC
ASP_SCLK
TSTO
TSTI
VL
40
39
38
37
36
35
34
33
32
31
1.2 QFN Pin Out (Through-Package View)
RESET
1
30
GNDL
INT
2
29
SCL
WAKE
3
28
SDA
DIGLDO_PDN
4
27
AD0
TSTI
5
26
AD1
VP
6
25
VA
VCP
7
24
FILT+
FLYP
8
23
GNDA
FLYC
9
22
TSTO
+VCP_FILT
10
21
GNDHS
13
14
15
16
17
18
19
20
HPOUTA
HPOUTB
TIP_SENSE
HS3_REF
TSTO
TSTO
HS3
12
GNDCP
–VCP_FILT
11
FLYN
Top-Down (Through Package ) View
40-Pin QFN Package
Figure 1-2. QFN Pin Diagram
1.3 Pin Descriptions
Table 1-1. Pin Descriptions
Pin Name
CSP
Pin #
QFN Power
I/O
Pin # Supply
Pin Description
Internal
Connection1
Driver
Receiver
State at
Reset
—
—
—
Input
—
—
—
Input
—
—
—
—
—
—
—
Input
—
Hi-Z
—
—
Headphone
HS3_REF
G4
17
HS3
G2
20
HPOUTA
HPOUTB
HPSENSA
HPSENSB
TIP_SENSE
E5
G5
14
15
D5
F5
—
—
E4
16
DS1081F3
VP
I
Headset Connection Reference. Input to
pseudodifferential HP output reference
VP
I Headset Connections. Input to headset and
mic-button detection functions
±VCP_ O Headphone Audio Output. Ground-centered audio
FILT
output.
±VCP_ I Headphone Audio Sense Input. Audio sense input.
FILT
WLCSP package only
VP
I Tip Sense. Output can be set to wake the system.
Independently configurable to be debounced on plug
and unplug events.
5
CS43L36
1.3 Pin Descriptions
Table 1-1. Pin Descriptions (Cont.)
Pin Name
CSP
Pin #
QFN Power
I/O
Pin # Supply
Internal
Connection1
Driver
Receiver
I2C Address Input. Address pins for I2C Instance ID
[1:0] input.
—
—
I/O ASP Left/Right Clock or Frame Sync. Left or right
word select, or frame start sync for the ASP interface.
—
CMOS
output
—
—
—
CMOS
output
—
—
Hysteresis
on CMOS
input
Hysteresis
on CMOS
input
Hysteresis
on CMOS
input
Hysteresis
on CMOS
input
Hysteresis
on CMOS
input
—
Pin Description
State at
Reset
Digital I/O
AD0
AD1
C3
B2
27
26
VL
ASP_LRCK/
FSYNC
B5
35
VL
ASP_SCLK
B4
34
VL
ASP_SDIN
A5
36
VL
DIGLDO_PDN
D4
4
VP
INT
B7
2
VP
O Interrupt output. Programmable, open-drain,
active-low programmable interrupt output.
—
RESET
C5
1
VP
I
Reset. Hardware reset.
—
SCL
A2
29
VL
I
I2C Clock. Clock input for the I2C interface.
—
SDA
A1
28
VL
VL_SEL
C4
40
VP
WAKE
C6
3
VP
I
I
ASP/ Serial Data Clock. Serial data-shift clock for
the ASP interface in I2S/TDM Mode. Source clock
used for internal master clock generation.
I/O ASP Serial Data Input. Serial data input and output
in serial data input for the ASP interface in I2S/TDM
mode.
I Digital LDO Power Down. Digital core logic LDO
power down.
I/O I2C Input/Output. I2C input and output.
I
VL Supply Voltage Select. Select for VL power
supply voltage level. Connect to VP for 1.8-V VL
supply, connect to GNDD for 1.2-V VL supply
O Wake up. Programmable, open-drain, active-low
output. This outputs the state of the Mic S0 or HP
wake detect.
—
—
—
CMOS
open-drain
output
Hysteresis
—
on CMOS
input
—
Hysteresis
on CMOS
input
CMOS
Hysteresis
open-drain on CMOS
output
input
—
Hysteresis
on CMOS
input
Hi-Z,
—
CMOS
open-drain
output
Input
Input
Input
Input
Input
Output
Input
Input
Input
Input
Output
Charge Pump
–VCP_FILT
G6
13
VCP/
VP2
+VCP_FILT
E6
10
VCP/
VP2
FLYC
F7
9
VCP/
VP2
FLYN
G7
11
FLYP
E7
8
VCP/
VP2
VCP/
VP2
O Inverting Charge Pump Filter Connection. Power
supply for the inverting charge pump that provides
the negative rail for the HP amplifier.
O Step Down Charge Pump Filter Connection.
Power supply for the step down charge pump that
provides the positive rail for the HP amplifier.
O Charge Pump Cap Common Node. Common
positive node for the HP amplifiers’ step-down and
inverting charge pumps’ flying capacitors.
O Charge Pump Cap Negative Node. Negative node
for the inverting charge pump’s flying capacitor.
O Charge Pump Cap Positive Node. Positive node for
HP amps’ step-down charge pump’s flying capacitor.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Power
FILT+
C1
24
VA
I
VA
B1
25
N/A
I
VCP
D6
7
N/A
I
VD_FILT
A7
39
N/A
I
VL
A3
31
N/A
I
DS1081F3
Positive Voltage Reference. Positive reference
voltage for internal sampling circuits.
Analog Power Supply. Power supply for the internal
analog section.
Charge Pump Power. Power supply for the internal
HP amplifiers charge pump.
1.2-V Digital Core Power Supply. Power supply for
internal digital logic.
I/O Power Supply. Power supply for external
interface and internal digital logic.
6
CS43L36
1.4 Electrostatic Discharge (ESD) Protection Circuitry
Table 1-1. Pin Descriptions (Cont.)
Pin Name
CSP
Pin #
QFN Power
I/O
Pin Description
Pin # Supply
6
N/A
I High Voltage Interface Supply. Power supply for
VP
D7
GNDA
C2
23
N/A
I
GNDL
B3
30
N/A
I
GNDHS
G1
21
N/A
I
GNDCP
F6
12
N/A
I
GNDD
B6
38
N/A
I
Driver
Receiver
—
—
State at
Reset
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Internal
Connection1
—
high voltage interface.
Ground
Analog Ground. Ground reference for the internal
analog section.
Digital Ground. Ground reference for interface
section.
Headset Ground. Ground reference for the internal
analog section.
Charge Pump Ground. Ground reference for the
internal HP amplifiers charge pump.
Digital Ground. Ground reference for the internal
digital circuits.
Test
TSTI
TSTI
TSTI
TSTI
TSTO
TSTO
C7
5
D3
32
D1, E1,
E2, F1,
F2, G3
D2
—
—
A4, A6 33,37
E3, F3, 18,19,
F4
22
N/A
VL
VP
I
I
I
Test input. Connect to GNDD
Test input. Connect to GNDD.
Test input. Connect to GNDA.
—
—
—
—
—
—
—
—
—
—
—
—
VA
VL
VP
I Test input. Connect to GNDA.
O Test output. No connection
O Test output. No connection
—
—
—
—
—
—
—
—
—
—
—
—
1.There are no internal connections for the CS43L36.
2.The power supply is determined by ADPTPWR setting (see Section 7.10.1). VP is used if ADPTPWR = 001 (VP_CP Mode) or when necessary for
ADPTPWR = 111 (Adapt-to-Signal Mode).
1.4 Electrostatic Discharge (ESD) Protection Circuitry
ESD-sensitive device. The CS43L36 is manufactured on a CMOS process. Therefore, it is generically
susceptible to damage from excessive static voltages. Proper ESD precautions must be taken while
handling and storing this device. This device is qualified to current JEDEC ESD standards.
Fig. 1-3 provides a composite view of the ESD domains showing the ESD protection paths between each pad and the
substrate (GNDA) and the interrelations between some domains. Note that this figure represents the structure for the
internal protection devices and that additional protections can be implemented as part of the integration into the board.
VL
GNDL
*
VD_FILT
GNDD
Substrate
(GNDA)
____________________ _______________
VL/GNDA Domain
VD_FILT/GNDA
Domain
GNDA
VA
*
VCP
VP/GNDA Domain
GNDHS
____________________ __________
VA/GNDA Domain
VCP/GNDA
Domain
Note: The asterisks indicate the pads with which the individual
pins from the corresponding domains are associated. These
pins are listed in Table 1-2.
–VCP_FILT/+VCP_FILT Domain
VP
+VCP_FILT
*
*
GNDCP
Substrate
(GNDA)
*
VP/–VCP_FILT Domain
–VCP_FILT
Figure 1-3. Composite ESD Topology
DS1081F3
7
CS43L36
1.4 Electrostatic Discharge (ESD) Protection Circuitry
Table 1-2 shows the individual ESD domains and lists the pins associated with each domain.
Table 1-2. ESD Domains
ESD
Signal Name
Domain (See * in Topology Figures for Pad)
VL/
AD0
GNDA 1 AD1
ASP_LRCK/FSYNC
GNDL
SCL
SDA
TSTO
TSTO
TSTI
ASP_SCLK
ASP_SDIN
VD_FILT
VL
VD_FILT/ VD_FILT
GNDA GNDD
TSTI
Topology
VL
GNDL
VD_FILT
*
Substrate
(GNDA)
VL
GNDD
VD_FILT
*
Substrate
(GNDA)
VA/
GNDA
FILT+
GNDA
TSTI
VA
VA
GNDA
*
Substrate
(GNDA)
VCP/
GNDA
VCP
VCP
Substrate
(GNDA)
DS1081F3
8
CS43L36
1.4 Electrostatic Discharge (ESD) Protection Circuitry
Table 1-2. ESD Domains (Cont.)
ESD
Signal Name
Domain (See * in Topology Figures for Pad)
VP/
GNDHS
GNDA HS3
TSTO
TSTI
TSTI
TSTO
TSTO
TSTI
VP
VL_SEL
INT
WAKE
RESET
DIGLDO_PDN
+VCP_ +VCP_FILT
FILT/ –VCP_FILT
–VCP_ FLYN
HPSENSA
FILT
HPSENSB
HPOUTA
HPOUTB
GNDCP
VP/
FLYC
–VCP_ FLYP
HS3_REF
FILT
TSTO
TSTI
TIP_SENSE
Topology
VP/GNDA Domain
GNDHS
VP
+VCP_FILT/–VCP_FILT Domain
+VCP_FILT
*
*
GNDCP
Substrate
(GNDA)
Substrate
(GNDA)
*
VP/–VCP_FILT Domain
–VCP_FILT
1.See Section 5.5 for additional information regarding VD_FILT andVL.
DS1081F3
9
CS43L36
2 Typical Connections
2 Typical Connections
CS43L36
WAKE
PMU
Headset Connector
R P_ W
VL_SEL
Note 1
Battery
(3.0–5.0 V)
1.8 V
1.8 V/1.2 V
See
DIGLDO_PDN
and VL_SEL
Configurations
VL or VP
2.2 µF
VL or VP
DIGLDO_PDN
VL
VD_FILT
TIP_SENSE
VA
Headphone
Output Filter
HPSENSA
HS3
HS3_REF
*
RP_ I
HPSENSB
HPOUTB
Note 2 HPOUTA
RP_ I2 C
Note 1
GNDHS
Note 3
To External
Microphone Input
and Bias Circuitry
(AFE/PGA + ADC)
INT
RESET
SCL
SDA
Applications
Processor
TSTO
TSTI
X
AD0
AD1
DIGLDO_PDN and VL_SEL Configurations
ASP_LRCK/FSYNC
DIGLDO_PDN = 0 (GNDD)
VL_SEL = 1 (3.0 to 5.0 V)
Battery
(VP = 3.0 to 5.0V)
ASP_SCLK
ASP_SDIN
GNDD
1.8 V
GNDL
0.1 µF
VCP
2.2 µF
2.2 µF
*
*
*
2.2 µF
*
FLYC
*
FLYN
DIGLDO_PDN = 1 (3.0 to 5.0 V)
VL_SEL = 1 (3.0 to 5.0 V)
Battery
(VP = 3.0 to 5.0V)
VL_SEL
DIGLDO_PDN
1.8 V
*
Note 6
FILT+
10 µF
Key for Capacitor Types Required:
*
Use low ESR, X7R/X5R capacitors
** Use C0G or NPO capacitors
If no type symbol is shown next to a
capacitor, any type may be used.
VD_FILT
*
VP
4.7 µF
VL_SEL
DIGLDO_PDN
VL
*
1 µF
GNDCP
FLYP
2.2 µF
Note 5
1.2 V
+VCP_FILT
–VCP_FILT
2.2 µF
Note 4
All external passive component
values shown are nominal.
Note: The headset GND
connection must be made
via the HS3 and HS3_REF
connections and not to the
PCB GND.
0.1 µF
*
*
VL
DIGLDO_PDN = 0 (GNDD)
VL_SEL = 0 (GNDD)
VL_SEL
DIGLDO_PDN
1.2 V
0.1 µF
*
1 µF
VD_FILT
VL
VD_FILT
*
GNDA
Figure 2-1. Typical Connection Diagram
Notes:
1. RP_I and RP_W values can be determined by the INT and WAKE pin specifications in Table 3-14.
2. HPSENSA and HPSENSB are supported only on the WLCSP package.
3. RP_I2C values can be determined by the I2C pull-up resistance specification in Table 3-13.
4. The headphone amplifier’s output power and distortion ratings use the nominal capacitances shown. Larger capacitance reduces ripple on
the internal amplifiers’ supplies and, in turn, reduces distortion at high-output power levels. Smaller capacitance may not reduce ripple
enough to achieve output power and distortion ratings. Because actual values of typical X7R/X5R ceramic capacitors deviate from nominal
values by a percentage specified in the manufacturer’s data sheet, capacitors must be selected for minimum output power and maximum
distortion required. Higher value capacitors than those shown may be used, however lower value capacitors must not (values can vary from
the nominal by ±20%). See Section 2.1.2 for additional details.
5. Series resistance in the path of the power supplies must be avoided. Any voltage drop on VCP directly affects the negative charge-pump
supply (–VCP_FILT) and clips the audio output.
6. Lowering capacitance below the value shown affects PSRR, THD+N performance, and interchannel isolation and intermodulation.
DS1081F3
10
CS43L36
2.1 Electromagnetic Compatibility (EMC) Circuitry
2.1 Electromagnetic Compatibility (EMC) Circuitry
The circuit in Fig. 2-2 may be applied to signals not local to the CS43L36 (i.e., that traverse significant distances) for EMC.
L1
L2
To/from
other
circuits
To/from DUT
D1
27 pF
X7R
Notes:
L1 and L2: Ferrite:
fTransition = 30–100 MHz
DCR = 0.09–0.30 
D1: Transorb:
VBreakdown > Normal operating peak
voltage of signal
Figure 2-2. Optional EMC Circuit
2.1.1
Low-Profile Charge-Pump Capacitors
In the typical connection for analog mics (Fig. 2-1), the recommended capacitor values for the charge-pump circuitry are
2.2 µF, rated as X7R/X5R or better. The following low-profile versions of these capacitors are suitable for the application:
•
Description: 2.2 µF ±20%, 6.3 V, X5R, 0201
•
Manufacturer, Part Number: Murata, GRM033R60J225ME47, nominal height = 0.3 mm
•
Manufacturer, Part Number: AVX, 02016D225MAT2A, nominal height = 0.33 mm
Note:
2.1.2
Although the 0201 capacitors described are suitable, larger capacitors such as 0402 or larger may provide
acceptable performance.
Ceramic Capacitor Derating
Note 4 in Fig. 2-1 highlights that ceramic capacitor derating factors can significantly affect in-circuit capacitance values
and, in turn, CS43L36 performance. Under typical conditions, numerous types and brands of large-value ceramic
capacitors in small packages exhibit effective capacitances well below their ±20% tolerance, with some being derated by
as much as –50%. These same capacitors, when tested by a multimeter, read much closer to their rated value. A similar
derating effect has not been observed with tantalum capacitors.
The derating observed varied with manufacturer and physical size: Larger capacitors performed better, as did ones from
Kemet Electronics Corp. and TDK Corp. of any size. This derating effect is described in data sheets and in applications
notes from capacitor manufacturers. For instance, as DC and AC voltages are varied from the standard test points (applied
DC and AC voltages for standard test points versus PSRR test are 0 and 1 VRMS @ 1 kHz versus 0.9 V and ~1 mVRMS
@ 20 Hz–20 kHz), it is documented that the capacitances vary significantly.
DS1081F3
11
CS43L36
3 Characteristics and Specifications
3 Characteristics and Specifications
Table 3-1 defines parameters as they are characterized in this section.
Table 3-1. Parameter Definitions
Parameter
Definition
Dynamic range The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. A
signal-to-noise ratio measurement over the specified bandwidth made with a –60 dB signal; 60 dB is added to resulting
measurement to refer the measurement to full scale. This technique ensures that distortion components are below the noise
level and do not affect the measurement. This measurement technique has been accepted by the Audio Engineering Society,
AES17–1991, and the Electronic Industries Association of Japan, EIAJ CP–307. Dynamic range is expressed in decibel units.
Idle channel
The rms value of the signal with no input applied (properly back-terminated analog input, digital zero, or zero modulation input).
noise
Measured over the specified bandwidth.
Interchannel
A measure of cross talk between the left and right channel pairs. Interchannel isolation is measured for each channel at the
isolation
converter's output with no signal to the input under test and a full-scale signal applied to the other channel. Interchannel
isolation is expressed in decibel units.
Load
The recommended minimum resistance and maximum capacitance required for the internal op-amp's stability and signal
resistance and integrity. The load capacitance effectively moves the band-limiting pole of the amp in the output stage. Increasing load
capacitance
capacitance beyond the recommended value can cause the internal op-amp to become unstable.
Offset error
The deviation of the midscale transition (111…111 to 000…000) from the ideal.
Output offset
The DC offset voltage present at the amplifier’s output when its input signal is in a mute state. The offset exists due to CMOS
voltage
process limitations and is proportional to analog volume settings. When measuring the offset out the headphone amplifier, the
headphone amplifier is ON.
Total harmonic The ratio of the rms sum of distortion and noise spectral components across the specified bandwidth (typically 20 Hz–20 kHz)
distortion +
relative to the rms value of the signal. THD+N is measured at –1 and –20 dBFS for the analog input and at 0 and –20 dB for
noise (THD+N) the analog output, as suggested in AES17–1991 Annex A. THD+N is expressed in decibel units.
Table 3-2. Recommended Operating Conditions
Test conditions: GNDA = GNDL = GNDCP = 0 V; voltages are with respect to ground.
Parameters
Symbol
VCP
Minimum 1
1.66
Maximum 1
1.94
Unit
V
LDO regulator for digital 2 DIGLDO_PDN = 0 and VL_SEL = 0
Serial interface control port DIGLDO_PDN = 0 and VL_SEL = 0
VL_SEL = 1
Analog
Battery supply
External voltage
TIP_SENSE pin
applied to pin 4,5
±VCP_FILT domain pins 6
VL domain pins
VA domain pins
VP domain pins
Ambient temperature
VD_FILT
1.10
1.30
V
DC power
supply
Charge pump
VL
VL
VA
VP
VINHI
VVCPF
VVL
VVA
VVP
TA
1.10
1.30
1.66
1.94
1.66
1.94
5.25
2.50 3
–VCP_FILT – 0.3
VP + 0.3
–VCP_FILT – 0.3 +VCP_FILT + 0.3
–0.3
VL + 0.3
–0.3
VA + 0.3
–0.3
VP + 0.3
–40
+85
V
V
V
V
V
V
V
V
V
C
1.Device functional operation is guaranteed within these limits; operation outside them is not guaranteed or implied and may reduce device reliability.
2.If DIGLDO_PDN is deasserted, no external voltage must be applied to VD_FILT.
3.Although device operation is guaranteed down to 2.5 V, device performance is guaranteed only down to 3.0 V. The following are affected when
VP < 3.0 V: charge pump LDO, TIP_SENSE threshold.
4.The maximum over/undervoltage is limited by the input current.
5.Table 1-1 lists the power supply domain in which each CS43L36 pin resides.
6.±VCP_FILT is specified in Table 3-8.
Table 3-3. Absolute Maximum Ratings
Test conditions: GNDA = GNDL = GNDCP = 0 V; voltages are with respect to ground.
Parameters
Symbol
Minimum Maximum Unit
Charge pump, LDO, serial/control, analog (see Section 4.9) VL, VA, VCP
–0.3
2.33
V
Digital core VD_FILT
–0.3
1.55
V
Battery
VP
–0.3
6.3
V
Iin
±10
mA
Input current 1
—
Ambient operating temperature (power applied)
TA
–50
+115
°C
Storage temperature
Tstg
–65
+150
°C
Caution: Stresses beyond “Absolute Maximum Ratings” levels may cause permanent damage to the device. These levels are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated in Table 3-2, “Recommended Operating
Conditions” is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC power supply
1.Any pin except supply pins. Transient currents of up to ±100 mA on analog input pins do not cause SCR latch-up.
DS1081F3
12
CS43L36
3 Characteristics and Specifications
Table 3-4. Combined DAC Digital, On-Chip Analog, and HPOUTx Filter Characteristics
Test conditions (unless specified otherwise): TA = +25°C; MCLK = 12 MHz, MCLK_SRC_SEL = 0, FsINT = 48 kHz; path is internal routing engine to
HPOUTx, analog and digital gains are all set to 0 dB; HPF disabled.
Parameter 1
Passband
–0.05-dB corner
–3.0-dB corner
Passband ripple (0.417x10–3 FsINT to 0.417 FsINT; normalized to 0.417x10–3 FsINT)
Stopband attenuation (0.545 FsINT to FsINT)
Total group delay 2
Minimum
—
—
–0.04
60
—
Typical
0.48
0.50
—
—
5.35/FsINT
Maximum
—
—
0.063
—
—
Unit
FsINT
FsINT
dB
dB
s
1. Response scales with FsINT (based on internal MCLK). Specifications are normalized to FsINT and denormalized by multiplying by FsINT.
2.Informational only; group delay cannot be measured for this block by itself. An additional 5.5/Fsint group delay may be present through the serial ports
and internal audio bus.
Table 3-5. DAC High-Pass Filter (HPF) Characteristics
Test conditions (unless specified otherwise) Analog and digital gains are all set to 0 dB; TA = +25°C.
Parameter 1
Passband
–0.05-dB corner
–3.0-dB corner
Passband ripple (0.417x10–3 FsINT to 0.417 FsINT; normalized to 0.417 FsINT)
Phase deviation @ 0.453x10–3 FsINT
Filter settling time 2
Minimum
—
—
—
—
—
Typical
0.180x10–3
19.5x10–6
—
2.45
24.5x103/FsINT
Maximum
—
—
0.01
—
—
Unit
FsINT
FsINT
dB
°
s
1.Response scales with FsINT (internal sample rate, based on MCLK). Specifications are normalized to FsINT and are denormalized by multiplying by FsINT.
2.Required time for the magnitude of the DC component present at the output of the HPF to reach 5% of the applied DC signal.
Table 3-6. SDIN to HPOUTx with SRC-Enabled Datapath Characteristics
Test conditions (unless specified otherwise): LRCK = FsINT = FsEXT = 48 kHz; MCLK = 12 MHz; HPF disabled; passband/stopband levels normalized to
0.417x10–3 FsEXT; entire path characteristics including serial port + SRC + DAC + HPOUT.
Parameters 1
Passband
–0.2-dB corner
–3.0-dB corner
Passband ripple (0.417x10–3 FsEXT to 0.417 FsEXT; normalized to 0.417x10–3 FsEXT)
Response at 0.5 FsEXT
Stopband rejection from 0.480 FsEXT to 0.524 FsEXT
Stopband rejection from 0.524 FsEXT to 0.545 FsEXT
Stopband rejection from 0.545 FsEXT to 3 FsEXT
Square wave overshoot
Group delay, bark-weighted average
FsEXT  48 kHz
Group delay
FsEXT  88.2 kHz)
SRC disabled group delay 2
Minimum
Typical
Maximum Unit
—
0.463
—
FsEXT
FsEXT
—
0.466
—
–0.16
—
0.02
dB
—
—
–54.9
dB
55
—
—
dB
39
—
—
dB
60
—
—
dB
—
—
3.1
dB
s
—
—
34/FsEXT
—
(15.8 ± 1.5)/FsEXT + 10.3/FsINT
—
s
(20.1 ± 1)/FsEXT + (11.6 ± 0.5)/FsINT
—
—
s
—
(15±1)/Fs
—
s
1. FsEXT is the external sample rate (LRCK/FSYNC frequency). Response scales with FsEXT.
2.This value varies by up to 1 Fs. If SRC is disabled, Fs = FsOUT = FsIN.
DS1081F3
13
CS43L36
3 Characteristics and Specifications
Table 3-7. Serial Data In-to-HPOUTx Characteristics
Test conditions (unless specified otherwise): Fig. 2-1 shows CS43L36 connections; input test signal is a 24-bit full-scale 997-Hz sine wave with 1 LSB of triangular
PDF dither applied; GNDA = GNDL = GNDCP = 0 V; voltages are with respect to ground; parameters can vary with VA; typical performance data taken with VL =
VA = 1.8 V, VP = 3.6 V; min/max performance data taken with VA = 1.66–1.94 V; VL = 1.8 V, VP = 3.6 V; VCP Mode; TA = +25°C; measurement bandwidth is
20 Hz–20 kHz; ASP_LRCK = FsINT = 48-kHz mode; MCLK = 12 MHz, MCLK_SRC_SEL = 0; volume = 0 dB; FULL_SCALE_VOL = 0 (0dB); HP load: RL = 30 
CL = 1 nF (HPOUT_LOAD = 0) and RL = 3 k CL = 10 nF (HPOUT_LOAD = 1)SRC bypassed.
RL = 3 k
VP_CP Mode
Parameter 1
Dynamic range
(defined in Table 3-1)
THD+N 2 (defined in Table 3-1)
18–24 bit
18–24 bit
16 bit
RL = 30 
VP_CP Mode
Idle channel noise (A-weighted)
Full-scale output voltage 3
Dynamic range (defined in Table 3-1)
18–24 bit
A-weighted
unweighted
Pout = 10 mW
Pout = 35 mW
Full-scale output voltage 3
Output power 2
Dynamic range (defined in Table 3-1)
18–24 bit
THD+N 2 (defined in Table 3-1)
Full-scale output voltage 3
Output power 2
Dynamic range
A-weighted
unweighted
Pout = 17.3 mW
18–24 bit
THD+N 2 (defined in Table 3-1)
RL = 15 
VCP Mode
(FULL_SCALE_
VOL = 1 [–6 dB])
A-weighted
unweighted
0 dB
–20 dB
–60 dB
0 dB
–20 dB
–60 dB
RL = 15 
VP_CP Mode
Other characteristics Interchannel isolation 3 (3 k)
(Table 3-1 gives
parameter definitions.)
Interchannel isolation 3 (30 )
A-weighted
unweighted
217 Hz
1 kHz
20 kHz
217 Hz
1 kHz
20 kHz
Output offset voltage: mute 3,4 (ANA_MUTE_x = 1, see p. 76)
HPOUTx
Output offset voltage 3,4
HPOUTx
Load resistance (RL)
Normal operation 3
Load capacitance (CL) 3,5
HPOUT_LOAD = 0
HPOUT_LOAD = 1
SLOW_START_EN = 000
Turn-on time 6
Minimum
108
105
—
—
—
—
—
—
—
1.50•VA
108
105
—
—
1.50•VA
—
102
99
—
0.71•VA
—
102
99
—
—
—
—
—
—
—
—
15
—
—
—
Typical Maximum Unit
114
—
dB
111
—
dB
–90
–84
dB
–83
—
dB
–51
–48
dB
–88
–82
dB
–73
—
dB
–33
–27
dB
2.0
—
µV
1.58•VA 1.66•VA VPP
114
—
dB
111
—
dB
–98
—
dB
–75
–69
dB
1.58•VA 1.66•VA VPP
35.0
—
mW
108
—
dB
105
—
dB
–75
–69
dB
0.79•VA 0.86•VA VPP
17.3
—
mW
108
—
dB
105
—
dB
90
—
dB
90
—
dB
80
—
dB
90
—
dB
90
—
dB
70
—
dB
±0.5
±1.0
mV
±0.5
±2.5
mV
—
—

—
1
nF
—
10
nF
—
25
ms
1.One LSB of triangular PDF dither is added to data.
2.Because VCP settings lower than VA reduce the HP amplifier headroom, the specified THD+N performance at full-scale output voltage and power
may not be achieved.
3.HP output test configuration. Symbolized component values are specified in the test
Test Load
Measurement
conditions above.
+
HPOUTx
Device
CL
HSx/HSx_REF
RL
–
4.Assumes no external impedance on HSx/HSx_REF. External impedance on HSx/HSx_REF affects the offset and step deviation. See Section 4.2.1.
5.Amplifier is guaranteed to be stable with either headphone load setting.
6.Turn-on time is measured from when the HP_PDN = 0 ACK signal is received to when the signal appears on the HP output. In most cases, enabling
the SRC increases the turn-on time and may exceed the maximum specified value.
DS1081F3
14
CS43L36
3 Characteristics and Specifications
Table 3-8. DC Characteristics
Test conditions (unless specified otherwise): Fig. 2-1 shows CS43L36 connections; GNDA = GNDL = GNDCP = 0 V; voltages are with respect to ground;
VL = VCP = VA = 1.8 V, VP = 3.6 V; TA = +25°C.
VCP_FILT (No load
connected to HPOUTx.)
Parameters
VP_CP Mode (ADPTPWR = 001)
+VCP_FILT
–VCP_FILT
+VCP_FILT
–VCP_FILT
+VCP_FILT
–VCP_FILT
+VCP_FILT
–VCP_FILT
VCP Mode (ADPTPWR = 010)
VCP/2 Mode (ADPTPWR = 011)
VCP/3 Mode (ADPTPWR = 100)
HS3 ground switch resistance (Typical values have ±25% tolerance.)
Other DC filter
FILT+ voltage
HP output current limiter on threshold. See Section 4.3.4. 1
VD_FILT and VL power-on reset threshold (VPOR)
Up
Down
HPOUT_PULLDOWN = 0000–0111, 1100
HPOUT_PULLDOWN = 1001
HPOUT_PULLDOWN = 1010
HPOUT pull-down
resistance 2,3
Minimum
—
—
—
—
—
—
—
—
—
—
80
—
—
—
—
—
Typical Maximum Unit
2.6
—
V
–2.6
—
V
VCP
—
V
–VCP
—
V
VCP/2
—
V
–VCP/2
—
V
VCP/3
—
V
–VCP/3
—
V
0.5
—

VA
—
V
115
160
mA
0.777
—
V
0.628
—
V
0.9
—
k
9.3
—
k
5.8
—
k
1.The HP output current limiter threshold spec is valid only while the Class H rails are in VCP Mode.
2.Typical values have ±20% tolerance.
3.Clamp is disabled (HPOUT_CLAMP = 1) and channel is powered down (HPOUT_PDN = 1).
Table 3-9. Power-Supply Rejection Ratio (PSRR) Characteristics
Test conditions (unless specified otherwise): Fig. 2-1 shows CS43L36 connections; input test signal held low (all zero data); GNDA = GNDL = GNDCP
= 0 V; voltages are with respect to ground; VL = VA = 1.8 V, VP = 3.6 V; TA = +25°C.
Parameters 1
HPOUTx (–6-dB analog gain)
PSRR with 100-mVpp signal AC coupled to VA supply 2
217 Hz
1 kHz
20 kHz
217 Hz
1 kHz
20 kHz
217 Hz
1 kHz
20 kHz
HPOUTx (–6-dB analog gain)
PSRR with 100-mVpp signal AC-coupled to VCP supply 2
HPOUTx (0-dB analog gain)
PSRR with 100-mVpp signal AC coupled to VP supply
1.PSRR test configuration: Typical PSRR can vary by approximately 6 dB below
the indicated values.
Minimum Typical Maximum
—
75
—
—
75
—
—
70
—
—
85
—
—
85
—
—
65
—
—
80
—
—
80
—
—
60
—
Unit
dB
dB
dB
dB
dB
dB
dB
dB
dB
Analog Output PSRR
+5 V
+5 V
DUT
–
Power DAC
PWR
+
OUT
GND
Operational Amplifier
GND
OUT
Analog Test Equipment
OUT
Analog Generator
– +
Analog Analyzer
– +
2.No load connected to any analog outputs.
DS1081F3
15
CS43L36
3 Characteristics and Specifications
Table 3-10. Power Consumption
Test conditions (unless specified otherwise): Fig. 2-1 shows CS43L36 connections; GNDA = GNDL = GNDCP = 0 V; voltages are with respect to ground;
performance data taken with VA = VCP = VL = 1.8 V; DIGLDO_PDN is deasserted; VP = 3.6 V; TA = +25°C; ASP_LRCK = 48-kHz Mode; FsINT = 48 kHz;
SCLK = 12 MHz, MCLK_SRC_SEL = 0; volume= 0 dB; FULL_SCALE_VOL = 1 (–6 dB) for HPOUTx, TIP_SENSE_CTRL = 11, all other fields are set to
defaults; no signal on any input; control port inactive; input clock/data are held low when not required; test load is RL = 30  and CL = 1 nF for HPOUTx;
measured values include currents consumed by the DAC and do not include current delivered to external loads unless specified otherwise (e.g., HPOUTx);
see Fig. 3-1.
Typical Current (µA)
ClassH
Mode
iVCP
iVL
iVP
iVA
—
0
0
0
3.1
—
0
0
0
20
—
0
0
343
31
Stereo HPOUT (no signal, HPOUT_LOAD = 0) VCP/3 1413 1204 858
58
Stereo HPOUT (0.1 mW, HPOUT_LOAD = 0) VCP/3 1441 2336 965
58
Use Cases
1
2
3
4
A
A
A
A
B
Off 1
Standby 2,3
Standby (RCO Mode) 4,5
Playback
Total Power
(µW)
11.16
72.0
729
6464
8744
1.Off configuration: Clock/data lines held low; RESET = LOW; VA = VL = VCP = 0 V; VP = 3.6 V.
2.Standby configuration: Clock/data lines held low; VA = VL = VCP = 0 V; VP = 3.6 V; M_HP_WAKE = 0 (unmasked).
3.SCLK_PRESENT = 1.
4.SCLK_PRESENT = 0 (RCO clocking).
5.Standby configuration (RCO clocking): Clock/data lines held low; VA = 0 V; VL = 1.8 V, VCP = 0 V, VP = 3.6 V; M_HP_WAKE = 0 (unmasked).
Voltmeter
DAC
–
+
DAC
–
+
DAC
–
+
10 
VCP
0.1 µF
+
–
DUT
10 
VA
0.1 µF
+
–
10 
VL
0.1 µF
Note: The current draw on the VA, VCP, and VL
power supply pins is derived from the measured
voltage drop across a 10- series resistor between
the associated supply source and each voltage
supply pin. Given the larger currents that are
possible on the VP supply, an ammeter is used for
the measurement.
+
–
Power Supply
Ammeter
4.7 µF
0.1 µF
VP GNDA/GNDCP/
GNDL/GND
Figure 3-1. Power Consumption Test Configuration
‘
Table 3-11. Register Field Settings
DS1081F3
A
A
A
A
B
HP_PDN
1
2
3
4
ASP_DAI_PDN
Use
Cases
PDN_ALL
Register Fields and Settings
—
1
1
0
0
—
—
—
0
0
—
—
—
0
0
Class H Mode
p. 23
—
—
—
VCP/3
VCP/3
16
CS43L36
3 Characteristics and Specifications
Table 3-12. Digital Audio Interface Timing Characteristics
Test conditions (unless specified otherwise): GNDA = GNDL = GNDCP = 0 V; all voltages with respect to ground; values are for both VL = 1.2 and 1.8 V;
inputs: Logic 0 = GNDL = 0 V, Logic 1 = VL; TA = +25°C; CLOAD = 30 pF (for VL = 1.2 V) and 60 pF (for VL = 1.8 V); input timings are measured at VIL
and VIH thresholds; output timings are measured at VOL and VOH thresholds (see Table 3-14); ASP_TX_HIZ_DLY = 00.
Parameters 12,3
ASP_SCLK frequency 4
SCLK high period 4
SCLK low period 4
SCLK duty cycle 4
Hybrid- FSYNC/LRCK frame rate
Master LRCK duty cycle
Mode FSYNC high period 6
FSYNC/LRCK delay time after SCLK launching edge 7
Slave
Mode
Symbol
fSCLK
tHI:SCLK
tLO:SCLK
—
—
—
tHI:FSYNC
Minimum Typical Maximum Unit
0.973 [5]
—
25.81
MHz
18.5
—
—
ns
18.5
—
—
ns
45
—
55
%
0.99
—
1.01
Fs
45
—
55
%
1/fSCLK
—
(n–1)/fSCLK
s
VL = 1.8 V tD:CLK–LRCK
0
—
15
ns
VL = 1.2 V
0
—
17
ns
tSU:SDI
10
—
—
ns
tH:SDI
5
—
—
ns
—
0.99
—
1.01
Fs
—
45
—
55
%
tSU:LRCK
10
—
—
ns
tH:LRCK
5
—
—
ns
tH:SDI
5
—
—
ns
—
45
—
55
%
SDIN setup time before SCLK latching edge 7
SDIN hold time after SCLK latching edge 7
FSYNC/LRCK frame rate
FSYNC/LRCK duty cycle
FSYNC/LRCK setup time before SCLK latching edge 7
FSYNC/LRCK hold time after SCLK latching edge 7
SDIN hold time after SCLK latching edge 7
FSYNC/LRCK duty cycle
1.Output clock frequencies follow SCLK frequency proportionally. Deviation of the bit-clock source from nominal supported rates is directly imparted to
the output clock rate by the same factor (e.g., +100-ppm offset in the frequency of SCLK becomes a +100-ppm offset in MCLK and LRCK).
2.I2S interface timing
t H:LRCLK
LRCK
t D:CLK‐LRCLK
t SU:LRCLK
1/fSCLK
SCLK
t HI:SCLK
t LO:SCLK
SDIN
t SU:SDI
3.TDM interface timing
tHI:FSYNC
1/Fs
fSCLK = N ∙ Fs
LRCK/FSYNC
t SU:FSYNC
t H:FSYNC
...
1/f SCLK
...
SCLK
tD:CLK-FSYNC
SDIN
t H:SDI
t LO:SCLK
t HI: SCLK
Frame location N-1
...
Don’t Care
tSU:SDI
tH:SDI
Frame location 0
4.SCLK is mastered from an external device. The external device is expected to maintain SCLK timing specifications.
5.SCLK operation below 2.8224 MHz may result in degraded performance.
6.Maximum LRCK duty cycle is equal to frame length, in SCLK periods, minus 1. Maximum duty cycle occurs when LRCK_HI is set to 511 SCLK
periods and LRCK period is set to 512 SCLK periods.
7.Data is latched on the rising or falling edge of SCLK, as determined by ASP_SCPOL_IN_x and ASP_FSD (See Section 7.3.6 and Section 7.3.7).
Table 3-13. I2C Slave Port Characteristics
Test conditions (unless specified otherwise): Fig. 2-1 shows typical connections; Inputs: GNDA = GNDL = GNDCP = 0 V; all voltages with respect to
ground; min/max performance data taken with VL = 1.66–1.94 V (VL_SEL = VP) or VL = 1.1–1.3 V (VL_SEL = GNDD); inputs: Logic 0 = GNDA = 0 V,
Logic 1 = VL; TA = +25°C; SDA load capacitance equal to maximum value of CB = 400 pF; minimum SDA pull-up resistance, RP(min).1 Table 3-1
describes some parameters in detail. All specifications are valid for the signals at the pins of the CS43L36 with the specified load capacitance.
Parameter 2
SCL clock frequency
Clock low time
Clock high time
Start condition hold time (before first clock pulse)
Setup time for repeated start
Rise time of SCL and SDA
DS1081F3
Standard Mode
Fast Mode
Fast Mode Plus
Symbol 3
fSCL
tLOW
tHIGH
tHDST
tSUST
tRC
Minimum
—
500
260
260
260
—
—
—
Maximum
1000
—
—
—
—
1000
300
120
Unit
kHz
ns
ns
ns
ns
ns
ns
ns
17
CS43L36
3 Characteristics and Specifications
Table 3-13. I2C Slave Port Characteristics (Cont.)
Test conditions (unless specified otherwise): Fig. 2-1 shows typical connections; Inputs: GNDA = GNDL = GNDCP = 0 V; all voltages with respect to
ground; min/max performance data taken with VL = 1.66–1.94 V (VL_SEL = VP) or VL = 1.1–1.3 V (VL_SEL = GNDD); inputs: Logic 0 = GNDA = 0 V,
Logic 1 = VL; TA = +25°C; SDA load capacitance equal to maximum value of CB = 400 pF; minimum SDA pull-up resistance, RP(min).1 Table 3-1
describes some parameters in detail. All specifications are valid for the signals at the pins of the CS43L36 with the specified load capacitance.
Parameter 2
Fall time of SCL and SDA
Standard Mode
Fast Mode
Fast Mode Plus
Setup time for stop condition
SDA setup time to SCL rising
SDA input hold time from SCL falling 4
Output data valid (Data/Ack) 5
Standard Mode
Fast Mode
Fast Mode Plus
Bus free time between transmissions
SDA bus capacitance
Fast Mode Plus
Standard Mode, Fast Mode
VL = 1.2 V
VL = 1.8 V
SCL/SDA pull-up resistance 1
Switching time between RCO and PLL or SCLK 6
Symbol 3
tFC
Minimum
—
—
—
260
50
0
—
—
—
500
—
—
200
250
150
tSUSP
tSUD
tHDDI
tVDDO
tBUF
CB
RP
—
Maximum
300
300
120
—
—
—
3450
900
450
—
550
400
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
pF


µs
1.The minimum RP value (see Fig. 2-1) is determined by using the maximum VL level, the minimum sink current strength of its respective output, and
the maximum low-level output voltage, VOL. The maximum RP value may be determined by how fast its associated signal must transition (e.g., the
lower the RP value, the faster the I2C bus can operate for a given bus load capacitance). See the I²C bus specification referenced in Section 13.
2.All timing is relative to thresholds specified in Table 3-14, VIL and VIH for input signals, and VOL and VOH for output signals.
3.I²C control-port timing
Repeated
Start
Stop
Start
Stop
SDA
tBUF
tHDST
tHDST
t HIGH
tFC
tSUSP
SCL
tLOW
4.Data must be held long enough to bridge the SCL transition time, tF.
tVDDO
t SUD
tSUST
tRC
tHDDI
5.Time from falling edge of SCL until data output is valid.
6.The switch between RCO and either SCLK or PLL occurs upon setting/clearing SCLK_PRESENT (see p. 63) and sending the I2C stop condition. An
SCLK_PRESENT transition (0 to 1 or 1 to 0) starts a switch between RCO and the selected SCLK or PLL. An I2C stop condition is sent, after which
a wait time of at least 150 s is required before the next I2C transaction can begin using the newly selected clock.
DS1081F3
18
CS43L36
3 Characteristics and Specifications
Table 3-14. Digital Interface Specifications and Characteristics
Test conditions (unless specified otherwise): Fig. 2-1 shows CS43L36 connections; GNDD = GNDCP = GNDA = 0 V; voltages are with respect to ground;
parameters can vary with VL and VP; min/max performance data taken with VCP = VA = 1.8 V, VD_FILT = 1.2 V; VP = 3.0–5.25 V; VL = 1.66–1.94 V
(VL_SEL = VP) or VL = 1.1–1.3 V (VL_SEL = GNDD); TA = +25°C; CL = 60 pF.
Parameters 1
Input leakage current 2,3
ASP_LRCK/FSYNC
ASP_SCLK,ASP_SDIN
TIP_SENSE
SDA, SCL
INT, WAKE, RESET
Symbol
Iin
Internal weak pull-down
Input capacitance 2
INT or WAKE current sink (VOL = 0.3 V maximum)
VL Logic (non-I2C)
VL Logic (I2C only)
VP Logic (excluding TIP_SENSE)
TIP_SENSE 4
TIP_SENSE current to –VCP_FILT 4
—
—
—
Min
—
—
—
—
—
550
—
825
High-level output voltage (IOH = –100 µA)
0.9*VL
VOH
VOL
Low-level output voltage
—
VIH
High-level input voltage
0.7*VL
VIL
Low-level input voltage
—
Low-level output voltage
—
VOL
VIH
High-level input voltage
0.7*VL
VIL
Low-level input voltage
—
VHYS
Hysteresis voltage
0.05*VL
—
Low-level output voltage
VOL
VIH
0.9
High-level input voltage
VIL
—
Low-level input voltage
High-level input voltage
VIH
0.87*VP
VIL
Low-level input voltage
—
TIP_SENSE_CTRL = 11 (Short-Detect Mode) ITIP_SENSE
1.00
1.See Table 1-1 for serial and control-port power rails.
2.Specification is per pin. The CS43L36 is not a low-leakage device, per the MIPI Specification. See Section 13.
3.Includes current through internal pull-up or pull-down resistors on pin.
4.TIP_SENSE input circuit. This circuit allows the TIP_SENSE signal to go as low as –VCP_
FILT and as high as VP. Section 4.8.2 provides configuration details.
Max
±4
±3
±100
±100
±100
2450
10
—
Unit
µA
µA
nA
nA
nA
k
pF
µA
—
0.1*VL
—
0.3*VL
0.2*VL
—
0.3*VL
—
0.2
—
0.2
—
2.0
2.91
V
V
V
V
V
V
V
V
V
V
V
V
V
µA
VP
ESD Protection
TIP_SENSE
Current to
–VCP_FILT
ITIP_SENSE
To Digital
Input Circuitry
TIP_SENSE
–VCP_FILT
–VCP_FILT
DS1081F3
19
CS43L36
4 Functional Description
4 Functional Description
This section provides a general description of the CS43L36 architecture and detailed functional descriptions of the various
blocks that make up the CS43L36. Fig. 4-1 shows the flow of signals through the CS43L36 and gives links to detailed
descriptions of the respective sections.
See Section 4.2 “Analog Output.”
VA
See Section 4.4,
“Clocking
Architecture.”
Clock
Gen
ASP_SCLK
ASP_LRCK
/FSYNC
CS43L36
Analog Core
PLL
ASP_SDIN
DIGLDO_PDN
VP
POR
LDO
VCP
VP_CP
Step-Down
+VCP_FILT
Inverting
–VCP_FILT
Digital
Core
See Section 4.1.“Digital Volume Control.”
SRC
Digital Audio
Input
SRC
See Section 4.7,
Headset Interface”
HS3_REF
VD_FILT
LDO
with
Bypass
MCLK
See Section 4.6,
“Sample-Rate
Converters (SRCs)”
HS3
VL
HPSENSA *
Interpolator
and
Volume
Control
Multibit 
Modulator
Interpolator
and
Volume
Control
Multibit 
Modulator
+VCP_FILT
DAC
HPOUTA
–VCP_FILT
HPSENSB *
+VCP_FILT
DAC
–
HPOUTB
+
–VCP_FILT
Pseudodifferential
Input
Headset
Impedance
Detect and
Switches
–
+
* WLCSP
package only
See Section 4.10, “Control-Port Operation”
I 2C Slave
TIP_SENSE
Headphone Detect
INT
WAKE
AD0 AD1 SDA SCL
Figure 4-1. Overview of Signal Flow
The CS43L36 is an ultralow-power stereo DAC. The DAC feeds a stereo pseudodifferential output amplifier. The
converters operate at a low oversampling ratio, maximizing power savings while maintaining high performance.
The serial data interface ports operate either at standard audio-sample rates as timing slaves or in Hybrid-Master Mode
as a bit-clock slave generating LRCK internally. An onboard fractional-N PLL can be used to generate the internal-core
timing (MCLKINT) if the SCLK source is not one of the following rates (where N = 2 or 4):
•
N x 5.6448 or 6.1440 MHz
•
USB rates (N x 6 MHz)
The CS43L36 significantly reduces overall power consumption, with a very low-voltage digital core and with low-voltage
Class H amplifiers (powered from an integrated LDO regulator and a step-down/inverting charge pump, respectively). The
CS43L36 comprises the following subblocks:
•
Volume control, described in Section 4.1, uses selectable attenuation to provide relative volume control and to avoid
clipping.
•
Analog outputs. The analog output block, described in Section 4.2, includes separate pseudodifferential headphone
Class H amplifiers. An on-chip step-down/inverting charge pump creates a positive and negative voltage equal to the
input or to either one-half or one-third of the input supply for the amplifiers, allowing an adaptable, full-scale output
swing centered around ground. The resulting internal amplifier supply can be ±VCP/3, ±VCP/2, ±VCP, or ±2.5 V.
The inverting architecture eliminates the need for large DC-blocking capacitors and allows the amplifier to deliver
more power to HP loads at lower supply voltages. The step-down architecture allows the amplifier’s power supply
to adapt to the required output signal. This adaptive power-supply scheme converts traditional Class AB amplifiers
into more power-efficient Class H amplifiers.
DS1081F3
20
CS43L36
4.1 Digital Volume Control
•
Class H amplifier. The HP output amplifiers, described in Section 4.3, use a patented Cirrus Logic four-mode
Class H technology that maintains high performance and maximizes operating efficiency of a typical Class AB
amplifier.
•
Clocking architecture. Described in Section 4.4, the clock for the device can be supplied internally from an
integrated fractional-N PLL using ASP_SCLK/ as the source clock or the internal PLL can be bypassed and derived
directly from the input pin.
•
Serial port. The CS43L36 TDM/I2S (ASP) port is a highly configurable serial port. See Section 4.5.
The ASP can operate in TDM Mode, which includes full-duplex communication, flexible data structuring via control
port registers, clock slave mode, and higher bandwidth, enabling more data to be transferred to and from the device.
•
Sample-rate converters (SRCs). SRCs, described in Section 4.6, are used to bridge different sample rates at the
serial ports within the digital-processing core. SRCs can be bypassed.
•
Headset interface. This interface is described in Section 4.7.
•
Power management. Several control registers provide independent power-down control of the analog and digital
sections of the CS43L36, allowing operation in select applications with minimal power consumption. Power
management considerations are described in Section 4.9.
•
Control-port operation. The control port, described in Section 4.10, provides access to the registers for configuring
the DAC. The control port operation may be completely asynchronous with respect to the audio sample rates. To
avoid potential interference problems, control-port data pins must remain static if no operation is required.
•
Resets. Section 4.11 describes the reset options—power-on reset (POR), asserting and RESET.
•
Interrupts. The CS43L36 includes an open-drain interrupt output, INT. Interrupt mask registers control whether an
event associated with an interrupt status/mask bit pair triggers the assertion of INT. See Section 4.12.
4.1 Digital Volume Control
The internal stereo volume control is shown in Fig. 4-2. Each input can be attenuated via CHx_VOLy. Outputs are
available as a source for the DACs.
Volume Control
Attenuation
CHA_VOL on p. 76
Serial Port B/SRC
Attenuation
Output B
To DACs
Serial Port A/SRC
Output A
CHB_VOL on p. 77
Figure 4-2. Digital Volume Control Subblocks
4.1.1
Attenuation Values
The volume control contains programmable attenuation blocks that are configured as described in the CHx_VOLy field
descriptions in Section 7.11.1—Section 7.11.2. For all settings except 0 dB, attenuation on the mixer input includes an
offset that increases as attenuation increases, as follows:
•
For commonly used –6n dB (n 1, 2, etc.}) attenuation settings, the offset rounds the attenuation exactly to the
desired 1/2n factor (e.g., 20Log(1/2) = 6.021 dB, not 6.000 dB).
•
For attenuation settings other than –6n dB, the always positive offset provides slightly more attenuation, giving
enough margin to avoid mixer clipping.
DS1081F3
21
CS43L36
4.2 Analog Output
4.2 Analog Output
This section describes the headphone (HP) outputs. The CS43L36 provides an analog output that is fed from the mixer.
Fig. 4-3 shows the general flow of the analog outputs.
DAC Data Path
Left
Interpolator
Invert
DACx_INV p. 75
Right
+VCP_FILT
HPOUT_LOAD p. 75 –VCP_FILT
FULL_SCALE_VOL p. 76
ANA_MUTE_B p. 76
ANA_MUTE_A p. 76 +VCP_FILT
DAC_HPF_EN
p. 76
Interpolator
Invert
+
DACA
DACB
+
-
HPOUTA
HSx_REF
HPOUTB
–VCP_FILT
Figure 4-3. Analog-Output Signal Flow
The output path is sourced directly from the digital volume control output. The playback path uses advanced analog and digital
signal-processing techniques to adapt to the input signal content and enhance dynamic range and power consumption of the
playback path. The HP output must be muted before changing the state of FULL_SCALE_VOL (see p. 76), which sets the
maximum HPOUT output voltage. See Table 3-7. HP outputs are muted by ANA_MUTE_B and ANA_MUTE_A (see p. 76).
Fig. 4-4 is an op-amp–level schematic for the analog output flow.
HPSENSx
DACx–
WLCSP version only
–
HPOUTx
+
DACx+
HSx_REF
DACx–
QFN version only
–
HPOUTx
+
DACx+
HSx_REF
Figure 4-4. Op-Amp-Level Schematic—Analog Outputs
4.2.1
Pseudodifferential Outputs
The analog output amplifiers use a pseudodifferential output topology that allows the amplifier to monitor the ground
potential at the load through the reference pins (HSx_REF). Minimize the impedance from the CS43L36 reference pin to
the load ground (typically the connector ground). Impedance in this path affects analog output attenuation as well as the
common-mode rejection of the output amplifier, which affects output offset and step deviation.
4.2.2
Output Load Detection
The CS43L36 can distinguish between the following output loads:
•
RL = 15, 30, or 3 k
•
CL < ~2 nF (low capacitance); CL > ~2 nF (high capacitance)
Note:
Channels A and B must have matching loads, although load detection is performed using Channel A.
Before output load detection is initiated, the following steps must be performed:
1. HS-type information must be determined to run a headset load-detection sequence, as described in Section 4.8.
DS1081F3
22
CS43L36
4.3 Class H Amplifier
2. Power down the HP block: HP_PDN = 1 (see p. 62).
3. Mute the analog outputs: ANA_MUTE_B = ANA_MUTE_A = 1 (see p. 76).
4. Disable the DAC high-pass filter: DAC_HPF_EN = 0 (see p. 76).
Note: Restore the previous setup after detection completes.
5. Set LATCH_TO_VP (see p. 74).
6. Set ADPTPWR = 100 (see p. 76).
7. Set the analog soft-ramp rate (ASR_RATE = 0111; see p. 60).
8. Set the digital soft-ramp rate (DSR_RATE; see p. 60) = 0001.
9. After load detection completes, ASR_RATE, DSR_RATE, ADPTPWR, and DAC_HPF_EN must be restored to
their previous values. See Section 4.3 for details.
After an HP-detect event, if HP_LD_EN is set (see p. 73), the CS43L36 proceeds to detect the resistance and capacitance
of the output load. A 24-kHz tone is output on HPOUTA, and HS3 is measured using an internal resistor bank as a
reference.
RLA_STAT (see p. 73) reports resistance-detection results for Channel A as follows:
•
•
•
•
00: 15 
01: 30 
10: 3 k
11: Reserved
If the typical output resistance of less than ~300 is indicated, a low-capacitance load is assumed. If the resistance is
greater than 300  capacitance detection proceeds. After the detection sequence completes, HPLOAD_DET_DONE (see
p. 73) is set. The results of capacitor detection is reported in CLA_STAT (see p. 73). This result can be used to program
the value in HPOUT_LOAD(see p. 75), which determines the compensation of the headphone amplifier.
Notes:
• The HP path must be powered down before updating the HPOUT_LOAD setting and repowered afterwards.
• Low capacitance results were determined with CL = 1 nF; high capacitance results were determined with CL = 10 nF.
4.2.3
Slow Start Control
Volume control, DAC, and HP soft ramping is enabled through SLOW_START_EN (p. 61). If SLOW_START_EN = 111,
changes to DAC/HP volumes are applied slowly by stepping through each volume-control setting with a delay between
steps equal to an integer number of Fs periods. The delay between steps, which can vary from 1/Fs to 72/Fs periods, is
set via DSR_RATE and ASR_RATE (see p. 60).
If ramping is disabled, changes occur immediately with the clock edge.
4.3 Class H Amplifier
Fig. 4-5 shows the Class H operation.
ADPTPWR on p. 76
VP_CP
LDO Output
VCP
Step-down/Inve rtin g
Cha rge Pump
Class H Control
+2.5 V
+VCP
+VCP/2
+VCP/3
+VCP_FILT
–2.5 V
–VCP
–VCP/ 2
–VCP/ 3
–VCP_FILT
Figure 4-5. Class H Operation
DS1081F3
23
CS43L36
4.3 Class H Amplifier
The CS43L36 HP output amplifiers use a Cirrus Logic four-mode Class H technology, which maximizes operating
efficiency of the typical Class AB amplifier while maintaining high performance. In a Class H amplifier design, the rail
voltages supplied to the amplifier vary with the needs of the music passage being amplified. This conserves energy during
low-power passages and when the program material is played back at low volume.
The internal charge pump, which creates the rail voltages for the HP amplifiers, is the central component of the four-mode
Class H technology. The charge pump receives its input voltage from the voltage present on either the VCP or VP pin.
From this voltage, the charge pump generates the differential rail voltages supplied to the amplifier output stages. The
charge pump can supply four sets of differential rail voltages: ±2.5, ±VCP, ±VCP/2, and ±VCP/3.
Table 4-1 shows the nominal signal- and volume-level ranges if the amplifier is set to the adapt-to-signal mode explained
in Section 4.3.1. In addition to adapting to the input signal, the Class H control is capable of monitoring the internal
headphone amplifier supply to allow more efficient, load-dependent, automatic Smart Class H Mode selection. In fixed
modes, if the signal level exceeds the maximum value of the indicated range, clipping can occur.
Table 4-1. Class H Supply Modes
Resistance
15 
Load
Capacitance
1 nF
10 nF
30 
1 or 10 nF
3 k
1 or 10 nF
Mode
Class-H Supply Voltage
Signal-Level Range 1,2,3,4
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
±2.5 V
± VCP
± VCP/2
± VCP/3
±2.5 V
± VCP
± VCP/2
± VCP/3
±2.5 V
± VCP
± VCP/2
± VCP/3
±2.5 V
± VCP
± VCP/2
± VCP/3
≥ –8 dB
–9 to –14 dB
–15 to –20 dB
≤ –21 dB
≥ –9 dB
–10 to –14 dB
–15 to –19 dB
≤ –20 dB
≥ –4 dB
–5 to –11 dB
–12 to –16 dB
≤ –17 dB
≥ –1 dB
–2 to –8 dB
–9 to –13 dB
≤ –14 dB
1.In Adapt-to-Signal Mode, volume level ranges are approximations but are within –0.5 dB from the values shown.
2.Relative to digital full scale with FULL_SCALE_VOL set to 0 dB.
3.In fixed modes, clipping occurs if the signal level exceeds the maximum of this range due to setting the amplifier’s supply too low.
4.To optimize efficiency, smart Class H thresholds automatically vary based on load conditions.
4.3.1
Power Control Options
This section describes the supported types of operation: standard Class AB and adapt to signal. The set of rail voltages
supplied to the amplifier output stages depends on the ADPTPWR setting, as described in Section 7.10.1.
4.3.1.1 Standard Class AB Operation (ADPTPWR = 001, 010, 011, or 100)
If ADPTPWR is set to 001, 010, 011, or 100, the rail voltages supplied to the amplifiers are held to ±2.5, ±VCP, ±VCP/2,
or ±VCP/3, respectively. For these settings, the rail voltages supplied to the output stages are held constant, regardless
of the signal level. In these settings, the CS43L36 amplifiers operate in a traditional Class AB configuration.
4.3.1.2 Adapt-to-Output Signal (ADPTPWR = 111)
If ADPTPWR = 111, the rail voltage sent to the amplifiers is based only on whether the signal sent to the amplifiers would
cause the amplifiers to clip when operating on the lower set of rail voltages at certain threshold values.
•
If clipping can occur, the control logic instructs the charge pump to provide the next higher set of rail voltages.
•
If clipping could not occur, the control logic instructs the charge pump to provide the lower set of rail voltages,
eliminating the need to advise the CS43L36 of volume settings external to the device.
DS1081F3
24
CS43L36
4.3 Class H Amplifier
4.3.2
Power-Supply Transitions
Charge-pump transitions from the lower to the higher set of rail voltages occur on the next FLYN/FLYP clock cycle. Despite
the system’s fast response time, the VCP_FILT pin’s capacitive elements prevent rail voltages from changing instantly.
Instead, the rail voltages ramp from the lower to the higher supply, based on the time constant created by the output
impedance of the charge pump and the capacitor on the VCP_FILT pin (the transition time is approximately 20 µs).
Fig. 4-6 shows Class H supply switching. During this transition, a high dV/dt transient on the inputs may briefly clip the
outputs before the rail voltages charge to the full higher supply level. This transitory clipping has been found to be inaudible
in listening tests.
+2.5 V
Ideal Transition
+VCP
+VCP
2
+VCP
3
Actual Transition caused
by +VCP_FILT Capacitor
Time
-VCP
3
-VCP
2
-VCP
-2.5 V
Figure 4-6. VCP_FILT Transitions—Headphone Output
When the charge pump transitions from the higher to the lower set of rail voltages, there is a 5.5-s delay before the charge
pump supplies the lower rail voltages to the amplifiers. This hysteresis ensures that the charge pump does not toggle
between the two rail voltages as signals approach the clip threshold. It also prevents clipping in the instance of repetitive
high-level transients in the input signal. Fig. 4-7 shows this transitional behavior.
DS1081F3
25
CS43L36
4.3 Class H Amplifier
Output Level
5.5 s
5.5 s
5.5 s
–4 dB
–4.5 dB
–10 dB
–10.5 dB
–14 dB
–14.5 dB
Time
Amplifier Rail
Voltage
+2.5 V
+VCP
+VCP
2
+VCP
3
Time
–VCP
3
–VCP
2
–VCP
–2.5 V
Figure 4-7. VCP_FILT Hysteresis—Headphone Output
4.3.3
Efficiency
As discussed in previous sections, amplifiers internal to the CS43L36 operate from one of four sets of rail voltages, based
on the needs of the signal being amplified. Fig. 4-8 and Fig. 4-9 show power curves for all modes of operation and provides
details regarding the power supplied to 15- and 30-stereo loads versus the power drawn from the supply for each
Class H mode.
If rail voltages are set to ±2.5 V, the amplifiers operate in their least efficient mode for low-level signals. If they are held at
±VCP, ±VCP/2, or ±VCP/3, amplifiers operate more efficiently, but are clipped if required to amplify a full-scale signal.
The adapt-to-signal trace shows the benefit of four-mode Class H operation. At lower output levels, amplifier output is
represented by the ±VCP/3 or ±VCP/2 curve, depending on the signal level. At higher output levels, amplifier output is
represented by the ±VCP or ±2.5-V curve. The duration for which the amplifiers operate within any of the four curves
(±VCP/3, ±VCP/2, ±VCP, or ±2.5 V) depends on both the content and the output level of the material being amplified. The
highest efficiency operation results from maintaining an output level that is close to, without exceeding, the clip threshold
of the particular supply curve.
Note that the Adapt-to-Signal Mode trace in Fig. 4-8 shows that it never transitions to Mode 0, because FULL_SCALE_
VOL = 1 (–6 dB) due to a 15- stereo load.
DS1081F3
26
CS43L36
4.3 Class H Amplifier
Total Power
from
VPfrom
+ VCP
Supplies
Total
Power
Supplies
(mW) (mW)
100
Mode 0: 2.5 V
Mode 1: VCP
Mode 2: VCP/2
Mode 3: VCP/3
Adapt−to−Signal Mode
10
1
0.01
0.1
1
Power Delivered to Load (mW)
10
Figure 4-8. Class H Power-to-Load Versus Power from Supply (15 , Stereo)
The Adapt-to-Signal Mode trace in Fig. 4-9 shows the transition to Mode 0, because FULL_SCALE_VOL = 0 (0 dB) due
to a 30- stereo load.
Total Power
from
VPfrom
+ VCP
Supplies
Total
Power
Supplies
(mW) (mW)
100
Mode 0: 2.5 V
Mode 1: VCP
Mode 2: VCP/2
Mode 3: VCP/3
Adapt−to−Signal Mode
10
1
0.01
0.1
1
Power Delivered to Load (mW)
10
Figure 4-9. Class H Power-to-Load Versus Power from Supply (30 , Stereo)
DS1081F3
27
CS43L36
4.4 Clocking Architecture
4.3.4
HP Current Limiter
The CS43L36 features built-in current-limit protection for the HP output. Table 3-8 lists the current limit threshold during
the short-circuit conditions shown in Fig. 4-10. For HP amplifiers, current is from the internal charge-pump output, and, as
such, applies the current from VCP or VP, depending on the mode.
VCP
VP
LDO
VP_CP
Charge
Pump
HPOUTA
I
HPOUTB
I
GNDA/GNDCP
Figure 4-10. HP Short-Circuit Setup
4.4 Clocking Architecture
The CS43L36 offers several ways to support control, ASP operation, data conversion, and signal processing. Internal
clocks are generated either from SCLK (ASP_SCLK) or from the integrated fractional-N PLL; see Fig. 4-11. Depending on
the MCLK_SRC_SEL setting (see Fig. 4-12), MCLKINT is provided by one of the following methods:
•
Externally sourced directly from the ASP_SCLK input pin
•
Internally generated from an integrated fractional-N PLL with ASP_SCLK as a reference clock
Digital Core
CCM
SCL
ASP_LRCK/
FSYNC
Control Port/APB
Clock
Generation
ASP Clock
Generation
MCLKINT
ASP_SCLK
FSYNC Generation
GFM 24/12 MHz
Delay
X2
Predivide
Digital Clock
Generation
I2C
* Use the RCO for
functionality only if
SCLK is unavailable.
PLL
RCO *
PoR
Analog
Core
Analog Clock
Generation
DAC analog clock
RESET
VP VL VD_FILT
Figure 4-11. Clock Architecture Block Diagram
DS1081F3
28
CS43L36
4.4 Clocking Architecture
4.4.1
Start-Up Clocking Using the RC Oscillator (RCO)
At power on, an integrated low-power RCO, shown in Fig. 4-11, functions as the default clock for the digital core of the
CS43L36, during which time SCLK is unavailable. A reset event always returns it to running off of the RCO. If SCLK is
unavailable, RCO clocking must be used only for I2C functionality.
RCO is multiplexed with MCLKINT and fed to the I2C slave control port. The SCLK must become active and the RCO must
be disabled before data conversion.
Note the following:
•
OSC_SW_SEL_STAT (see p. 63) indicates the status of the clock switching (in transition, RCO, or SCLK/PLL). With
the existing encoding, only one bit can physically change at a time, and the bit changing is always synchronous to
the clock that is currently selected.
•
OSC_PDNB_STAT (see p. 63) indicates the RCO power-down status.
•
SCLK_PRESENT is used to determine the internal MCLK source. See Section 7.2.4 for details.
The clock-switch state machine uses the transition of SCLK_PRESENT to both initiate switches between the selected
internal MCLK between the SCLK pin (SCLK_PRESENT = 1) or the internal RCO (SCLK_PRESENT = 0) and to send the
I2C stop condition that each switching event requires. During switching, a delay of at least 150 S is needed before
additional successful I2C communication can begin to use the new clocking source.
Notes:
•
Muting the system is recommended when a new clock source is chosen.
•
For normal operation, SCLK—not RCO—must be used (SCLK_PRESENT = 1) for running the ASP data path.
4.4.1.1 Switching from RCO
With SCLK running, an SCLK_PRESENT 0-to-1 transition starts a switch from the RCO to the selected SCLK or PLL. This
switch is superseded by any outstanding I2C transactions. After the I2C stop condition is sent, the transition begins, taking
150 s to complete, during which time the system requires that no new I2C transactions be initiated. The next I2C
transaction can begin after this 150-s delay.
4.4.1.2 Switching to RCO
To stop SCLK, the system must revert to RCO clocking to ensure that I2C communications function properly. To power
the RCO back up, SCLK_PRESENT must be cleared before stopping SCLK. A 1-to-0 SCLK_PRESENT transition
generates a glitch-free mux switch timing from SCLK to RCO. SCLK must remain running during the transition and new
I2C transactions must not be initiated for at least 150 s after an I2C stop is received. The next I2C transaction cannot
begin until after this 150-s delay.
Failure to account for this could cause communications to fail.
4.4.2
MCLKINT Sources
The MCLKINT source is supplied directly from ASP_SCLK input pin or from the fractional-N PLL. MCLKDIV must be set
according to the MCLKINT frequency, which must be set to either the 12-MHz region (11.2896–12.288 MHz) or the 24-MHz
region (22.5792–24.576 MHz). Table 4-4 shows several examples. Table 4-2 lists further restrictions.
Table 4-2. MCLKINT Source Restrictions
MCLKINT Source MCLK_SRC_SEL (see p. 64)
ASP_SCLK
0
Fractional-N PLL
1
MCLKDIV (see p. 64)
0
1
0
1
Nominal ASP_SCLK Pin Frequency
12 MHz
24 MHz
12 MHz
24 MHz
MCLKINT is switched through internal glitchless clock muxing. Doing so during operation may cause audible artifacts, but
does not put the device into an unrecoverable state. Therefore, it is recommended to mute the system for at least 150 s.
DS1081F3
29
CS43L36
4.4 Clocking Architecture
If MCLKINT is sourced from the PLL, on-the-fly frequency changes to the source may cause the PLL to go out of phase
lock with the clock source. To reduce the risk of audible artifacts, it is recommended to mute the system first. Any
necessary configuration changes based on the new clock source frequency must occur before unmuting the system.
Internal MCLK
MCLK
Fractional-N PLL
1
0
MCLK_SRC_SEL p. 64
0 = Div by 1
1 = Div by 2
MCLKDIV p. 64
0 = Div by 250
1 = Div by 256
FSINT
INTERNAL_FS p. 60
Figure 4-12. MCLK INT Source Switching
For proper internal Fs clocking, the INTERNAL_FS and MCLKDIV bits must be configured, as shown in Table 4-2.
Table 4-3. Determining FsINT
MCLKINT (MHz) MCLKDIV (see p. 64
11.2896
0
12
0
12.288
0
22.5792
1
24
1
24.576
1
Note:
4.4.3
INTERNAL_FS (see p. 60) Resulting FsINT (kHz)
1
44.1
0
48
1
48
1
44.1
0
48
1
48
The control-port frequency is equal to the MCLKINT frequency.
Fractional-N PLL
The CS43L36 has an integrated fractional-N PLL to support the clocking requirements of the internal analog circuits and
converters. This PLL can be enabled or bypassed to suit system-clocking needs. The input reference clock for the PLL is
the ASP_SCLK input pin. The reference clock frequency must be between 2.8224 and 25 MHz.
The PLL can be configured for a wide range of combinations of SCLK and MCLKINT. PLL_REF_INV (see p. 66) can be
used to invert the PLL reference clock. Table 4-4 lists common settings.
Table 4-4. Common PLL Setting Examples
SCLK MCLK_SRC_SEL SCLK_PREDIV PLL_DIV_INT PLL_DIV_FRAC PLL_MODE PLL_DIVOUT MCLKINT PLL_CAL_RATIO [4]
n
(MHz)
(MHz)
(see p. 64) 1
(see p. 66) 2
(see p. 72)
(see p. 72) 2
(see p. 72) (see p. 72) 3
(see p. 72)
1.024
1
00
0xAC
0x44 0000
01
0x10
11.2896
118
3
1
00
0xBB
0x80 0000
11
0x10
12
125
3
1
00
0xC0
0x00 0000
11
0x10
12.288
128
3
1.536
1
00
0x72
0xD8 0000
01
0x10
11.2896
118
2
1
00
0x7D
0x00 0000
11
0x10
12
125
2
1
00
0x80
0x00 0000
11
0x10
12.288
128
2
1
00
0x7D
0x00 0000
11
0x08
24
125
4
1
00
0x80
0x00 0000
11
0x08
24.576
128
4
2.048
1
00
0x56
0x22 0000
01
0x10
11.2896
88
2
1
00
0x5D
0xC0 0000
11
0x10
12
94
2
1
00
0x60
0x00 0000
11
0x10
12.288
96
2
2.8224
1
00
0x40
0x00 0000
11
0x10
11.2896
128
1
1
00
0x40
0x00 0000
11
0x08
22.5792
128
2
3
1
00
0x3C
0x36 1134
11
0x10
11.2896
120
1
1
00
0x40
0x00 0000
11
0x10
12
128
1
1
00
0x40
0x00 0000
01
0x10
12.288
131
1
1
00
0x40
0x00 0000
11
0x08
24
128
2
1
00
0x40
0x00 0000
01
0x08
24.576
131
2
3.072
1
00
0x39
0x6C 0000
01
0x10
11.2896
118
1
1
00
0x3E
0x80 0000
11
0x10
12
125
1
1
00
0x40
0x00 0000
11
0x10
12.288
128
1
1
00
0x3E
0x80 0000
11
0x08
24
125
2
1
00
0x40
0x00 0000
11
0x08
24.576
128
2
DS1081F3
30
CS43L36
4.4 Clocking Architecture
Table 4-4. Common PLL Setting Examples (Cont.)
SCLK MCLK_SRC_SEL SCLK_PREDIV PLL_DIV_INT PLL_DIV_FRAC PLL_MODE PLL_DIVOUT MCLKINT PLL_CAL_RATIO [4]
n
(MHz)
(MHz)
(see p. 64) 1
(see p. 66) 2
(see p. 72)
(see p. 72) 2
(see p. 72) (see p. 72) 3
(see p. 72)
4.00
1
00
0x2D
0x28 8CE7
11
0x10
11.2896
90
1
1
00
0x30
0x00 0000
11
0x10
12
96
1
1
00
0x30
0x00 0000
01
0x10
12.288
98
1
4.096
1
00
0x2B
0x11 0000
01
0x10
11.2896
88
1
1
00
0x2E
0xE0 0000
11
0x10
12
94
1
1
00
0x30
0x00 0000
11
0x10
12.288
96
1
5.6448
1
01
0x40
0x00 0000
11
0x10
11.2896
128
1
1
01
0x40
0x00 0000
11
0x08
22.5792
128
2
6
1
01
0x3C
0x36 1134
11
0x10
11.2896
120
1
1
01
0x40
0x00 0000
11
0x10
12
128
1
1
01
0x40
0x00 0000
01
0x10
12.288
131
1
1
01
0x40
0x00 0000
11
0x08
24
128
2
1
01
0x40
0x00 0000
01
0x08
24.576
131
2
6.144
1
01
0x39
0x6C 0000
01
0x10
11.2896
118
1
1
01
0x3E
0x80 0000
11
0x10
12
125
1
1
01
0x40
0x00 0000
11
0x10
12.288
128
1
1
01
0x3E
0x80 0000
11
0x08
24
125
2
1
01
0x40
0x00 0000
11
0x08
24.576
128
2
9.6
1
10
0x49
0x80 0000
01
0x10
11.2896
150
1
1
10
0x50
0x00 0000
11
0x10
12
80
2
1
10
0x50
0x00 0000
01
0x10
12.288
82
2
1
10
0x49
0x80 0000
01
0x08
22.5792
150
2
1
10
0x50
0x00 0000
11
0x08
24
107
3
1
10
0x50
0x00 0000
01
0x08
24.576
109
3
11.2896
0
—
—
—
—
—
11.2896
—
—
1
10
0x40
0x00 0000
11
0x08
22.5792
128
2
12
1
10
0x3C
0x36 1134
11
0x10
11.2896
120
1
0
—
—
—
—
—
12.0000
—
—
1
10
0x40
0x00 0000
01
0x10
12.288
131
1
1
10
0x40
0x00 0000
11
0x08
24
128
2
1
10
0x40
0x00 0000
01
0x08
24.576
131
2
12.2880
1
10
0x39
0x6C 0000
01
0x10
11.2896
118
1
1
10
0x3E
0x80 0000
11
0x10
12
125
1
0
—
—
—
—
—
12.2880
—
—
1
10
0x3E
0x80 0000
11
0x08
24
125
2
1
10
0x40
0x00 0000
11
0x08
24.576
128
2
13
1
10
0x39
0xAB 52B5
01
0x11
11.2896
111
1
1
10
0x3B
0x13 B13B
11
0x10
12
118
1
1
10
0x3B
0x13 B13B
01
0x10
12.288
121
1
19.2
1
11
0x49
0x80 0000
01
0x10
11.2896
150
1
1
11
0x50
0x00 0000
11
0x10
12
80
2
1
11
0x50
0x00 0000
01
0x10
12.288
82
2
1
11
0x49
0x80 0000
01
0x08
22.5792
150
2
1
11
0x50
0x00 0000
11
0x08
24
107
3
1
11
0x50
0x00 0000
01
0x08
24.576
109
3
22.5792
1
11
0x40
0x00 0000
11
0x10
11.2896
128
1
0
—
—
—
—
—
22.5792
—
—
24
1
11
0x3C
0x36 1134
11
0x10
11.2896
120
1
1
11
0x40
0x00 0000
11
0x10
12
128
1
1
11
0x40
0x00 0000
01
0x10
12.288
131
1
0
—
—
—
—
—
24
—
—
1
11
0x40
0x00 0000
01
0x08
24.576
131
2
24.576
1
11
0x39
0x6C 0000
01
0x10
11.2896
118
1
1
11
0x3E
0x80 0000
11
0x10
12
125
1
1
11
0x40
0x00 0000
11
0x10
12.288
128
1
1
11
0x3E
0x80 0000
11
0x08
24
125
2
0
—
—
—
—
—
24.576
—
—
DS1081F3
31
CS43L36
4.4 Clocking Architecture
Table 4-4. Common PLL Setting Examples (Cont.)
SCLK MCLK_SRC_SEL SCLK_PREDIV PLL_DIV_INT PLL_DIV_FRAC PLL_MODE PLL_DIVOUT MCLKINT PLL_CAL_RATIO [4]
n
(MHz)
(MHz)
(see p. 64) 1
(see p. 66) 2
(see p. 72)
(see p. 72) 2
(see p. 72) (see p. 72) 3
(see p. 72)
26
1
11
0x39
0xAB 52B5
01
0x11
11.2896
111
1
1
11
0x3B
0x13 B13B
11
0x10
12
118
1
1
11
0x3B
0x13 B13B
01
0x10
12.288
121
1
1. If MCLK_SRC_SEL = 0, the PLL is bypassed and can be powered down by clearing PLL_START (see p. 71).
2. Refer to the register description for the decode.
3. The text following this table explains the use of PLL_DIVOUT, shown by the example configurations in Section 4.4.3.1 and Section 4.4.3.2.
4. The variable n represents the divide ratio. See Eq. 4-2.
Powering up the PLL can be accomplished in several configurations. Table 4-4 shows example configurations; the
sequences in Section 4.4.3.1 and Section 4.4.3.2 can be used as models.
MCLKINT combinations not shown in Table 4-4 can be determined by Eq. 4-1:
Equation 4-1. Configuring SCLK, MCLKINT Configurations
MCLKINT =
SCLK
(PLL_DIV_INT + PLL_DIV_FRAC)
1
X
X
(500/512 or 1029/1024 or 1)
SCLK_PREDIV
PLL_DIVOUT
The internal PLL output must be between ~150 and ~300 MHz. The PLL_DIVOUT value must be an even integer. To
maximize flexibility in sample-rate choice, MCLKINT must be nominally 12 or 24 MHz.
PLL_CAL_RATIO determines the operating point for the internal VCO. For most configurations, the default value gives
proper performance. However, to keep the VCO within range, some scenarios require PLL_CAL_RATIO to be set during
the PLL power-up sequence (see Section 4.4.3). Use Eq. 4-2 to calculate the proper VCO setting at PLL start-up:
Equation 4-2. Calculating the PLL_CAL_RATIO
PLL_CAL_RATIO =
MCLKINT x 32 x SCLK_PREDIV
n x SCLK
The value of n in Eq. 4-2 is determined by the following:
•
If the result is less than or equal to 151, by default, n equals 1.
•
If the result is less than 151, use the result to determine the PLL_CAL_RATIO setting.
•
If the result is greater than 151, select another divide factor of n configurations for SCLK (where n = 2,3, …). The result
must be between 50 and 151 (see the power-up sequence in Section 4.4.3.2). Use the same n value to multiply PLL_
DIVOUT during the power-up sequence; see Step 2 in Section 4.4.3.1. The functional value must be restored (Step 8).
The same is shown in both standard examples.
4.4.3.1 PLL Power-Up Sequence (Example: SCLK = 4.096 MHz and MCLKINT = 12.288 MHz)
In this example, SCLK = 4.096 MHz and MCLKINT = 12.288 MHz.
1. Set SCLK_PREDIV to Divide-by-1 Mode (0x00).
2. Set PLL_DIVOUT to Divide-by-16 Mode (0x10). This reflects a value of n = 1, because the PLL_CAL_RATIO
generated by Eq. 4-2 equals 96. See that the PLL_DIVOUT entry for this configuration in Table 4-4 used a
Divide-by-16 Mode (0x10).
3. Clear the three fractional factor registers, PLL_DIV_FRAC (see Section 7.5.2).
4. Set the integer factor, PLL_DIV_INT to 48 (0x30).
5. Set the PLL Mode multipliers, PLL_MODE to 11 to bypass both 500/512 and 1029/1024 factors (0x03).
6. Set the PLL_CAL_RATIO to 96 (0x60, see Section 7.5.5).
7. Turn on the PLL by setting PLL_START (see p. 71).
8. As part of a standard sequence, after at least 800 s, the PLL_DIVOUT value would need to restored to 16 (0x10),
which is unnecessary here because that value did not change.
DS1081F3
32
CS43L36
4.4 Clocking Architecture
4.4.3.2 PLL Power-Up Sequence (Example: SCLK = 12 MHz and MCLKINT = 24 MHz)
In this example, SCLK = 12 MHz and MCLKINT = 24 MHz.
1. Set SCLK_PREDIV to Divide-by-4 Mode (0x02).
2. Set PLL_DIVOUT to Divide-by-16 Mode (0x10). This reflects a value of n = 2, because the PLL_CAL_RATIO
generated by Eq. 4-2 was greater than 151. See that the PLL_DIVOUT entry for this configuration in Table 4-4
used a Divide-by-8 Mode (0x08).
3. Clear the three fractional factor registers, PLL_DIV_FRAC.
4. Set the integer factor, PLL_DIV_INT to 64 (0x40).
5. Set the PLL mode multipliers, PLL_MODE to 11 to bypass both 500/512 and 1029/1024 factors (0x03).
6. Set the PLL_CAL_RATIO to 128 (0x80).
7. Turn on the PLL by setting PLL_START.
8. After at least 800 s, the PLL_DIVOUT value must be restored from 16 to 8 (0x08).
4.4.3.3 Nonstandard PLL Setting (Example: SCLK = 19.2 MHz and MCLKINT = 12 MHz)
In this example, SCLK = 19.2 MHz and MCLKINT = 12 MHz. (Note that a power-up sequence similar to Section 4.4.3.2 is
required for this configuration due to n = 1.)
•
•
•
•
•
•
•
SCLK = 19.2 MHz = available reference clock.
MCLKINT = 12 MHz = desired internal MCLK.
SCLK_PREDIV = 11 = divide SCLK by 8 as reference to PLL.
PLL_DIV_INT = 0x50 = multiply reference clock by 80, yielding PLL out = 192 MHz.
PLL_DIV_FRAC = 0x00 0000 = fractional portion equal to zero.
PLL_MODE = 11 = 500/512 and 1029/1024 multipliers are bypassed.
PLL_DIVOUT = 0x10 = divide PLL out by 16 to achieve MCLKINT of 12 MHz.
Table 4-5 shows nonstandard PLL configurations.
Table 4-5. Nonstandard PLL Settings
MCLK_SRC_SEL SCLK_PREDIV PLL_DIV_INT PLL_DIV_FRAC PLL_MODE PLL_DIVOUT MCLKINT PLL_CAL_RATIO [1]
n
(MHz)
(see p. 72)
(see p. 64)
(see p. 66)
(see p. 72)
(see p. 72)
(see p. 72)
(see p. 72)
1
10
0x6E
0x40 0000
01
0x18
11.2896
75
1
1
10
0x50
0x00 0000
11
0x10
12
80
1
1
10
0x50
0x00 0000
01
0x10
12.288
82
1
1
10
0x6E
0x400000
01
0x0C
22.5792
150
1
1
10
0x50
0x00 0000
11
0x08
24
80
2
1
10
0x50
0x00 0000
01
0x08
24.576
82
2
19.2
1
11
0x6E
0x40 0000
01
0x18
11.2896
150
1
1
11
0x50
0x00 0000
11
0x10
12
80
2
1
11
0x50
0x00 0000
01
0x10
12.288
82
2
1
11
0x6E
0x40 0000
01
0x0C
22.5792
150
2
1
11
0x50
0x00 0000
11
0x08
24
107
3
1
11
0x50
0x00 0000
01
0x08
24.576
109
3
1. The variable n represents the divide ratio. See Eq. 4-2.
SCLK
(MHz)
9.6
As shown in Fig. 4-13, the input to the PLL is the ASP_SCLK input pin.
PLL_START
ASP_SCLK
VA
(+1.8 V)
Fractional-N
PLL
MCLKINT
Figure 4-13. Clocking Architecture
DS1081F3
33
CS43L36
4.5 Audio Serial Port (ASP)
4.4.3.4 Powering Down the PLL
To power down the PLL, clear PLL_START.
4.5 Audio Serial Port (ASP)
The CS43L36 has an ASP to communicate audio and voice data between system devices, such as application processors
and Bluetooth® transceivers. ASP_SCLK_EN (see p. 65) must be set whenever DAI is used. The ASP can be configured
to TDM, I2S, and left justified (LJ) audio interfaces.
Note:
4.5.1
A maximum of two input channels are supported in TDM Mode.
Slave Mode Timing
The ASP can operate as a slave to another device’s timing, requiring ASP_SCLK and ASP_LRCK/FSYNC to be mastered
by the external device. If ASP_HYBRID_MODE is cleared (see p. 65), the serial port acts as a slave. If ASP_HYBRID_
MODE is set, the port is in Hybrid-Master Mode (see Section 4.5.2).
In Slave Mode, ASP_SCLK and ASP_LRCK are inputs. Although the CS43L36 does not generate interface timings in
Slave Mode, the expected LRCK and SCLK format must be programmed as it is in Hybrid-Master Mode. Table 4-8 shows
supported serial-port sample rate examples. Note that some rates require use of the PLL and/or SRC.
4.5.2
Hybrid-Master Mode Timing
In Hybrid-Master Mode, ASP_LRCK is derived from ASP_SCLK; the ASP_SCLK/ASP_LRCK ratio must be N x FS, where
N is a large enough integer to support the total number of bits per ASP_LRCK period for the audio stream to be transferred.
In either 50/50 Mode or I2S/LJ Mode, the ASP_SCLK/ASP_LRCK ratio must be NE x FS, where NE is an even integer.
The serial port generates an internal LRCK/FSYNC from an externally mastered ASP_SCLK, allowing single clock-source
mastering to the CS43L36. In Hybrid-Master Mode, the serial port must provide a left-right/frame sync signal (ASP_LRCK/
FSYNC) given an externally generated bit clock (ASP_SCLK).
Table 4-6 shows supported serial-port sample-rate examples. Other rates are possible, but the rules stipulated above must
be met. Note that some rates require use of the PLL or SRC.
Table 4-6. Supported Serial-Port Sample Rates
SCLK
Frequency (MHz) 8.0 11.025 11.029 12
1.4112
—
x
—
—
2.8224
—
x
—
—
5.6448
—
x
—
—
11.2896
—
x
—
—
22.5792
—
x
—
—
1.024
x
—
—
—
2.048
x
—
—
—
4.096
x
—
—
—
8.192
x
—
—
—
2
x
—
—
—
3
x
—
x
x
4
x
—
—
—
6
x
—
x
x
12
x
—
x
x
24
x
—
x
x
1.536
x
—
—
x
3.072
x
—
—
x
6.144
x
—
—
x
12.288
x
—
—
x
24.576
x
—
—
x
9.6
x
—
—
x
19.2
x
—
—
x
DS1081F3
Serial Port Sample Rate (kHz)
16 22.05 22.059 24 32 44.1 44.118 48
—
x
—
—
—
x
—
—
—
x
—
—
—
x
—
—
—
x
—
—
—
x
—
—
—
x
—
—
—
x
—
—
—
x
—
—
—
x
—
—
x
—
—
—
x
—
—
—
x
—
—
—
x
—
—
—
x
—
—
—
x
—
—
—
x
—
—
—
x
—
—
—
x
—
—
—
—
—
—
—
—
—
x
x
—
—
x
—
x
—
—
—
x
—
—
—
x
—
x
x
—
—
x
x
x
—
x
x
x
—
x
x
x
—
x
x
x
—
x
x
x
—
—
x
x
—
—
x
x
—
—
x
x
—
—
x
x
—
—
x
x
—
—
x
x
—
—
x
x
—
—
x
x
—
—
x
x
—
—
x
x
—
—
x
x
—
—
x
x
—
—
x
x
—
—
x
88.2 88.235
x
—
x
—
x
—
x
—
x
—
—
—
—
—
—
—
—
—
—
—
—
x
—
—
—
x
—
x
—
x
—
—
—
—
—
—
—
—
—
—
—
—
—
—
96
—
—
—
—
—
—
—
—
—
—
—
—
—
x
x
x
x
x
x
x
x
x
176.4 176.471 192
x
—
—
x
—
—
x
—
—
x
—
—
x
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
x
—
—
—
—
—
x
—
—
x
—
—
x
x
—
—
x
—
—
x
—
—
x
—
—
x
—
—
x
—
—
x
—
—
x
34
CS43L36
4.5 Audio Serial Port (ASP)
Fig. 4-14 and Fig. 4-15 show the serial-port clocking architectures.
ASP_SCLK
0
SCLK in to DAI CLKGEN
1
ASP_SCLK_EN = 1
(See p. 65)
ASP_SCPOL_IN_DAC p. 65
SCLK
IN
To
LRCK_GEN
OUT
CLK DIV
MCLKDIV
p. 64
DIVSEL
Figure 4-14. ASP SCLK Architecture
LR Generation
From SCLK
FSYNC_PULSE_WIDTH_LB p. 64
FSYNC_PULSE_WIDTH_UB p. 64
FSYNC_PERIOD_LB p. 65,
FSYNC_PERIOD_UB p. 65
IN
OUT
HI
ASP_HYBRID_MODE p. 65
0
1
ASP_LRCK/FSYNC
PER
ASP_5050 p. 66
5050
ASP_FSD p. 66
DELAY
ASP_HYBRID_MODE p. 65
ASP_LCPOL_OUT p. 65
LRCK in
0
1
EN
ASP_LCPOL_IN p. 65
Figure 4-15. ASP LRCK Architecture
As shown in Fig. 4-16, the LRCK period (FSYNC_PERIOD_LB and FSYNC_PERIOD_UB, see p. 65) controls the number
of SCLK periods per frame. This effectively sets the frame length and the number of SCLK periods per Fs. Frame length
may be programmed in single SCLK period multiples from 16 to 4096 SCLK:Fs. If ASP_HYBRID_MODE (see p. 65) is
set, the SCLK period multiples must be set to 2 * n * Fs, where n  {8, 9, …, 2048}.
FSYNC_PERIOD
LRCK
SCLK
FSYNC_PULSE_WIDTH
...
...
Falling
Edge
...
...
Rising
Edge
...
...
Figure 4-16. ASP LRCK Period, High Width
FSYNC_PULSE_WIDTH_LB and FSYNC_PULSE_WIDTH_UB (see p. 64) control the number of SCLK periods for which
the LRCK signal is held high during each frame. Like the LRCK period, the LRCK-high width is programmable in single
SCLK periods, from at least one period to at most the LRCK period minus one. That is, the LRCK-high width must be
shorter than the LRCK period.
As shown in Fig. 4-17, if 50/50 Mode is enabled (ASP_5050 = 1, see p. 66), the LRCK high duration must be programmed
to the LRCK period divided by two (rounded down to the nearest integer when the LRCK period is odd). When the serial
port is in 50/50 Mode, setting the LRCK high duration to a value other than half of the period causes erroneous operation.
DS1081F3
35
CS43L36
4.5 Audio Serial Port (ASP)
FSYNC_PERIOD
LRCK
SCLK
FSYNC_PULSE_WIDTH
...
...
Falling
Edge
...
...
Rising
Edge
...
...
Even FSYNC_PERIOD
FSYNC_PERIOD
LRCK
SCLK
FSYNC_PULSE_WIDTH
...
FSYNC_PULSE_WIDTH
...
Falling
Edge
...
...
Rising
Edge
...
...
FSYNC_PERIOD count clock is absent
Odd FSYNC_PERIOD
Figure 4-17. ASP LRCK Period, High Width, 50/50 Mode
Fig. 4-18 shows how LRCK frame start delay (ASP_FSD, see p. 66) controls the number of SCLK periods from LRCK
synchronization edge to the start of frame data.
LRCK
FSD = 101
...
FSD = 100
...
FSD = 011
...
FSD = 010
...
FSD = 001
...
FSD = 000
...
0
0.5
1
1.5
2
2.5
SCLK
SDIN
...
0
1
2
3
4
5
6
7
8
9
... N – 5 N – 4 N – 3 N – 2 N – 1
End of frame
Channel location and size
Figure 4-18. LRCK Frame-Start Delay Example Diagram
4.5.3
Channel Location and Resolution
Each serial-port channel’s location and offset is configured through the registers in Table 4-7. Location is programmable
in single SCLK-period resolution. If set to the minimum location offset, a channel sends or receives on the first SCLK period
of a new frame. Channel size is programmable in 8- to 32-bit byte resolutions. DAC ports are limited to 24 bits and truncate
the 8 LSBs of a 32-bit audio stream.
Table 4-7. ASP Channel Controls
Channel
Resolution
MSB Location
LSB Location
ASP Receive DAI0 Channel 1 ASP_RX0_CH1_RES ASP_RX0_CH1_BIT_ST_MSB ASP_RX0_CH1_BIT_ST_LSB
ASP Receive DAI0 Channel 2 ASP_RX0_CH2_RES ASP_RX0_CH2_BIT_ST_MSB ASP_RX0_CH2_BIT_ST_LSB
Channel size and location must not be programmed such that channel data exceeds the frame boundary. In other words,
channel size and offset must not exceed the expected SCLK per LRCK settings. Size and location must not be
DS1081F3
36
CS43L36
4.5 Audio Serial Port (ASP)
programmed such that data from a given SCLK period is assigned to more than one channel. However, an exception exists
for the DAI as the same data can be used for both received channels’ location, if desired. For an example, see Section 5.1.
Fig. 4-19 shows channel location and size. See ASP_RX0_2FS (p. 78).
First SCLK latching edge of a new frame after frame sync
7
0
503
504
N
511
SCLK
Traditional
‘Slot’
TDM
Channel M Data
7
Slot 0
0 7
Slot 1
0 7
Slot 62
Channel Location = N
Channel Resolution = 10
23
Ch. M MSB
Channel Resolution = 01
15
Ch. M MSB
Channel Resolution = 00
7
Ch. M MSB
Ch. M LSB
Ch. M LSB
0
0
0
Slot 63
0
Don’t Care
Don’t Care
Figure 4-19. Example Channel Location and Size
4.5.4
Isochronous Serial-Port Operation
In Isochronous Mode, audio data can be transferred between the internal audio data paths and a serial port at isochronous
frequencies slower than the LRCK frequency. In all cases, the sample rate/LRCK frequency ratio must be one for which
there are points at which rising edges regularly align.
Notes: Combining an isochronous audio stream on a channel (or on multiple channels) concurrently with a native audio
stream on another channel (or other multiple channels) is not supported.
In Isochronous Mode, if a stream’s sample rate does not match the LRCK frequency, it must include nulls, indicated by
the negative full-scale (NFS) code (1 followed by 0s) or by adding nonaudio bits (NSB Mode) to the data stream.
SP_RX_NFS_NSBB (see p. 77) selects between the NFS and NSB modes.In NFS Mode, to achieve a desired
isochronous output sample rate, a null-insert block adds NFS samples to the output stream. NFS samples input to the
null-insert block are incremented and are passed to the output as valid, nonnull samples.
In NSB Mode, a null-insert block adds 8 bits to the data stream and inserts null samples to achieve a desired isochronous
output sample rate. Inserted null samples are defined as NFS including the nonaudio bits. NFS samples that are input to
the null-insert block are passed as valid, nonnull samples to the output. Valid samples are indicated by a nonzero value
in the null sample indicator bit. The null sample indicator bit is globally defined by the SP_RX_NSB_POS (see p. 77). Total
data stream sample width, including the nonaudio bits, is N + 8 bits. Therefore, the maximum HD audio sample width is
24 bits in NSB Mode.
In NFS Mode, a null-remove block deletes null samples, restoring the stream’s original sample rate. NFS samples that are
input to the null-remove block are removed from the data stream as invalid, null samples.
In NSB Mode, a null-remove block deletes samples that have a zero null sample indicator bit, restoring the stream’s
original sample rate. Furthermore, the output data has the least-significant 8 bits of nonaudio data removed. Samples with
a zero null sample indicator bit are removed from the data stream as invalid, null samples.
In either NSB or NFS Mode, setting the Rx rate fields (SP_RX_FS, see p. 78) matters only if an isochronous mode is
selected via SP_RX_ISOC_MODE (see p. 77). Supported isochronous rates are 48k, 96k, and 192k. The ASPx Rx rate
bits are used only to help determine when to remove nulls and to provide the correct fSI/fSO to the SRCs while in
Isochronous Mode.
For null-remove operations, the rates do not need to match the actual data rate. Likewise, if data is being or captured at
its native rate, these registers have no effect.
DS1081F3
37
CS43L36
4.5 Audio Serial Port (ASP)
As Fig. 4-20 shows, the null-sample bit (NSB) flag may be any bit of the least-significant sample byte. NSB-encoded
streams are assumed to contain 8 bits of nonaudio data as the LSB.
N +8
N
0
Audio Sample
0
ISO null sample indicator bit (selectable, Non‐PCM)
1: Normal sample
0: Null sample
Other bits are ignored
Figure 4-20. NSB Null Encoding
To send isochronous audio data to a serial port, the data pattern must be such that the LRCK/FSYNC transition preceding
any given nonnull sample on the 48-kHz serial port does not deviate by more than one sample period from a virtual clock
running at the desired sample rate. Use the following example to determine the data word as it appears on the serial port.
error = 0
for each LRCK
if(error < 1/FLRCK)
output = <<next sample>>
error = error + (1/Fs - 1/FLRCK)
else
output = NULL
error = error - 1/FLRCK
The null-sample sequences in Table 4-8 result from the example above for common sample rates. This method ensures
that the internal receive data FIFO does not underrun or overrun, which would cause audio data loss. Depending on the
internal audio data FIFOs’ startup conditions and on the serial-port clock-phase relationships, isochronous data sent from
a serial port may not adhere to the data patterns in Table 4-8. In all cases, the transmitted audio data rate matches the
stream sample rate.
Table 4-8. Isochronous Input Data Pattern Examples
Sample Rate (kHz)
Isochronous Data Pattern for LRCK = 48 kHz
8.000
1S5N (repeat)
11.025
[[[1s3nx2]1s4n]x5 1s3n1s4n]x4 [[1s3nx2]1s4n]x4 1s3n1s4n [[[1s3nx2]1s4n]x5 1s3n1s4n]x3
[[1s3nx2]1s4n]x4 1s3n1s4n (repeat)
12.000
1S3N (repeat)
16.000
1S2N (repeat)
22.05
[[1s1nx6]1n [1s1nx6]1n [1s1nx5]1n]x8 [1s1nx6]1n [1s1nx5]1n (repeat)
24.000
1S1N (repeat)
32.000
2S1N (repeat)
44.100
[12s1n[11s1n]x2]x3 11s1n (repeat)
48.000
1S (repeat)
Note: N = Null sample, S = Normal sample
4.5.5
50/50 Mode
Regardless of the state of ASP_LRCK/FSYNC, in 50/50 Mode (ASP_5050 = 1, see p. 66), the ASP can start a frame.
The ASP_STP setting (see p. 66) determines which LRCK/FSYNC phase starts a frame in 50/50 Mode, as follows:
DS1081F3
38
CS43L36
4.5 Audio Serial Port (ASP)
•
If ASP_STP = 0, the frame begins when LRCK/FSYNC transitions from high to low. See Fig. 4-21.
...
LRCK
x_STP = 0
...
SCLK
...
Channel location index
x_CHy_LOC, x_CHz_LOC)
0
1
2
...
...
N/2 – 3 N/2 – 2 N/2 – 1
...
N/2 – 3 N/2 – 2 N/2 – 1
Next Sample
x_CHz_LOC = 0, x_CHz_AP = 1
Channel z
Previous Sample
2
Channel z
x_CHy_LOC = 0, x_CHy_AP = 0
This diagram assumes x_FSD = 0
1
Channel y
Previous Sample
SDIN
0
Channel y
x_CHz_LOC = 0, x_CHz_AP = 0
Next Sample
x_CHy_LOC = 0, x_CHy_AP = 1
Figure 4-21. Example 50/50 Mode (ASP_STP = 0)
•
If ASP_STP = 1, the frame begins when LRCK/FSYNC transitions from low to high. See Fig. 4-22.
LRCK
...
x_STP = 1
...
SCLK
...
Channel location index (x_CHy_LOC, x_CHz_LOC)
Previous Sample
0
1
2
...
...
N/2 – 3 N/2 – 2 N/2 – 1
Previous Sample
1
Channel y
x_CHy_LOC = 0, x_CHy_AP = 1
SDIN
0
...
N/2 – 3 N/2 – 2 N/2 – 1
Channel z
Next Sample
x_CHz_LOC = 0, x_CHz_AP = 0
Channel y
Channel z
x_CHz_LOC = 0, x_CHz_AP = 1
2
Next Sample
x_CHy_LOC = 0, x_CHy_AP = 0
Figure 4-22. Example 50/50 Mode (ASP_STP = 1)
In 50/50 Mode, left and right channels are programmed independently to output when LRCK/FSYNC is high or low—that
is, the channel-active phase. The active phase is controlled by ASP_RXx_CHy_AP (see Section 7.14). If x_AP = 1, the
respective channel is output if LRCK/FSYNC is high. If x_AP = 0, the channel is output if LRCK/FSYNC is low.
Note:
Active phase has no function if 50/50 Mode = 0 or ASP_RX1_2FS = 1.
In 50/50 Mode, the channel location (see Section 4.5.3) is calculated within the channel-active phase. If there are N bits
in a frame, the location of the last bit of each active phase is equal to (N/2) – 1.
4.5.6
Serial Port Status
Each serial port has sticky, write-1-to-clear status bits related to capture paths. These bits are described in Section 7.4.3.
Mask bits (Section 7.4.12) determine whether INT is asserted when a status bit is set. Table 4-9 provides an overview.
Table 4-9. Serial Port Status
Name
Direction
Description
Request
Rx
Set when too many input buffers request processing at the same time. If all channel
Overload
registers are properly configured, this error status should never be set.
LRCK Error
Rx
Logical OR of LRCK Early and LRCK Late (see below).
LRCK Early
Rx
Set when the number of SCLK periods per LRCK phase (high or low) is less than the
expected count as determined by x_LCPR and x_LCHI.
Note: The Rx LRCK early interrupt status is set during the first receive LRCK early event.
Subsequent receive LRCK early events are indicated only if valid LRCK transitions are
detected.
LRCK Late
Rx
Set when the number of SCLK periods per LRCK phase (high or low) is greater than the
expected count as determined by x_LCPR and x_LCHI.
No LRCK
Rx
Note: Set when the number of SCLK periods counted exceeds twice the value of LRCK
period (x_LCPR) without an LRCK edge.
DS1081F3
Register Reference
ASPRX_OVLD p. 67
ASPRX_ERROR p. 67
ASPRX_EARLY p. 67
ASPRX_LATE p. 67
ASPRX_NOLRCK p. 67
39
CS43L36
4.6 Sample-Rate Converters (SRCs)
4.5.7
Recommended Serial-Port Power-Up and Power-Down Strategies
Although multiple safeguards and controls are implemented to prevent a run on the FIFOs involved in passing data from
the input port to the output port, the following power-up sequence is recommended. Section 5 gives detailed sequences.
1. Configure all playback channel characteristics—bit resolution, channel select, source (DAI), native/isochronous,
sample rates, etc.
2. Power up playback, and ASRCs.
3. Release the PDN_ALL bit.
4. Power up the serial ports (DAI).
The following power-down sequence is recommended:
1. Power down the playback path.
2. Power down the serial ports.
4.6 Sample-Rate Converters (SRCs)
SRCs bridge different sample rates at the serial ports within the digital-processing core. SRCs are used for the following:
•
Two ASP input channels (Channels 1 and 2).
•
SRCs are bypassable by setting SRC_BYPASS_DAC (see p. 60).
An SRC’s digital-processing side (as opposed to its serial-port side) connects to the DAC. Multirate DSP techniques are
used to up-sample incoming data to a very high rate and then down-sample to the outgoing rate. Internal filtering is
designed so that a full-input audio bandwidth of 20 kHz is preserved if the input and output sample rates are at least
44.1 kHz. If the output sample rate becomes less than the input sample rate, the input is automatically band limited to avoid
aliasing artifacts in the output signal.
The following restrictions must be met:
•
The Fso-to-FSI ratio must be no more than 1:6 or 6:1. For example, if the DAC is at 48 kHz, the input to the SRC
must be at least 8 kHz.
•
SRC operation cannot be changed on-the-fly. Before changing the SRC operation (e.g., changing SRC frequencies
or bypassing or adding the SRCs), the user must follow the power sequences provided in Section 4.5.7.
•
The MCLK frequency must be as close as possible to, but not less than the minimum SRC MCLK frequency,
MCLKMIN, which must be at least 125 times the higher of the two sample rates (FSI or Fso).
For example, if Fso is 48 kHz and FSI is 32 kHz, the MCLK must be as close as possible to, but not less than, an
MCLKMIN of 6.0 MHz. The MCLK frequency for the SRCs is configured through CLK_IASRC_SEL (see p. 66).
Table 4-10 shows settings for the supported sample rates and corresponding MCLKINT frequencies.
Table 4-10. Supported Sample Rates and Corresponding MCLKINT Encodings
Serial Port Sample Rate (kHz)
Fsint
(kHz) 8.0 11.025 11.029 12 16 22.05 22.059 24 32 44.1 44.118 48 88.2 88.235 96
44.1
00
00
00
00 00
00
00
00 00 00
00
00 01
01
01
48
00
00
00
00 00
00
00
00 00 00
00
00 01
01
01
Note: SRC MCLKINT Freq= 00 (6 MHz), 01 (12 MHz), 11 (24 MHz), configured in CLK_IASRC_SEL (see p. 66)
176.4
10
10
176.471
10
10
192
10
10
Jitter in the incoming signal has little effect on rate-converter dynamic performance. It does not affect the output clock.
A digital PLL continually measures the heavily low-pass-filtered phase difference and the frequency ratio between input
and output sample rate clocks. It uses the data to dynamically adjust coefficients of a linear time-varying filter that
processes a synchronously oversampled version of the input data. The filter output is resampled to the output sample rate.
For input serial ports, input and output sample-rate clocks are respectively derived from the external serial-port sample
clock (x_LRCK) and the internal Fs clock. FS_EN (see p. 66) must be set according to the FSI or Fso SRC sample rates.
DS1081F3
40
CS43L36
4.7 Headset Interface
Minimize the SRCs’ lock time by programming the serial-port interface sample rates into the x_FS registers (see
Section 7.13.1). If the rates are unknown, programming these registers to “don’t know” would likely increase lock times.
Proper operation is not assured if sample rates are misprogrammed.
4.7 Headset Interface
Split digital-power domains (VD_FILT and VP) within the headset interface support an ultralow-power standby mode
where only the VP supply is used. An output signal may be used to tell the system to wake from its low-power state when
a headset plug is inserted or removed. The interface may be reset by three types of resets with progressively less effect.
VA
VD_FILT
VP
VP
VA
VD_FILT
VL
LDO Regulator
and POR
Generator
Power On Reset
Headset Interface
TIP_SENSE
WAKE
Logic
Plug Detect
INT
RESET
RESET
Step-Down,
Inverting Charge
Pump
RESET
–VCP_FILT
–VCP_FILT
Control
Port
GND
GND
Level
Shifters
Control Port
VL
Figure 4-23. Headset Interface Block Diagram
The control port includes registers that source individually maskable interrupts. Event-change debouncing is used to filter
applicable status registers. Latchable duplicate registers are used to pass information to the Standby Mode supply domain.
4.8 Plug Presence Detect
The CS43L36 uses TIP_SENSE to detect plug presence. The sense pin is debounced to filter out brief events before being
reported to the corresponding presence-detect bit and generating an interrupt if appropriate.
4.8.1
Plug Types
The CS43L36 supports the following industry-standard plug types:
•
Tip–Ring–Sleeve (TRS)—Consists of a segmented metal barrel with the tip connector used for HPOUTA, a ring
connector used for HPOUTB, and a sleeve connector used for HSGND.
•
Tip–Ring–Ring–Sleeve (TRRS)—Like TRS, with an additional ring connector for the mic connection. There are two
common pinouts for TRRS plugs:
— One uses the tip for HPOUTA, the first ring for HPOUTB, the second ring for HSGND, and the sleeve for mic.
— The CS43L36 does not support OMTP, or China, headset, which swaps the third and fourth connections, so that
the second ring carries mic and the sleeve carries HSGND.
4.8.2
Tip-Sense Methods
The following methods are used to detect the presence or absence of a plug:
•
Tip sense (TS)—A sense pin is connected to a terminal on the receptacle such that, if no plug is inserted, the pin is floating.
If a plug is inserted, the pin is shorted to the tip (T) terminal. The tip is sensed by having a small current source in the
device pull up the pin if it is left floating (no plug). If a plug is inserted and the sense pin is shorted to HPOUTA, the sense
DS1081F3
41
CS43L36
4.8 Plug Presence Detect
pin is assumed to be pulled low via clamps at the HP amp output when it is in power down. If the HP amp is running, the
sense pin is shorted to the output signal and, therefore, is pulled below a certain threshold via the output stage of the HP
amp. Thus, a low level at the sense pin indicates plug inserted, and a high level at the sense pin indicates plug removed.
•
Inverted tip sense (ITS)—Like tip sense, but with a connector whose sense pin is shorted to the tip terminal if the
plug is removed and is left floating if it is inserted. Therefore, a low level at the sense pin indicates plug removed
and a high level at the sense pin indicates plug inserted. Inversion is controlled by the following:
— The invert (TIP_SENSE_INV, p. 74), which goes to the analog and affects a number of other features.
— The tip-sense invert (TS_INV, p. 63), which affects only the configuration bits in Section 6.2.
4.8.3
Tip-Sense Debounce Settings
Fig. 4-24 shows the tip-sense controls and the associated interrupt, status, and mask registers.
Headset Interface Block
Interrupt Handler Block
TIP_SENSE_PLUG p. 68
TIP_SENSE_UNPLUG p. 68
Interrupt (0x1B7B)
Mask (0x1B79)
Rising/Falling
Edge Detect
INT
M_TS_UNPLUG p. 71
M_TS_PLUG p. 71
TIP_SENSE p. 75
TS_RISE_DBNCE_
TIME p. 63
TIP_SENSE_
DEBOUNCE p. 74
TIP_SENSE
Tip Sense
Plug/Unplug Interrupt
Mask (0x1320)
No
Delay
0
0
PLUG
1
1
UNPLUG
TIP_SENSE_
INV. p. 74
TS_INV p. 63
TS_UNPLUG p. 69
TS_PLUG p. 69
No
Delay
TS_FALL_DBNCE_
TIME p. 63
Tip Sense
Plug/Unplug Interrupt
Status (0x130F)
Tip Sense Indicator
Status Registers (0x1115)
TS_UNPLUG_DBNCp. 64
TS_PLUG_DBNCp. 64
Read
Clears INT
Shadow
Copy
Figure 4-24. Tip-Sense Controls
The tip-sense debounce register fields behave and interact as follows:
•
TS_UNPLUG_DBNC. Shows tip sense status after being unplugged with the associated debounce time.
•
TS_PLUG_DBNC. Shows tip sense status after being plugged in with the associated debounce time.
Note:
TS_INV must be set to have TS_PLUG/TS_PLUG_DBNC status match TIP_SENSE_PLUG status.
The debounce bits are described in Section 7.2.7. Multiple debounce settings can be configured for insertion, removal,
and tip sense:
•
TIP_SENSE_DEBOUNCE (see p. 74) controls the tip-sense removal debounce time.
•
TS_FALL_DBNCE_TIME and TS_RISE_DBNCE_TIME (see p. 63) settings configure the corresponding debounce
times.
4.8.4
Setup Instructions
The following steps are required to activate the tip-sense debounce interrupt status:
1. Clear PDN_ALL (see p. 62).
2. Set LATCH_TO_VP (see p. 74) to latch analog controls into analog circuits.
3. Write TIP_SENSE_CTRL (see p. 74) to 01 or 11 to enable debounce for tip sense plug/unplug.
4. Clear interrupt masks (0x1320, see Section 7.4.17).
Interrupt status (see Section 7.4.9) does not contain an event-capture latch—a read always yields the current condition.
DS1081F3
42
CS43L36
4.9 Power-Supply Considerations
Table 4-11 describes the plug/unplug status.
Table 4-11. Tip Plug/Unplug Status
Plug Status
0
1
0
1
Unplug Status
0
0
1
1
Interpretation
Tip is fully unplugged/not present
Reserved
Tip connection is in a transitional state
Tip is fully plugged/present
4.9 Power-Supply Considerations
Because some power supply combinations can produce unwanted system behavior, note the following:
•
Control-port transactions can occur 1 ms after VP, VD_FILT, VCP, and VL exceed the minimum operating voltage.
•
If VP supply is off, it is recommended that all other supplies are also off. VP must be the first supply turned on.
•
RESET must be asserted until VP is valid.
•
If VD_FILT is supplied externally (DIGLDO_PDN = GND), VL must be supplied before VD_FILT, VA, VL, and VCP
can come up in any order. Due to the VD_FILT POR, VD_FILT must be turned off before VA, VL, or VCP are turned
off; otherwise, current could be drawn from supplies that remain on.
Table 4-12 shows the maximum current for each supply when VP is on, but other supplies are on or off (all clocks are off
and all registers are set to default values, i.e., reset).
Table 4-12. Typical Leakage Current during Nonoperational Supply States (with VP Powered On)
Supply
Current (µA)
Notes
IVCP
IVA
IVL
VA
VL
IVp
On
Off
14
0
0
0
VA may source or sink current
On
On
25
0
0
328
VA may source or sink current
Off
Off
14
0
0
0
—
Off
On
25
0
0
328
—
On
Off
14
0
0
0
VA may source or sink current
On
On
25
0
0
328
—
• Values shown reflect typical voltage and temperature. Leakage current may vary by orders of magnitude across the maximum
and minimum recommended operating supply voltages and temperatures listed in Table 3-2.
• Test conditions: Clock/data lines are held low, RESET is held high, and all registers are set to their default values.
VCP
Off
Off
On
On
On
On
Notes:
Table 4-13 shows requirements and available features for valid power-supply configurations.
Table 4-13. Valid Power-Supply Configurations
Configuration
On: VP
Off: VD_FILT = VCP = VL = VA
On: VP = VL
Off: VD_FILT = VCP = VA = OFF
On: VP = VD_FILT = VCP = VL = VA
4.9.1
Notes
Limited set of headset plug-detect and WAKE output features, see Section 4.7 and Section 4.8.
Limited set of headset plug-detect and WAKE output features, see Section 4.7 and Section 4.8.
Digital I/O ESD diodes are powered to prevent conduction in pin-sharing applications.
Full chip functionality
VP Monitor
The CS43L36 voltage comparator monitors the VP power supply for potential brown-out conditions due to power-supply
overload or other fault conditions. To perform according to specifications, VP is expected to remain above 3.0 V at all
times. The VP monitor is enabled by setting VPMON_PDNB (see p. 63). Fig. 4-25 shows the behavior of the VP monitor.
3.6 V
3.0 V
2.6 V
VPMON_TRIP
Figure 4-25. VP Monitor
DS1081F3
43
CS43L36
4.9 Power-Supply Considerations
The following describes the VP monitor behavior with respect to the voltage level:
•
If VP drops below 3.0 V, TIP_SENSE performance may be compromised.
•
If VP drops below 2.6 V, the VPMON_TRIP status bit is set (see p. 68). An interrupt is triggered if M_VPMON_
TRIP = 0 (see p. 71). This bit must be unmasked/enabled only if VP is above the detection-voltage threshold. It must
be masked/disabled by default to eliminate erroneous interrupts while VP is ramping or is known to be below the
threshold voltage.
•
A brown-out condition remains until VP returns to a voltage level above 3.0 V.
•
The VP monitor circuit becomes unreliable at VP levels below 2.4 V.
•
The VP monitor is intended to detect slow transitioning signals about the 2.6-V threshold. Pulses of short duration
are filtered by the monitor and may not trigger at the 2.6-V threshold, but at a value much lower than expected.
DS1081F3
44
CS43L36
4.10 Control-Port Operation
4.10 Control-Port Operation
Control-port registers are accessed through the I2C interface, allowing the DAC to be configured for the desired
operational modes and formats.
4.10.1 I2C Control-Port Operation
The I2C control port can operate completely asynchronously with the audio sample rates. However, to avoid interference
problems, the I2C control port pins must remain static if no operation is required.
The control port uses the I2C interface, with the DAC acting as a slave device. The I2C control port can operate in the
following modes, which are configured through the I2C debounce register in Section 7.1.9:
•
Standard Mode (SM), with a bit rate of up to 100 kbit/s
•
Fast Mode (FM), with a bit rate of up to 400 kbit/s
•
Fast Mode Plus (FM+), with a bit rate of up to 1 Mbit/s.
Note:
ASP_SCLK is not required to be on when the control port is accessed, for state machines affected by register
settings to advance.
SDA is a bidirectional data line. Data is clocked into and out of the CS43L36 by the SCL clock. Fig. 4-26–Fig. 4-29 show
signal timings for read and write cycles. A Start condition is defined as a falling transition of SDA while the clock is high.
A Stop condition is defined as a rising transition of SDA while the clock is high. All other SDA transitions occur while the
clock is low.
The register address space is partitioned into 8-bit page spaces that each comprise up to 127 8-bit registers. Address 0x00
of each page is reserved as the page indicator, PAGE. Writing to address 0x00 of any page changes the page pointer to
the address written to address 0x00.
To initiate a write to a particular register in the map, the page address, 0x00, must be written following the chip address.
Subsequent accesses to register addresses are treated as offsets from the page address written in the initial transaction.
To change the page address, initiate a write to address 0x00. To determine which page is active, read address 0x00.
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
19
24 25 26 27
SCL
3
Addr = 10010
START
SDA
Source
2
1
0
ACK
7
INCR = 0
4
AD0
5
R/W = 0
6
AD1
7
SDA
MAP BYTE
6
5
4
3
2
DATA
1
MAP Addr = 0
0
7
ACK
Pullup
Master
Master
Slave
6
1
Addr Data
to Addr 0
CHIP ADDRESS (WRITE)
0
ACK
STOP
Master
Master
Slave
Slave Pullup
Figure 4-26. Control-Port Timing, I2C Write of Page Address
The first byte sent to the CS43L36 after a Start condition consists of a 7-bit chip address field and a R/W bit (high for a
read, low for a write) in the LSB. To communicate with the CS43L36, the chip address field must match 1_0010, followed
by the state of the AD1 and AD0 pins.
Note:
Because AD0 and AD1 logic states are latched at POR, dynamic addressing is not supported.
If the operation is a write, the next byte is the memory address pointer (MAP); the 7 LSBs of the MAP byte select the
address of the register to be read or written to next. The MSB of the MAP byte, INCR, selects whether autoincrementing
is to be used (INCR = 1), allowing successive reads or writes of consecutive registers.
Each byte is separated by an acknowledge (ACK) bit, which the CS43L36 outputs after each input byte is read and is input
to the CS43L36 from the microcontroller after each transmitted byte.
DS1081F3
45
CS43L36
4.10 Control-Port Operation
For write operations, the bytes following the MAP byte are written to the CS43L36 register addresses pointed to by the
last received MAP address, plus however many autoincrements have occurred. Note that, while writing, any
autoincrementing block accesses that go past the maximum 0x7F address write to address 0x00—the page address. The
writes then continue to the newly selected page. Fig. 4-27 shows a write pattern with autoincrementing.
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
24 25 26 27 28
19
SCL
SDA
Source
1
0
7
ACK
6
5
4
3
2
1
0
7
MAP Addr = X
ACK
6
1
DATA
0
7
ACK
6
1
DATA
0
7
6
1
0
ACK
STOP
Data to Addr X+n
Addr = 10010
START
2
DATA
Data to Addr X+1
3
INCR = 1
4
AD0
5
R/W = 0
6
AD1
7
SDA
MAP BYTE
Data to Addr X
CHIP ADDRESS (WRITE)
Master
Master
Pullup
Master
Master
Master
Master
Slave
Slave
Slave
Slave Pullup
Slave
Figure 4-27. Control-Port Timing, I2C Writes with Autoincrement
For read operations, the contents of the register pointed to by the last received MAP address, plus however many
autoincrements have occurred, are output in the next byte. While reading, any autoincrementing block access that goes
past the maximum 0x7F address wraps around and continues reading from the same page address. Fig. 4-28 shows a
read pattern following the write pattern in Fig. 4-27. Notice how read addresses are based on the MAP byte from Fig. 4-27.
0
1
2
3
4
5
6
7
8
9
16
17
18
25
27
34
35
36
SCL
DATA
3
Addr = 10010
START
2
1
0
7
ACK
Pullup
SDA
Source
7
0
ACK
0
Master
Master
Slave
DATA
7
0
Data from
Addr X+n+3
4
Data from
Addr X+n+1
5
R/W = 1
6
AD0
7
AD1
SDA
DATA
Data from
Addr X+n+2
CHIP ADDRESS (READ)
Master
Slave
NO
ACK
STOP
Master
Pullup
Slave
Figure 4-28. Control-Port Timing, I2C Reads with Autoincrement
To generate a read address not based on the last received MAP address, an aborted write operation can be used as a
preamble (see Fig. 4-29). Here, a write operation is aborted (after the ACK for the MAP byte) by sending a Stop condition.
DS1081F3
46
CS43L36
4.11 Reset
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
16
17 18
19
20 21 22 23 24 25 26 27 28
SCL
ACK
6
5
4
3
2
MAP Addr = Z
1
0
7
6
5
4
ACK
Addr = 10010
START
3
2
1
0
ACK
7
0
7
ACK
Master
Slave
Master
Slave
Slave
0
7
0
Slave
Slave
Pullup
Master
DATA
Data from Addr Z+n
7
0
DATA
Data from Addr Z+1
SDA
Source
1
DATA
Data from Addr Z
Addr = 10010
START
2
AD0
3
CHIP ADDRESS (READ)
R/W = 1
4
INCR = 1
5
AD0
6
R/W = 0
7
AD1
SDA
STOP
MAP BYTE
AD1
CHIP ADDRESS(WRITE)
Master
Master
NO
ACK
STOP
Pullup
Master
Figure 4-29. Control-Port Timing, I2C Reads with Preamble and Autoincrement
The following pseudocode illustrates an aborted write operation followed by a single read operation, assumes page
address has been written. For multiple read operations, autoincrement would be set to on (as shown in Fig. 4-29).
Send start condition.
Send 10010(AD1)(AD0)0 (chip address and write operation).
Receive acknowledge bit.
Send MAP byte, autoincrement off.
Receive acknowledge bit.
Send stop condition, aborting write.
Send start condition.
Send 10010(AD1)(AD0)1 (chip address and read operation).
Receive acknowledge bit.
Receive byte, contents of selected register.
Send acknowledge bit.
Send stop condition.
4.11 Reset
The CS43L36 offers the reset options described in Table 4-14.
Table 4-14. Reset Summary
Reset
Cause
Result
Asserting RESET If RESET is asserted, all registers (both VP and VD_FILT domains) and all state machines are
immediately set to their defaults. No operation can begin until RESET is deasserted. Before normal
operation can begin, RESET must be asserted at least once after the VP supply is first brought up.
Power-on reset (POR) Power up
If VD_FILT is lower than the POR threshold, the VD_FILT register fields and the state machines are
held in reset, setting them to their default values/states. This does not reset the VP registers. The
POR releases the reset when the VD_FILT supply goes above the POR threshold.
VL and VA supplies must be turned at the same time the VD_FILT supply is turned on.
Device hard reset
4.12 Interrupts
The following sections describe the CS43L36 interrupt implementation.
4.12.1 Standard Interrupts
The interrupt output pin, INT, is used to signal the occurrence of events within the device’s interrupt status registers. Events
can be masked individually by setting corresponding bits in the interrupt mask registers. Table 4-15 lists interrupt status
and mask registers. The configuration of mask bits determines which events cause the immediate assertion of INT:
•
When an unmasked interrupt status event is detected, the status bit is set and INT is asserted.
•
When a masked interrupt status event is detected, the interrupt status bit is set, but INT is not affected.
Once asserted, INT remains asserted until all status bits that are unmasked and set have been read. Interrupt status bits
are sticky and read-to-clear: Once set, they remain set until the register is read and the associated interrupt condition is
not present. If a condition is still present and the status bit is read, although INT is deasserted, the status bit remains set.
DS1081F3
47
CS43L36
5 System Applications
To clear status bits set due to initiation of a path or block, the status bits must be read after the corresponding module is
enabled and before normal operation begins. Otherwise, unmasking previously set status bits causes assertion of INT.
Table 4-15. Interrupt Status Registers and Corresponding Mask Registers—0x13
Interrupt Source Status Register
SRC Interrupt Status (Section 7.4.2)
ASP RX Interrupt Status (Section 7.4.3)
DAC Interrupt Status (Section 7.4.4)
Detect Interrupt Status 1 (Section 7.4.5)
SRC Partial Lock Interrupt Status (Section 7.4.6)
VP Monitor Interrupt Status (Section 7.4.7)
PLL Lock Interrupt Status (Section 7.4.8)
Interrupt Mask Register
SRC Interrupt Mask (Section 7.4.11)
ASP RX Interrupt Mask (Section 7.4.12)
DAC Interrupt Mask (Section 7.4.13)
Detect Interrupt Mask 1 (Section 7.7.5)
SRC Partial Lock Interrupt Mask (Section 7.4.14)
VP Monitor Interrupt Mask (Section 7.4.15)
PLL Lock Mask (Section 7.4.16)
As Table 4-16 indicates, interrupt sources are categorized into two groups:
•
Condition-based interrupt source bits are set when the condition is present and they remain set until the register is
read and the condition that caused the bit to assert is no longer present.
•
Event-based interrupt source bits are cleared when read. In the absence of subsequent source events, reading one
of these status bits returns a 0.
Table 4-16. Interrupt Source Types
Group
Status Registers
Tip sense debounce (see Section 7.2.7) TS_UNPLUG_DBNC
TS_PLUG_DBNC
CHA_OVFL
Channel Overflow Interrupt
CHB_OVFL
(see Section 7.4.1)
ASPRX_OVLD
Serial port
ASPRX_ERROR
(see Section 7.4.2, Section 7.4.3)
ASPRX_LATE
ASPRX_EARLY 1
ASPRX_NOLRCK 1
SRC_IUNLK
SRC_ILK
PDN_DONE
Global (see Section 7.4.4)
Headset (see Section 7.4.5)
TIP_SENSE_PLUG
TIP_SENSE_UNPLUG
DAC_LK
DAC (see Section 7.4.6)
VP monitor (see Section 7.4.7)
VPMON_TRIP
PLL (see Section 7.4.8)
PLL_LOCK
TS_UNPLUG
Tip sense plug/unplug status (see
Section 7.4.9)
TS_PLUG
Interrupt Source Type
Event
Event
Event
Event
Event
Event
Event
Event
Condition
Condition
Condition
Condition
All are events.
Condition
Condition
Condition
Events. Although a true event interrupt
clears when read, these dynamically reflect
the state of the debounced input signal.
1.Reading this bit following an early LRCK/SM error/no LRCK returns a 1. Subsequent reads return a 0. Valid LRCK transitions or exiting the transmit
overflow condition rearms the detection of the corresponding event. See Table 4-9 for details.
5 System Applications
This section provides recommended procedures and instruction sequences for standard operations.
5.1 Power-Up Sequence
Ex. 5-1 is the procedure for implementing HP playback from the ASP. This example sequence configures the CS43L36
for SCLK = 12.288 MHz, LRCK = 48 kHz, and TDM playback, in Slave Mode.
Example 5-1. Power-Up Sequence
STEP
1
2
TASK
REGISTER/BIT FIELDS
VALUE
DESCRIPTION
Apply all relevant power supplies, then assert RST before applying SCLK and LRCK to the CS43L36.
Wait 2.5 ms.
DS1081F3
48
CS43L36
5.1 Power-Up Sequence
Example 5-1. Power-Up Sequence (Cont.)
STEP
3
4
TASK
Power up the DAC.
REGISTER/BIT FIELDS
Power Down Control 2. 0x1102
Reserved
DISCHARGE_FILT+
SRC_PDN_OVERRIDE
Reserved
DAC_SRC_PDNB
Reserved
Configure the device’s ASP and ASP SRC.
4.1 Configure switch
Oscillator Switch Control. 0x1107
from RCO to SCLK. Reserved
SCLK_PRESENT
4.2 Power down the
Oscillator Switch Status. 0x1109
RCO.
Reserved
OSC_PDNB_STAT
OSC_SW_SEL_STAT
4.3 Configure device’s MCLK Control. 0x1009
internal sample rate Reserved
with the applied
INTERNAL_FS
MCLK signal.
Reserved
4.4 Select MCLK
MCLK Source Select. 0x1201
source.
Reserved
MCLKDIV
MCLK_SRC_SEL
4.5 Configure the
FSYNC Period, Lower Byte. 0x1205
FSYNC period.
FSYNC_PERIOD_LB
4.6 Configure the
FSYNC Period, Upper Byte. 0x1206
FSYNC period.
FSYNC_PERIOD_UB
4.7 Configure FSYNC FSYNC Pulse Width, Lower Byte. 0x1203
pulse width.
FSYNC_PULSE_WIDTH_LB
4.8 Configure the ASP ASP Clock Configuration 1. 0x1207
clock.
Reserved
ASP_SCLK_EN
ASP_HYBRID_MODE
Reserved
ASP_SCPOL_IN_DAC
ASP_LCPOL_OUT
ASP_LCPOL_IN
4.9 Configure the ASP ASP Frame Configuration. 0x1208
frame.
Reserved
ASP_STP
ASP_5050
ASP_FSD
4.10Configure serial port Serial Port Receive Channel Select. 0x2501
receive channel
Reserved
positions.
SP_RX_CHB_SEL
SP_RX_CHA_SEL
4.11Set receive sample Serial Port Receive Sample Rate. 0x2503
rate.
Reserved
SP_RX_FS
4.12Configure the SRC SRC Input Sample Rate. 0x2601
sample rate
Reserved
detection.
SRC_SDIN_FS
4.13Configure Channel 2 ASP Receive DAI0 Channel 2 Phase and Resolution.
size to 24 bits per 0x2A05
sample.
Reserved
ASP_RX0_CH2_AP
Reserved
ASP_RX_CH2_RES
4.14Configure location of ASP Receive DAI0 Channel 2 Bit Start MSB. 0x2A06
the Channel 2 MSB Reserved
with respect to SOF. ASP_RX0_CH2_BIT_ST_MSB
4.15Configure location of ASP Receive DAI0 Channel 2 Bit Start LSB. 0x2A07
the Channel 2 LSB
ASP_RX0_CH2_BIT_ST_LSB
with respect to SOF.
DS1081F3
VALUE
DESCRIPTION
0x83
100
0
0
0
1
1
—
FILT+ is not clamped to ground.
SRC is powered up.
—
DAC SRC is powered up.
—
0x01
0000 000 —
1
SCLK is present.
0x01
0000 0 —
0
RCO powered down
01
RCO selected for internal MCLK
0x02
0000 00 —
1
Internal sample rate is MCLK/256= 48 kHz.
0
—
0x00
0000 00 —
0
Divide by 1.
0
SCLK pin is MCLK source.
0xFF
1111 1111 256 SCLKs per LRCK lower byte.
0x00
0000 0000 0 SCLKs per LRCK upper byte
0x1F
0001 1111 LRCK is one SCLK Wide.
0x00
00
—
0
ASP SCLK disabled.
0
LRCK is an input from an external source.
0
—
0
SCLK input drive polarity for DAC is normal.
0
LRCK output drive polarity is normal.
0
LRCK input polarity (pad to logic) is normal.
0x10
000
—
1
Frame begins when LRCK transitions low to high
0
LRCK duty cycle per FSYNC_PULSE_WIDTH_LB/UB
000
Zero SCLK frame start delay
0x04
0000 —
01
SP RX Channel B position is 1.
00
SP RX Channel A position is 0.
0x8C
100
—
0 1100 SP receive sample rate = 48 kHz.
0x20
0010 —
0000 ASP sample rate is autodetected.
0x02
0
—
0
In 50/50 mode, channel data valid if LRCK is low.
00 00 —
10
Size is 24 bits per sample.
0x00
0000 000 —
0
ASP receive bit start MSB = 0.
0x18
0001 1000 ASP transmit bit start LSB = 24.
49
CS43L36
5.2 Power-Down Sequence
Example 5-1. Power-Up Sequence (Cont.)
STEP
TASK
4.16Disable the SRC
bypass.
5
Enable SCLK.
REGISTER/BIT FIELDS
Serial Port SRC Control. 0x1007
Reserved
I2C_DRIVE
Reserved
SRC_BYPASS_DAC
Reserved
ASP Clock Configuration 1. 0x1207
Reserved
ASP_SCLK_EN
ASP_HYBRID_MODE
Reserved
ASP_SCPOL_IN_DAC
ASP_LCPOL_OUT
ASP_LCPOL_IN
6 Configure the DAC.
DAC Control 1. 0x1F01
Reserved
DACB_INV
DACA_INV
7 Configure the appropriate volume controls and DAC source selects.
7.1 Set Mixer A input to Channel A Input Volume. 0x2301
0 dB.
Reserved
CHA_VOL
7.2 Set Mixer B input to Channel B Input Volume. 0x2303
0 dB.
Reserved
CHB_VOL
8 Configure the HP control.HP Control. 0x2001
Reserved
ANA_MUTE_B
ANA_MUTE_A
FULL_SCALE_VOL
Reserved
9 Power up the DAC/HP. Power Down Control 1. 0x1101
Reserved
ASP_DAI_PDN
MIXER_PDN
Reserved
HP_PDN
Reserved
PDN_ALL
10 The headphone amplifier is operational after 10 ms.
VALUE
DESCRIPTION
0x10
0001
0
0
0
0
0x20
00
1
0
0
0
0
0
0x00
0000 00
0
0
0x00
00
00 0000
0x00
00
00 0000
0x03
0000
0
0
1
1
0x96
1
0
0
1
0
11
0
—
I2C output drive strength normal
—
SRC not bypassed for DAC path
—
—
ASP SCLK enabled.
LRCK is an input generated from SCLK.
—
SCLK input drive polarity for DAC is normal.
LRCK output drive polarity is normal.
LRCK input polarity (pad to logic) is normal.
—
DACA signal not inverted.
DACB signal not inverted.
—
Input A is set to 0 dB.
—
Input B is set to 0 dB.
—
Channel B is unmuted.
Channel A is unmuted.
Full-scale volume is -6dB for headphone output.
—
—
ASP input path is powered up.
Mixer is powered up.
—
HPOUT powered up.
—
DAC powered up.
5.2 Power-Down Sequence
Ex. 5-2 is the procedure for powering down the HP playback.
Example 5-2. Power-Down Sequence
STEP TASK
REGISTER/BIT FIELDS
1 Configure the DAC/volume Channels.
1.1 Mute Volume A input. Channel A Input Volume. 0x2301
Reserved
CHA_VOL
1.2 Mute Volume B input. Channel B Input Volume. 0x2303
Reserved
CHB_VOL
1.3 Mute Channel A and HP Control. 0x2001
B inputs.
Reserved
ANA_MUTE_B
ANA_MUTE_A
FULL_SCALE_VOL
Reserved
1.4 Disable SCLK.
ASP Clock Configuration 1. 0x1207
Reserved
ASP_SCLK_EN
ASP_HYBRID_MODE
Reserved
ASP_SCPOL_IN_DAC
ASP_LCPOL_OUT
ASP_LCPOL_IN
DS1081F3
VALUE
0x3F
00
11 1111
0x3F
00
11 1111
0x0F
0000
1
1
1
1
0x00
00
0
0
0
0
0
0
DESCRIPTION
—
Input A is muted.
—
Input B is muted.
—
Channel B is muted.
Channel A is muted.
Full-scale volume is –6 dB for headphone output.
—
—
ASP SCLK disabled.
LRCK is an output generated from SCLK.
—
SCLK input drive polarity for DAC is normal.
LRCK output drive polarity is normal.
LRCK input polarity (pad to logic) is normal.
50
CS43L36
5.3 Page 0x30 Read Sequence
Example 5-2. Power-Down Sequence (Cont.)
STEP TASK
REGISTER/BIT FIELDS
2 Power down the HP
amplifier.
VALUE
Power Down Control 1. 0x1101
0xFE
Reserved
1
ASP_DAI_PDN
1
MIXER_PDN
1
Reserved
1
HP_PDN
1
Reserved
11
PDN_ALL
0
Power down the ASP and Power Down Control 2. 0x1102
0x8C
SRC.
Reserved
100
DISCHARGE_FILT+
0
SRC_PDN_OVERRIDE
1
Reserved
1
DAC_SRC_PDNB
0
Reserved
0
Power down the DAC.
Power Down Control 1. 0x1101
0xFF
Reserved
1
ASP_DAI_PDN
1
MIXER_PDN
1
Reserved
1
HP_PDN
1
Reserved
11
PDN_ALL
0
Read PDN_DONE to
DAC Interrupt Status. 0x1308
0x01
confirm that the DAC is
Reserved
0000 000
completely powered down. PDN_DONE
1
Repeat Step 5 until the PDN_DONE status bit indicates the DAC has powered down.
Discharge the capacitor
Power Down Control 2. 0x1102
0x9C
attached to the FILT+ pin.
Reserved
100
DISCHARGE_FILT+
1
SRC_PDN_OVERRIDE
1
Reserved
1
DAC_SRC_PDNB
0
Reserved
0
If required, remove the SCLK signal.
If required, remove all relevant power supplies from the DAC.
3
4
5
6
7
8
9
DESCRIPTION
—
ASP input path is powered down
Mixer is powered down
—
HPOUT powered down
—
DAC powered up
—
FILT+ is not clamped to ground.
SRC is powered down.
—
DAC SRC is powered down.
—
—
ASP input path is powered down
Mixer is powered down
—
HPOUT powered down
—
DAC powered down.
—
Power-down done.
—
FILT+ is clamped to ground.
SRC is powered down.
—
DAC SRC is powered down.
—
5.3 Page 0x30 Read Sequence
The following sequence is required to read from Page 0x30:
1. Power up Page 0x30 by clearing bit 7 of register 0x1102.
2. Enable Page 0x30 reads by writing the value 0x01 to register 0x1801.
3. Perform the read from Page 0x30.
5.4 PLL Clocking
Data-path logic is in the MCLK domain, where SCLK is expected to be 12 or 24 MHz. For clocking scenarios where ASP_
SCLK is neither 12 nor 24 MHz, the PLL must be turned on to provide the desired internal MCLK. At startup, the system
sets the SCLK bypass as default mode and switches to PLL output after it settles. PLL start-up time is a maximum of 1 ms.
5.5
VD_FILT/VL ESD Diode
Note the following:
•
If VD_FILT is supplied externally, VL must be supplied before VD_FILT.
•
If the internal LDO is enabled, it generates VD_FILT from VL.
•
If the LDO is disabled (DIGLDO_PDN asserted) and VD_FILT is supplied externally; however, the LDO diode could
be forward biased in cases where VD_FILT is supplied first.
•
If the LDO is disabled and VD_FILT and VL are respectively powered via separate 1.2- and 1.8-V supplies, it is
recommended to have an ESD diode between VD_FILT and VL.
DS1081F3
51
CS43L36
6 Register Quick Reference
6 Register Quick Reference
Table 6-1 lists the register page addresses for each module.
Table 6-1. Register Base Addresses
Module Group
Chip-Level
Page
0x10
0x11
0x12
0x13
0x14
0x15
0x16–0x18
0x19
0x1A
Analog Input
0x1B
0x1E
Analog Outputs
0x1F
0x20
0x21
0x22
Internal Modules
0x23
0x24
0x25
0x26
0x27
Serial Ports
0x28
0x29
0x2A
—
0x2B–0x2F
ID registers
0x30
—
0x31–0xFF
Module
Reference
Section 6.1 on p. 52
Section 6.2 on p. 53
Section 6.3 on p. 54
Section 6.4 on p. 54
—
Section 6.5 on p. 55
—
Section 6.6 on p. 56
—
Section 6.7 on p. 56
—
Section 6.8 on p. 57
Section 6.9 on p. 57
Section 6.10 on p. 57
—
Section 6.11 on p. 57
—
Section 6.12 on p. 58
Section 6.13 on p. 58
—
—
—
Section 6.14 on p. 58
—
Section 6.15 on p. 59
—
Global
Power-down and headset detect
Clocking
Interrupt
Reserved
Fractional-N PLL
Reserved
Headphone load detect
Reserved
Headset Interface
Reserved
DAC
HP control
Class H
Reserved
Mixer volume
Reserved
AudioPort interface
SRC
Reserved
Reserved
Reserved
ASP receive
Reserved
ID registers
Reserved
Notes:
•
•
•
•
•
Default values are shown below the bit field names.
Default bits marked “x” are reserved or undetermined.
Fields shown in red are controls that are also located in the VP power supply domain.
Fields shown in turquoise are status indicators from the VP power supply domain that are selectively raw or sticky.
Fields shown in orange are affected by the FREEZE bit (see p. 59).
6.1 Global Registers
I2C Address: 10010(AD1)(AD0)[R/W] through 10010(AD1)(AD0)0 = 0x94(Write); 10010(AD1)(AD0)1 = 0x95 (Read)
Page 0x10—Global Registers
Function
Address
0x00
7
6
5
4
Control Port Page
0
0
0
1
0x01–0x04 Reserved
p. 59
0x06
Revision ID (Read
Only)
0x07
x
x
x
x
0
DS1081F3
0
0
0
0
0
x
x
x
x
x
MTLREVID
x
x
x
x
x
0
0
0
—
0
0
0
1
x
FREEZE
—
Serial Port SRC
Control
p. 60
1
AREVID
Freeze Control
p. 59
2
—
x
0x05
3
PAGE
0
0
0
0
I2C_DRIVE
—
SRC_
BYPASS_DAC
—
0
0
0
0
52
CS43L36
6.2 Power-Down and Headset-Detect Registers
I2C Address: 10010(AD1)(AD0)[R/W] through 10010(AD1)(AD0)0 = 0x94(Write); 10010(AD1)(AD0)1 = 0x95 (Read)
Page 0x10—Global Registers
Function
Address
0x08
p. 60
0x09
5
0
0
0
0
0
0
0
0
0
—
x
0x0F
0
0x10
1
x
0
1
x
I2C_SDA_DBNC_CNT
1
I2C Timeout
p. 61
1
0
0
0
0
0
0
x
x
0
1
—
0
0
x
x
I2C_SDA_
DBNC_EN
0
x
I2C_SCL_DBNC_CNT
0
I2C Stretch
p. 61
0
—
—
I2C Debounce
p. 61
x
DSR_RATE
1
1
0
—
INTERNAL_FS
SLOW_START_EN
0
1
INTERNAL_
FS_STAT
0
0
0x0C–0x0D Reserved
0x0E
2
ASR_RATE
1
p. 61
3
—
Soft Ramp Rate
Slow Start Enable
4
—
0
p. 60
0x0B
6
MCLK Control
p. 60
0x0A
7
MCLK Status
(Read Only)
1
0
0
0
I2C_SCL_
DBNC_EN
0
0
1
1
I2C_STRETCH
0
0
MAS_I2C_
NACK
MAS_TO_DIS
0
1
0
0
MAS_TO_SEL
1
ACC_TO_DIS
1
0x11–0x7F Reserved
ACC_TO_SEL
0
1
1
1
x
x
x
x
—
x
x
x
x
6.2 Power-Down and Headset-Detect Registers
Address
0x00
0x01
I2C Address: 10010(AD1)(AD0)[R/W] through 10010(AD1)(AD0)0 = 0x94(Write); 10010(AD1)(AD0)1 = 0x95 (Read)
Page 0x11—Power-Down and Headset-Detect Registers
Function
7
6
5
4
3
2
1
Control Port Page
PAGE
0
0
0
1
0
0
0
Power Down Control 1
ASP_DAI_
MIXER_PDN
HP_PDN
—
—
PDN
p. 62
0x02
1
Power Down Control 2
p. 62
0x03
1
1
—
1
0
0
Power Down Control 3
p. 63
0
1
1
1
1
1
1
SRC_PDN_
OVERRIDE
—
DAC_SRC_
PDNB
—
0
0
1
0
VPMON_
PDNB
0
0x04–0x06 Reserved
x
x
Oscillator Switch
Control
p. 63
Reserved
0x09
Oscillator Switch
Status (Read Only)
x
0
0
p. 63
0x15
x
x
0
x
0
x
0
x
0
x
OSC_PDNB_
STAT
0
x
x
TS_INV
—
0
0
x
0
1
x
x
x
TS_FALL_DBNCE_TIME
0
1
—
0
0
0
x
0
0
x
x
OSC_SW_SEL_STAT
0
1
x
x
TS_RISE_DBNCE_TIME
1
0
TS_UNPLUG_
DBNC
TS_PLUG_
DBNC
x
x
x
x
x
x
x
x
0
0x16–0x7F Reserved
1
1
—
—
x
DS1081F3
x
0
—
Tip Sense Indicator
Status (Read Only)
p. 64
x
—
0
Tip Sense Control 1
0
SCLK_
PRESENT
0
0x0A–0x12 Reserved
0x13
0
—
x
p. 63
0
—
0
0x08
0
—
—
x
0x07
1
PDN_ALL
DISCHARGE_
FILT+
—
0
0
x
x
x
53
CS43L36
6.3 Clocking Registers
6.3 Clocking Registers
I2C Address: 10010(AD1)(AD0)[R/W] through 10010(AD1)(AD0)0 = 0x94 (Write); 10010(AD1)(AD0)1 = 0x95 (Read)
Page 0x12—Clocking Registers
Function
Address
0x00
Control Port Page
0x01
MCLK Source Select
7
6
0
Reserved
0x03
FSYNC Pulse Width
Lower Byte
0x04
p. 65
0x05
p. 65
0x06
p. 65
0x07
FSYNC Pulse Width
Upper Byte
FSYNC Period Lower
Byte
FSYNC Period Upper
Byte
0x08
p. 66
0x09
p. 66
0
0x0B
Reserved
0x0C
PLL Divide
Configuration 1
0
x
0
0
0
0
1
MCLKDIV
0
MCLK_SRC_
SEL
0
0
0
0
x
x
x
x
x
0
0
0
0
0
0
0
FSYNC_PULSE_WIDTH_UB
0
0
0
0
0
0
0
0
1
FSYNC_PERIOD_LB
1
1
1
1
1
—
0
0
—
0
FSYNC_PERIOD_UB
0
0
0
0
0
0
ASP_SCLK_
EN
ASP_
HYBRID_
MODE
—
ASP_SCPOL_
IN_DAC
ASP_LCPOL_
OUT
ASP_LCPOL_
IN
0
0
0
0
—
0
0
0
0
0
ASP_STP
ASP_5050
1
0
ASP_FSD
0
—
0
0
0
0
0
FS_EN
0
0
0
0
0
0
0
CLK_IASRC_SEL
—
0
0
0
0
0
x
x
x
x
—
x
p. 66
0
—
0
Input ASRC Clock
Select
1
0
x
Fs Rate Enable
p. 66
0x0A
1
FSYNC_PULSE_WIDTH_LB
0
ASP Frame
Configuration
2
—
ASP Clock
Configuration 1
p. 65
0
0
x
p. 65
3
—
0
0x02
4
PAGE
0
p. 64
5
x
x
x
SCLK_PREDIV
—
0
0
0
0
0x0D–0x7F Reserved
0
0
0
0
x
x
x
x
—
x
x
x
x
6.4 Interrupt Registers
Address
0x00
0x01
I2C Address: 10010(AD1)(AD0)[R/W] through 10010(AD1)(AD0)0 = 0x94 (Write); 10010(AD1)(AD0)1 = 0x95 (Read)
Page 0x13—Interrupt Registers
Function
7
6
5
4
3
2
1
Control Port Page
PAGE
0
0
0
1
0
0
1
Reserved
—
x
0x02
p. 67
0x03
p. 67
0x04
Channel Overflow
Interrupt Status (Read
Only)
SRC Interrupt Status
(Read Only)
x
x
0
0
0
0
0
0
0
—
0
p. 68
0x09
Detect Status 1 (Read
Only)
0
0
x
CHB_OVFL
x
x
x
SRC_IUNLK
—
SRC_ILK
0
x
x
x
x
ASPRX_OVLD
ASPRX_
ERROR
ASPRX_LATE
ASPRX_
EARLY
ASPRX_
NOLRCK
x
x
x
x
x
x
x
x
x
x
x
0
—
0
TIP_SENSE_
PLUG
x
0
TIP_SENSE_
UNPLUG
x
x
PDN_DONE
0
x
Reserved
0
0
—
x
x
x
x
x
x
x
x
x
x
—
x
DS1081F3
x
CHA_OVFL
—
x
p. 68
0x0A
x
1
—
x
DAC Interrupt Status
(Read Only)
x
—
0x05–0x07 Reserved
0x08
x
—
ASP RX Interrupt
Status (Read Only)
p. 67
x
0
x
x
x
54
CS43L36
6.5 Fractional-N PLL Registers
Address
0x0B
p. 68
0x0C
I2C Address: 10010(AD1)(AD0)[R/W] through 10010(AD1)(AD0)0 = 0x94 (Write); 10010(AD1)(AD0)1 = 0x95 (Read)
Page 0x13—Interrupt Registers
Function
7
6
5
4
3
2
1
DAC Lock Status
—
DAC_LK
DAC_UNLK
—
(Read Only)
x
x
x
x
x
x
x
Reserved
—
x
0x0D
p. 68
0x0E
VPMON Interrupt
(Read Only)
p. 69
0
Channel Overflow
Interrupt Mask
0x19
0x1B
x
0x1E
VPMON Interrupt
Mask
0
0
x
x
x
x
x
0
0
0
x
0
x
0
0
TS_UNPLUG
TS_PLUG
x
x
x
x
0
x
—
x
x
x
x
M_CHA_OVFL M_CHB_OVFL
0
1
1
1
1
M_SRC_
IUNLK
M_SRC_ILK
0
1
1
1
1
M_ASPRX_
ERROR
1
M_ASPRX_
LATE
1
M_ASPRX_
EARLY
1
M_ASPRX_
NOLRCK
1
x
x
x
x
M_PDN_
DONE
1
0
0
0
M_ASPRX_
OVLD
1
x
x
x
x
—
—
0
0
M_DAC_UNLK
0
0
—
0
0
M_DAC_LK
1
0
1
1
1
1
1
1
0
0
0
—
1
—
0
0
0
0
M_VPMON_
TRIP
—
0
0
0
0
0
0
0
1
M_PLL_LOCK
—
0
0
0
Tip Sense Plug/Unplug
Interrupt Mask
p. 71
0
0
—
PLL Lock Mask
p. 71
x
PLL_LOCK
—
0
p. 71
0
—
DAC Lock Mask
Reserved
0x20
0
0
DAC Interrupt Mask
0x1D
0x1F
0
Reserved
p. 70
x
—
0
p. 70
0x1C
x
VPMON_TRIP
—
ASP RX Interrupt Mask
p. 70
0x1A
0
0
SRC Interrupt Mask
p. 69
x
x
—
x
0x18
x
—
0
Tip Sense Plug/Unplug
Interrupt Status (Read
Only)
0x10–0x16 Reserved
p. 69
x
PLL Lock (Read Only)
0x0F
p. 69
0x17
x
0
—
0
—
0
0
0
0
0x21–0x7F Reserved
0
0
M_TS_
UNPLUG
M_TS_PLUG
0
1
1
1
1
1
0
0
0
0
—
—
0
0
0
0
6.5 Fractional-N PLL Registers
Address
0x00
0x01
I2C Address: 10010(AD1)(AD0)[R/W] through 10010(AD1)(AD0)0 = 0x94 (Write); 10010(AD1)(AD0)1 = 0x95 (Read)
Page 0x15—Fractional-N PLL Registers
Function
7
6
5
4
3
2
1
Control Port Page
PAGE
0
0
0
1
0
1
0
PLL Control 1
—
p. 71
0x02
p. 72
0x03
p. 72
0x04
p. 72
0x05
0
PLL Division Fractional
Byte 0
PLL Division Fractional
Byte 1
PLL Division Fractional
Byte 2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
x
x
x
x
0
PLL_DIV_FRAC[15:8]
0
0
0
0
0
PLL_DIV_FRAC[23:16]
0
0
0
0
0
PLL_DIV_INT[7:0]
0
1
0
0
0x06–0x07 Reserved
—
x
DS1081F3
0
1
PLL_START
PLL_DIV_FRAC[7:0]
Division Integer
p. 72
0
0
x
x
x
55
CS43L36
6.6 HP Load Detect Registers
Address
0x08
I2C Address: 10010(AD1)(AD0)[R/W] through 10010(AD1)(AD0)0 = 0x94 (Write); 10010(AD1)(AD0)1 = 0x95 (Read)
Page 0x15—Fractional-N PLL Registers
Function
7
6
5
4
3
2
1
PLL Control 3
PLL_DIVOUT
p. 72
0
0x09
Reserved
0x0A
p. 72
PLL Calibration Ratio
0
0
1
x
x
x
0
0
0
x
x
x
x
0
0
0
0
x
x
x
PLL_CAL_RATIO
1
0
0
0
0x0B–0x1A Reserved
—
x
x
x
x
—
PLL Control 4
p. 72
0
—
x
0x1B
0
0
0
0
x
PLL_MODE
0
0x1C–0x7F Reserved
0
0
1
1
x
x
x
x
—
x
x
x
x
6.6 HP Load Detect Registers
I2C Address: 10010(AD1)(AD0)[R/W] through 10010(AD1)(AD0)0 = 0x94 (Write); 10010(AD1)(AD0)1 = 0x95 (Read)
Page 0x19—HP Load Detect Registers
Address
Function
7
6
5
4
3
2
1
0x00
Control Port Page
PAGE
0
0
0
1
1
0
0
—
0x01–0x24 Reserved
x
x
x
x
x
x
x
0x25
p. 73
0x26
Load Detect R/C
Status (Read Only)
p. 73
0
0
0
HP Load Detect Done
(Read Only)
p. 73
0x27
CLA_STAT
—
0
0
0
0
0
0
0
0
0
0
0
0
0
HP_LD_EN
—
0
0x28–0x7F Reserved
x
HPLOAD_
DET_DONE
—
0
HP Load Detect
Enable
0
1
RLA_STAT
—
0
0
0
0
0
0
x
x
x
x
—
x
x
x
x
6.7 Headset Interface Registers
I2C Address: 10010(AD1)(AD0)[R/W] through 10010(AD1)(AD0)0 = 0x94 (Write); 10010(AD1)(AD0)1 = 0x95 (Read)
Page 0x1B—Headset Interface Registers
Address
Function
7
6
5
4
3
2
1
0x00
Control Port Page
PAGE
0
0
0
1
1
0
1
0x01–0x6F Reserved
—
x
0x70
Reserved
0x71
Wake Control
p. 73
0x72
Reserved
0x73
Tip Sense Control
p. 74
0x74
Reserved
0x75
Mic Detect Control 1
p. 74
0x76
Reserved
0x77
p. 75
Detect Status 1 (Read
Only)
x
x
x
x
x
x
x
1
x
—
x
x
x
—
M_HP_W
AKE
1
WAKEB_
MODE
1
0
x
x
—
0
x
WAKEB_
CLEAR
0
0
x
x
0
0
x
x
—
x
x
TIP_SENSE_CTRL
0
0
x
TIP_SENSE_
INV
0
x
—
0
TIP_SENSE_DEBOUNCE
0
0
1
0
x
x
x
1
1
1
1
x
x
x
x
x
x
—
x
x
x
x
—
x
x
LATCH_TO_
VP
0
EVENT_
STATUS_SEL
0
x
x
x
—
0
1
—
x
DS1081F3
x
0
TIP_SENSE
x
x
x
x
0
56
CS43L36
6.8 DAC Registers
Address
0x78
0x79
I2C Address: 10010(AD1)(AD0)[R/W] through 10010(AD1)(AD0)0 = 0x94 (Write); 10010(AD1)(AD0)1 = 0x95 (Read)
Page 0x1B—Headset Interface Registers
Function
7
6
5
4
3
2
1
Reserved
—
Detect Interrupt
Mask 1
x
x
x
—
M_TIP_
SENSE_PLUG
1
1
M_TIP_
SENSE_
UNPLUG
1
p. 75
0x7A–0x7F Reserved
x
x
x
0
x
x
—
0
0
0
0
0
x
x
x
x
—
x
x
x
x
6.8 DAC Registers
Address
0x00
0x01
I2C Address: 10010(AD1)(AD0)[R/W] through 10010(AD1)(AD0)0 = 0x94 (Write); 10010(AD1)(AD0)1 = 0x95 (Read)
Page 0x1F—DAC Registers
Function
7
6
5
4
3
2
1
Control Port Page
PAGE
0
0
0
1
1
1
1
DAC Control 1
DACB_INV
—
p. 75
0
0
0
0
0x02–0x05 Reserved
x
DAC Control 2
p. 75
0
0
1
DACA_INV
0
—
x
0x06
0
0
x
x
HPOUT_PULLDOWN
0
0
0
x
x
x
x
HPOUT_LOAD
HPOUT_
CLAMP
DAC_HPF_EN
—
0
0
1
0
x
x
x
x
0
0x07–0x7F Reserved
—
x
x
x
x
6.9 HP Control Registers
Address
0x00
0x01
I2C Address: 10010(AD1)(AD0)[R/W] through 10010(AD1)(AD0)0 = 0x94 (Write); 10010(AD1)(AD0)1 = 0x95 (Read)
Page 0x20—HP Control Registers
Function
7
6
5
4
3
2
1
Control Port Page
PAGE
0
0
1
0
0
0
0
HP Control
—
ANA_MUTE_B ANA_MUTE_A FULL_SCALE_
VOL
p. 76
0
0
0
0
0x02–0x7F Reserved
0
0
—
1
1
0
1
0
0
0
0
—
0
0
0
0
6.10 Class H Registers
Address
0x00
0x01
I2C Address: 10010(AD1)(AD0)[R/W] through 10010(AD1)(AD0)0 = 0x94 (Write); 10010(AD1)(AD0)1 = 0x95 (Read)
Page 0x21—Class H Registers
Function
7
6
5
4
3
2
1
Control Port Page
PAGE
0
0
1
0
0
0
0
Class H Control
—
ADPTPWR
p. 76
0
0
0
0
0x02–0x7F Reserved
0
1
0
1
1
1
x
x
x
x
—
x
x
x
x
6.11 Mixer Volume Registers
p. 76
I2C Address: 10010(AD1)(AD0)[R/W] through 10010(AD1)(AD0)0 = 0x94 (Write); 10010(AD1)(AD0)1 = 0x95 (Read)
Page 0x23—Mixer Volume Registers
Function
7
6
5
4
3
2
1
Control Port Page
PAGE
0
0
1
0
0
0
1
Channel A Input
CHA_VOL
—
Volume
1
1
1
1
1
0
0
0x02
Reserved
0x03
Channel B Input
Volume
Address
0x00
0x01
DS1081F3
1
1
—
x
p. 77
0
x
x
x
x
0
x
x
x
1
1
1
CHB_VOL
—
0
1
1
1
57
CS43L36
6.12 AudioPort Interface Registers
I2C Address: 10010(AD1)(AD0)[R/W] through 10010(AD1)(AD0)0 = 0x94 (Write); 10010(AD1)(AD0)1 = 0x95 (Read)
Page 0x23—Mixer Volume Registers
Address
Function
7
6
5
4
3
2
1
0x04–0x7F Reserved
—
x
x
x
x
x
x
0
x
x
6.12 AudioPort Interface Registers
Address
0x00
0x01
p. 77
0x02
I2C Address: 10010(AD1)(AD0)[R/W] through 10010(AD1)(AD0)0 = 0x94 (Write); 10010(AD1)(AD0)1 = 0x95 (Read)
Page 0x25—AudioPort Interface Registers
Function
7
6
5
4
3
2
1
0
Control Port Page
PAGE
0
0
1
0
0
1
0
1
Serial Port Receive
—
SP_RX_CHB_SEL
SP_RX_CHA_SEL
Channel Select
0
0
0
0
0
1
0
0
Serial Port Receive
Isochronous Control
p. 77
0x03
p. 78
—
0
Serial Port Receive
Sample Rate
SP_RX_
RSYNC
0
SP_RX_NSB_POS
0
0
SP_RX_NFS_
NSBB
0
0
0
0
SP_RX_FS
—
1
1
SP_RX_ISOC_MODE
0
0
0x04–0x7F Reserved
1
1
0
0
x
x
x
x
—
x
x
x
x
6.13 SRC Registers
Address
0x00
0x01
p. 78
I2C Address: 10010(AD1)(AD0)[R/W] through 10010(AD1)(AD0)0 = 0x94 (Write); 10010(AD1)(AD0)1 = 0x95 (Read)
Page 0x26—SRC Registers
Function
7
6
5
4
3
2
1
Control Port Page
PAGE
0
0
1
0
0
1
1
SRC_SDIN_FS
SRC Input Sample
—
Rate
0
1
0
0
0
0
0
0x02–0x08 Reserved
0
0
0
—
x
x
x
x
0x09–0x7F Reserved
x
x
x
x
x
x
x
x
—
x
x
x
x
6.14 Serial Port Receive Registers
Address
0x00
0x01
p. 78
0x02
p. 78
0x03
I2C Address: 10010(AD1)(AD0)[R/W] through 10010(AD1)(AD0)0 = 0x94 (Write); 10010(AD1)(AD0)1 = 0x95 (Read)
Page 0x2A—Serial Port Receive Registers
Function
7
6
5
4
3
2
1
Control Port Page
PAGE
0
0
1
0
1
0
1
ASP Receive DAI0
—
ASP_RX0_CH_EN
Enable
0
0
0
0
0
0
0
ASP Receive DAI0
Channel 1 Phase and
Resolution
p. 79
0x05
p. 79
0x06
p. 79
0
0
0
0
0
0
0
—
ASP_RX0_
CH2_AP
0
0
0
0
1
1
ASP_RX0_
CH1_BIT_ST_
MSB
0
0
0
0
0
0
0
0
0
0
0
ASP_RX0_CH2_RES
—
0
0
0
0
1
0
0
0
1
ASP_RX0_
CH2_BIT_ST_
MSB
—
0
DS1081F3
0
ASP_RX0_CH1_BIT_ST_LSB
ASP Receive DAI0
Channel 2 Bit Start
MSB
ASP Receive DAI0
Channel 2 Bit Start
LSB
0
0
—
ASP_RX0_CH1_RES
—
—
0
ASP Receive DAI0
Channel 1 Bit Start
LSB
ASP Receive DAI0
Channel 2 Phase and
Resolution
p. 79
0x07
ASP_RX0_
CH1_AP
ASP Receive DAI0
Channel 1 Bit Start
MSB
p. 79
0x04
—
0
0
0
0
0
0
0
0
ASP_RX0_CH2_BIT_ST_LSB
0
0
0
0
0
58
CS43L36
6.15 ID Registers
I2C Address: 10010(AD1)(AD0)[R/W] through 10010(AD1)(AD0)0 = 0x94 (Write); 10010(AD1)(AD0)1 = 0x95 (Read)
Page 0x2A—Serial Port Receive Registers
Address
Function
7
6
5
4
3
2
1
0x08–0x7F Reserved
—
x
x
x
x
x
x
0
x
x
6.15 ID Registers
I2C Address: 10010(AD1)(AD0)[R/W] through 10010(AD1)(AD0)0 = 0x94(Write); 10010(AD1)(AD0)1 = 0x95 (Read)
Page 0x30—ID Registers
Function
Address
0x00
7
6
5
4
Control Port Page
0
0
1
1
0x01–0x13 Reserved
Subrevision
0x15
Device ID A and B
(Read Only)
x
p. 80
p. 80
0x–0x7F
x
x
0
0
0
0
0
x
x
x
x
x
x
x
x
x
x
x
1
1
1
1
1
DEVIDB
0
0
0
0
DEVIDC
1
Device ID E (Read
Only)
0x17
0
DEVIDA
Device ID C and D
(Read Only)
0x16
1
SUBREVISION
x
p. 80
2
—
x
0x14
p. 80
3
PAGE
0
DEVIDD
1
0
0
0
DEVIDE
0
1
—
1
0
Reserved
x
x
x
x
x
x
x
x
—
x
x
x
x
7 Register Descriptions
The tables in this section give bit assignments, definitions, and default states after power-up or reset. Reserved register
fields must maintain default states. Section 6 describes the red, turquoise, and orange indicators.
7.1 Global Registers
7.1.1
Revision ID
R/O
7
Address 0x1005
6
5
4
3
2
AREVID
Default
Bits
7:4
x
x
1
0
x
x
MTLREVID
x
x
x
x
Name
AREVID
Description
Alpha revision. CS43L36 alpha revision level. AREVID and MTLREVID form the complete device revision ID (e.g.,: A0, B2).
0x00 … 0xFF
3:0 MTLREVID Metal revision. CS43L36 metal revision level. AREVID and MTLREVID form the complete device revision ID (e.g.,: A0, B2).
0x00 … 0xFF
7.1.2
Freeze Control
R/W
7
6
Address 0x1006
5
4
3
2
1
—
Default
0
0
0
0
0
FREEZE
0
0
0
0
Bits Name
Description
7:1
—
Reserved
0 FREEZE Freeze registers. Configures a hold on all volume-control and power-down register settings. Use this bit only during normal
operation after all circuit blocks in use have powered up. Using the bit when an affected circuit block is powering up could cause
the change to occur immediately when power up completes (i.e., not gated by the FREEZE bit). Bits affected by FREEZE are
shown in orange throughout Section 6 and Section 7.
0 (Default) Volume-control and power-down register changes take effect immediately.
1 Modifications made to volume-control and power-down registers take effect only after this bit is cleared.
DS1081F3
59
CS43L36
7.1 Global Registers
7.1.3
Serial Port SRC Control
R/W
7
6
Address 0x1007
5
4
—
Default
Bits
7:4
3
2
1
0
0
0
0
1
3
2
1
0
I2C_DRIVE
—
SRC_BYPASS_DAC
—
0
0
0
0
Description
Reserved
I2C output drive strength. Selects drive strength used for the SDA output
0 (Default) Normal
1 Decreased
—
Reserved
SRC_
Bypass SRC (DAC path). Determines the bypass of the input SRCs. See Section 4.6 for details.
BYPASS_ 0 (Default) No bypass
DAC
1 Bypass. SRC_SDIN_FS (see p. 78) must be set equal to FsINT.
—
Reserved
7.1.4
Name
—
I2C_
DRIVE
MCLK Status
R/W
7
Address 0x1008
6
5
4
3
2
—
Default
0
0
0
0
0
1
0
INTERNAL_FS_STAT
—
x
0
0
Bits
Name
Description
7:2
—
Reserved
1 INTERNAL_ Internal sample rate status. Indicates the divide ratio from MCLKINT (set in INTERNAL_FS, see Section 7.1.5) to produce
FS_STAT the internal sample rate for all converters.
0 FsINT = MCLKINT/250. Indicates that the internal MCLK is 12 or 24 MHz.
1 FsINT = MCLKINT/256. Indicates that the internal MCLK is 11.2896, 12.288, 22.5792, or 24.576 MHz.
0
—
Reserved
7.1.5
MCLK Control
R/W
7
Address 0x1009
6
5
4
3
2
—
Default
0
0
0
0
0
1
0
INTERNAL_FS
—
1
0
0
Bits
Name
Description
7:2
—
Reserved
1 INTERNAL_ Internal sample rate (FsINT). Selects the divide ratio from MCLKINT to produce the internal sample rate for all converters.
FS
See Table 4-4 for programming details. This bit always returns zero when read. Reports status in INTERNAL_FS_STAT.
0 FsINT = MCLKINT/250. Set if internal MCLK is 12 or 24 MHz.
1 (Default) FsINT = MCLKINT/256. Set if internal MCLK is 11.2896, 12.288, 22.5792, or 24.576 MHz.
If MCLKINT 11.2896, 12, or 12.288 MHz, MCLKDIV must be 0. If it is 22.5792, 24, or 24.576 MHz, MCLKDIV must be 1.
0
—
Reserved
7.1.6
Soft Ramp Rate
R/W
7
Address 0x100A
6
5
4
3
2
ASR_RATE
Default
1
0
1
0
0
0
DSR_RATE
1
0
0
1
Bits Name
Description
7:4 ASR_ Analog soft-ramp rate (number of Fs periods between steps). Selects the soft ramp rate for all analog volumes. Step size = 1 dB
RATE or 2 dB for HPOUTx. See Section 4.2.2 for details.
0000 1
0010 4
0100 8
0110 12
1000 22
1010 (Default) 33
1100 44
1110 66
0001 2
0011 6
0101 11
0111 16
1001 24
1011 36
1101 48
1111 72
3:0 DSR_ Digital soft-ramp rate (number of Fs periods between steps). Selects soft ramp rate for all digital volumes. Step size = 0.125 dB.
RATE 0000 1
0010 4
0100 (Default) 8
0110 12
1000 22
1010 33
1100 44
1110 66
0001 2
0011 6
0101 1
0111 16
1001 24
1011 36
1101 48
1111 72
DS1081F3
60
CS43L36
7.1 Global Registers
7.1.7
Slow Start Enable
R/W
7
6
—
Default
Bits
7
6:4
3:0
Address 0x100B
5
4
3
2
SLOW_START_EN
0
1
1
0
0
0
—
1
1
0
0
Name
Description
—
Reserved
SLOW_
Slow startup enable. Selects between fast and slow start-up times. See Section 4.2.3 for details.
START_EN
000 Disabled. Shortens start-up time of the volume control, DAC, and HP. Useful for high-definition audio applications.
111 (Default) Enabled
—
Reserved
I2C Debounce
7.1.8
R/W
7
6
Address 0x100E
5
4
I2C_SDA_DBNC_CNT
Default
1
Bits
7:5
Name
I2C_SDA_
DBNC_CNT
4
I2C_SDA_
DBNC_EN
3:1
I2C_SCL_
DBNC_CNT
0
I2C_SCL_
DBNC_EN
7.1.9
0
3
I2C_SDA_DBNC_EN
0
0
2
1
0
I2C_SCL_DBNC_CNT
1
0
I2C_SCL_DBNC_EN
0
0
Description
I2C debounce count. Number of MCLKs to debounce SDA input
Note: The I2C_SDA_DBNC_CNT and I2C_SCL_DBNC_CNT settings must be identical.
000 0 MCLKs
010 2 MCLKs
100 (Default) 4 MCLKs 110 6 MCLKs
001 1 MCLK
011 3 MCLKs
101 5 MCLKs
111 7 MCLKs
I2C SDA debounce enable. SDA debounce enable
Note: The I2C_SDA_DBNC_EN and I2C_SCL_DBNC_EN settings must be identical.
0 (Default) Disabled. Must be 0 for Fast Mode or Fast-Mode Plus.
1 Enabled
I2C SCL debounce count. Number of MCLKs to debounce SCL input
Note: The I2C_SDA_DBNC_CNT and I2C_SCL_DBNC_CNT settings must be identical.
000 0 MCLKs
010 2 MCLKs
100 (Default) 4 MCLKs 110 6 MCLKs
001 1 MCLK
011 3 MCLKs
101 5 MCLKs
111 7 MCLKs
I2C SCL debounce count enable.
Note: The settings of I2C_SDA_DBNC_EN and I2C_SCL_DBNC_EN must be identical.
0 (Default) Disabled. Must be 0 for Fast Mode or Fast-Plus Mode.
1 Enabled
I2C Stretch
R/W
7
Address 0x100F
6
5
4
3
2
1
0
0
0
1
1
I2C_STRETCH
Default
Bits
7:0
0
Name
I2C_
STRETCH
0
0
0
Description
I2C stretch. Number of additional MCLKs to clock stretch after the slave is ready
0000 0011 (Default) 3 MCLKs
7.1.10 I2C Timeout
R/W
7
Address 0x1010
6
5
MAS_I2C_NACK MAS_TO_DIS
Default
Bits
7
1
0
4
MAS_TO_SEL
1
3
2
ACC_TO_DIS
1
0
1
0
ACC_TO_SEL
1
1
1
Name
MAS_
I2C_
NACK
Description
APB master I2C NACK. Determines whether clock stretching or a NACK occurs if an APB access is attempted and I2C is not APB
master.
0 I2C clock stretches if an APB access is attempted while I2C is not APB master.
1 (Default) I2C NACKs if APB access is attempted while I2C is not APB master.
6
MAS_ APB master access timeout disable
TO_DIS 0 (Default) Enabled
1 Disabled
5:4 MAS_ APB master access timeout select. Determines the timeout duration.
TO_SEL 00 64 ms
01 128 ms
10 256 ms
11 (Default) 512 ms
3
ACC_ APB access timeout disable.
TO_DIS 0 (Default) Enabled
1 Disabled
DS1081F3
61
CS43L36
7.2 Power Down and Headset Detects
Bits
2:0
Name
Description
ACC_ APB access timeout select. Determines the timeout duration in MCLKs.
TO_SEL 000 7 MCLKs
010 31 MCLKs
100 127 MCLKs
001 15 MCLKs
011 63 MCLKs
101 255 MCLKs
110 511 MCLKs
111 (Default) 65,535 MCLKs
7.2 Power Down and Headset Detects
7.2.1
Power Down Control 1
R/W
Default
Bits
Name
7
—
6
ASP_
DAI_
PDN
5
Address 0x1101
7
6
5
4
3
—
ASP_DAI_PDN
MIXER_PDN
—
HP_PDN
1
1
1
1
1
2
1
—
1
0
PDN_ALL
1
1
Description
Reserved
ASP DAI0 input path power down. Configures ASP DAI0 SDIN path power state.
0 Powered up
1 (Default) Powered down. Setting this bit does not tristate the serial port clock.
MIXER_ Mixer power down. Configures the mixer power state.
PDN
0 The mixer is powered up.
1 (Default) The mixer is powered down.
4
—
3
HP_
PDN
2:1
—
0
PDN_
ALL
7.2.2
Reserved
HPOUTx power down
0 The HP driver and DACx are powered up.
1 (Default) The HP driver and DACx are powered down.
Reserved
DAC power down. Configures the entire DAC’s power state except for PLL_START. After power up (PDN_ALL: 1  0),
individual subblocks are powered according to power-control programming. This bit is affected by LATCH_TO_VP (see p. 74).
Note: The SRC power-down state depends on the SRC_PDN_OVERRIDE setting (see p. 62).
0 Powered up, per the individual x_PDN controls
1 (Default) Powered down. PDN_ALL must not be set without first enabling LATCH_TO_VP. After PDN_ALL is set and the
entire DAC is powered down, PDN_DONE is set, indicating that SCLK can be removed.
Power Down Control 2
R/W
7
6
Address 0x1102
5
—
Default
1
0
0
4
3
2
1
0
DISCHARGE_
FILT+
SRC_PDN_
OVERRIDE
—
DAC_SRC_
PDNB
—
0
0
1
0
0
Bits
Name
Description
7:5
—
Reserved
4 DISCHARGE_ Discharge FILT+ capacitor. Configures the state of the FILT+ pin internal clamp. Before setting this bit, ensure that the
FILT+
VD_FILT device input is connected to a supply, as shown in Table 3-2.
0 (Default) FILT+ is not clamped to ground.
1 FILT+ is clamped to ground. This must be set only if PDN_ALL = 1. Discharge time with an external 2.2-µF
capacitor on FILT+ is ~46 ms.
3
SRC_PDN_ SRC power down override. Configures the SRCs’ power states.
OVERRIDE
0 (Default) Power state control for the DAC SRCs, which are controlled by the following smart logic:
• DAC SRCs are off if SRC_BYPASS_DAC = 1.
• • If PDN_ALL = 1, all SRCs are off.
• If PDN_ALL = 0 and the respective DAC bypass bits = 0, the following controls each SRC’s power state:
–If DAI0 is enabled, the DAC SRCs are powered up.
1 DAC SRCs are controlled by DAC_SRC_PDNB.
2
—
Reserved
1
DAC_SRC_ DAC SRC power down. Configures the DAC ASP power state if SRC_PDN_OVERRIDE = 1.
PDNB
0 (Default) Power down
1 Power up audio DAC SRC only
0
—
Reserved
DS1081F3
62
CS43L36
7.2 Power Down and Headset Detects
7.2.3
Power Down Control 3
R/W
7
6
Address 0x1103
5
4
3
2
—
Default
0
0
1
0
VPMON_PDNB
1
0
0
—
0
0
0
Bits Name
Description
7:3
—
Reserved
2 VPMON_ VPMON power down. VP monitor is described in Section 4.9.1.
PDNB
0 (Default) Power down VPMON.
1 Power up VPMON.
1:0
—
Reserved
7.2.4
Oscillator Switch Control
R/W
7
6
Address 0x1107
5
4
3
2
1
0
—
Default
Bits
7:1
0
0
0
0
SCLK_PRESENT
0
0
0
0
0
Name
Description
—
Reserved
SCLK_
SCLK present. Used to select the internal MCLK source. See Section 4.4 for programming details.
PRESENT
0 →1 transition starts switch from RCO to selected internal MCLK (SCLK must be running first).
1→0 transition starts switch from selected internal MCLK to RCO (SCLK must keep running during transition).
0 (Default) SCLK may be present, but the internal MCLK is sourced from the RCO.
1 SCLK is present and the internal MCLK is sourced from the SCLK pin.
7.2.5
Oscillator Switch Status
R/O
7
6
Address 0x1109
5
4
3
2
—
Default
0
0
1
OSC_PDNB_STAT
0
0
0
1
0
OSC_SW_SEL_STAT
x
x
Bits
7:3
2
Name
Description
—
Reserved
OSC_
RCO power-down status. Indicates the RCO power state. See Section 4.4 for programming details.
PDNB_STAT 0 RCO powered down
1 (Default) RCO powered up
1:0 OSC_SW_ RCO switch status. Indicates the RCO oscillator switch status. See Section 4.4 for programming details.
SEL_STAT
00 In transition
10–11Reserved
01 (Default) RCO selected for internal MCLK
7.2.6
Tip Sense Control 1
R/W
Default
Bits
7
7
6
TS_INV
—
0
0
Address 0x1113
5
4
3
2
TS_FALL_DBNCE_TIME
0
1
1
0
TS_RISE_DBNCE_TIME
1
0
1
1
Name
TS_INV
Description
Tip sense raw signal invert. Used to invert the raw signal from the tip-sense circuit. Reverses the meaning of TS_
UNPLUG_DBNC and TS_PLUG_DBNC (see p. 64).
0 (Default) Not inverted
1 Inverted
6
—
Reserved
5:3
TS_FALL_
Tip sense falling debounce time. Section 4.8.3 gives programming details.
DBNCE_TIME
000 0 ms
010 250 ms
100 750 ms
110 1.25 s
001 125 ms
011 (Default) 500 ms
101 1.0 s
111 1.5 s
2:0
TS_RISE_
Tip sense rising debounce time. Section 4.8.3 gives programming details.
DBNCE_TIME
000 0 ms
010 250 ms
100 750 ms
110 1.25 s
001 125 ms
011 (Default) 500 ms
101 1.0 s
111 1.5 s
DS1081F3
63
CS43L36
7.3 Clocking Registers
7.2.7
Tip Sense Indicator Status
R/O
7
6
Address 0x1115
5
4
—
Default
Bits
7:4
3
2
1:0
0
0
0
0
3
2
TS_UNPLUG_
DBNC
TS_PLUG_
DBNC
1
x
x
0
—
x
x
Name
Description
—
Reserved
TS_
Tip sense unplug debounce status. See Section 4.8.3 for details. Setting TS_INV reverses the meaning of this bit.
UNPLUG_
0 Condition is not present.
DBNC
1 Condition is present.
TS_PLUG_ Tip sense plug debounce status. See Section 4.8.3 for details. Setting TS_INV reverses the meaning of this bit.
DBNC
0 Condition is not present.
1 Condition is present.
—
Reserved
7.3 Clocking Registers
7.3.1
MCLK Source Select
R/W
7
6
Address 0x1201
5
4
3
2
—
Default
0
0
0
0
0
0
1
0
MCLKDIV
MCLK_SRC_SEL
0
0
Bits Name
Description
7:2
—
Reserved
1 MCLKDIV Master clock divide ratio. Selects the divide ratio between the selected MCLK source and the MCLKINT. Section 4.4.2 lists
supported MCLK rates and their associated programming settings.
0 (Default) Divide by 1 (source MCLKINT = ~12 MHz).
1 Divide by 2 (source MCLKINT = ~24 MHz)
Note: Change this field only if PDN_ALL = 1.
0
MCLK_ Master clock source select. Selects the internal master clock source. For programming details and examples, see Section 4.4.
SRC_
0 (Default) SCLK pin
SEL
1 PLL clock
7.3.2
FSYNC Pulse Width, Lower Byte
R/W
7
6
5
Address 0x1203
4
3
2
1
0
0
0
0
FSYNC_PULSE_WIDTH_LB
Default
Bits
7:0
0
Name
FSYNC_
PULSE_
WIDTH_
LB
7.3.3
0
0
0
0
Description
FSYNC pulse width LB. FSYNC_PULSE_WIDTH_UB | FSYNC_PULSE_WIDTH_LB provides an 11-bit field to set the duty
cycle of LRCK in Hybrid-Master Mode. These combined value forms an integer number of SCLK periods within an LRCK
frame that governs the LRCK high time. See Section 4.5.2 for usage details and Section 5 for a programming example. The
value must be 1 less than the desired width of the LRCK pulse, measured in SCLK counts, as illustrated by the value below.
FSYNC_PULSE_WIDTH_UB | FSYNC_PULSE_WIDTH_LB yield the following setting value:
000 0000 0000 (Default) LRCK is one SCLK wide.
FSYNC Pulse Width, Upper Byte
R/W
7
6
5
Address 0x1204
4
3
2
—
Default
Bits
7:3
2:0
0
Name
—
FSYNC_PULSE_
WIDTH_UB
DS1081F3
0
0
1
0
FSYNC_PULSE_WIDTH_UB
0
0
0
0
0
Description
Reserved
FSYNC pulse width UB. See description for FSYNC_PULSE_WIDTH_LB in Section 7.3.2.
000 (Default)
64
CS43L36
7.3 Clocking Registers
7.3.4
FSYNC Period, Lower Byte
R/W
7
6
5
Address 0x1205
4
3
2
1
0
0
0
1
FSYNC_PERIOD_LB
Default
1
1
1
1
1
Bits Name
Description
7:0 FSYNC_ FSYNC period LB. FSYNC_PERIOD_UB | FSYNC_PERIOD_LB controls frequency (number of SCLKs per LRCK) of LRCK
PERIOD_ for ASP. Section 4.5.2 for details on how this register is used and Section 5 for a programming example. The final SCLKs per
LB
LRCK count is +1 of the value set in the UB|LB register field
FSYNC_PERIOD_UB | FSYNC_PERIOD_LB yield the following setting values:
0x000 1 SCLK/LRCK …
0x0F9 (Default) 250 SCLKs/ LRCK …
0xFFF 4096 SCLKs/ LRCK
7.3.5
FSYNC Period, Upper Byte
R/W
7
6
5
Address 0x1206
4
3
2
—
Default
Bits
7:4
3:0
0
R/W
0
Default
3
2
1
0
0
0
0
0
0
ASP Clock Configuration 1
7
6
—
4
0
0
Name
Description
—
Reserved
FSYNC_
FSYNC period UB. See description for FSYNC_PERIOD_LB in Section 7.3.4.
PERIOD_UB
0000 (Default)
7.3.6
Bits
7:6
5
1
FSYNC_PERIOD_UB
0
5
4
ASP_SCLK_EN ASP_HYBRID_MODE
0
0
0
Address 0x1207
3
—
0
2
1
0
ASP_SCPOL_IN_DAC ASP_LCPOL_OUT ASP_LCPOL_IN
0
0
0
Name
Description
—
Reserved
ASP_SCLK_ ASP SCLK enable. Must be set if DAI functionality is used.
EN
0 (Default) Disabled
1 Enabled
ASP_
ASP Hybrid-Master Mode. Allows the internal LRCK to be generated from SCLK. See Fig. 4-15 for details.
HYBRID_
0 (Default) LRCK is input from external source which is synchronous to SCLK (Slave Mode).
MODE
1 LRCK is an output generated from SCLK (Hybrid Master Mode).
—
Reserved
ASP_SCPOL_ ASP SCLK input polarity. Determines the polarity for the DAC path. See Fig. 4-15 for details.
IN_DAC
0 (Default) Normal
1 Inverted
ASP_LCPOL_ ASP LRCK output drive polarity. Determines the polarity for the ASP LRCK output drive. See Fig. 4-15 for details.
OUT
0 (Default) Normal
1 Inverted
ASP_LCPOL_ ASP LRCK input polarity. Determines ASP LRCK input polarity (pad to logic). See Fig. 4-15 for details.
IN
0 (Default) Normal
1 Inverted
DS1081F3
65
CS43L36
7.3 Clocking Registers
7.3.7
ASP Frame Configuration
R/W
7
6
Address 0x1208
5
—
Default
0
0
0
4
3
ASP_STP
ASP_5050
1
0
2
1
0
ASP_FSD
0
0
0
Bits Name
Description
7:5
—
Reserved
4
ASP_ ASP start phase. Controls which LRCK/FSYNC phase starts a frame. See Section 4.5.5 for details.
STP
0 The frame begins when LRCK/FSYNC transitions from high to low
1 (Default) The frame begins when LRCK/FSYNC transitions from low to high
3
ASP_ ASP LRCK fixed 50/50 duty cycle. Determines whether the duty cycle is fixed or programmable. See Section 4.5.5 for details.
5050
0 (Default) Programmable duty cycle. Determined by FSYNC_PULSE_WIDTH_LB (see p. 64), FSYNC_PULSE_WIDTH_
UB, and FSYNC_PERIOD_xSB (see p. 65).
1 50/50 Mode. Fixed 50% duty cycle
2:0 ASP_ ASP frame-start delay. Determines the delay before the start of an ASP frame in ASP_SCLK periods. See Section 4.5.2.
FSD
000 (Default) 0 delay 001 0.5 delay
010 1.0 delay … 101 2.5 delay 110–111 Reserved
7.3.8
FS Rate Enable
R/W
7
6
Address 0x1209
5
4
3
2
—
Default
0
0
1
0
FS_EN
0
0
0
0
0
0
Bits Name
Description
7:3
—
Reserved
2:0 FS_EN Fs rate enable. Provides enables for all internally generated Fs rates. 0 = disabled; 1 = enabled. Section 4.6 gives details.
FS_EN[0] Enable IASRC 96K and lower rates.
FS_EN[2] Enable IASRC 192, 176.4, and 176.471 K rates
00 (Default) All disabled
7.3.9
Input ASRC Clock Select
R/W
7
6
Address 0x120A
5
4
3
2
—
Default
0
0
0
1
0
CLK_IASRC_SEL
0
0
0
0
0
Bits
Name
Description
7:2
—
Reserved
1:0 CLK_IASRC_ Input ASRC clock select. Selects input ASRC MCLKINT frequency. See Section 4.6 for programming details.
SEL
00 (Default) 6 MHz
01 12 MHz
10 24 MHz
11 Reserved
7.3.10 PLL Divide Configuration 1
R/W
7
6
5
Address 0x120C
4
3
—
Default
0
0
0
0
0
Bits
Name
Description
7:3
—
Reserved
2 PLL_REF_ Invert PLL reference clock. See Table 4.4.3 for programming guidelines.
INV
0 (Default) Normal
1 Inverted
1:0
SCLK_
PLL reference divide select. See Table 4.4.3 for programming guidelines.
PREDIV
00 (Default) Divide by 1
01 Divide by 2
10 Divide by 4
DS1081F3
2
1
PLL_REF_INV
0
0
SCLK_PREDIV
0
0
11 Divide by 8
66
CS43L36
7.4 Interrupt Registers
7.4 Interrupt Registers
7.4.1
Channel Overflow Interrupt Status
R/O
7
6
5
Address 0x1302
4
3
2
—
Default
Bits
7:2
1
0
7.4.2
0
Name
—
CHA_
OVFL
CHB_
OVFL
0
0
0
x
x
1
0
CHA_OVFL
CHB_OVFL
x
x
Description
Reserved
Channel overflow. Indicates the overrange status in the corresponding signal path. Rising-edge state transitions may cause
an interrupt, depending on the programming of the associated interrupt mask bit.
0 No digital clipping has occurred in the data path of the respective signal source.
1 Digital clipping has occurred in the data path of the respective signal source.
SRC Interrupt Status
R/O
7
Address 0x1303
6
5
4
3
—
Default
0
0
0
0
2
1
0
SRC_IUNLK
—
SRC_ILK
x
x
x
x
Bits
Name
Description
7:3
—
Reserved
2 SRC_IUNLK SRC unlock status. Indicates SRC unlock status for the input path. Status is valid only if serial-port LRCK is toggling.
0 Locked
1 Unlocked
1
—
Reserved
0
SRC_ILK SRC lock status. Indicates SRC lock status for the ASP input path. Status is valid only if serial-port LRCK is toggling.
0 Unlocked
1 Locked
7.4.3
ASP RX Interrupt Status
R/O
7
6
5
—
Default
0
0
Address 0x1304
4
3
2
ASPRX_OVLD ASPRX_ERROR ASPRX_LATE
0
x
x
x
1
0
ASPRX_EARLY ASPRX_NOLRCK
x
x
Bits Name
Description
7:5
—
Reserved
4 ASPRX_ ASP RX request overload. Set when too many input buffers request processing at once. 0No interrupt
1 Interrupt detected. ASP RX cannot retrieve data from the internal input buffers because at least one of the following
OVLD
violations has occurred:
—The ASP RX core clock frequency is less than SCLK/8.
—The LRCK frame (non-50/50 Mode) or LRCK subframe (50/50 Mode) period is less than 16 SCLK periods (assuming
the ASP RX core clock frequency is equal to SCLK/8).
3 ASPRX_ ASP RX LRCK error. Logical OR of ASPRX_LATE and ASPRX_EARLY, described below.
ERROR
0 No interrupt
1 Interrupt detected
2 ASPRX_ ASP RX LRCK late. Determines whether the number of SCLK periods per LRCK phase (high or low) is greater than the
LATE expected count, as determined by the FSYNC_PERIOD_xSB and FSYNC_PULSE_WIDTH_x fields.
0 No interrupt
1 Interrupt detected
1 ASPRX_ ASP RX LRCK early. Determines whether the number of SCLK periods per LRCK phase (high or low) is less than the expected
EARLY count, as determined by FSYNC_PERIOD_xSB (see p. 65) and FSYNC_PULSE_WIDTH_x (see p. 64).
0 No interrupt
1 Interrupt detected
0 ASPRX_ ASP RX no LRCK. Determines whether the SCLK periods counted exceeds twice the value of LRCK period (FSYNC_
NOLRCK PERIOD_xSB) without an LRCK edge.
0 No interrupt
1 Interrupt detected
DS1081F3
67
CS43L36
7.4 Interrupt Registers
7.4.4
DAC Interrupt Status
R/O
7
6
Address 0x1308
5
4
3
2
1
0
—
Default
Bits
7:1
0
0
Name
—
PDN_
DONE
7.4.5
0
0
PDN_DONE
0
0
0
0
x
Description
Reserved
Power-down done. Indicates when the DAC has powered down and MCLK can be stopped, as determined by various
power-control and headset-interface register settings.
0 Not completely powered down
1 Powered down as a result of PDN_ALL having been set.
Detect Interrupt Status 1
R/O
7
6
—
Default
Address 0x1309
5
4
3
2
TIP_SENSE_PLUG TIP_SENSE_UNPLUG
x
x
Bits
7
6
Name
—
TIP_SENSE_PLUG
5
TIP_SENSE_UNPLUG
4:0
—
x
1
0
x
x
—
x
x
x
Description
Reserved
Tip sense plug event. Indicates the undebounced status of a plug event on the TIP_SENSE pin.1
0 No HP plug event
1 HP plug event
Tip sense unplug event. Indicates the undebounced status of an unplug event on the TIP_SENSE pin.1
0 (Default) No HP unplug event
1 HP unplug event
Reserved
1. It is active only if TIP_SENSE_CTRL (p. 74) is configured so the tip-sense circuit is powered up. If the system is configured for standby operation,
the sticky version of this bit (that also accounts for events that occurred during standby) can be read back after a wake event.
7.4.6
SRC Partial Lock Interrupt Status
R/O
Default
7
6
—
DAC_UNLK
x
x
Bits
7
6
Name
—
DAC_UNLK
5:3
2
—
DAC_LK
1:0
—
7.4.7
5
Address 0x130B
4
3
—
x
x
2
1
DAC_LK
x
x
x
7
Description
6
5
Address 0x130D
4
3
2
1
—
Default
0
x
Reserved
ASP input SRC unlock status.
0 Locked
1 Unlocked
Reserved
ASP input partial SRC lock status.
0 Unlocked
1 Locked
Reserved
VP Monitor Interrupt Status
R/O
0
—
0
0
0
0
VPMON_TRIP
0
0
0
x
Bits
Name
Description
7:1
—
Reserved
0 VPMON_TRIP VP monitor interrupt. If the VP power supply falls below 2.6 V, this bit is set. See Section 4.9.1 for details.
0 No interrupt
1 Interrupt detected
DS1081F3
68
CS43L36
7.4 Interrupt Registers
7.4.8
PLL Lock Interrupt Status
R/O
7
6
Address 0x130E
5
4
3
2
1
0
—
Default
Bits
7:1
0
0
Name
—
PLL_LOCK
7.4.9
0
0
PLL_LOCK
0
0
0
0
Description
Reserved
PLL lock. Indicates the lock state of the PLL.
0 No interrupt
1 Interrupt detected
Tip Sense Plug/Unplug Interrupt Status
R/O
7
6
5
0
0
Address 0x130F
4
—
Default
x
0
3
2
TS_UNPLUG
TS_PLUG
x
x
0
1
0
–
x
x
Bits
Name
Description
7:4
—
Reserved
3
TS_UNPLUG Tip sense unplug status. See Section 4.8.3 for details. Setting TS_INV reverses the meaning of this bit.
0 Condition is not present.
1 Condition is present.
2
TS_PLUG
Tip sense plug status. See Section 4.8.3 for details. Setting TS_INV reverses the meaning of this bit.
0 Condition is not present.
1 Condition is present.
1:0
—
Reserved
7.4.10 Mixer Interrupt Mask
R/W
7
6
Address 0x1317
5
4
3
2
—
Default
Bits
7:2
1
0
0
0
Name
—
M_CHA_OVFL
M_CHB_OVFL
0
0
1
1
0
M_CHA_OVFL
M_CHB_OVFL
1
1
1
Description
Reserved
CHx_OVFL mask.
0 Unmasked
1 (Default) Masked
7.4.11 SRC Interrupt Mask
R/W
7
6
Address 0x1318
5
4
3
—
Default
0
Bits
7:3
2
Name
—
M_SRC_
IUNLK
1
0
—
M_SRC_ILK
DS1081F3
0
0
0
1
2
1
0
M_SRC_IUNLK
—
M_SRC_ILK
1
1
1
Description
Reserved
SRC_IUNLK mask.
0 Unmasked
1 (Default) Masked
Reserved
SRC_ILK mask.
0 Unmasked
1 (Default) Masked
69
CS43L36
7.4 Interrupt Registers
7.4.12 ASP RX Interrupt Mask
R/W
7
6
5
4
—
Default
0
Name
—
M_ASPRX_
OVLD
3
M_ASPRX_
ERROR
2
M_ASPRX_
LATE
1
M_ASPRX_
EARLY
0
M_ASPRX_
NOLRCK
3
2
1
0
M_ASPRX_OVLD M_ASPRX_ERROR M_ASPRX_LATE M_ASPRX_EARLY M_ASPRX_NOLRCK
0
Bits
7:5
4
Address 0x1319
0
1
1
1
1
1
Description
Reserved
ASPRX_OVFL mask.
0 Unmasked
1 (Default) Masked
ASPRX_ERROR mask.
0 Unmasked
1 (Default) Masked
ASPRX_LATE mask.
0 Unmasked
1 (Default) Masked
ASPRX_EARLY mask.
0 Unmasked
1 (Default) Masked
ASPRX_NOLRCK mask.
0 Unmasked
1 (Default) Masked
7.4.13 DAC Interrupt Mask
R/W
7
6
Address 0x131B
5
4
3
2
1
0
—
Default
Bits
7:1
0
0
Name
—
M_PDN_
DONE
0
0
0
M_PDN_DONE
0
0
1
1
Description
Reserved
PDN_DONE mask.
0 Unmasked
1 (Default) Masked
7.4.14 SRC Partial Lock Interrupt Mask
R/W
Default
7
6
—
M_DAC_UNLK
0
1
Bits
7
6
Name
—
M_DAC_
UNLK
5–3
2
—
M_DAC_LK
1:0
—
DS1081F3
5
Address 0x131C
4
3
—
1
1
2
1
M_DAC_LK
1
1
0
—
1
1
Description
Reserved
ASP input unlock mask.
0 Unmasked
1 (Default) Masked
Reserved
ASP input lock mask.
0 Unmasked
1 (Default) Masked
Reserved
70
CS43L36
7.5 Fractional-N PLL Registers
7.4.15 VP Monitor Interrupt Mask
R/W
7
6
5
Address 0x131E
4
3
2
1
0
—
Default
Bits
7:1
0
0
0
0
M_VPMON_TRIP
0
0
0
0
1
Name
Description
—
Reserved
M_
VP monitor mask.
VPMON_ 0 Unmasked. Unmask/enable this bit only when VP exceeds the detection voltage threshold; applicable to power-up
TRIP
conditions or if VP is not at its steady-state voltage.
1 (Default) Masked
7.4.16 PLL Lock Mask
R/W
7
Address 0x131F
6
5
4
3
2
1
0
M_PLL_LOCK
—
Default
Bits
7:1
0
0
Name
—
M_PLL_
LOCK
0
0
0
0
0
0
1
Description
Reserved
PLL lock mask.
0 Unmasked
1 (Default) Masked
7.4.17 Tip Sense Plug/Unplug Interrupt Mask
R/W
7
6
5
4
—
Default
Bits
7:4
3
0
0
0
0
Name
—
Reserved
M_TS_ Tip sense unplug mask.
UNPLUG
0 Unmasked
1 (Default) Masked
M_TS_ Tip sense plug mask.
PLUG
0 Unmasked
1 (Default) Masked
—
Reserved
2
1:0
Address 0x1320
3
2
M_TS_UNPLUG
M_TS_PLUG
1
1
1
0
—
1
1
Description
7.5 Fractional-N PLL Registers
7.5.1
PLL Control 1
R/W
7
6
Address 0x1501
5
4
3
2
1
—
Default
Bits
7:1
0
0
0
0
0
0
PLL_START
0
0
0
0
Name
Description
—
Reserved
PLL_ PLL start. If MCLK_SRC_SEL = 0, the PLL is bypassed and can be powered down by clearing PLL_START. See Section 4.4.3.
START
0 (Default) Powered off.
1 Powered on
DS1081F3
71
CS43L36
7.5 Fractional-N PLL Registers
7.5.2
PLL Division Fractional Bytes 0–2
R/W
7
6
5
Address 0x1502–0x1504
4
3
0x1502
PLL_DIV_FRAC[7:0]
0x1503
PLL_DIV_FRAC[15:8]
0x1504
1
0
0
0
0
PLL_DIV_FRAC[23:16]
Default
Bits
7:0
2
0
0
0
0
0
Name
PLL_DIV_
FRAC[7:0]
Description
PLL fractional portion of divide ratio LSB. See Section 4.4.3 for details. There are 3 bytes of PLL feedback divider fraction
portion: This is LSB byte; e.g., 0xFF means (2–17 + 2–18 + …+2–24)
0000 0000 (Default)
7:0
PLL_DIV_ PLL fractional portion of divide ratio middle byte; e.g., 0xFF means (2–9 + 2–10 + …+2–16). See Section 4.4.3 for details.
FRAC[15:8]
0000 0000 (Default)
7:0
PLL_DIV_ PLL fractional portion of divide ratio MSB; e.g., 0xFF means (2–1 + 2–2 + …+2–8). See Section 4.4.3 for details.
FRAC[23:16] 0000 0000 (Default)
7.5.3
PLL Division Integer
R/W
7
6
Address 0x1505
5
4
3
2
1
0
0
0
0
0
PLL_DIV_INT
Default
0
1
0
0
Bits
Name
Description
7:0 PLL_DIV_INT PLL integer portion of divide ratio. Integer portion of PLL feedback divider. See Section 4.4.3 for details.
0100 0000 (Default)
7.5.4
PLL Control 3
R/W
7
6
Address 0x1508
5
4
3
2
1
0
0
0
0
0
PLL_DIVOUT
Default
Bits
7:0
0
0
0
1
Name
Description
PLL_ Final PLL clock output divide value. See Section 4.4.3 for configuration details.
DIVOUT
0001 0000 (Default)
7.5.5
PLL Calibration Ratio
R/W
7
6
Address 0x150A
5
4
3
2
1
0
0
0
0
PLL_CAL_RATIO
Default
1
Bits
Name
7:0 PLL_CAL_
RATIO
7.5.6
0
0
0
0
Description
PLL calibration ratio. See Section 4.4.3 for configuration details. Target value for PLL VCO calibration.
1000 0000 (Default)
PLL Control 4
R/W
7
6
Address 0x151B
5
4
3
2
1
Default
0
0
0
0
PLL_MODE
—
0
0
0
1
1
Bits Name
Description
7:2
—
Reserved
1:0 PLL_ PLL bypass mode. Configures 500/512 and 1029/1024 factor bypasses. See Section 4.4.3 for configuration details.
MODE
00 Unsupported
10 1029/1024 only (500/512 bypassed)
01 500/512 only (1029/1024 bypassed)
11 (Default) Both bypassed
DS1081F3
72
CS43L36
7.6 HP Load-Detect Registers
7.6 HP Load-Detect Registers
7.6.1
Load-Detect R/C Status
R/O
7
6
Address 0x1925
5
—
Default
0
0
Bits
7:6
4
Name
CLA_STAT
1:0
RLA_STAT
—
7.6.2
4
3
CLA_STAT
0
2
1
—
0
0
0
0
0
Description
Reserved
Capacitor load-detection result for HPA. See Section 4.2.2 for details.
Note: Low capacitance results were determined with CL = 1 nF; high capacitance results were determined with CL = 10 nF.
0 (Default) High capacitance (CL  ~2 nF)
1 Low capacitance (CL < ~2 nF)
Resistor load-detection result for HPA. See Section 4.2.2 for details.
00 (Default) 15 
10 3 k
01 30 
11 Reserved
HP Load Detect Done
R/O
7
6
Address 0x1926
5
4
3
2
1
0
—
Default
Bits
7:1
0
0
RLA_STAT
0
0
0
HPLOAD_DET_DONE
0
0
0
0
0
Name
Description
Reserved
HPLOAD_ HP load detect done. Indicates whether HP load detection is finished. See Section 4.2.2 for details.
DET_DONE
0 (Default) HP load is not finished.
1 HP load is finished.
—
7.6.3
HP Load Detect Enable
R/O
7
6
Address 0x1927
5
4
3
2
1
Default
Bits
7:1
0
0
0
Name
—
HP_LD_EN
0
0
0
HP_LD_EN
—
0
0
0
0
Description
Reserved
HP load detect enable. A 0-to-1 bit transition initiates load detection. See Section 4.2.2 for details.
0 (Default) Disabled
1 Enabled
7.7 Headset Interface Registers
7.7.1
Wake Control
R/W
Default
Bits
7
6
5
4:1
Name
—
M_HP_
WAKE
Address 0x1B71
7
6
5
—
M_HP_WAKE
WAKEB_MODE
1
1
0
4
3
2
1
—
0
0
0
WAKEB_CLEAR
0
0
0
Description
Reserved
Mask tip sense wake.1 Configures the mask for the tip-sense wake status.
0 Unmasked. The occurrence of a wake interrupt affects WAKE. Before unmasking, pending wake events must be cleared
via WAKEB_CLEAR.
1 (Default) Masked. The occurrence of a wake interrupt does not affect WAKE.
WAKEB_ WAKE output mode.1 Configures the mode of operation for the WAKE output
MODE
0 (Default) Output is latched low after a trigger event until WAKEB_CLEAR is toggled.
1 Output follows the combination logic directly (nonlatched).
—
Reserved
DS1081F3
73
CS43L36
7.7 Headset Interface Registers
Bits Name
Description
0 WAKEB_ WAKE output clear. Applicable only if WAKEB_MODE = 0 and an event triggers the WAKE output to latch low.
CLEAR
0 (Default) WAKE output normal operation. If WAKEB_MODE = 1, WAKEB_CLEAR does not deassert WAKE, but clears
TIP_SENSE_PLUG, TIP_SENSE_UNPLUG in the VP domain.
1 WAKE output deasserted (the TIP_SENSE_PLUG, TIP_SENSE_UNPLUG bits in the VP domain are also cleared).
1.This bit can be changed only if LATCH_TO_VP is enabled (see p. 74).
7.7.2
Tip Sense Control 2
R/W
7
6
5
TIP_SENSE_CTRL
Default
0
Address 0x1B73
4
3
TIP_SENSE_INV
0
0
2
1
—
0
0
TIP_SENSE_DEBOUNCE
0
0
1
0
Bits
Name
Description
7:6 TIP_SENSE_ Tip sense control.Configures operation of the tip-sense circuit.
CTRL
Note: This bit can be updated only if LATCH_TO_VP (see p. 74) is enabled.
00 (Default) Disabled. The tip-sense circuit is powered down and does not report to the status registers (TIP_
SENSE_PLUG and TIP_SENSE_UNPLUG in the VP domain are also cleared).
01 Digital input. Internal weak current source pull-up is disabled.
10 Reserved
11 Short detect. Internal weak current source pull-up is enabled.
5
TIP_SENSE_ Tip sense invert. Used to invert the signal from the tip-sense circuit. Updatable only if LATCH_TO_VP is enabled.
INV
0 (Default) Not inverted
1 Inverted
4:2
—
Reserved
1:0 TIP_SENSE_ Tip sense debounce time. Sets tip sense unplug event (TIP_SENSE = 0) debounce time before status is reported.
DEBOUNCE Timings are approximate and vary with MCLKINT and FsINT.
00 No debounce
01 200 ms
10 (Default) 500 ms 11 1000 ms
7.7.3
Mic Detect Control 1
R/W
7
6
Address 0x1B75
5
4
3
LATCH_TO_VP EVENT_STATUS_SEL
Default
Bits
7
6
5:0
0
0
2
1
0
1
1
1
—
0
1
1
Name
LATCH_
TO_VP
Description
Latch to VP registers. Controls the transfer of writable control registers in the VD_FILT supply domain to duplicate registers
in the VP supply domain. Can be used to enable setting sticky status bits in the VP domain.
0 (Default) Inhibits the transfer of VD_FILT registers to VP registers (latched mode). Enables the setting of VP sticky
status latches.
1 Transfers VD_FILT fields to VP fields (transparent mode). Disables setting of VP sticky status latches.
Affected registers:
• TIP_SENSE_CTRL on p. 74
• M_HP_WAKE on p. 73
• WAKEB_MODE p. 73
• TIP_SENSE_INV on p. 74
Note: The description of PDN_ALL on p. 62 describes the interdependency between LATCH_TO_VP and PDN_ALL.
EVENT_ Event status selection. Selects the level of processing on readable status originating in the VP supply domain.
STATUS_
0 (Default) Raw (unprocessed) status events are selected.
SEL
1 Sticky processed status events are selected.
Affected registers:
• TIP_SENSE_PLUG on p. 68
•
• TIP_SENSE_UNPLUG on p. 68
—
Reserved
DS1081F3
74
CS43L36
7.8 DAC Control Registers
7.7.4
Detect Status 1
R/O
7
Address 0x1B77
6
5
4
TIP_SENSE
Default
x
x
Bits
7
Name
TIP_SENSE
6:0
—
7.7.5
3
2
1
0
x
x
x
x
—
0
x
Description
TIP_SENSE circuit status. The plug-to-unplug edge is debounced for the set debounce time (see TIP_SENSE_
DEBOUNCE, p. 74).
0 HP not plugged in
1 HP plugged in
Reserved
Detect Interrupt Mask 1
R/W
7
—
Default
Address 0x1B79
6
5
4
3
2
M_TIP_SENSE_PLUG M_TIP_SENSE_UNPLUG
1
1
1
1
0
0
0
—
0
0
0
Interrupt mask register bits serve as a mask for the interrupt sources in the interrupt status registers. Interrupts are described in Section 4.12.
Bits
7
6
Name
—
M_TIP_
SENSE_
PLUG
5
M_TIP_
SENSE_
UNPLUG
4:0
—
Description
Reserved
TIP_SENSE_PLUG mask
0 Unmasked
1 (Default) Masked
TIP_SENSE_UNPLUG mask
0 Unmasked
1 (Default) Masked
Reserved
7.8 DAC Control Registers
7.8.1
DAC Control 1
R/W
7
6
Address 0x1F01
5
4
3
2
—
Default
0
0
0
0
0
0
1
0
DACB_INV
DACA_INV
0
0
Bits
Name
Description
7:2
—
Reserved
1:0 DACx_INV DACx invert signal polarity. Configures the polarity of the DAC channel x signal. See Section 4.2 for details.
0 (Default) Not inverted
1 Inverted
7.8.2
DAC Control 2
R/W
7
6
Address 0x1F06
5
4
HPOUT_PULLDOWN
Default
Bits
7:4
3
0
0
0
3
2
1
HPOUT_LOAD HPOUT_CLAMP DAC_HPF_EN
0
0
0
1
0
—
0
Name
Description
HPOUT_ Although bits 2:0 are independent, the final resistance from the resistor string is dictated by the lowest resistance chosen;
PULLDOWN e.g., if HPOUT_PULLDOWN = 1011, a nominal 6-k pull-down resistance results even if 9.6-k resistance is also
selected.
0000 (Default) 0.9 k
1000 No pulldown
1010 5.8 k
1100 0.9 k
0001–0111 0.9 k
1001 9.3 k
1011 Reserved
1101–1111 Reserved
HPOUT_ HP output load. Sets HP amplifier capacitive load capability. Table 3-7 gives output specifications. See Section 4.2 for
LOAD
details.
0 (Default) 1 nF Mode
1 10 nF Mode
Note: The HP path must be powered down before reconfiguring this bit and repowered afterwards. See Section 4.2.2.
DS1081F3
75
CS43L36
7.9 HP Control Register
Bits
2
1
0
Name
HPOUT_
CLAMP
Description
HPOUT clamp. Configures an override of the HPOUT clamp to ground when the channels are powered down.
0 (Default) Clamp to ground when channels are powered down.
1 Clamp is disabled when the channels are powered down. The pulldown to GNDA depends on the HPOUT_
PULLDOWN setting.
DAC_HPF_ DAC high-pass filter enable. Configures the internal HPF before DAC. Changes to this bit must be made only if PDN_
EN
ALL = 1. See Section 4.2 for details.
0 Disabled. This must be cleared only for test purposes.
1 (Default) Enabled. The corner frequency is set to 0.935 Hz when FsINT = 48 kHz.
—
Reserved
7.9 HP Control Register
7.9.1
HP Control
R/W
7
Address 0x2001
6
5
4
3
—
Default
0
0
2
1
0
ANA_MUTE_B ANA_MUTE_A FULL_SCALE_VOL
0
0
1
1
0
—
1
Bits
Name
Description
7:4
—
Reserved
3 ANA_MUTE_ Analog mute Channel B. See Section 4.2 for details.
B
0 Unmuted
1 (Default) Muted
2 ANA_MUTE_ Analog mute Channel A. See Section 4.2 for details.
A
0 Unmuted
1 (Default) Muted
Full-scale volume. Determines the maximum volume for the headphone output. See Section 4.2 for details.
1
FULL_
0 (Default) 0 dB
SCALE_VOL
1 –6 dB. This setting is recommended if the load is approximately 15 .
0
—
Reserved
7.10 Class H Register
7.10.1 Class H Control
R/W
7
Address 0x2101
6
5
4
3
2
—
Default
0
0
0
1
0
ADPTPWR
0
0
1
1
1
Bits
Name
Description
7:3
—
Reserved
2:0 ADPTPWR Adaptive power adjustment. Configures how power to HP output amplifiers adapts to the output signal level. Section 4.2
gives detailed descriptions of supported settings.
000 Reserved
100 Fixed, Mode 3 —VCP/3 Mode (±VCP/3)
101–110 Reserved
001 Fixed, Mode 0—VP_CP Mode (±2.5V)
010 Fixed, Mode 1—VCP Mode (±VCP)
111 (Default) Adapt to signal. The output signal dynamically determines
011 Fixed, Mode 2 —VCP/2 Mode (±VCP/2)
the voltage level.
7.11 Volume Control
7.11.1 Channel A Input Volume
R/W
7
6
Address 0x2301
5
4
3
—
2
1
0
1
1
1
CHA_VOL
Default
0
Bits
7:6
5:0
Description
Reserved
Input attenuation. Sets the attenuation level to be applied to various stereo digital inputs. See Section 4.1 for details. Each input
can be muted or attenuated from –62 to 0 dB in 1-dB steps.
00 0000 0 dB
11 1110 –62.0 dB
00 0001 –1.0 dB …
11 1111 (Default) Mute.
Name
—
CHA_
VOL
DS1081F3
0
1
1
1
76
CS43L36
7.12 AudioPort Interface Registers
7.11.2 Channel B Input Volume
R/W
7
6
Address 0x2303
5
4
3
—
2
1
0
1
1
1
CHB_VOL
Default
0
Bits
7:6
5:0
Description
Reserved
Input attenuation. Sets the attenuation level to be applied to various stereo digital inputs. See Section 4.1 for details. Each
input can be muted or attenuated from –62 to 0 dB in 1-dB steps.
00 0000 0 dB
11 1110 –62.0 dB
00 0001 –1.0 dB …
11 1111 (Default) Mute.
Name
—
CHB_
VOL
0
1
1
1
7.12 AudioPort Interface Registers
7.12.1 Serial Port Receive Channel Select
R/W
7
6
5
Address 0x2501
4
3
—
Default
Bits
7:4
3:2
1:0
0
0
0
0
2
1
0
SP_RX_CHB_SEL
SP_RX_CHA_SEL
0
0
1
0
Name
Description
—
Reserved
SP_RX_ SP RX Channel B select for DAI0. Selects right input channel. See Section 5 for programming examples.
CHB_SEL
00 Channel 0
01 (Default) Channel 1 10 Channel 2
11 Channel 3
SP_RX_ SP RX Channel A select for DAI0. Selects right input channel.
CHA_SEL
00 (Default) Channel 0 01 Channel 1
10 Channel 2
11 Channel 3
7.12.2 Serial Port Receive Isochronous Control
R/W
Default
7
6
—
SP_RX_RSYNC
0
0
5
4
Address 0x2502
3
SP_RX_NSB_POS
0
0
2
SP_RX_NFS_NSBB
0
1
1
0
SP_RX_ISOC_MODE
0
0
Bits Name
Description
7
—
Reserved
6
SP_RX_ Serial port receive synchronization.
RSYNC
0 (Default) Normal state
1 Recenter the FIFO. No read and writes when asserted
5:3 SP_RX_ Serial-port receive null-sample bit position. Selects the position of the null byte in the resultant 16-, 24-, or 32-bit sample.
NSB_ For all samples, if SP_RX_ISOC_MODE ≠ 00, SP_RX_NFS_NSBB = 0, the following applies:
POS
• For a 16-bit sample (8-bit audio + null byte), [23:16] is the null byte.
• For a 24-bit sample (16-bit audio + null byte), [15:8] is the null byte.
• For a 32-bit sample (24-bit audio + null byte), [7:0] is the null byte.
Note: NSB Mode does not support 32-bit audio samples.
The ASP_RXn_CHn_RES fields in Section 7.14 set the output resolution of the ASP receive channel samples.
Clearing SP_RX_NSB_POS indicates that Bit 0 must be zero for the sample to be classified as a null.
000 (Default) 0 … 111 7
2
SP_RX_ Serial-port receive NSB/NFS Mode select.
NFS_
0 NSB Mode valid only if SP_RX_ISOC_MODE ≠ 00.
NSBB
1 (Default) NFS Mode
1:0 SP_RX_ Serial port receive isochronous mode. Selecting an isochronous mode allows for null removal. The ASP Rx rate bits (SP_RX_
ISOC_ FS, see p. 78) are used only to help the device determine when to insert nulls.
MODE
00 (Default) Native mode
10 96k isochronous stream
01 48k isochronous stream
11 192k isochronous stream
DS1081F3
77
CS43L36
7.13 SRC Registers
7.12.3 Serial Port Receive Sample Rate
R/W
7
6
5
Address 0x2503
4
3
2
—
Default
1
1
0
0
0
SP_RX_FS
0
0
0
1
1
Bits Name
Description
7:5
— Reserved
4:0 SP_ SP receive sample rate. Configures the sample rate of the SRC FSI when in Isochronous Mode. This setting autoscales when
RX_ configuring for a isochronous rate of 96 or 192 kHz with respect to the 48-kHz isochronous rate, e.g., 24-kHz setting in
FS isochronous rate of 48 kHz would be scaled to a 48-kHz setting in isochronous rate of 96 kHz.
0 0000 Reserved
0 0100 12.000 kHz 0 1000 24.000 kHz 0 1100 (Default) 48.000 kHz
1 0000 176.400 kHz
0 0001 8.00 kHz
0 0101 16.000 kHz 0 1001 32.000 kHz 0 1101 88.200 kHz
1 0001 176.472 kHz
0 0010 11.025 kHz
0 0110 22.050 kHz 0 1010 44.100 kHz 0 1110 88.236 kHz
1 0010 192.000 kHz
0 0011 11.0295 kHz 0 0111 22.059 kHz 0 1011 44.118 kHz 0 1111 96.000 kHz
1 0011–1 1111 Reserved
7.13 SRC Registers
7.13.1 SRC Input Sample Rate
R/W
7
6
Address 0x2601
5
4
3
2
—
Default
0
1
0
0
0
Bits Name
7:5
4:0
—
1
0
0
0
SRC_SDIN_FS
0
Description
Reserved
SRC_ SRC input sample rate. Must equal FsINT if SRC_BYPASS_DAC = 1.
SDIN_ 0 0000 (Default) Don’t know 0 0100 12.000 kHz 0 1000 24.000 kHz
FS
0 0001 8.00 kHz
0 0101 16.000 kHz 0 1001 32.000 kHz
0 0010 11.025 kHz
0 0110 22.050 kHz 0 1010 44.100 kHz
0 0011 11.0295 kHz
0 0111 22.059 kHz 0 1011 44.118 kHz
0 1100 48.000 kHz
0 1101 88.200 kHz
0 1110 88.236 kHz
0 1111 96.000 kHz
1 0000 176.400 kHz
1 0001 176.472 kHz
1 0010 192.000 kHz
1 0011–1 1111 Reserved
7.14 Serial Port Receive Registers
7.14.1 ASP Receive Enable
R/W
7
6
Address 0x2A01
5
4
3
—
Default
0
Bits
7:4
3:2
Name
—
ASP_
RX0_
CH_EN
1
0
—
ASP_
RX0_
2FS
0
0
0
2
1
0
ASP_RX0_CH_EN
—
ASP_RX0_2FS
0
0
0
0
Description
Reserved
ASP receive DAI0 enable. Determines whether the channel buffer gets populated.
ASP_RX0_CH_EN[0] = Channel 1
ASP_RX0_CH_EN[1] = Channel 2
0 (Default) The corresponding channel buffer does not get populated.
1 The corresponding channel buffer is populated
Reserved
ASP receive DAI0 double-rate mode.
0 (Default) Standard sample rate, Fs (not doubled)
1 Sample rate is doubled, 2 Fs
7.14.2 ASP Receive DAI0 Channel 1 Phase and Resolution
R/W
Default
7
6
—
ASP_RX0_CH1_AP
0
0
5
4
3
Address 0x2A02
2
—
0
0
1
0
ASP_RX0_CH1_RES
0
0
1
1
Bits
Name
Description
7
—
Reserved
6 ASP_RX0_ ASP receive DAI0 active phase. Valid only in 50/50 Mode (ASP_5050 = 1 and ASP_RX0_2FS = 0).
CH1_AP
0 (Default) Low. In 50/50 Mode, channel data is valid if LRCK/FSYNC is low.
1 High. In 50/50 Mode, channel data is valid when LRCK/FSYNC is high.
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78
CS43L36
7.14 Serial Port Receive Registers
Bits
Name
Description
5:2
—
Reserved
1:0 ASP_RX0_ ASP Receive DAI0 channel bit width. Sets output resolution of the ASP receive DAI0 channel x samples.
CH1_RES
00 8 bits per sample (only for isochronous NFS and native modes) 10 24 bits per sample
01 16 bits per sample
11 (Default) 32 bits per sample
7.14.3 ASP Receive DAI0 Channel 1 Bit Start MSB
R/W
7
6
5
4
Address 0x2A03
3
2
1
—
Default
0
0
0
0
ASP_RX0_CH1_BIT_ST_MSB
0
0
0
0
0
Bits
Name
Description
7:1
—
Reserved
0 ASP_RX0_CH1_ ASP receive DAI0 Channel 1 bit start MSB. Configures the MSB location of the channel with respect to SOF (LRCK
BIT_ST_MSB edge + phase lag)
7.14.4 ASP Receive DAI0 Channel 1 Bit Start LSB
R/W
7
6
5
Address 0x2A04
4
3
2
1
0
0
0
0
ASP_RX0_CH1_BIT_ST_LSB
Default
0
0
0
0
0
Bits
Name
Description
7:0 ASP_RX0_CH1_ ASP receive DAI0 Channel 1 bit start LSB. Configures the LSB location of the channel with respect to SOF (LRCK
BIT_ST_LSB
edge + phase lag)
7.14.5 ASP Receive DAI0 Channel 2 Phase and Resolution
R/W
Default
7
6
—
ASP_RX0_CH2_AP
5
0
0
4
Address 0x2A05
3
2
—
0
1
0
ASP_RX0_CH2_RES
0
0
0
1
1
Bits
Name
Description
7
—
Reserved
6 ASP_RX0_ ASP receive DAI0 active phase. Valid only in 50/50 Mode (ASP_5050 = 1 and ASP_RX0_2FS = 0).
CH2_AP
0 (Default) Low. In 50/50 Mode, channel data is input when LRCK/FSYNC is low.
1 High. In 50/50 Mode, channel data is input when LRCK/FSYNC is high.
5:2
—
Reserved
1:0 ASP_RX0_ ASP receive DAI0 channel bit width. Sets the output resolution of the ASP receive DAI0 channel x samples.
00 8 bits per sample (valid only for isochronous NFS and native mode) 10 24 bits per sample
CH2_RES
01 16 bits per sample
11 (Default) 32 bits per sample
7.14.6 ASP Receive DAI0 Channel 2 Bit Start MSB
R/W
7
6
5
4
Address 0x2A06
3
2
1
—
Default
0
0
0
0
ASP_RX0_CH2_BIT_ST_MSB
0
0
0
0
0
Bits
Name
Description
7:1
—
Reserved
0 ASP_RX0_CH2_ ASP receive DAI0 Channel 2 bit start MSB. Configures the MSB location of the channel with respect to SOF (LRCK
BIT_ST_MSB edge + phase lag).
7.14.7 ASP Receive DAI0 Channel 2 Bit Start LSB
R/W
7
6
5
4
Address 0x2A07
3
2
1
0
0
0
0
ASP_RX0_CH2_BIT_ST_LSB
Default
0
0
0
0
0
Bits
Name
Description
7:0 ASP_RX0_CH2_ ASP receive DAI0 Channel 2 bit start LSB. Configures the LSB location of the channel with respect to SOF (LRCK
BIT_ST_LSB edge + phase lag).
DS1081F3
79
CS43L36
7.15 ID Registers
7.15 ID Registers
7.15.1 Subrevision
R/O
7
Address 0x3014
6
5
4
3
2
1
0
x
x
x
x
SUBREVISION
Default
x
x
x
x
Bits
Name
Description
7:0 SUBREVISION Subrevision. Identifies the CS43L36 subrevision. The Page 0x30 read sequence in Section 5.3 must be followed to read
this register.
0000 0011 Initial version.
7.15.2 Device ID A and B
R/O
7
6
Address 0x3015
5
4
3
2
DEVIDA
Default
0
1
1
0
1
1
DEVIDB
0
0
0
0
7.15.3 Device ID C and D
R/O
7
6
Address 0x3016
5
4
3
2
DEVIDC
Default
1
0
1
0
1
1
DEVIDD
1
0
0
0
7.15.4 Device ID E
R/O
7
Address 0x3017
6
5
4
3
2
DEVIDE
Default
0
1
1
0
x
x
—
1
0
x
x
Bits Name
Description
7:4 DEVIDA Device ID code. Identifies the CS43L36. The Page 0x30 read sequence in Section 5.3 must be followed to read this register.
DEVIDC DEVIDA 0x4
DEVIDE DEVIDB 0x3
3:0 DEVIDB DEVIDC 0xA Represents the “L” in the CS43L36.
DEVIDD DEVIDD 0x3
DEVIDE 0x6
DS1081F3
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CS43L36
8 PCB Layout Considerations
8 PCB Layout Considerations
The following sections provide general guidelines for PCB layout to ensure the best performance of the CS43L36.
8.1 Power Supply
As with any high-resolution converter, to realize its potential, the CS43L36 requires careful attention to power supply and
grounding arrangements. Fig. 2-1 shows the recommended power arrangements, with VA and VCP connected to clean
supplies. VL, which powers the digital circuitry, may be run from the system logic supply. Alternatively, VL may be powered
from the analog supply via a ferrite bead. In this case, no additional devices should be powered from VL.
8.2 Grounding
Note the following:
•
Extensive use of power and ground planes, ground-plane fill in unused areas, and surface-mount decoupling
capacitors are recommended.
•
Decoupling capacitors should be as close as possible to the CS43L36 pins.
•
To minimize inductance effects, the low-value ceramic capacitor must be closest to the pin and mounted on the
same side of the board as the CS43L36.
•
To avoid unwanted coupling into the modulators, all signals, especially clocks, must be isolated from the FILT+ pin.
•
The FILT+ capacitor must be positioned to minimize the electrical path from the pin to GNDA.
•
The +VCP_FILT and –VCP_FILT capacitors must be positioned to minimize the electrical path from each respective
pin to GNDCP.
8.3 QFN Thermal Pad
The CS43L36 comes in a compact QFN package, the underside of which reveals a large metal pad that serves as a
thermal relief to provide maximum heat dissipation. This pad must mate with a matching copper pad on the PCB and must
be electrically connected to ground. A series of vias should be used to connect this copper pad to one or more larger
ground planes on other PCB layers. For best performance in split-ground systems, connect this thermal to GNDA.
DS1081F3
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CS43L36
9 Plots
9 Plots
9.1 Digital Filter Response
9.1.1
Highpass Filter—DAC
0.5
0
−0.5
Amplitude in dB
−1
−1.5
−2
−2.5
−3
−3.5
0
0.2
0.4
0.6
0.8
1
1.2
Normalised to Fs
1.4
1.6
1.8
2
−3
x 10
Figure 9-1. DAC HPF Response
DS1081F3
82
CS43L36
9.1 Digital Filter Response
9.1.2
DAC to HP, Fsint = 44.118 kHz, MCLK = 136 x LRCK
2
0
−10
1
−20
−30
Magnitude (dB)
Magnitude (dB)
0
−1
−2
−40
−50
−60
−70
−3
−80
−4
−90
−5
−100
0
0.05
0.1
0.15
0.2
0.25
0.3
Frequency (Normalised to Fs)
0.35
0.4
0.45
0.5
Figure 9-2. Passband—DAC, Fsint = 44.118 kHz
0
0.5
1
1.5
2
Frequency (Normalised to Fs)
2.5
3
Figure 9-3. Stopband—DAC, Fsint = 44.118 kHz
0
0
−10
−5
−20
−10
−30
Magnitude (dB)
Magnitude (dB)
−40
−50
−15
−20
−60
−25
−70
−30
−80
−35
−90
−100
0.4
0.42
0.44
0.46
0.48
0.5
0.52
Frequency (Normalised to Fs)
0.54
0.56
0.58
0.6
Figure 9-4. Transition Band—DAC, Fsint = 44.118 kHz
p
−40
0.45
0.46
0.47
0.48
0.49
0.5
0.51
Frequency (Normalised to Fs)
0.52
0.53
0.54
0.55
Figure 9-5. Transition Band (Detail)—DAC,
Fsint = 44.118 kHz
0
−100
Phase (degree)
−200
−300
−400
−500
−600
−700
0
0.05
0.1
0.15
0.2
0.25
0.3
Frequency Normalised to Fs
0.35
0.4
0.45
0.5
Figure 9-6. Phase Response—DAC, Fsint = 44.118 kHz
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CS43L36
9.1 Digital Filter Response
9.1.3
DAC to HP, Fsint = 48.000 kHz, MCLK = 125 x LRCK
2
0
−10
1
−20
−30
Magnitude (dB)
Magnitude (dB)
0
−1
−2
−40
−50
−60
−70
−3
−80
−4
−90
−5
0
0.05
0.1
0.15
0.2
0.25
0.3
Frequency (Normalised to Fs)
0.35
0.4
0.45
−100
0.5
Figure 9-7. Passband—DAC, Fsint = 48.000 kHz
0
0.5
1
1.5
2
Frequency (Normalised to Fs)
2.5
3
Figure 9-8. Stopband—DAC, Fsint = 48.000 kHz
0
0
−10
−5
−20
−10
Magnitude (dB)
−30
Magnitude (dB)
−40
−50
−15
−20
−60
−25
−70
−30
−80
−35
−90
−100
0.4
0.42
0.44
0.46
0.48
0.5
0.52
Frequency (Normalised to Fs)
0.54
0.56
0.58
0.6
Figure 9-9. Transition Band—DAC, Fsint = 48.000 kHz
−40
0.45
0.46
0.47
0.48
0.49
0.5
0.51
Frequency (Normalised to Fs)
0.52
0.53
0.54
0.55
Figure 9-10. Transition Band (Detail)—DAC,
Fsint = 48.000 kHz
0
−100
Phase (degree)
−200
−300
−400
−500
−600
−700
0
0.05
0.1
0.15
0.2
0.25
0.3
Frequency Normalised to Fs
0.35
0.4
0.45
0.5
Figure 9-11. Phase Response—DAC, Fsint = 48.000 kHz
DS1081F3
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CS43L36
9.1 Digital Filter Response
9.1.4
SDIN ASRC, FsINT = 48 kHz
p
p
0
0.25
−10
0.2
−20
0.15
−30
Magnitude (dB)
Magnitude (dB)
0.1
0.05
0
−0.05
−40
−50
−60
−0.1
−70
−0.15
−80
−0.2
−90
−0.25
0
0.05
0.1
0.15
0.2
0.25
0.3
frequency (Normalized to Fs)
0.35
0.4
0.45
0.5
−100
Figure 9-12. Passband—ASRC, Notch Disabled
0
0.5
1
1.5
2
frequency (Normalized to Fs)
2.5
3
Figure 9-13. Stopband—ASRC, Notch Disabled
p
0
p
p
0.2
0.25
0
−10
−50
−20
−100
Magnitude (dB)
−30
−40
−150
−50
−200
−60
−70
−250
−80
−300
−90
−100
0
0.1
0.2
0.3
0.4
0.5
0.6
frequency (Normalized to Fs)
0.7
0.8
0.9
1
Figure 9-14. Transition Band—ASRC, Notch Disabled
DS1081F3
−350
0
0.05
0.1
0.15
0.3
0.35
0.4
0.45
0.5
Figure 9-15. Phase Response—ASRC, Notch Disabled
85
CS43L36
10 Package Dimensions
10 Package Dimensions
10.1 WLCSP Package Dimensions
A
X
X
Ball A1 Location Indicator (seen through package)
A2
M
A1
b
Ball A1 Location
Indicator
Y
N
e
c
Y
Z
Seating Plane
WAFER BACK SIDE
b
Øb
Øddd Z X Y
Øccc Z
SIDE VIEW
e
d
BUMP SIDE
Notes:
• Dimensioning and tolerances per ASME Y 14.5M–1994.
• The Ball A1 position indicator is for illustration purposes only and may not be to scale.
• Dimension “b” applies to the solder sphere diameter and is measured at the maximum solder-ball diameter, parallel to primary Datum Z.
Table 10-1. WLCSP Package Dimensions
Dimension
A
Minimum
Millimeters
Nominal
0.443
0.148
0.474
0.174
A1
A2
0.284
0.300
M
BSC
2.100
N
BSC
2.100
b
0.225
0.250
c
REF
0.272
d
REF
0.272
e
BSC
0.350
X
2.614
2.644
Y
2.614
2.644
ccc = 0.015
ddd = 0.015
Note: Controlling dimension is millimeters.
DS1081F3
Maximum
0.505
0.200
0.316
BSC
BSC
0.300
REF
REF
BSC
2.674
2.674
86
CS43L36
10.2 QFN Package Dimensions
10.2 QFN Package Dimensions
Table 10-2. QFN Package Dimensions
Dimension
A
A1
A2
A3
b
D
K
e
E
J
L
aaa
bbb
ccc
ddd
eee
DS1081F3
Minimum
0.7
0.00
—
0.15
3.4
3.4
0.35
mm
Nominal
0.75
0.035
0.55
0.203 REF
0.20
5.00 BSC
3.5
0.40 BSC
5.00 BSC
3.5
0.40
0.10
0.10
0.08
0.10
0.10
Maximum
0.8
0.05
0.67
0.25
3.6
3.6
0.45
87
CS43L36
11 Thermal Characteristics
11 Thermal Characteristics
Table 11-1. Typical JEDEC Four-Layer, 2s2p Board Thermal Characteristics
Parameter 1
Junction-to-ambient thermal resistance
Junction-to-board thermal resistance
Junction-to-case thermal resistance
Junction-to-board thermal-characterization parameter
Junction-to-package-top thermal-characterization parameter
Symbol
JA
JB
JC
JB
JT
QFN
35.0
9.0
0.98
8.9
0.19
WLCSP
52.0
17.8
0.15
17.7
0.04
Unit
°C/W
°C/W
°C/W
°C/W
°C/W
1.Thermal setup:
Still air @ maximum allowed ambient temperature
JEDEC 2s2p printed wiring board (JEDEC Standard JESD51-11, June 2001)
Size: 114.5 x 101.5 x 1.6 mm
12 Ordering Information
Table 12-1. Ordering Information1
Product
Description
Package
CS43L36 Low-Power,
40-pin QFN
High-Performance
Audio DAC with
49-ball
Class H
WLCSP
Headphone Drivers
RoHS
Compliant
Yes
Yes
Grade
Temperature
Range
Container
Order #
Extended –40 to +85°C
Commercial
Tape and reel
CS43L36-CNZR
Tray
CS43L36-CNZ
Extended –40 to +85°C
Commercial
Tape and reel
CS43L36-CWZR
1.The Revision ID fields in Section 7.1.1, “Revision ID,” list the alpha (AREVID) and metal (MTLREVID) revision
13 References
•
NXP Semiconductors, UM10204 Rev. 06, April 2014, The I2C-Bus Specification and User Manual, http://
www.nxp.com
•
JEDEC Solid State Technology Association, Guidelines for Reporting and Using Electronic Package Thermal
Information, JEDEC Standard No. 51-12.01, November 2012, http://www.jedec.org/
DS1081F3
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CS43L36
14 Revision History
14 Revision History
Table 14-1. Revision History
Revision
Changes
F1
• Corrected TSTI pin descriptions in Section 1.3.
MAY ‘16 • Added note about options regarding 0402 capacitors to Section 2.1.1.
• Updated CMRR typical values in Table 3-7.
• Added HPOUT pull-down resistance to Table 3-8.
• Updated Table 4-12, Typical Leakage Current during Nonoperational Supply States (with VP Powered On),” in Section 4.9.
• Added Section 5.3, “Page 0x30 Read Sequence.”
• Added HPOUT_PULLDOWN to Section 6.8 and Section 7.8.2.
• Refined wording for Section 7.4.9.
F2
• Changed references to VD to VD_FILT in Section 5.5.
AUG ‘17 • Updated VL/VD_FILT ordering in Section 4.9.
• Relabelled the Y axes in Fig. 4-8 and Fig. 4-10 in Section 4.3.3.
F3
• Updated QFN package dimensions diagram in Section 10.2 (Aesthetic only—no content change).
JAN ‘18 • Added missing text in first bullet in Section 5.5.
• Added footnote 1 and updated package certification information in Table 12-1 (Nomenclature change only; no change to
package).
Important: Please check with your Cirrus Logic sales representative to confirm that you are using the latest revision of this document and to
determine whether there are errata associated with this device.
Contacting Cirrus Logic Support
For all product questions and inquiries, contact a Cirrus Logic Sales Representative.
To find the one nearest you, go to www.cirrus.com.
IMPORTANT NOTICE
The products and services of Cirrus Logic International (UK) Limited; Cirrus Logic, Inc.; and other companies in the Cirrus Logic group (collectively either “Cirrus
Logic” or “Cirrus”) are sold subject to Cirrus Logic’s terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to
warranty, indemnification, and limitation of liability. Software is provided pursuant to applicable license terms. Cirrus Logic reserves the right to make changes to
its products and specifications or to discontinue any product or service without notice. Customers should therefore obtain the latest version of relevant information
from Cirrus Logic to verify that the information is current and complete. Testing and other quality control techniques are utilized to the extent Cirrus Logic deems
necessary. Specific testing of all parameters of each device is not necessarily performed. In order to minimize risks associated with customer applications, the
customer must use adequate design and operating safeguards to minimize inherent or procedural hazards. Cirrus Logic is not liable for applications assistance
or customer product design. The customer is solely responsible for its selection and use of Cirrus Logic products. Use of Cirrus Logic products may entail a choice
between many different modes of operation, some or all of which may require action by the user, and some or all of which may be optional. Nothing in these
materials should be interpreted as instructions or suggestions to choose one mode over another. Likewise, description of a single mode should not be interpreted
as a suggestion that other modes should not be used or that they would not be suitable for operation. Features and operations described herein are for illustrative
purposes only.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR
ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS LOGIC PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN
PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, NUCLEAR SYSTEMS, LIFE SUPPORT PRODUCTS OR
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CUSTOMER OR CUSTOMER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS LOGIC PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY
SUCH USE, TO FULLY INDEMNIFY CIRRUS LOGIC, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL
LIABILITY, INCLUDING ATTORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES.
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rights, copyrights, trademarks, trade secrets or other intellectual property rights. Any provision or publication of any third party’s products or services does not
constitute Cirrus Logic’s approval, license, warranty or endorsement thereof. Cirrus Logic gives consent for copies to be made of the information contained herein
only for use within your organization with respect to Cirrus Logic integrated circuits or other products of Cirrus Logic, and only if the reproduction is without
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responsibility is assumed by Cirrus Logic for the use of information herein, including use of this information as the basis for manufacture or sale of any items, or
for infringement of patents or other rights of third parties. Cirrus Logic, Cirrus, the Cirrus Logic logo design, and SoundClear are among the trademarks of Cirrus
Logic. Other brand and product names may be trademarks or service marks of their respective owners.
Copyright © 2014–2018 Cirrus Logic, Inc. All rights reserved.
DS1081F3
89