MUN5214DW1, NSBC114YDXV6, NSBC114YDP6 Dual NPN Bias Resistor Transistors R1 = 10 kW, R2 = 47 kW http://onsemi.com NPN Transistors with Monolithic Bias Resistor Network This series of digital transistors is designed to replace a single device and its external resistor bias network. The Bias Resistor Transistor (BRT) contains a single transistor with a monolithic bias network consisting of two resistors; a series base resistor and a base-emitter resistor. The BRT eliminates these individual components by integrating them into a single device. The use of a BRT can reduce both system cost and board space. PIN CONNECTIONS (3) (2) R1 • Simplifies Circuit Design Reduces Board Space Reduces Component Count S and NSV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC-Q101 Qualified and PPAP Capable* These Devices are Pb-Free, Halogen Free/BFR Free and are RoHS Compliant R2 Q1 Q2 R2 Features • • • • (1) (4) R1 (5) (6) MARKING DIAGRAMS 6 7D M G G SOT−363 CASE 419B 1 MAXIMUM RATINGS (TA = 25°C, common for Q1 and Q2, unless otherwise noted) Rating Symbol Max Unit Collector-Base Voltage VCBO 50 Vdc Collector-Emitter Voltage VCEO 50 Vdc Collector Current − Continuous IC 100 mAdc Input Forward Voltage VIN(fwd) 40 Vdc Input Reverse Voltage VIN(rev) 6 Vdc Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. ORDERING INFORMATION Package Shipping† MUN5214DW1T1G, SMUN5214DW1T1G* SOT−363 3,000 / Tape & Reel NSVMUN5214DW1T3G* SOT−363 10,000 / Tape & Reel NSBC114YDXV6T1G NSVBC114YDXV6T1G SOT−563 4,000 / Tape & Reel NSBC114YDXV6T5G SOT−563 8,000 / Tape & Reel NSBC114YDP6T5G SOT−963 8,000 / Tape & Reel Device 7D M G G SOT−563 CASE 463A 1 PMG G SOT−963 CASE 527AD 1 7D/P M G = Specific Device Code = Date Code* = Pb-Free Package (Note: Microdot may be in either location) *Date Code orientation may vary depending upon manufacturing location. †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2014 September, 2014 − Rev. 2 1 Publication Order Number: DTC114YD/D MUN5214DW1, NSBC114YDXV6, NSBC114YDP6 THERMAL CHARACTERISTICS Characteristic Symbol Max Unit 187 256 1.5 2.0 mW MUN5214DW1 (SOT−363) ONE JUNCTION HEATED Total Device Dissipation TA = 25°C PD (Note 1) (Note 2) (Note 1) (Note 2) Derate above 25°C Thermal Resistance, Junction to Ambient (Note 1) (Note 2) RqJA mW/°C 670 490 °C/W 250 385 2.0 3.0 mW MUN5214DW1 (SOT−363) BOTH JUNCTION HEATED (Note 3) PD Total Device Dissipation TA = 25°C (Note 1) (Note 2) (Note 1) (Note 2) Derate above 25°C Thermal Resistance, Junction to Ambient (Note 1) (Note 2) Thermal Resistance, Junction to Lead (Note 1) (Note 2) Junction and Storage Temperature Range RqJA RqJL TJ, Tstg mW/°C °C/W 493 325 °C/W 188 208 −55 to +150 °C 357 2.9 mW mW/°C NSBC114YDXV6 (SOT−563) ONE JUNCTION HEATED PD Total Device Dissipation TA = 25°C Derate above 25°C (Note 1) (Note 1) Thermal Resistance, Junction to Ambient (Note 1) RqJA °C/W 350 NSBC114YDXV6 (SOT−563) BOTH JUNCTION HEATED (Note 3) PD Total Device Dissipation TA = 25°C Derate above 25°C (Note 1) (Note 1) Thermal Resistance, Junction to Ambient (Note 1) Junction and Storage Temperature Range 500 4.0 RqJA TJ, Tstg mW mW/°C °C/W 250 −55 to +150 °C 231 269 1.9 2.2 MW NSBC114YDP6 (SOT−963) ONE JUNCTION HEATED PD Total Device Dissipation TA = 25°C (Note 4) (Note 5) (Note 4) (Note 5) Derate above 25°C Thermal Resistance, Junction to Ambient (Note 4) (Note 5) RqJA mW/°C °C/W 540 464 NSBC114YDP6 (SOT−963) BOTH JUNCTION HEATED (Note 3) PD Total Device Dissipation TA = 25°C (Note 4) (Note 5) (Note 4) (Note 5) Derate above 25°C Thermal Resistance, Junction to Ambient (Note 4) (Note 5) Junction and Storage Temperature Range 1. 2. 3. 4. 5. 339 408 2.7 3.3 RqJA TJ, Tstg FR−4 @ Minimum Pad. FR−4 @ 1.0 × 1.0 Inch Pad. Both junction heated values assume total power is sum of two equally powered channels. FR−4 @ 100 mm2, 1 oz. copper traces, still air. FR−4 @ 500 mm2, 1 oz. copper traces, still air. http://onsemi.com 2 MW mW/°C °C/W 369 306 −55 to +150 °C MUN5214DW1, NSBC114YDXV6, NSBC114YDP6 ELECTRICAL CHARACTERISTICS (TA = 25°C, common for Q1 and Q2, unless otherwise noted) Symbol Characteristic Min Typ Max − − 100 − − 500 − − 0.2 50 − − 50 − − 80 140 − − − 0.25 − 0.7 0.3 1.4 0.8 − − − 0.2 4.9 − − Unit OFF CHARACTERISTICS Collector-Base Cutoff Current (VCB = 50 V, IE = 0) ICBO Collector-Emitter Cutoff Current (VCE = 50 V, IB = 0) ICEO Emitter-Base Cutoff Current (VEB = 6.0 V, IC = 0) IEBO nAdc nAdc mAdc Collector-Base Breakdown Voltage (IC = 10 mA, IE = 0) V(BR)CBO Collector-Emitter Breakdown Voltage (Note 6) (IC = 2.0 mA, IB = 0) V(BR)CEO Vdc Vdc ON CHARACTERISTICS hFE DC Current Gain (Note 6) (IC = 5.0 mA, VCE = 10 V) Collector-Emitter Saturation Voltage (Note 6) (IC = 10 mA, IB = 0.3 mA) VCE(sat) Input Voltage (Off) (VCE = 5.0 V, IC = 100 mA) Vi(off) Input Voltage (On) (VCE = 0.2 V, IC = 1.0 mA) Vi(on) Output Voltage (On) (VCC = 5.0 V, VB = 2.5 V, RL = 1.0 kW) VOL Output Voltage (Off) (VCC = 5.0 V, VB = 0.5 V, RL = 1.0 kW) VOH V Vdc Vdc Vdc Vdc Input Resistor R1 7 10 13 Resistor Ratio R1/R2 0.17 0.21 0.25 6. Pulsed Condition: Pulse Width = 300 ms, Duty Cycle ≤ 2%. PD, POWER DISSIPATION (mW) 400 350 300 250 200 (1) SOT−363; 1.0 × 1.0 Inch Pad (2) SOT−563; Minimum Pad (3) SOT−963; 100 mm2, 1 oz. Copper Trace (1) (2) (3) 150 100 50 0 −50 −25 0 25 50 75 100 125 150 AMBIENT TEMPERATURE (°C) Figure 1. Derating Curve http://onsemi.com 3 kW MUN5214DW1, NSBC114YDXV6, NSBC114YDP6 1 1000 IC/IB = 10 VCE = 10 V hFE, DC CURRENT GAIN VCE(sat), COLLECTOR−EMITTER VOLTAGE (V) TYPICAL CHARACTERISTICS MUN5214DW1, NSBC114YDXV6 25°C 0.1 150°C −55°C 10 20 30 40 50 −55°C 10 1 10 IC, COLLECTOR CURRENT (mA) IC, COLLECTOR CURRENT (mA) Figure 2. VCE(sat) vs. IC 100 Figure 3. DC Current Gain 3.6 100 2.8 IC, COLLECTOR CURRENT (mA) f = 10 kHz IE = 0 A TA = 25°C 3.2 2.4 2 1.6 1.2 0.8 0.4 0 0 10 20 30 40 50 10 −55°C 1 25°C 150°C 0.1 0.01 0.001 VO = 5 V VR, REVERSE VOLTAGE (V) 3 4 5 6 7 Vin, INPUT VOLTAGE (V) Figure 4. Output Capacitance Figure 5. Output Current vs. Input Voltage 0 1 2 100 Vin, INPUT VOLTAGE (V) Cob, OUTPUT CAPACITANCE (pF) 150°C 100 1 0.1 0.01 0 25°C 10 −55°C 25°C 1 150°C VO = 0.2 V 0.1 0 10 20 30 40 IC, COLLECTOR CURRENT (mA) Figure 6. Input Voltage vs. Output Current http://onsemi.com 4 50 8 9 10 MUN5214DW1, NSBC114YDXV6, NSBC114YDP6 1 1000 IC/IB = 10 VCE = 10 V hFE, DC CURRENT GAIN VCE(sat), COLLECTOR−EMITTER VOLTAGE (V) TYPICAL CHARACTERISTICS NSBC114YDP6 25°C 0.1 150°C −55°C 10 20 30 40 100 50 10 1 10 IC, COLLECTOR CURRENT (mA) IC, COLLECTOR CURRENT (mA) Figure 7. VCE(sat) vs. IC 100 Figure 8. DC Current Gain 2.4 100 2 IC, COLLECTOR CURRENT (mA) f = 10 kHz IE = 0 A TA = 25°C 1.6 1.2 0.8 0.4 0 0 10 20 30 40 50 −55°C 10 1 25°C 0.1 0.01 0.001 150°C VO = 5 V VR, REVERSE VOLTAGE (V) 2 3 4 5 Vin, INPUT VOLTAGE (V) Figure 9. Output Capacitance Figure 10. Output Current vs. Input Voltage 0 1 100 Vin, INPUT VOLTAGE (V) Cob, OUTPUT CAPACITANCE (pF) 150°C −55°C 1 0.1 0.01 0 25°C 10 25°C −55°C 1 150°C VO = 0.2 V 0.1 0 10 20 30 40 IC, COLLECTOR CURRENT (mA) Figure 11. Input Voltage vs. Output Current http://onsemi.com 5 50 6 7 MUN5214DW1, NSBC114YDXV6, NSBC114YDP6 PACKAGE DIMENSIONS SC−88/SC70−6/SOT−363 CASE 419B−02 ISSUE Y 2X aaa H D D A D 6 5 GAGE PLANE 4 2 L L2 E1 E 1 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.20 PER END. 4. DIMENSIONS D AND E1 AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY AND DATUM H. 5. DATUMS A AND B ARE DETERMINED AT DATUM H. 6. DIMENSIONS b AND c APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.08 AND 0.15 FROM THE TIP. 7. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 TOTAL IN EXCESS OF DIMENSION b AT MAXIMUM MATERIAL CONDITION. THE DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OF THE FOOT. H DETAIL A 3 aaa C 2X bbb H D 2X 3 TIPS e B 6X ddd TOP VIEW DIM A A1 A2 b C D E E1 e L L2 aaa bbb ccc ddd b A2 M C A-B D DETAIL A A 6X ccc C A1 SIDE VIEW C SEATING PLANE c MILLIMETERS MIN NOM MAX −−− −−− 1.10 0.00 −−− 0.10 0.70 0.90 1.00 0.15 0.20 0.25 0.08 0.15 0.22 1.80 2.00 2.20 2.00 2.10 2.20 1.15 1.25 1.35 0.65 BSC 0.26 0.36 0.46 0.15 BSC 0.15 0.30 0.10 0.10 END VIEW RECOMMENDED SOLDERING FOOTPRINT* 6X 6X 0.30 0.66 2.50 0.65 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 6 INCHES NOM MAX −−− 0.043 −−− 0.004 0.035 0.039 0.008 0.010 0.006 0.009 0.078 0.086 0.082 0.086 0.049 0.053 0.026 BSC 0.010 0.014 0.018 0.006 BSC 0.006 0.012 0.004 0.004 MIN −−− 0.000 0.027 0.006 0.003 0.070 0.078 0.045 MUN5214DW1, NSBC114YDXV6, NSBC114YDP6 PACKAGE DIMENSIONS SOT−563, 6 LEAD CASE 463A ISSUE F D −X− 6 5 1 2 A L 4 E −Y− 3 b e NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETERS 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. DIM A b C D E e L HE HE C 5 PL 6 0.08 (0.003) M X Y MILLIMETERS MIN NOM MAX 0.50 0.55 0.60 0.17 0.22 0.27 0.08 0.12 0.18 1.50 1.60 1.70 1.10 1.20 1.30 0.5 BSC 0.10 0.20 0.30 1.50 1.60 1.70 SOLDERING FOOTPRINT* 0.3 0.0118 0.45 0.0177 1.35 0.0531 1.0 0.0394 0.5 0.5 0.0197 0.0197 SCALE 20:1 mm Ǔ ǒinches *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 7 INCHES NOM MAX 0.021 0.023 0.009 0.011 0.005 0.007 0.062 0.066 0.047 0.051 0.02 BSC 0.004 0.008 0.012 0.059 0.062 0.066 MIN 0.020 0.007 0.003 0.059 0.043 MUN5214DW1, NSBC114YDXV6, NSBC114YDP6 PACKAGE DIMENSIONS SOT−963 CASE 527AD ISSUE E D X Y 6 5 4 1 2 3 HE E DIM A b C D E e HE L L2 C SIDE VIEW TOP VIEW e 6X 6X 6X L2 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. A L MILLIMETERS MIN NOM MAX 0.34 0.37 0.40 0.10 0.15 0.20 0.07 0.12 0.17 0.95 1.00 1.05 0.75 0.80 0.85 0.35 BSC 0.95 1.00 1.05 0.19 REF 0.05 0.10 0.15 b 0.08 X Y BOTTOM VIEW RECOMMENDED MOUNTING FOOTPRINT* 6X 6X 0.35 0.20 PACKAGE OUTLINE 1.20 0.35 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. 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