CMX138A CML Microcircuits Audio Scrambler and Sub-Audio Signalling Processor COMMUNICATION SEMICONDUCTORS D/138A/4 October 2014 CMX138A: Audio Scrambler and Sub-Audio Signalling Processor with Auxiliary System Clock, ADC and DAC for use in Analogue Radio Systems Features Programmable Audio Scrambler Selectable Audio Processing Order Concurrent Audio/Signalling Operations Sub-audio Signalling: CTCSS, DCS Full Audio-band Processing: Pre and De-emphasis, Compandor, Scrambler and Selectable 2.55/3 kHz Filters Auxiliary System Clock Output Auxiliary ADC and Auxiliary DAC Flexible Powersave Modes C-BUS Serial Interface to Host µController Available in 28-pin TSSOP Package Tx Output for Single-point Modulation Low-power (3.0V to 3.6V) Operation Two Analogue Inputs (Mic or Discriminator) DAC Output ADC Input 3.0V to 3.6V Modulator Discriminator CMX138A GPIO Audio Scrambler and Sub-Audio Processor RF Built on FirmASIC technology ® C-BUS Host µC System Clock 1 Reference Clock 1 Brief Description The CMX138A is a half-duplex, audio scrambler and sub-audio signalling processor IC for Analogue Twoway Radio applications. This makes it a suitable device for the leisure radio markets (FRS, MURS, PMR446 and GMRS). This device provides a user programmable frequency inversion audio scrambler, companding and pre/deemphasis – performing simultaneous processing of Sub-audio and In-band signalling. Other features include an auxiliary ADC channel and an auxiliary DAC interface (with optional RAMDAC, to facilitate transmitter power ramping). The device has flexible powersaving modes and is available in a 28-pin (E1) TSSOP package. 2014 CML Microsystems Plc Audio Scrambler and Sub-Audio Signalling Processor CMX138A CONTENTS Section Page 1 Brief Description ...................................................................................................................... 1 2 History ...................................................................................................................................... 5 3 Block Diagram .......................................................................................................................... 6 4 Signal List................................................................................................................................. 7 4.1 Signal Definitions .......................................................................................................... 8 5 External Components.............................................................................................................. 9 5.1 PCB Layout Guidelines and Power Supply Decoupling .............................................. 11 6 General Description............................................................................................................... 12 7 Detailed Descriptions ............................................................................................................ 13 7.1 Xtal Frequency............................................................................................................ 13 7.2 Host Interface ............................................................................................................. 13 7.2.1 C-BUS Operation ................................................................................................. 13 7.3 Device Control ............................................................................................................ 15 7.3.1 Signal Routing ...................................................................................................... 15 7.3.2 Mode Control ........................................................................................................ 16 7.4 Audio Functions .......................................................................................................... 17 7.4.1 Audio Receive Mode ............................................................................................ 17 7.4.2 Audio Transmit Mode ........................................................................................... 19 7.4.3 Audio Compandor ................................................................................................ 23 7.5 Sub-audio Signalling ................................................................................................... 25 7.5.1 Receiving and Decoding CTCSS Tones .............................................................. 27 7.5.2 Receiving and Decoding DCS Codes .................................................................. 28 7.5.3 Transmit CTCSS Tone ......................................................................................... 30 7.5.4 Transmit DCS Code ............................................................................................. 30 7.6 In-band Signalling – User Tones ................................................................................ 30 7.6.1 Receiving and Decoding In-band Tone ................................................................ 30 7.6.2 Transmitting In-band Tone ................................................................................... 31 7.7 Auxiliary ADC Operation ............................................................................................. 31 7.8 Auxiliary DAC/RAMDAC Operation ............................................................................ 32 7.9 Digital System Clock Generator.................................................................................. 33 7.9.1 Main Clock Operation........................................................................................... 33 7.9.2 System Clock Operation ...................................................................................... 33 7.10 GPIO ........................................................................................................................... 34 7.11 Signal Level Optimisation ........................................................................................... 34 7.11.1 Transmit Path Levels ........................................................................................... 34 7.11.2 Receive Path Levels............................................................................................. 34 8 C-BUS Register Summary..................................................................................................... 35 8.1.1 Interrupt Operation ............................................................................................... 36 8.1.2 General Notes ...................................................................................................... 36 9 Configuration Guide .............................................................................................................. 37 2014 CML Microsystems Plc Page 2 D/138A/4 Audio Scrambler and Sub-Audio Signalling Processor CMX138A 9.1 C-BUS Register Details .............................................................................................. 37 9.1.1 Reset Operations ................................................................................................. 38 9.1.2 General Reset - $01 write .................................................................................... 38 9.1.3 AuxADC and TX MOD Mode - $A7 write ............................................................. 40 9.1.4 AuxDAC Control/Data - $A8 write ........................................................................ 40 9.1.5 AuxADC Data - $A9 read ..................................................................................... 41 9.1.6 System Clk PLL Data - $AB write ........................................................................ 42 9.1.7 System Clk REF - $AC write ................................................................................ 42 9.1.8 Analogue Input Gain - $B0 write .......................................................................... 43 9.1.9 Analogue Output Gain - $B1 write........................................................................ 44 9.1.10 AuxADC Threshold Data - $B5 write.................................................................... 45 9.1.11 Power Down Control - $C0 write .......................................................................... 45 9.1.12 Mode Control – $C1 write..................................................................................... 46 9.1.13 Audio Control – $C2 write .................................................................................... 46 9.1.14 Tx In-band Tone - $C3 write ................................................................................ 47 9.1.15 Status – $C6 read ................................................................................................ 47 9.1.16 Programming – $C8 write .................................................................................... 48 9.1.17 Scrambler Inversion Frequency – $CB write ........................................................ 48 9.1.18 Tone Status - $CC read ....................................................................................... 48 9.1.19 Audio Tone - $CD: 16-bit write ............................................................................. 49 9.1.20 Interrupt Mask - $CE write ................................................................................... 52 9.1.21 Reserved - $CF write ........................................................................................... 52 9.2 Programming Register Operation ............................................................................... 53 9.2.1 Program Block 0 – reserved ................................................................................ 54 9.2.2 Program Block 1 – In-band Tone Setup: .............................................................. 54 9.2.3 Program Block 2 – CTCSS and DCS Setup ........................................................ 55 9.2.4 Program Block 3 – AuxDAC, RAMDAC and Clock Control: ................................ 57 9.2.5 Program Block 4 – Gain and Offset Setup: .......................................................... 58 9.2.6 Initialisation of the Programming Register Blocks: ............................................... 62 10 Application Notes .................................................................................................................. 63 11 Performance Specification ................................................................................................... 63 11.1 Electrical Performance ............................................................................................... 63 11.1.1 Absolute Maximum Ratings ................................................................................. 63 11.1.2 Operating Limits ................................................................................................... 63 11.1.3 Operating Characteristics..................................................................................... 64 11.1.4 Parametric Performance ...................................................................................... 69 11.2 C-BUS Timing ............................................................................................................. 72 11.3 Packaging ................................................................................................................... 73 Table Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Page Definition of Power Supply and Reference Voltages.......................................................... 8 Xtal/clock Frequency Settings for Program Block 3 ......................................................... 13 DCS Codes and CTCSS Tones ....................................................................................... 26 DCS Modulation Modes ................................................................................................... 28 DCS 23 Bit Codes ............................................................................................................ 29 In-band Tone .................................................................................................................... 31 2014 CML Microsystems Plc Page 3 D/138A/4 Audio Scrambler and Sub-Audio Signalling Processor CMX138A Table 7 C-BUS Registers .............................................................................................................. 35 Table 8 Reset Operations ............................................................................................................. 38 Table 9 Voice Level Attenuation.................................................................................................... 50 Table 10 Voice Level Attenuation.................................................................................................. 50 Table 11 RAMDAC Values ............................................................................................................ 57 Table 12 Voice Level Attenuation.................................................................................................. 59 Figure Page Figure 1 Block Diagram ................................................................................................................... 6 Figure 2 CMX138A Recommended External Components ............................................................ 9 Figure 3 CMX138A Power Supply Connections and De-coupling ................................................ 11 Figure 4 C-BUS Transactions ....................................................................................................... 14 Figure 5 Signal Routing ................................................................................................................. 16 Figure 6 Rx 25kHz Channel Audio Filter Frequency Response .................................................... 18 Figure 7 De-emphasis Curve for TIA/EIA-603 Compliance .......................................................... 18 Figure 8 Tx Channel Audio Filter Response and Template (ETSI) ............................................... 20 Figure 9 Tx Channel Audio Filter Response and Template (TIA) ................................................. 20 Figure 10 Audio Frequency Pre-emphasis .................................................................................... 21 Figure 11 Expandor Transient Response ..................................................................................... 23 Figure 12 Compressor Transient Response ................................................................................. 24 Figure 13 Low Pass Sub-audio Band Filter for CTCSS and DCS ................................................. 27 Figure 14 AuxADC IRQ Operation ................................................................................................ 32 Figure 15 Digital Clock Generation Schemes ............................................................................... 33 Figure 16 Default Tx Audio Filter Line-up ..................................................................................... 61 Figure 17 Default Rx Audio Filter Line-up ..................................................................................... 61 Figure 18 C-BUS Timing ............................................................................................................... 72 Figure 19 Mechanical Outline of 28-pin TSSOP (E1) ................................................................... 73 It is always recommended that you check for the latest product datasheet version from the CML website: [www.cmlmicro.com]. 2014 CML Microsystems Plc Page 4 D/138A/4 Audio Scrambler and Sub-Audio Signalling Processor 2 CMX138A History Version 4 3 2 1 Changes Updated CTCSS detector response times, following product characterisation. Added note 74 about statistical processes. Added description of fine attenuation settings to $CD and P4.2, P4.3 Note that it is possible to alter standard CTCSS settings when in Tx mode, but not custom settings or DCS settings Update MOD and AUDIO output drive parameters, after characterisation Correct minor typos and change document status to full issue. Enhanced description of C-BUS latency time, just before Fig 4. Correction to Audio Tone ($CD) register, code 1100b, section 9.1.19. Correction to Program Block 4, registers P4.10 and P4.11, section 9.2.5. First Issue of CMX138A 2014 CML Microsystems Plc Page 5 Date Oct 2014 Dec 2012 Nov 2010 Jun 2010 D/138A/4 Audio Scrambler and Sub-Audio Signalling Processor 3 CMX138A Block Diagram Transmit Functions Sub-audio Signalling Pre-programmed 51 Tone CTCSS Encoder Programmable CTCSS Tone Encoder Programmable 23/24bit DCS Encoder In-band signalling Mux MOD Programmable In-band Encoder Audio processing MIC Voice Filter Compressor (Optional) PreEmphasis (Optional) Scrambler (Optional) Soft Limiter Channel Filter Receive Functions Audio Processing DISC Voice Filter De-Scrambler (Optional) De-Emphasis (Optional) Expander (Optional) sw AUDIO VBias Sub-audio signalling Pre-programmed 51 Tone CTCSS Decoder LPF Programmable CTCSS Tone Decoder Programmable 23/24bit DCS Decoder In-band signalling HPF Programmable tone decoder System Control Auxiliary Functions AVdd VBias Auxiliary System Clocks Bias Programmable PLL Clock Clock O/P AVss I/O Configuration DVdd Tx Enable VDec Bias I/O DVss Clock/Xtal XtalN Rx Enable Clock Select Crystal oscillator Main clock PLL Auxiliary DAC Ramp Profile RAM DAC 1 DAC O/P IRQN RDATA CSN Auxiliary ADC C-BUS Interface CDATA SCLK Thresholds Power control ADC Registers sw ADC I/P Averaging Figure 1 Block Diagram 2014 CML Microsystems Plc Page 6 D/138A/4 Audio Scrambler and Sub-Audio Signalling Processor 4 CMX138A Signal List CMX138A Signal Name Type 1 TXENA OP 2 VDEC PWR 3 SYSCLK OP Synthesised digital system clock output. 4 IRQN OP C-BUS: A 'wire-ORable' output for connection to the Interrupt Request input of the host. Pulled down to DVSS when active and is high impedance when inactive. An external pull-up resistor is required. 5 RDATA TS OP 6 SCLK IP C-BUS: The C-BUS serial clock input from the µC. 7 CDATA IP C-BUS: Serial data input from the µC. 8 CSN IP C-BUS: The C-BUS chip select input from the µC - there is no internal pullup on this input. 9 DVDD PWR The 3.3V positive supply rail for the digital on-chip circuits. This pin should be decoupled to DVSS by capacitors mounted close to the device pins. 10 XTAL/CLOCK IP Input to the oscillator inverter from the Xtal circuit or external clock source. 11 XTALN OP The output of the on-chip Xtal oscillator inverter. 12 DVSS PWR 13 MOD OP Modulator output. 14 MICFB OP MIC input amplifier feedback. 15 MICN IP MIC inverting input. 16 MICP IP MIC non-inverting input. Description Digital output pin – TxENA (active low). Internally generated 2.5V digital supply voltage. Must be decoupled to DVSS by capacitors mounted close to the device pins. No other connections allowed. C-BUS: A 3-state C-BUS serial data output to the µC. This output is high impedance when not sending data to the µC. Digital ground. Positive 3.3V supply rail for the analogue on-chip circuits. Levels and thresholds within the device are proportional to this voltage. This pin should be decoupled to AVSS by capacitors mounted close to the device pins. 17 AVDD PWR 18 AUXADC IP Auxiliary ADC input (inverted). 19 VBIAS OP Internally generated bias voltage of about AV DD/2, except when the device is in ‘Powersave’ mode when VBIAS pin will discharge to AV SS. Must be decoupled to AVSS by a capacitor mounted close to the device pins. No other connections allowed. 20 DISCN2 IP DISC inverting input 2. 21 DISCN1 IP DISC inverting input 1. 22 DISCFB OP DISC input amplifier feedback. 23 AUDIO OP Audio output. 24 AVSS PWR 25 AUXDAC OP 26 DVSS PWR 2014 CML Microsystems Plc Analogue ground. Auxiliary DAC output/RAMDAC. Digital ground. Page 7 D/138A/4 Audio Scrambler and Sub-Audio Signalling Processor CMX138A Signal Name 27 CLKSEL 28 RXENA Notes: 4.1 IP OP BI TS OP PWR NC = = = = = = CMX138A Type Description IP+PU Clock speed select (hi = 6.144MHz, lo = 3.6864MHz). OP Digital output pin – RxENA (active lo). Input (+ PU/PD = internal pullup/pulldown resistor) Output Bidirectional 3-state Output Power Connection No Connection - should NOT be connected to any signal. Signal Definitions Table 1 Definition of Power Supply and Reference Voltages Signal Name AVDD DVDD VDEC VBIAS AVSS DVSS Pins AVDD DVDD VDEC VBIAS AVSS DVSS 2014 CML Microsystems Plc Usage Power supply for analogue circuits Power supply for digital circuits Power supply for core logic, derived from DVDD by on-chip regulator Internal analogue reference level, derived from AVDD Ground for all analogue circuits Ground for all digital circuits Page 8 D/138A/4 Audio Scrambler and Sub-Audio Signalling Processor 5 CMX138A External Components TXENA C14 VDEC C15 SYSCLK IRQN R10 RDATA SCLK CDATA DVDD DVDD C13 C12 C9 DVSS R9 MOD C8 2 27 3 26 4 25 5 24 6 23 7 22 8 21 9 20 10 X1 C11 DVss 28 CMX138A CSN C10 1 19 11 18 12 17 13 16 14 15 RXENA CLKSEL DVSS DVSS AUXDAC AVSS AUDIO C1 R1 AVSS DISCFB C17 R2 R11 DISCN1 C16 R3 DISCN2 R4 VBIAS C2 R12 AVDD AUXADC AVDD C5 C3 MICP MICN C4 R5 C6 R6 R7 MICFB AVSS R8 C7 Figure 2 CMX138A Recommended External Components R1 R2 R3 R4 R5 R6 R7 See note 3 100k 100k 100k 100k 100k 100k X1 6.144MHz See note 1 R8 R9 R10 R11 R12 100k See note 3 10k 10k 10k C1 C2 C3 C4 C5 C6 C7 C8 See note 3 100nF 10µF 10nF 10nF 100pF 100pF See note 3 C9 C10 C11 C12 C13 C14 C15 C16 C17 39pF 39pF 10µF 10nF 10nF 10µF 10nF 100nF 100pF Resistors 5%, capacitors and inductors 20% unless otherwise stated. Notes: 1 X1 can be a crystal or an external clock generator; this will depend on the application. The tracks between the crystal and the device pins should be as short as possible to achieve maximum stability and best start up performance. 2014 CML Microsystems Plc Page 9 D/138A/4 Audio Scrambler and Sub-Audio Signalling Processor 2 CMX138A R2 and R3 should be selected to provide the desired dc gain of the discriminator input, as follows: GAINDISC = R2 / R3 The gain should be such that the resultant output at the DISCFB pin is within the discriminator input signal range specified in 7.11.2. If the DISCN2 pin is selected the gain becomes: GAINDISC = R2 / (R3//R4) (assuming that R3 and R4 are both connected to the same input signal). 3 R5, R6, R7 and R8 should be selected to provide the desired dc gain of the microphone input. The gain should be such that the resultant output at the MICFB pin is within the microphone input signal range specified in 7.11.1. For optimum performance with low signal microphones, an additional external gain stage may be required. C6 and C7 should be chosen to maintain a flat low pass response up to 3kHz. If a single-ended microphone is used, then R6 should be connected to VBIAS and R5 deleted. R1 and C1 should be chosen to maintain a flat low pass response up to 3kHz. R9 and C8 should be chosen to maintain a flat low pass response up to 3kHz. 4 If the DISC input is ac coupled, the selection of the coupling capacitor should allow for frequencies from below 50Hz and up to 3kHz to be passed without significant distortion to allow both Audio and sub-audio decoders to function within their specification. 5 If the MIC input is dc coupled, the selection of the coupling capacitor should allow for frequencies from 300Hz and up to 3kHz to be passed without significant distortion to allow the audio filtering and processing to function within their specification. 2014 CML Microsystems Plc Page 10 D/138A/4 Audio Scrambler and Sub-Audio Signalling Processor 5.1 CMX138A PCB Layout Guidelines and Power Supply Decoupling 1 VDEC C14 C15 DVss DVss Ground Plane 28 2 27 3 26 4 25 5 24 6 23 7 DVSS DVSS AVSS AVSS 22 CMX138A DVDD C13 C12 DVss C11 DVSS 8 21 9 20 10 19 11 18 12 17 13 16 14 15 AVSS Ground Plane VBIAS C2 AVSS AVDD C5 C3 C4 AVSS Figure 3 CMX138A Power Supply Connections and De-coupling Notes: 1. It is important to protect the analogue pins from extraneous in-band noise and to minimise the impedance between the device and the supply and bias de-coupling capacitors. The de-coupling capacitors should be as close as possible to the device. It is therefore recommended that the printed circuit board is laid out with separate ground planes for the AVSS, and DVSS supplies in the area of the CMX138A, with provision to make links between them, close to the device. Use of a multi-layer printed circuit board will facilitate the provision of ground planes on separate layers. 2. VBIAS is used as an internal reference for detecting and generating the various analogue signals. It must be carefully decoupled, to ensure its integrity, so apart from the decoupling capacitor shown, no other loads should be connected. If VBIAS needs to be used to set the discriminator mid-point reference, it must be buffered with a high input-impedance buffer. 2014 CML Microsystems Plc Page 11 D/138A/4 Audio Scrambler and Sub-Audio Signalling Processor 6 CMX138A General Description The CMX138A is intended for use in half duplex analogue two way mobile radio or family radio equipment and is particularly suited to enhanced MURS/GMRS/FRS designs. The CMX138A provides a user programmable frequency inversion audio scrambler integrated with signal processing functions, CTCSS, DCS and in-band tones, permitting sophisticated levels of tone control and voice processing. A flexible power control facility allows the device to be placed in its optimum powersave mode when not actively processing signals. The CMX138A includes a crystal clock generator, with buffered output, to provide a common system clock if required. A block diagram of the CMX138A is shown in Figure 1. The signal processing blocks are assigned to particular inputs/outputs. A facility to completely bypass the device is provided (with programmable gain). Tx functions: o Single microphone input with input amplifier, programmable gain adjust and AGC o Filtering selectable for 12.5kHz and 25kHz channels o Selectable pre-emphasis o Selectable compression o Selectable frequency inversion voice scrambling o Programmable scrambler inversion frequency o Selectable audio processing order o Single-point modulation outputs with programmable level adjustment o Pre-programmed 51-tone CTCSS encoder o 180 degree CTCSS phase shift generation o Programmable 23/24-bit DCS encoder o Programmable In-band Tone generator o Programmable audio tone generator (for custom audio tones) Rx functions: o Demodulator input with input amplifier and programmable gain adjustment o Audio-band and sub-audio rejection filtering o Selectable de-emphasis o Selectable expansion o Selectable frequency inversion voice de-scrambling o Programmable scrambler inversion frequency o Selectable audio processing order o Software volume control o 1 from 51 CTCSS decoder + Tone Clone™ mode o 23/24-bit DCS decoder o In-band Tone decoder Auxiliary functions: o Programmable system clock output o Auxiliary ADC o Auxiliary DAC, with built-in programmable RAMDAC o Selectable default Xtal options, 6.144MHz or 3.6864MHz Interface: o o o C-BUS: 4-wire high speed synchronous serial command/data bus Open drain IRQ to host Two Output Enable pins 2014 CML Microsystems Plc Page 12 D/138A/4 Audio Scrambler and Sub-Audio Signalling Processor 7 7.1 CMX138A Detailed Descriptions Xtal Frequency The CMX138A is designed to work with a Xtal or external frequency source of 6.144MHz or 3.6864MHz (as selected by the state of the CLKSEL pin). If either of these default configurations is not suitable, then Program Register Block 3 should to be loaded with the correct values to ensure that the device will work to specification with the user specified clock frequency. A table of common values can be found in Table 2. Note the maximum Xtal frequency is 12.288MHz, although an external clock source of up to 24.576MHz can be used. The register values in Table 2 are shown in hex (however only the lower 10 bits are relevant), the default settings are shown in bold, and the settings which do not give an exact setting (but are within acceptable limits) are in italics. The new P3.2-3 settings take effect following the write to P3.3 (the settings in P3.4-7 are implemented on a change to Rx or Tx mode). Check that the PRG flag is set in the Status register ($C6 bit 0 is set to '1') before writing each new P3.2 – P3.7 value via the Programming register ($C8). If a default frequency is not used, the register values in Table 2 should be programmed into the CMX138A immediately after power-up. Table 2 Xtal/clock Frequency Settings for Program Block 3 Program Register 3.579 3.6864 6.144 9.0592 12.0 12.8 16.368 16.8 19.2 GP Timer $017 $017 $018 $018 $019 $019 $018 $019 $018 VCO output and AUX clk divide $085 $085 $088 $10F $10F $110 $095 $115 $099 Ref clk divide $043 $024 $040 $0C6 $07D $0C8 $155 $15E $0C8 PLL clk divide $398 $1E0 $200 $370 $200 $300 $400 $400 $200 VCO output and AUX clk divide $140 $140 $140 $140 $140 $140 $140 $140 $140 Internal ADC / DAC clk divide $008 $008 $008 $008 $008 $008 $008 $008 $008 DVSS DVSS DVDD DVDD DVDD DVDD DVDD DVDD DVDD Idle P3.2 P3.3 P3.4 P3.7 Rx or Tx P3.5 P3.6 Connect CLKSEL pin to: 7.2 External frequency source (MHz) Host Interface A serial data interface (C-BUS) is used for command, status and data transfers between the CMX138A and the host µC; this interface is compatible with microwire, SPI. Interrupt signals notify the host µC when a change in status has occurred and the µC should read the status register across the C-BUS and respond accordingly. Interrupts only occur if the appropriate mask bit has been set. See section 8.1.1. The device will monitor the state of the C-BUS registers that the host has written to every 250µs (the CBUS latency period) hence it is not advisable for the host to make successive writes to the same C-BUS register within this period. To minimise activity on the C-BUS interface, optimise response times and ensure reliable data transfers, it is advised that the IRQ facility be utilised (using the IRQ mask register, $CE). It is permissible for the host to poll the IRQ pin if the host uC does not support a fully interrupt-driven architecture. This removes the need to continually poll the C-BUS status register ($C6) for status changes. 7.2.1 C-BUS Operation This block provides for the transfer of data and control or status information between the CMX138A’s internal registers and the host µC over the C-BUS serial interface. Each transaction consists of a single 2014 CML Microsystems Plc Page 13 D/138A/4 Audio Scrambler and Sub-Audio Signalling Processor CMX138A Address byte sent from the µC which may be followed by one or more Data byte(s) sent from the µC to be written into one of the CMX138A’s Write Only registers, or one or more data byte(s) read out from one of the CMX138A’s Read Only registers, as illustrated in Figure 4. Data sent from the µC on the CDATA line is clocked into the CMX138A on the rising edge of the SCLK input. RData sent from the CMX138A to the µC is valid when the SCLK is high. The CSN line must be held low during a data transfer and kept high between transfers. The C-BUS interface is compatible with most common µC serial interfaces and may also be easily implemented with general purpose µC I/O pins controlled by a simple software routine. The number of data bytes following an Address byte is dependent on the value of the Address byte. The most significant bit of the address or data are sent first. For detailed timings see section 11.2. Note that, due to internal timing constraints, there may be a delay of up to 250µs between the end of a C-BUS write operation and the CMX138A responding to the C-BUS command. Ensure that this C-BUS latency time (up to 250µs) is observed when writing multiple commands to the same C-BUS register. C-BUS Write: See Note 1 See Note 2 CSN SCLK CDATA 7 6 5 4 3 2 1 MSB 0 7 LSB MSB Address / Command byte 6 … 0 7 LSB MSB Upper 8 bits … 0 LSB Lower 8 bits RDATA High Z state C-BUS Read: See Note 2 CSN SCLK CDATA 7 6 5 4 3 2 MSB 1 0 LSB Address byte Upper 8 bits RDATA 7 High Z state MSB 6 … Lower 8 bits 0 7 LSB MSB … 0 LSB Data value unimportant Repeated cycles Either logic level valid (and may change) Either logic level valid (but must not change from low to high) Figure 4 C-BUS Transactions Notes: 1. For Command byte transfers only the first 8 bits are transferred ($01 = Reset) 2. For single byte data transfers only the first 8 bits of the data are transferred 3. The CDATA and RDATA lines are never active at the same time. The Address byte determines the data direction for each C-BUS transfer. 4. The SCLK input can be high or low at the start and end of each C-BUS transaction 5. The gaps shown between each byte on the CDATA and RDATA lines in the above diagram are optional, the host may insert gaps or concatenate the data as required. 2014 CML Microsystems Plc Page 14 D/138A/4 Audio Scrambler and Sub-Audio Signalling Processor 7.3 CMX138A Device Control CMX138A can be set into many modes to suit the environment in which it is to be used. These modes are described in the following sections and are programmed over the C-BUS: either directly to operational registers or, for parameters that are not likely to change during operation, via the Programming register ($C8). For basic operation: 1. Enable the relevant hardware sections via the Power Down Control register 2. Set the appropriate mode registers to the desired state (Audio, In-band, Sub-Audio etc.) 3. Select the required Signal Routing and Gain 4. Use the Mode Control register to place the device into Rx or Tx mode To conserve power when the device is not actively processing an analogue signal, place the device into Idle mode. Additional powersaving can be achieved by disabling the unused hardware blocks, however, care must be taken not to disturb any sections that are automatically controlled. See: o o Power Down Control - $C0 write Mode Control – $C1 write 7.3.1 Signal Routing The CMX138A offers a flexible routing architecture, with two signal inputs, a single signal processing path with an optional bypass and both Tx Modulation and Audio outputs. Each of the signalling processing blocks is routed directly to the appropriate input and output blocks. See: o o o Analogue Output Gain - $B1 write AuxADC and TX MOD Mode - $A7 write Mode Control – $C1 write. 2014 CML Microsystems Plc Page 15 D/138A/4 Audio Scrambler and Sub-Audio Signalling Processor CMX138A MIC - MOD bypass gain MIC Input Enable: $C0:1 Gain: $B1:5-2 MOD output gain Enable: $C0:14 Gain: $B0:4-2 MOD Output Enable: $C0:8 Enable: $C0:11 Gain: $B1:12-10 DISC Input DISC – AUDIO bypass gain Select: $B0:5 Enable: $C0:2 Gain: $B1:9-6 AUDIO output gain Enable: $C0:15 Gain: $B0:10-8 AUDIO Output Enable: $C0:10 Enable: $C0:12 Gain: $B1:15-13 Input Select Enable: $C0:13 Select: $B0:1-0 Tx MOD mux mux Enable: $A7:13-12 Enable: $C0:6 Signal Processing Figure 5 Signal Routing The analogue gain/attenuation of each input and output can be set individually, with additional Fine Gain control available via the Programming registers. See: o o o Analogue Input Gain - $B0 write Analogue Output Gain - $B1 write Audio Tone - $CD: 16-bit write. 7.3.2 Mode Control The CMX138A operates in one of three modes: o Idle o Rx o Tx At power-on or following a Reset, the device will automatically enter Idle mode, which allows for the maximum powersaving whilst still retaining the capability of monitoring the AuxADC input (if enabled). It is only possible to write to the Programming register whilst in Idle mode. See: o Mode Control – $C1 write. 2014 CML Microsystems Plc Page 16 D/138A/4 Audio Scrambler and Sub-Audio Signalling Processor 7.4 CMX138A Audio Functions The audio signal can be processed in several ways, depending on the implementation required, by selecting the relevant bits in the Audio Control – $C2 write register. In both Rx and Tx, a selectable channel filter to suit either the 12.5kHz or 25kHz TIA/ETSI channel mask can be selected. This filter also incorporates a selectable hard or soft limiter to reduce the effects of over-modulation. Other features include 300Hz HPF, pre- and de-emphasis, companding and frequency inversion scrambling, all of which may be individually enabled. The order in which these features are executed is selectable to ensure compatibility with existing implementations and provide optimal performance (see section 9.2.5). 7.4.1 Audio Receive Mode The CMX138A operates in half duplex, so whilst in receive mode the transmit path (microphone input and modulator output amplifiers) can be disabled and powered down. The audio output signal level is equalised (to VBIAS) before switching between the audio port and the modulator ports, to minimise unwanted audible transients. In the powersave state, the audio output pin enters a hi-Z state, however, if left enabled and the preceding stages powersaved, it will be driven to the VBIAS level. See: o Audio Control – $C2 write. Receiving Audio Band Signals When a voice-based signal is being received, it is up to the host µC, in response to signal status information provided by the CMX138A, to control muting/enabling of the audio signal to the AUDIO output. The discriminator path through the device has a programmable gain stage. Whilst in receive mode this should normally be set to 0dB (the default) gain. Receive Filtering The incoming signal is filtered, as shown in Figure 6 (with the 300Hz HPF also active), to remove subaudio components and to minimise high frequency noise. When appropriate, the audio signal can then be routed to the AUDIO output. Separate selectable filters are available for: 300Hz High Pass (to reject sub-audible signalling) 2.55kHz Low Pass (for 12.5kHz channel operation) 3.0kHz Low Pass (for 25kHz channel operation) Note that with no filters selected, the low frequency response extends to below 5Hz at the low end but still rolls off above 3.3kHz at the top end. 2014 CML Microsystems Plc Page 17 D/138A/4 Audio Scrambler and Sub-Audio Signalling Processor CMX138A Figure 6 Rx 25kHz Channel Audio Filter Frequency Response Figure 7 De-emphasis Curve for TIA/EIA-603 Compliance 2014 CML Microsystems Plc Page 18 D/138A/4 Audio Scrambler and Sub-Audio Signalling Processor CMX138A De-emphasis Optional de-emphasis at -6dB per octave from 300Hz to 3000Hz (shown in Figure 7) can be selected, to facilitate compliance with TIA/EIA-603, EN 300 086, EN 301 025 etc. The template shows the +1, -3dB limits. Rx Companding (Expanding) The CMX138A incorporates an optional syllabic compandor in both transmit and receive modes. This expands received audio band signals that have been similarly compressed in the transmitter to enhance dynamic range. See section 7.4.3 and: o Audio Control – $C2 write. Audio De-scrambling The CMX138A incorporates an optional frequency inversion de-scrambler in receive mode. This descrambles received audio band signals that have been scrambled in the transmitter. The inversion frequency can be programmed using the Scramble Frequency register, $CB. The default value is 3300Hz. See: o o Audio Control – $C2 write Scrambler Inversion Frequency – $CB write. 7.4.2 Audio Transmit Mode The device operates in half duplex, so when the device is in transmit mode the receive path (discriminator and audio output amplifiers) should be disabled, and can be powered down, by the host µC. A single modulator output with programmable gain is provided which combines both the audio and subaudio signals to facilitate single or two-point modulation. To avoid spurious transmissions when changing from Rx to Tx the MOD output is ramped to the quiescent modulator output level, VBIAS before switching. Similarly, when starting a transmission, the transmitted signal is ramped up from the quiescent VBIAS level and when ending a transmission the transmitted signal is ramped down to the quiescent VBIAS level. The ramp rates are set in the Programming register P4.6 and enabled by bits 0,1 of the Analogue Input Gain register. When the modulator output is disabled, their outputs will be set to VBIAS. When the modulator output driver is powered down, its output will enter a hi-Z state (high impedance), so the external RF modulator should be disabled to avoid unwanted transmissions. For all transmissions, the host µC must only enable signals after the appropriate data and settings for those signals are loaded into the C-BUS registers. As soon as any signalling is enabled the CMX138A will use the settings to control the way information is transmitted. A programmable gain stage in the microphone input path facilitates a host controlled VOGAD capability. See: o o Audio Control – $C2 write Analogue Input Gain - $B0 write. Processing Audio Signals for Transmission over Analogue Channels The microphone input, with programmable gain, can be selected as the audio input source. Pre-emphasis is selectable with either of the two analogue Tx audio filters (for 12.5kHz and 25kHz channel spacing). These are designed for use in EN 300 086, TIA/EIA-603 or EN 301 025 compliant applications. When the 300Hz HPF is enabled, it will attenuate sub-audio frequencies below 250Hz by more than 33dB with respect to the signal level at 1kHz. These filters, together with a built in limiter, help ensure compliance with EN 300 086 and EN 301 025 (25kHz and 12.5kHz channel spacing) when levels and gain settings are set up correctly in the target system. The channel filters incorporate a soft-limiter function by default, however, should a hard-limiter be required, this can be enabled by setting bit 13 of Program Register P4.9 (see section 9.2.5). The level at which the limiter starts to operate can also be adjusted using Program Register P4.7 (see section 9.2.5). 2014 CML Microsystems Plc Page 19 D/138A/4 Audio Scrambler and Sub-Audio Signalling Processor CMX138A Figure 8 Tx Channel Audio Filter Response and Template (ETSI) Figure 9 Tx Channel Audio Filter Response and Template (TIA) 2014 CML Microsystems Plc Page 20 D/138A/4 Audio Scrambler and Sub-Audio Signalling Processor CMX138A The characteristics of the 12.5kHz channel filter fit the template shown in Figure 8 and Figure 9. This filter also facilitates implementation of systems compliant with TIA/EIA-603 ‘A’ , ‘B’ and ‘C’ bands . The CMX138A provides selectable pre-emphasis filtering of +6dB per octave from 300Hz to 3000Hz, matching the template shown in Figure 10. Figure 10 Audio Frequency Pre-emphasis Modulator Output Routing The sub-audio component is combined with the audio band signal and this composite signal routed to the MOD output in accordance with the settings of: o o AuxADC and TX MOD Mode - $A7 write Analogue Output Gain - $B1 write Input AGC An Automatic Gain Control system can be enabled by setting the relevant bits of the Program register P4.9. The setting of the Input 1 Gain stage is recorded when the device enters Tx mode and if the signal exceeds the pre-set threshold, the Input 1 Gain is automatically reduced in 3.2dB steps until it falls within the operational levels or the range of the gain stage is exhausted. When the signal level drops, the gain will be automatically increased in 3.2dB steps at the rate set in P4.9 until the initial value has been reached. For maximum effect the system should be designed such that the +22.4dB setting of the Input 1 Gain stage achieves the nominal levels. To ensure consistent operation, it is recommended that the Input 1 Gain stage value be re-initialised before entering Tx mode. The signal that is used as an input to this process can be selected to be either: o Output of Input1 gain stage o Output of the Pre-emphasis filter. by selecting the relevant bit in P4.9. The Pre-emphasis option should only be chosen if this block is actually in use. 2014 CML Microsystems Plc Page 21 D/138A/4 Audio Scrambler and Sub-Audio Signalling Processor o CMX138A Analogue Output Gain - $B1 writeProgram Block 4 – Gain and Offset Setup: Tx Companding (Compressing) The CMX138A incorporates an optional syllabic compandor in both transmit and receive mode. This compresses audio band signals before transmission to enhance dynamic range. See section 7.4.3 and: o Audio Control – $C2 write. Audio Scrambling The CMX138A incorporates an optional frequency inversion scrambler in transmit and receive modes. This scrambles transmitted audio band signals, which can then be de-scrambled in the receiver. The inversion frequency can be programmed using the Scramble Frequency register, $CB. The default value is 3300Hz. The scrambler frequency may be changed while the device is in an active Rx or Tx mode. See: o o Audio Control – $C2 write Scrambler Inversion Frequency – $CB write 2014 CML Microsystems Plc Page 22 D/138A/4 Audio Scrambler and Sub-Audio Signalling Processor CMX138A 7.4.3 Audio Compandor The compandor is comprised of a compressor and an expandor. The compressor’s function is to reduce the dynamic range of a given signal by attenuating larger amplitudes while amplifying smaller amplitudes. The expandor’s function is to expand the dynamic range of a given signal by attenuating small amplitude signals (e.g. noise) while amplifying large amplitude signals. The compressor is used prior to transmission and the expandor is used in the receiver. Hence, using a compandor will enhance performance in a communication system by transmitting a compressed signal, which is less likely to be corrupted by noise, and then at the receiver expanding the compressed signal, which will push the noise picked up during transmission down further. The CMX138A uses a “syllabic compandor.” This type of compandor, as opposed to the instantaneous compandor (e.g. µ/A-law PCM), responds to changes in the average envelope of the signal amplitude according to a syllabic time constant . Typically, the steady state output for the compressor is proportional to the square root of the input signal, i.e: for a 2 dB change in input signal, the output change will be 1 dB. Generally for voice communication systems a compressor is expected to have an input dynamic range of 60 dB, providing an output dynamic range of 30 dB. The expandor does the inverse. Figure 11 Expandor Transient Response 2014 CML Microsystems Plc Page 23 D/138A/4 Audio Scrambler and Sub-Audio Signalling Processor CMX138A Figure 12 Compressor Transient Response 2014 CML Microsystems Plc Page 24 D/138A/4 Audio Scrambler and Sub-Audio Signalling Processor 7.5 CMX138A Sub-audio Signalling Sub-audio signalling is available in the audio band below 260Hz. When sub-audio signalling is enabled, the 300Hz HPF in the audio section should also be enabled to remove the sub-audio signalling from the audio signal (in both Tx and Rx). Both CTCSS tones and DCS codes are supported, as well as a special Tone Clone™ mode which will report back any received CTCSS tone rather than look for a specific tone. There are 51 CTCSS tones defined in the CMX138A and there is provision for a user-specified tone. In Tx only, tone phase adjustment (180 or 120 degrees) to implement “Reverse Tone Burst” for squelch tail elimination can be accomplished by setting b9, b8 of the Audio Control register, $C2. The DCS coder/decoder supports both 23- and 24-bit modes with both true and inverse modulation formats and the 134Hz end of transmission burst. The CTCSS tone and DCS code values for both Rx and Tx operation are specified in the Audio Control register ($C2), in the lowest 8 bits (shown in decimal): o o o o o o o o 0 1 to 83 84 101 to 183 184 200 201 to 254 255 No tone DCS code 1 to 83 User-defined DCS code Inverted DCS code 1 to 83 Inverted user-defined DCS code CTCSS Tone Clone™ mode CTCSS tones 1 to 51, User, XTCSS and DCS off tones Invalid tone. These are detailed in Table 3. The inverted DCS codes are shown in the grey section of the table. The CTCSS and DCS functions are enabled by the relevant bits in the Mode Control register, $C1, so that the host can turn the functionality on or off without having to re-program the values in the Audio Control register, $C2. See: o o o Analogue Input Gain - $B0 write Mode Control – $C1 write Audio Control – $C2 write. 2014 CML Microsystems Plc Page 25 D/138A/4 Audio Scrambler and Sub-Audio Signalling Processor CMX138A DCS and Inve rte d DCS Code s Decimal 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 HEX 000 001 002 003 004 005 006 007 008 009 00A 00B 00C 00D 00E 00F 010 011 012 013 014 015 016 017 018 019 01A 01B 01C 01D 01E 01F 020 021 022 023 024 025 026 027 028 029 02A 02B 02C 02D 02E 02F 030 031 032 033 034 035 036 037 038 039 03A 03B 03C 03D 03E 03F data No Tone 023 025 026 031 032 043 047 051 054 065 071 072 073 074 114 115 116 125 131 132 134 143 152 155 156 162 165 172 174 205 223 226 243 244 245 251 261 263 265 271 306 311 315 331 343 346 351 364 365 371 411 412 413 423 431 432 445 464 465 466 503 506 516 Decimal 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 HEX 040 041 042 043 044 045 046 047 048 049 04A 04B 04C 04D 04E 04F 050 051 052 053 054 055 056 057 058 059 05A 05B 05C 05D 05E 05F 060 061 062 063 064 065 066 067 068 069 06A 06B 06C 06D 06E 06F 070 071 072 073 074 075 076 077 078 079 07A 07B 07C 07D 07E 07F data 532 546 565 606 612 624 627 631 632 654 662 664 703 712 723 731 732 734 743 754 Us e r Code x x x x x x x x x x x x x x x x 023 025 026 031 032 043 047 051 054 065 071 072 073 074 114 115 116 125 131 132 134 143 152 155 156 162 165 CTCSS Tone s Decimal 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 HEX 080 081 082 083 084 085 086 087 088 089 08A 08B 08C 08D 08E 08F 090 091 092 093 094 095 096 097 098 099 09A 09B 09C 09D 09E 09F 0A0 0A1 0A2 0A3 0A4 0A5 0A6 0A7 0A8 0A9 0AA 0AB 0AC 0AD 0AE 0AF 0B0 0B1 0B2 0B3 0B4 0B5 0B6 0B7 0B8 0B9 0BA 0BB 0BC 0BD 0BE 0BF data 172 174 205 223 226 243 244 245 251 261 263 265 271 306 311 315 331 343 346 351 364 365 371 411 412 413 423 431 432 445 464 465 466 503 506 516 532 546 565 606 612 624 627 631 632 654 662 664 703 712 723 731 732 734 743 754 Us e r Code x x x x x x x Decimal 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 HEX 0C0 0C1 0C2 0C3 0C4 0C5 0C6 0C7 0C8 0C9 0CA 0CB 0CC 0CD 0CE 0CF 0D0 0D1 0D2 0D3 0D4 0D5 0D6 0D7 0D8 0D9 0DA 0DB 0DC 0DD 0DE 0DF 0E0 0E1 0E2 0E3 0E4 0E5 0E6 0E7 0E8 0E9 0EA 0EB 0EC 0ED 0EE 0EF 0F0 0F1 0F2 0F3 0F4 0F5 0F6 0F7 0F8 0F9 0FA 0FB 0FC 0FD 0FE 0FF data x x x x x x x x Tone Clone 67 71.9 74.4 77 79.7 82.5 85.4 88.5 91.5 94.8 97.4 100 103.5 107.2 110.9 114.8 118.8 123 127.3 131.8 136.5 141.3 146.2 151.4 156.7 162.2 167.9 173.8 179.9 186.2 192.8 203.5 210.7 218.1 225.7 233.6 241.8 250.3 69.3 62.5 159.8 165.5 171.3 177.3 183.5 189.9 196.6 199.5 206.5 229.1 254.1 Us e r Tone XTCSS DCS off Invalid Tone Table 3 DCS Codes and CTCSS Tones 2014 CML Microsystems Plc Page 26 D/138A/4 Audio Scrambler and Sub-Audio Signalling Processor CMX138A 7.5.1 Receiving and Decoding CTCSS Tones The CMX138A is able to accurately detect valid CTCSS tones quickly, to avoid losing the beginning of audio or data transmissions, and is able to continuously monitor the detected tone with minimal probability of falsely dropping out. The received signal is filtered in accordance with the template shown in Figure 13, to prevent signals outside the sub-audio range from interfering with the sub-audio tone detection. 10 0 Gain (dB) -10 -20 -30 -40 -50 -60 -70 0 200 400 600 800 1000 Frequency (Hz) Figure 13 Low Pass Sub-audio Band Filter for CTCSS and DCS Once a valid CTCSS tone has been detected, Status register ($C6) b11 will be set and the host µC can then route the audio band signal to the audio output. The audio band signal is extracted from the received signal by bandpass filtering as shown in Figure 6. To optimise the CTCSS tone decoder, adjustable decoder bandwidths and threshold levels allow the user to trade-off decode certainty against signal-to-noise performance when congestion or range restrict the system performance. The tone decoder bandwidth and threshold level are set in P2.1 of the Programming register ($C8) and the desired tone is programmed in the Audio Control register ($C2). In systems which make use of tones 41 to 51 or other “split” tones (tones in between the frequencies of tones 1 to 40), the CTCSS decoder bandwidth should be reduced to avoid false detection of adjacent tones. When enabled, an interrupt will be issued when an input signal matching a CTCSS tone in Table 3 changes state (ie: on, off or to or from a different tone). If a sub-audio tone is present, but it is not one of the valid CTCSS tones (as shown in Table 3), then it will be reported as an unrecognised tone. If a tone other than the programmed tone is detected, it will be reported as an Invalid tone, unless Tone Cloning is enabled, in which case it will report the detected tone number. Note that CTCSS phase changes are not detected. If enabled, an IRQ will be generated under the following conditions: State change from: No Tone Own Tone No Tone Unrecognised Tone No Tone Invalid Tone To: Own Tone No Tone Unrecognised Tone No Tone Invalid Tone No Tone IRQ yes yes yes yes yes yes Tone Status value b7-0 Own Tone $00 $FF $00 $FF or detected Tone $00 Tone Cloning ™ Tone Cloning facilitates the detection of CTCSS tones 1 to 39 in receive mode which allows the device to non-predictively detect any tone in this range. This mode is activated by programming CTCSS Tone Number 00 (b0-7 of Audio Control register = 200 decimal). The received tone number will be reported in the Tone Status register ($CC) and can then be programmed into the Audio Control register by the host µC. The cloned tone will only be active when CTCSS is enabled in the Mode Control register ($C1). This setting has no effect in Tx mode and the CTCSS generator will output no signal. TTone Cloning™ is a trademark of CML Microsystems Plc. 2014 CML Microsystems Plc Page 27 D/138A/4 Audio Scrambler and Sub-Audio Signalling Processor CMX138A Tone Cloning™ should not be used in systems where tones 41 to 51 or other “split” tones (tones between the frequencies of tones 1 to 40) may be received. The all-call tone 40 can still be used after Tone Cloning™ has been performed. The CTCSS decoder detection bandwidth should be set to its lowest value (in P2.1 of the Programming Register) to ensure accurate detection. CTCSS Tones Table 3 lists the CTCSS tones available, the tone numbers and the equivalent (decimal) values that need to be programmed into b7-0 of the Audio Control register ($C2) and which will be reported back in the Tone Status register ($CC). Notes 1. Register value 00 in b0-7 of the Tone Status register ($CC) indicates that none of the above subaudio tones is being detected. If register value 00 is programmed into the Audio Control register ($C2) and CTCSS enabled in the Mode Control register ($C1), only CTCSS tone 40 (240 decimal) will be scanned for. If CTCSS transmit is selected, this tone setting will cause the CTCSS generator to output no signal. 2. Tone number 40 (240 decimal) provides an all-user CTCSS tone option; regardless of the subaudio tones set, the CMX138A will report the presence of this tone whenever the CTCSS detector is enabled. This feature is useful for implementing emergency type calls e.g. All-Call. 3. Tone number 55 (255 decimal) is reported in the Tone Status register ($CC), when CTCSS receive is enabled and a sub-audio tone is detected that does not correspond to the selected tone or the all-call tone (tone number 40). This could be a tone in the sub-audio band which is not in the table or a tone in the table which is not the selected tone or All-Call tone. 4. Tones 40 to 51 (240 to 251 decimal) are not in the TIA-603 standard. 5. Tone number 52 (252 decimal) will select the User Programmable Tone value in Program Block 2 – CTCSS and DCS Setup. 6. Tone number 53 (253 decimal) will select the XTCSS call maintenance tone, 64.7Hz. 7. Tone number 54 (254 decimal) will select the DCS turn-off tone, 134.4Hz. 8. Tone Clone, register value 200, is a write-only value to the Audio Control register ($C2). It will not be reported back in the Tone Status register ($CC). Instead, the received tone number is reported back in this register. 7.5.2 Receiving and Decoding DCS Codes DCS code is in NRZ format and transmitted at 134.40.4bps. The CMX138A is able to decode any 23- or 24-bit pattern in either of the two DCS modulation modes defined by TIA/EIA-603 and described in Table 4. The CMX138A can detect a valid DCS code quickly enough to avoid losing the beginning of audio transmissions. Modulation Type: A B Table 4 DCS Modulation Modes Data Bit: FM Frequency Change: 0 Negative frequency shift 1 Positive frequency shift 0 Positive frequency shift 1 Negative frequency shift The CMX138A detects the DCS code that matches the programmed code defined in the Audio Control register ($C2) in either its true or inverted form. Register values 1 to 83 correspond to modulation type A (“true”) and register values 101 to 183 correspond to modulation type B (“inverted”). A facility for a userdefined code is available via Program Block 2 – CTCSS and DCS Setup. The signal inversion caused by the input amplifier is automatically compensated for in the device, so that a true DCS signal applied at its input will be decoded as a true code in the Tone Status register ($CC). Note that monitoring this signal at the DISCFB pin will show an inverted waveform. To detect the pre-programmed DCS code, the signal is low-pass filtered to suppress all but the sub-audio band, using the filter shown in Figure 13. Further equalisation filtering, signal slicing and level detection are performed to extract the code being received. The extracted code is then matched with the 2014 CML Microsystems Plc Page 28 D/138A/4 Audio Scrambler and Sub-Audio Signalling Processor CMX138A programmed 23- or 24-bit DCS code to be recognised, in the order least significant first through to most significant DCS code bit last. Table 5 shows a selection of valid 23-bit DCS codes: this does not preclude other codes being programmed. Recognition of a valid DCS code will be flagged if the decode is successful (3 or less errors) by setting b10 of the Status register ($C6) to 1. A failure to decode is indicated by clearing this bit to 0. This bit is updated after the decoding of every 4th bit of the incoming signal. The actual code received is reported back in the Tone Status register ($CC) according to Table 3, so that the host µC can determine if it was the true or inverted form of the code. Once a valid DCS code has been detected, the host µC can route the audio band signal to the audio output. The audio signal is extracted from the received input signal by band pass filtering, see Figure 6. The end of DCS transmissions is indicated by a 134.4 0.5Hz tone for 150-200ms. When a valid DCS code has been detected, the CMX138A will automatically scan for the turn-off tone. When the DCS turn-off tone is detected it will cause a DCS interrupt and report tone 54 (Tone Status b0-7 value 254 decimal); the receiver audio output can then be muted by the host. Note that, due to the asynchronous nature of the turn-off tone, it is possible for both a “no-tone” and a “turn-off” tone to be indicated at the end of a DCS transmission. Note that DCS detection and CTCSS detection can not be performed concurrently. Table 5 DCS 23 Bit Codes Reg Value True Reg Value Invert DCS Code DCS bits 22-12 763 DCS bits 11-0 813 Reg Value True Reg Value Invert DCS Code DCS bits 22-12 18B DCS bits 11-0 87C Reg Value True Reg Value Invert DCS Code DCS bits 22-12 7B8 DCS bits 11-0 925 101 129 57 157 1 29 023 174 445 6B7 815 6E9 885 27E 934 102 130 58 158 2 30 025 205 464 65D 816 68E 893 60B 935 103 131 59 159 3 31 026 223 465 51F 819 7B0 896 6E1 936 104 132 60 160 4 32 031 226 466 5F5 81A 45B 8A3 3C6 943 105 133 61 161 5 33 032 243 503 5B6 823 1FA 8A4 2F8 946 106 134 62 162 6 34 043 244 506 0FD 827 58F 8A5 41B 94E 107 135 63 163 7 35 047 245 516 7CA 829 627 8A9 0E3 95A 108 136 64 164 8 36 051 251 532 6F4 82C 177 8B1 19E 966 109 137 65 165 9 37 054 261 546 5D1 835 5E8 8B3 0C7 975 110 138 66 166 10 38 065 263 565 679 839 43C 8B5 5D9 986 111 139 67 167 11 39 071 265 606 693 83A 794 8B9 671 98A 112 140 68 168 12 40 072 271 612 2E6 83B 0CF 8C6 0F5 994 113 141 69 169 13 41 073 306 624 747 83C 38D 8C9 01F 997 114 142 70 170 14 42 074 311 627 35E 84C 6C6 8CD 728 999 115 143 71 171 15 43 114 315 631 72B 84D 23E 8D9 7C2 99A 116 144 72 172 16 44 115 331 632 7C1 84E 297 8E3 4C3 9AC 117 145 73 173 17 45 116 343 654 07B 855 3A9 8E6 247 9B2 118 146 74 174 18 46 125 346 662 3D3 859 0EB 8E9 393 9B4 119 147 75 175 19 47 131 351 664 339 85A 685 8F4 22B 9C3 120 148 76 176 20 48 132 364 703 2ED 85C 2F0 8F5 0BD 9CA 121 149 77 177 21 49 134 365 712 37A 863 158 8F9 398 9D3 122 150 78 178 22 50 143 371 723 1EC 86A 776 909 1E4 9D9 123 151 79 179 23 51 152 411 731 44D 86D 79C 90A 10E 9DA 124 152 80 180 24 52 155 412 732 4A7 86E 3E9 90B 0DA 9DC 125 153 81 181 25 53 156 413 734 6BC 872 4B9 913 14D 9E3 126 154 82 182 26 54 162 423 743 31D 875 6C5 919 20F 9EC 127 155 83 183 27 55 165 431 754 05F 87A 62F 91A User Defined 128 156 84 184 28 56 172 432 Notes: 1. Register value 84 will select the User Programmable DCS code value in Program Block 2 – CTCSS and DCS Setup Register value 184 will select the inverted form of the User Programmable DCS code. 2. Note that the Audio Control register values are shown in decimal. 2014 CML Microsystems Plc Page 29 D/138A/4 Audio Scrambler and Sub-Audio Signalling Processor CMX138A 7.5.3 Transmit CTCSS Tone The sub-audio CTCSS tone generated is defined in the Audio Control register ($C2). Table 3 lists the CTCSS tones and the corresponding decimal values for programming b0-7 of the register. To facilitate Squelch Tail elimination and Reverse Tone Burst, the phase of the transmitted tone can be altered by either 120, 180 or 240 degrees by setting b9, b8 in the Audio Control register ($C2). The phase change is not instantaneous, but implemented by retarding the phase of the tone to its new value over a number of cycles to avoid the generation of spurious signals. A 180 degree change will be completed within 20ms. 7.5.4 Transmit DCS Code A 23- or 24-bit sub-audio DCS code can be generated, as defined by the Audio Control register ($C2). The same DCS code pattern is used for detection and transmission. The DCS code is NRZ encoded at 134.40.4 bps, low-pass filtered and added to the audio band signal, before being passed to the modulator output stages. Valid 23-bit DCS codes and the corresponding settings for the Audio Control Register are shown in Table 5, and include a user-defined facility. The least significant bit of the DCS code is transmitted first and the most significant bit is transmitted last. The CMX138A is able to encode and transmit either of the two DCS modulation modes defined by TIA/EIA-603 (true and inverted) described in Table 4. If 24-bit mode is required, bit 11 of Programming register P2.1 should be set. The MOD output inverts the signal from the device, so, depending on the detailed design of the following modulator sections, it may be necessary to select an inverted DCS code in the Audio Control register ($C2) in order to produce a true DCS code "on-air". To signal the end of the DCS transmission, the host should set the Audio Control register ($C2) to the DCS turn off tone (register value b0-7 = 254 decimal) for 150ms to 200ms. After this time period has elapsed the host should then disable DCS in the Mode Control register ($C1). Note that if a CTCSS tone is to be transmitted following the DCS turn-off tone (in a subsequent transmission) the new CTCSS value will need to be written to the Audio Control register ($C2) immediately after the selection of Tx mode. 7.6 In-band Signalling – User Tones The CMX138A supports a user-programmable in-band tone between 288Hz and 3000Hz. Note that if a tone below 400Hz is used, sub-audio signalling should be disabled and the 300Hz HPF disabled. By default, the CMX138A will use a 1750Hz tone, however this may be changed by the host to any valid tone within its operational range by use of the Programming register. This ensures that the device can remain compatible with all available tone systems in use. The CMX138A does not implement automatic repeat tone insertion or deletion: it is up to the host to correctly implement the appropriate protocol. Selection of the In-band signalling mode is performed by bits 10-9 of the Mode register ($C1). Detection of the selected In-band signalling mode can be performed in parallel with audio or data reception. See: o o o Mode Control – $C1 write Tx In-band Tone - $C3 write Tone Status - $CC read. 7.6.1 Receiving and Decoding In-band Tone In-band tones can be used to flag the start of a call or to confirm the end of a call. If they occur during a call the tone may be audible at the receiver. When a valid input signal is detected, it will be reported in the Tone Status register, $CC. If the input signal matches the In-band tone value then b15 will be set (tone detected), otherwise b14-11 will be set (unrecognised tone) – see Table 6. If enabled, an IRQ will be generated as shown below: State Change From: No Tone Own Tone No Tone Own Tone Unrecognised Tone To: Own Tone No Tone Unrecognised Tone Unrecognised Tone No Tone IRQ yes yes no yes no Tone Status Value b15-11 10000 00000 00000 01111 00000 The frequency of the tone is defined in Programming register P1.2. 2014 CML Microsystems Plc Page 30 D/138A/4 Audio Scrambler and Sub-Audio Signalling Processor CMX138A Adjustable decoder bandwidths and threshold levels are programmable via the Programming register. These allow certainty of detection to be traded against signal to noise performance when congestion or range limits the system performance. The in-band signal is derived from the received input signal after the bandpass filtering shown in Figure 6. Table 6 In-band Tone b15 0 1 x b14 0 0 1 b13 0 0 1 b12 0 0 1 b11 0 0 1 Rx Mode $CC No Tone Tone Detected Unrecognised Tone Tx Mode $C3 No Tone Transmit In-band Tone reserved 7.6.2 Transmitting In-band Tone The In-band tone to be generated is defined in the TX TONE register ($C3). The tone level is set in the Programming register (P1.0). The In-band tone must be transmitted without other signals in the audio band, so the host µC must disable the audio path prior to initiating transmission of an In-band tone and restore it after the In-band tone transmission is complete. 7.7 Auxiliary ADC Operation The input to the Auxiliary ADC is routed through an inverting op-amp from the AuxADC input pin under control of the AuxADC and Tx MOD mode register, $A7. Conversions will be performed as long as the input source is selected; to stop the ADC, the input source should be set to “none”. Register $C0, b6 (BIAS) must be enabled for Auxiliary ADC operation. Averaging can be applied to the ADC readings by selecting the relevant bits in the Signal Routing register, $A7, the length of the averaging is determined by the value in the Programming register (P3.0), and defaults to a value of 0. This is a rolling average system such that a proportion of the current data will be added to the last average value. The proportion is determined by the value of the average counter in P3.0, as follows: For an average value of: 0 = 50% of the current value will be added to 50% of the last average value, 1 = 25% of the current value will be added to 75% of the last average value 2 = 12.5% etc. The maximum useful value of this field is 8. For a step input signal, this provides an exponential-style response in the output data. High and low thresholds may be independently applied to the ADC channel (the comparison is applied after averaging, if this is enabled) and b8 of the IRQ Status register ($C6) will be set (and an IRQ generated, if enabled) whenever the signal crosses above the High threshold or below the Low threshold (except in the case where the high threshold has been set below the low threshold). The threshold status can be determined from b15 and b14 of the AuxADC data register ($A9). The thresholds are programmed via the AuxADC Threshold register ($B5). Auxiliary ADC data is read back in the AuxADC Data register ($A9) and includes the threshold status as well as the actual conversion data (subject to averaging, if enabled). Note that the thresholds are inverted due to the op-amp on the AuxADC input pin. 2014 CML Microsystems Plc Page 31 D/138A/4 Audio Scrambler and Sub-Audio Signalling Processor IRQ CMX138A IRQ IRQ IRQ High Threshold Signal (after inverter) Low Threshold Figure 14 AuxADC IRQ Operation To avoid multiple threshold IRQs when a noisy signal is present, the thresholds can be re-programmed following the initial event to provide hysteresis. See: o o o 7.8 AuxADC and TX MOD Mode - $A7 write AuxADC Data - $A9 read AuxADC Threshold Data - $B5 write. Auxiliary DAC/RAMDAC Operation The Auxiliary DAC channel is programmed via the AuxDAC Control register, $A8. AuxDAC may also be programmed to operate as a RAMDAC which will automatically output a pre-programmed profile at a programmed rate. The AuxDAC Control register, $A8, with b12 set, controls this mode of operation. The default profile is a raised cosine (see Table 11), but this may be over-written with a user defined profile by writing to Programming register P3.11. The RAMDAC operation is only available in Tx mode and, to avoid glitches in the ramp profile, it is important not to change to Idle or Rx mode whilst the RAMDAC is still ramping. The AuxDAC output holds the user-programmed level during a powersave operation if left enabled, otherwise it will return to zero. See: o AuxDAC Control/Data - $A8 write. 2014 CML Microsystems Plc Page 32 D/138A/4 Audio Scrambler and Sub-Audio Signalling Processor 7.9 CMX138A Digital System Clock Generator LPF Ref CLK div /1 to 512 $AC b0-8 PD SysCLK SysCLK Ref Div 48 - 192kHz (96kHz typ) VCO SysCLK VCO 24.57698.304MHz (49.152MHz typ) PLL div /1 to 1024 $AB b0-9 SysCLK Pre-CLK $AC b11-15 LPF Ref CLK div /1 to 512 $BD b0-8 PD MainCLK MainCLK Ref Div 48 - 192kHz (96kHz typ) VCO VCO op div /1 to 64 $AB b10-15 SYSCLK Output 384kHz-20MHz MainCLK VCO 24.57698.304MHz (49.152MHz typ) PLL div /1 to 1024 $BC b0-9 MainCLK Pre-CLK $BD b11-15 VCO op div /1 to 64 $BC b10-15 MainCLK Output 384kHz-50MHz (24.576MHz typ) To Internal ADC / DAC dividers OSC 3.0 - 12.288MHz Xtal or 3.0 - 24.576MHZ Clock AuxADC Div AuxADC (83.3kHz typ) Figure 15 Digital Clock Generation Schemes The CMX138A includes a two-pin crystal oscillator circuit. This can either be configured as an oscillator, as shown in Figure 2, or the XTAL input can be driven by an externally generated clock. The crystal (Xtal) source frequency can go up to 12.288MHz (clock source frequency up to 24.576MHz), but a 6.144MHz or 3.6864MHz Xtal is assumed for the default functionality provided in the CMX138A (see section 7.1). 7.9.1 Main Clock Operation A PLL is used to create the Main Clock (nominally 24.576MHz) for the internal sections of the CMX138A. At the same time, other internal clocks are generated by division of either the XTAL Reference Clock or the Main Clock. These internal clocks are used for determining the sample rates and conversion times of A-to-D and D-to-A converters, running a General Purpose Timer and the signal processing block. It should be noted that in Idle mode the setting of the GP Timer divider directly affects the C-BUS latency (with the default values this is nominally 250μs). The CMX138A defaults to the settings appropriate for a 6.144MHz or 3.6864MHz Xtal, however if other frequencies are to be used (to facilitate commonality of Xtals between the external RF synthesizers and the CMX138A for instance) then the Program Block registers P3.2 to P3.7 will need to be programmed appropriately at power-on. A table of common values is provided in Table 2. The C-BUS registers $BC and $BD are controlled automatically and must not be accessed directly by the user. See: o Program Block 3 – AuxDAC, RAMDAC and Clock Control: 7.9.2 System Clock Operation A System Clock output, SysClock1 Out, is available to drive additional circuits, as required. This is a phase locked loop (PLL) clock that can be programmed via the System Clock registers with suitable values chosen by the user. The System Clock PLL Configure register ($AB) controls the values of the VCO Output divider and Main Divide registers, while the System Clock Ref. Configure register ($AC) controls the values of the Reference Divider and signal routing configurations. The PLL is designed for a reference frequency of 96kHz. If not required, this clock can be independently powersaved. The clock generation scheme is shown in the block diagram of Figure 15. Note that at power-on the System Clock output is turned off and the output is held at '0'. See: o o System Clk PLL Data - $AB write System Clk REF - $AC write. 2014 CML Microsystems Plc Page 33 D/138A/4 Audio Scrambler and Sub-Audio Signalling Processor CMX138A 7.10 GPIO Two pins on the CMX138A are provided for Rx and Tx Enables. These pins become active low when the device enters the appropriate mode. These can be used for driving external circuitry and have the advantage of having minimal delay from the activation of the selected mode and so are not dependant upon any delays due to the transfer of commands / data over the C-BUS. $C1 Mode b1 b0 Tx_ENA Rx_ENA Idle 0 0 1 1 Rx 0 1 1 0 Tx 1 0 0 1 reserved 1 1 1 1 7.11 Signal Level Optimisation The internal signal processing of the CMX138A will operate with wide dynamic range and low distortion only if the signal level at all stages in the signal processing chain is kept within the recommended limits. For a device working from a 3.3V ±10% supply, the maximum signal level which can be accommodated without distortion is [(3.3 x 90%) – (2 x 0.3V)] Volts pk-pk = 838mV rms, assuming a sine wave signal. Compared to the reference level of 308mV rms, this is a signal of +8.69dB. This should not be exceeded at any stage. 7.11.1 Transmit Path Levels For the maximum undistorted signal out of the MOD attenuator, the signal level at the output of the Analogue block should not exceed +8.69dB, assuming both fine and coarse output attenuators are set to a gain of 0dB. The sub-audio level is normally set to 31mV rms ±1.0dB, which means that the output from the soft limiter must not exceed 803mV rms. If pre-emphasis is used, an output signal at 3000Hz will have three times the amplitude of a signal at 1000Hz, so the signal level before pre-emphasis should not exceed 268mV rms. If the compressor is also used, its ‘knee’ is at 100mV rms, which would allow a signal into the compressor of 718mV rms, which is less than the maximum signal level. The Fine Input Gain adjustment has a maximum attenuation of 3.5dB and no gain, whereas the Coarse Input Gain adjustment has a variable gain of up to +22.4dB and no attenuation. If the highest gain setting were used, then the maximum allowable input signal level at the MICFB pin would be 54mV rms. With the lowest gain setting (0dB), the maximum allowable input signal level at the MICFB pin would be 718mV rms. In some applications where there is a requirement for the system to operate with a significant overload on the MIC input (+20dB) an external limiter may be required to ensure that the signal input does not exceed the recommended CMX138A input levels. This can result in significant harmonic content (above 6kHz) that should be removed by suitable input filtering. 7.11.2 Receive Path Levels For the maximum undistorted signal out of the audio attenuator, the signal level at the output of the Analogue Routing block should not exceed +8.69dB, assuming both fine and coarse output attenuators are set to a gain of 0dB. In this case, there is no sub-audio signal to be added, so the maximum signal level remains at 838mV rms. If de-emphasis is used, an output signal at 300Hz will have three and a third times the amplitude of a signal at 1000Hz, so the signal level before de-emphasis should not exceed 251mV rms. If the expander is also used, its ‘knee’ is at 100mV rms, which would allow a signal into the expander of 158mV rms. The Fine Input Gain adjustment has a maximum attenuation of 3.5dB and no gain, whereas the Coarse Input Gain adjustment has a variable gain of up to +22.4dB and no attenuation. If the highest gain setting were used, then the maximum allowable input signal level at the DISCFB pin would be 12.0mV rms. With the lowest gain setting (0dB), the maximum allowable input signal level at the DISCFB pin would be 158mV rms. The signal level of +8.69dB (838mV rms) is an absolute maximum, which should not be exceeded anywhere in the signal processing chain if severe distortion is to be avoided. 2014 CML Microsystems Plc Page 34 D/138A/4 Audio Scrambler and Sub-Audio Signalling Processor 8 CMX138A C-BUS Register Summary Table 7 C-BUS Registers ADDR. (hex) $01 REGISTER W C-BUS RESET Word Size (bits) 0 $A7 $A8 $A9 $AA $AB $AC $AD $AE $AF W W R R W W AuxADC and TX MOD Mode AuxDAC Control/Data AuxADC Data Checksum 2 lo System Clk PLL Data System Clk REF reserved reserved reserved 16 16 16 16 16 16 $B0 $B1 $B2 $B3 $B4 $B5 $B6 $B8 $B9 $BB $BC $BD $BE $BF W W Analogue Input Gain Analogue Output Gain reserved reserved reserved AuxADC Threshold Data reserved Checksum 1 hi Checksum 1 lo reserved reserved reserved reserved reserved 16 16 $C0 $C1 $C2 $C3 $C5 $C6 $C7 $C8 $C9 $CA $CB $CC $CD $CE $CF W W W W R R Power-Down Control Mode Control Audio Control Tx In-band Tone Device ID Status reserved Programming reserved reserved Scrambler Inversion Frequency Tone Status Audio Tone Interrupt Mask reserved 16 16 16 16 16 16 W R R W W R W W 16 16 16 16 16 16 16 16 All other C-BUS addresses (including those not listed above) are either reserved for future use or allocated for production testing and must not be accessed in normal operation. 2014 CML Microsystems Plc Page 35 D/138A/4 Audio Scrambler and Sub-Audio Signalling Processor CMX138A 8.1.1 Interrupt Operation The CMX138A will issue an interrupt on the IRQN line when the IRQ bit (bit 15) of the Status register and the IRQ Mask bit (bit 15) are both set to 1. The IRQ bit is set when the state of the interrupt flag bits in the Status register change from a 0 to 1 and the corresponding mask bit(s) in the Interrupt Mask register is(are) set. Enabling an interrupt by setting a mask bit (01) after the corresponding Status register bit has already been set to 1 will also cause the IRQ bit to be set. All interrupt flag bits in the Status register, except the Programming Flag (bit 0), are cleared and the interrupt request is cleared following the command/address phase of a C-BUS read of the Status register. The Programming Flag bit is set to 1 only when it is permissible to write a new word to the Programming register. See: o o Status – $C6 read Interrupt Mask - $CE write 8.1.2 General Notes In normal operation, the most significant registers are: o o o o o Mode Control – $C1 write Status – $C6 read Analogue Input Gain - $B0 write Analogue Output Gain - $B1 write Audio Control – $C2 write. Setting the Mode register to either Rx or Tx will automatically increase the internal clock speed to its operational speed, whilst setting the Mode register to Idle will automatically return the internal clock to a lower (powersaving) speed. To access the Program Blocks (through the Programming register, $C8) the device MUST be in Idle mode. The CMX138A manages the internal clocks automatically to minimise power consumption, using the default values loaded in Program Block 3. 2014 CML Microsystems Plc Page 36 D/138A/4 01 w A7 w A8 w A9 r A9 r AA r AA r AB w AC w AD w AE w B0 w B1 w B2 w B3 w B4 r B5 w B6 w B7 w B8 r B9 r BA r BB r C0 w C1 w C2 w C3 w C5 r C6 r C7 w C8 w C9 r CA w CB w CC r CD w CE w CF w 2014 CML Microsystems Plc Page 37 ADC sel AuxADC Threshold Scrambler Freq Tone Status Audio Tone Interrupt Mask Test Control Programming 0 Tx MOD RamDAC x 12 0 0 x 11 0 0 0 0 0 0 MOD output gain 0 9 0 0 8 Rx In 0 0 IRQ x In-Band Tone Detected 0 0 0 0 Rx In 0 Prgram Block Address x 0 IRQ CTCSS CTCSS DCS x DCS 0 x x 0 7 x 5 0 4 3 MIC Input gain MIC-MOD bypass gain Aux ADC Threshold data DISCsel 2 0 Rx / Tx select 0 0 RampUP RampDN 1 x Program Block Data x BIAS ena x x Detected DCS or CTCSS code Audio Tone Frequency 0 0 0 0 res x 0 x Program Program reset Protect XTAL dis DISC by MIC by 0 0 0 0 Sub Audio mode Idle / Rx / Tx Sub Audio tone number - CTCSS / DCS / none 0 0 0 0 0 0 0 0 Ref CLK divider System CLK1 Feedback divider Scrambler Inversion Frequency AuxADC x AuxADC 0 0 0 power-on checksum 1 lo power-on checksum 1 hi DISC-AUDIO bypass gain 0 6 Aux ADC Av mode Aux ADC ip select Aux DAC data Aux ADC data power-on checksum 2 lo DISC Input gain OP slew rate 0 0 x 10 DISC amp MIC amp Input ena AUD gain MOD gain AUD ena 0 MOD ena 0 Audio 0 0 0 0 In-Band modes scramble compand emphasis 12k5 25k hpf CTCSS Invert 0 0 0 Tx In-band tone Hi / Lo AUDIO oupput gain 0 Power Down Ctrl Mode Control Audio Control Tx In-band Tone Device ID Status 0 x 13 System CLK1 VCO divider op select ENA CLK ENA DIV bypass IP sel Analog Input Gain Analog Output Gain pon checksum 1 hi pon checksum 1 lo 0 0 14 9.1 Threshold Status 0 ENA 15 9 pon checksum 2 lo Sys Clk PLL Data System Clk REF C-BUS Reset AuxADC, TX mode AuxDAC Ctrl Data AuxADC 1 Data Audio Scrambler and Sub-Audio Signalling Processor CMX138A Configuration Guide C-BUS Register Details D/138A/4 Audio Scrambler and Sub-Audio Signalling Processor CMX138A The detailed descriptions of the C-BUS registers are presented in numerical order and should be read in conjunction with the relevant functional descriptions. 9.1.1 Reset Operations A reset is automatically performed when power is applied to the CMX138A. A reset can be issued as a CBUS command, either as a General Reset command ($01), or by setting the appropriate bit (b5) in the Powerdown Control register ($C0). In the latter case, an option exists to protect the values held in the Program Block (which is accessed via the Programming register, $C8). The action of each reset type is shown in the table below: Table 8 Reset Operations Reset type 1 Power On General Reset (C-BUS $01) Reset 3 (C-BUS $C0 b5) Reset 4 (C-BUS $C0 b5) 2 Protect bit ($C0 b4) state Program Block state cleared by h/w default cleared by h/w default 0 default 1 protected Following a Reset operation, the internal checksum values are made available in the $AA, $B8 and $B9 registers. The device ID is available in $C5. The status of the Power-Down register, $C0, can be read back in $C4 to ensure that C-BUS communications are operational. 9.1.2 General Reset - $01 write The General Reset command has no data attached to it. It puts the device registers into the states listed below. A power-on reset performs the same action. 2014 CML Microsystems Plc Page 38 D/138A/4 Audio Scrambler and Sub-Audio Signalling Processor ADDR. REGISTER CMX138A 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 $A7 $A8 $A9 $AA $AB $AC $AD $AE $AF AuxADC/TX MOD Mode AuxDAC Control/Data AuxADC data power-on checksum 2 lo System Clk PLL Data System Clk Ref reserved reserved reserved 0 0 0 c 0 0 0 0 0 0 0 0 c 0 0 0 0 0 0 0 0 c 0 0 0 0 0 0 0 0 c 0 0 0 0 0 0 0 0 c 0 0 0 0 0 0 0 0 c 0 0 0 0 0 0 0 0 c 0 0 0 0 0 0 0 0 c 0 0 0 0 0 0 0 0 c 0 0 0 0 0 0 0 0 c 0 0 0 0 0 0 0 0 c 0 0 0 0 0 0 0 0 c 0 0 0 0 0 0 0 0 c 0 0 0 0 0 0 0 0 c 0 0 0 0 0 0 0 0 c 0 0 0 0 0 0 0 0 c 0 0 0 0 0 $B0 $B1 $B2 $B3 $B4 $B5 $B6 $B8 $B9 $BB $BC $BD $BE $BF Analogue Input Gain Analogue Output Gain reserved reserved reserved AuxADC Threshold Data reserved power-on checksum 1 hi power-on checksum 1 lo reserved reserved reserved reserved reserved 0 0 0 0 0 0 0 c c 0 0 0 0 0 0 0 0 0 0 0 0 c c 0 0 0 0 0 0 0 0 0 0 0 0 c c 0 0 0 0 0 0 0 0 0 0 0 0 c c 0 0 0 0 0 0 0 0 0 0 0 0 c c 0 0 0 0 0 0 0 0 0 0 0 0 c c 0 0 0 0 0 0 0 0 0 0 0 0 c c 0 0 0 0 0 0 0 0 0 0 0 0 c c 0 0 0 0 0 0 0 0 0 0 0 0 c c 0 0 0 0 0 0 0 0 0 0 0 0 c c 0 0 0 0 0 0 0 0 0 0 0 0 c c 0 0 0 0 0 0 0 0 0 0 0 0 c c 0 0 0 0 0 0 0 0 0 0 0 0 c c 0 0 0 0 0 0 0 0 0 0 0 0 c c 0 0 0 0 0 0 0 0 0 0 0 0 c c 0 0 0 0 0 0 0 0 0 0 0 0 c c 0 0 0 0 0 $C0 $C1 $C2 $C3 $C5 $C6 $C7 $C8 $C9 $CA $CB $CC $CD $CE $CF PowerDown Control Mode Control Audio Control Tx In-band Tone product identification Status reserved Programming reserved reserved Scrambler Inv. Frequency Tone Status Audio Tone Interrupt Mask reserved 0 0 0 0 c 0 0 0 0 0 0 0 0 0 0 0 0 0 0 c 0 0 0 0 0 0 0 0 0 0 0 0 0 0 c 0 0 0 0 0 0 0 0 0 0 0 0 0 0 c 0 0 0 0 0 0 0 0 0 0 0 0 0 0 c 0 0 0 0 0 0 0 0 0 0 0 0 0 0 c 0 0 0 0 0 0 0 0 0 0 0 0 0 0 c 0 0 0 0 0 0 0 0 0 0 0 0 0 0 c 0 0 0 0 0 0 0 0 0 0 0 0 0 0 c 0 0 0 0 0 0 0 0 0 0 0 0 0 0 c 0 0 0 0 0 0 0 0 0 0 0 0 0 0 c 0 0 0 0 0 0 0 0 0 0 0 0 0 0 c 0 0 0 0 0 0 0 0 0 0 0 0 0 0 c 0 0 0 0 0 0 0 0 0 0 0 0 0 0 c 0 0 0 0 0 0 0 0 0 0 0 0 0 0 c 0 0 0 0 0 0 0 0 0 0 0 0 0 0 c 0 0 0 0 0 0 0 0 0 0 Notes: 'c' is the power-on checksum or product identification, returned in registers $AA, $B8, $B9 and $C5. Any registers not mentioned above are undefined. 2014 CML Microsystems Plc Page 39 D/138A/4 Audio Scrambler and Sub-Audio Signalling Processor 9.1.3 CMX138A AuxADC and TX MOD Mode - $A7 write 15 14 0 0 b15-14 13 12 11 10 9 8 7 0 0 0 0 0 b13 1 1 0 0 b12 1 0 1 0 Tx MOD Mode 6 5 AuxADC AV Mode 4 3 2 AuxADC I/P Select 1 0 RU RD 1 0 reserved, clear to 0 Tx MOD mode output In-band + Sub-Audio reserved reserved bias For normal operation, these bits should both be set to 1 in both Rx and Tx modes. b11-7 b1 b0 reserved, clear to 0 b5 1 0 1 0 AuxADC Averaging Mode reserved reserved rolling average, uses Program Block 3.0 value No averaging b4 1 1 1 1 0 0 0 0 b3 1 1 0 0 1 1 0 0 b2 1 0 1 0 1 0 1 0 MOD Ramping Up MOD Ramping Down 9.1.4 AuxADC Input Select reserved reserved reserved reserved reserved reserved AuxADC off 0 = off 0 = off 1 = enable 1 = enable AuxDAC Control/Data - $A8 write 15 14 13 ENA 0 0 b15 b14 b13 b12 b6 1 1 0 0 12 RAM DAC 11 10 0 0 enable Aux DAC reserved reserved RAMDAC enable 9 0 = disable 8 7 6 5 4 3 2 AUX DAC data / RAMDAC control 1 = enable 0 = AuxDAC operates normally 1 = AuxDAC operates as a RAMDAC1. Data in b0-6 controls the RAMDAC functions. b11 reserved b10 reserved b9 – b0 AuxDAC data (unsigned) 1 Do NOT write to directly to AuxDAC whilst the RAMDAC is in operation. RAMDAC is only available when in Tx mode. 2014 CML Microsystems Plc Page 40 D/138A/4 Audio Scrambler and Sub-Audio Signalling Processor CMX138A Note: when $A8 b12 is set to 1, writing data to this register controls the RAMDAC settings. Writing to AuxDAC whilst the RAMDAC is still ramping may cause un-intended operation. In this mode b9 to b0 perform the following functions: b9 b8 b7 b6 reserved, clear to 0 reserved, clear to 0 reserved, clear to 0 RAMDAC RAM access, 0 resets the internal RAMDAC address pointer. b5 0 0 0 0 1 1 1 1 b2 b1 b0 Scan direction: Autocycle RAMDAC start b4 0 0 1 1 0 0 1 1 RAMDAC Scan Time Divider Time (ms) 1024 10.50 512 5.25 256 2.63 128 1.31 64 0.66 32 0.33 16 0.16 8 0.08 b3 0 1 0 1 0 1 0 1 0 = ramp down 0 = disable 0 = stop 1 = ramp up 1 = continuous ramp up/down 1 = start RAMDAC ramping Before using the RAMDAC, the AuxDAC must be powered up by writing $8000, then after the C-BUS latency period of 250µs: To initiate a RAMDAC ramp up write: $9005. To initiate a RAMDAC ramp down, write: $9001. To place AuxDAC back into powersave, it must be written to explicitly. Do NOT change IDLE/Rx/Tx mode whilst the RAMDAC is still ramping. 9.1.5 AuxADC Data - $A9 read 15 14 Threshold status 13 12 11 10 x x x x 9 8 7 6 5 4 3 2 1 0 AUX ADC Data b15, b14 Threshold Status b15 b14 =1 =0 =1 =0 signal is above the high threshold signal is below the high threshold signal is below the low threshold signal is above the low threshold b13 reserved b12 reserved b11 reserved b10 reserved b9 –b0 AuxADC data or last reading (unsigned) - $000 = DVDD, $3FF = DVSS 2014 CML Microsystems Plc Page 41 D/138A/4 Audio Scrambler and Sub-Audio Signalling Processor 9.1.6 15 System Clk PLL Data - $AB write 14 13 12 11 VCO OP Divide Ratio <5-0> b15-b10 b9-b0 9.1.7 15 10 8 7 6 5 4 3 2 PLL Feedback Divide Ratio <9-0> 1 0 System Clk REF - $AC write 10 9 OP Slew b15,12,11 Clk output divider source SYSCLK Source Xtal Sys Clk PLL Main PLL Reserved: <do not use> Powersave PLL Powersave Output Divider Output Slew Rate b10 0 0 1 b8-b0 9 divide the selected output clock source by the value in these bits, to generate the System Clk output. Divide by 64 is selected by setting these bits to '0'. divide System Clk PLL VCO clock by the value set in these bits as feedback to the PLL phase detector (PD); when the PLL is stable, this will be the same frequency as the internal reference as set by b8-b0 of the System Clk Reference and Source Configuration register ($AC). Divide by 1024 is selected by setting these bits to '0'. 14 13 12 11 Select & PS Clock Sources b14 b13 b10-9 CMX138A 8 7 b15 0 1 1 1 6 5 4 3 2 Ref Clock Divide Ratio <8-0> b12 x 0 0 1 0 = powersave 0 = powersave / bypass b9 0 1 X 1 0 b11 x 0 1 x 1 = enabled 1 = enabled Output Slew Rate normal slow fast Reference Clk divide value. Divide by 512 is selected by setting these bits to '0'. Note that on power-up, or after a General Reset, the default settings will not provide a SYSCLK output. To set SYSCLK to the XTAL frequency it is first necessary to write a '1' to bit 10 of the System CLK PLL data register ($AB) and also write a '1' to bit 13 of the System CLK REF register ($AC). This will set SYSCLK to the XTAL frequency and also make the signal available on the SYSCLK pin. 2014 CML Microsystems Plc Page 42 D/138A/4 Audio Scrambler and Sub-Audio Signalling Processor 9.1.8 CMX138A Analogue Input Gain - $B0 write 15 14 13 12 11 10 8 7 6 5 0 0 0 0 0 DISC Input Gain 0 0 DISC select 9 4 3 2 MIC Input Gain 1 0 Rx/Tx b15 to 11 reserved – clear to 0 b10 b9 b8 DISC Input Gain b4 b3 b2 MIC Input Gain 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0dB 3.2dB 6.4dB 9.6dB 12.8dB 16.0dB 19.2dB 22.4dB b7 to 6 are reserved - clear to 0 b5 DISCselect: 0 – select DISCN1 input only 1 – select DISCN2 input (does NOT disconnect DISCN1 input) b1 b0 Rx/Tx 0 0 1 1 0 1 0 1 Idle Idle Rx Tx Note that b1, b0 of this register control the routing of the signal to the processing blocks, whereas b1, b0 of the Mode register ($C1) control the processing functions of the device. BOTH registers MUST be set appropriately for the device to operate correctly in Rx or Tx modes. 2014 CML Microsystems Plc Page 43 D/138A/4 Audio Scrambler and Sub-Audio Signalling Processor 9.1.9 CMX138A Analogue Output Gain - $B1 write 15 14 13 AUDIO Output Gain 12 11 10 MOD Output Gain b15 b12 0 0 0 0 1 1 1 1 b9 b5 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 b8 b4 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 9 b14 b11 0 0 1 1 0 0 1 1 b7 b3 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 8 7 6 DISC-AUDIO Bypass b13 b10 0 1 0 1 0 1 0 1 5 4 3 2 MIC-MOD Bypass 1 0 0 0 AUDIO Output Gain MOD Output Gain mute -19.2dB -16.0dB -12.8B -9.6dB -6.4dB -3.2dB 0dB b6 b2 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 DISC-AUDIO Bypass Gain MIC-MOD Bypass Gain mute -22.4dB -19.2dB -16.0dB -12.8dB -9.6dB -6.4dB -3.2dB 0dB 3.2dB 6.4dB 9.6B 12.8dB 16.0dB 19.2dB 22.4dB Bits 1, 0 are reserved – clear to 0 2014 CML Microsystems Plc Page 44 D/138A/4 Audio Scrambler and Sub-Audio Signalling Processor CMX138A 9.1.10 AuxADC Threshold Data - $B5 write 15 14 ADC sel Hi /Lo 13 12 11 10 0 0 0 0 b15 AuxADC select b14 high/low select b13 reserved b12 reserved b11 reserved b10 reserved b9 –b0 threshold data 9 8 7 6 5 4 3 2 1 0 Aux ADC Threshold Data 0 = AuxADC 0 = low threshold 0 0 0 0 1 = reserved – do not use 1 = high threshold 9.1.11 Power Down Control - $C0 write 15 DISC Input b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 14 MIC Input 13 Input ENA 12 AUD Gain 11 MOD Gain 10 AUD ENA 9 0 8 MOD ENA 7 0 6 5 BIAS Reset 4 Prot 3 2 1 XTAL DISC MIC DIS bypass bypass 0 0 DISC Input/Gain block enable 0 = off 1 = enabled MIC Input/Gain block enable 0 = off 1 = enabled Input amp enable 0 = off 1 = enabled AUD Gain block enable 0 = off 1 = enabled MOD Gain block enable 0 = off 1 = enabled AUD Output enable 0 = off 1 = enabled reserved must be cleared to 0 MOD Output enable 0 = off 1 = enabled reserved must be cleared to 0 BIAS block enable 0 = off 1 = enabled Reset 0 = normal 1 = reset/powersave Program Block Protect 0 = normal 1 = protected If cleared, the Program Blocks will be initialised on Power on or Reset. If set, then the Program Blocks will retain their previous contents. XTAL disable 0 = enabled 1 = disabled/powersave Setting this bit effectively stops all signal processing within the device. DISC bypass gain 0 = disabled / powersave 1 =enabled MIC bypass gain 0 = disabled / powersave 1 =enabled reserved must be cleared to 0 Note: Care should be taken when writing to b5 and b3. These are automatically programmed to an operational state following a power-on (ie: all 0’s). Writing a 1 to either b5 or b3 will effectively cause the device to cease all processing activity, including responding to other C-BUS commands (except General Reset, $01). When b5 is set, the device will be held in reset and all signal processing will cease (including AuxADC operation. When b3 is set the Xtal is disabled. When b3 is subsequently cleared, it may take some time for the clock signal to become stable, hence care should be taken in using this feature. 2014 CML Microsystems Plc Page 45 D/138A/4 Audio Scrambler and Sub-Audio Signalling Processor CMX138A 9.1.12 Mode Control – $C1 write 15 14 13 12 11 0 Audio 0 0 0 b15 b14 b13-11 b10 b9 b8,7 b6 b5 b4-2 b1, b0 10 9 In-band modes reserved Audio processing enable reserved Audio Tone enable In-band Tone enable reserved CTCSS enable DCS enable reserved Operational Mode 8 7 0 0 0 0 = off 0 0 = off 0 = off 0 0 = off 0 = off 0 00 IDLE 01 Rx 10 Tx 11 reserved 6 5 Sub Audio Mode 4 3 2 0 0 0 1 0 Idle/Rx/Tx 1 = enabled 1 = enabled 1 = enabled 1 = enabled 1 = enabled Changes to the settings of the bits in this register are implemented as soon as they are received over the C-BUS (note that the C-BUS has a potential latency of up to 250μs). In Tx mode, it is only permissible to select ONE of the following at any time: Audio Tone In-band Tone It is essential that changes to the Program Register and the Audio Control register are completed before entering Rx or Tx mode. It is possible, however, to change the CTCSS tone whilst in Tx mode if the CTCSS enable bit is set in the Mode Control Register. DCS codes and custom CTCSS tones cannot be updated in Tx mode. The following other registers or bits can be changed as appropriate (Note: not all possible changes are appropriate), whilst the device is in Tx or Rx mode: Analogue Input Gain - $B0 write AuxADC and TX MOD Mode - $A7 write Analogue Output Gain - $B1 write Power Down Control - $C0 write Tx In-band Tone - $C3 write Audio Tone - $CD: 16-bit write Scrambler Inversion Frequency – $CB write Interrupt Mask - $CE write 9.1.13 Audio Control – $C2 write 15 scramble 14 13 comp emph 12 11 10 12k5 25k hpf b15 Audio Scrambling enable b14 Audio Compandor enable b13 Audio Pre/De-emphasis b12 Audio 12.5kHz Filter enable b11 Audio 25kHz Filter enable b10 Audio 300Hz HPF enable b9, b8 CTCSS Phase 2014 CML Microsystems Plc 9 8 CTCSS Phase 7 6 5 4 3 2 1 0 Sub Audio Tone Number: CTCSS/DCS/none 0 = off 1 = enabled 0 = off 1 = enabled 0 = off 1 = enabled 0 = off 1 = enabled 0 = off 1 = enabled 0 = off 1 = enabled 00 0 degrees (normal) 01 120 degrees 10 180 degrees Page 46 D/138A/4 Audio Scrambler and Sub-Audio Signalling Processor CMX138A 11 b7 – b0 240 degrees Sub-Audio Tone number (dec) 0 1 to 83 84 101 to 183 184 200 201 to 251 252 253 254 255 no tone select DCS code 1 to 83 select User Defined DCS code select DCS tone 1 to 83 inverted select User Defined DCS code inverted select Tone Clone™ mode select CTCSS tone 1 to 51 select User Defined CTCSS tone select XTCSS maintenance tone select DCS turn-off tone Invalid tone See Table 3. Selecting the ‘DCS turn-off tone (254)’ during DCS transmit will cause the DCS turn off tone to be transmitted. CTCSS does not need to be enabled in the Mode Control register to receive the ‘DCS turn off tone’. TM If the Tone Clone mode is selected this allows the device in Rx to non-predictively detect any CTCSS frequency in the range of valid tones, the received tone number will be reported in the Tone Status register ($CC) and the CTCSS decoder detection bandwidth should be set to its lowest value (P2.1). 9.1.14 Tx In-band Tone - $C3 write 15 14 13 12 Tx In-band tone b15-11 b10-6 b5-0 11 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 In-band Tone, see Table 6 In-band Tone in the Datasheet. reserved, clear to '0'. 0. 9.1.15 Status – $C6 read 15 14 13 12 IRQ 0 Rx in 0 11 10 CTCSS DCS 9 0 8 Aux ADC 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 PRG b15 IRQ b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 Changes in the Status register will cause this bit to be set to 1 if the corresponding interrupt mask bit is enabled. An interrupt request is issued on the IRQN pin when this bit is 1 and the IRQ MASK bit (b15 of Interrupt Mask register, $CE) is set to 1. reserved In-band Tone event The Tone Status register $CC should be read to determine the exact cause. Cleared to 0 in Tx. reserved CTCSS event A CTCSS code has been detected or ceased. The Tone Status register $CC should be read to determine the exact cause. Cleared to 0 in Tx. DCS event A DCS code has been detected or ceased. The Tone Status register $CC should be read to determine the exact cause. Cleared to 0 in Tx. reserved AuxADC Threshold change AUX ADC signal has just gone above the high threshold or has just gone below the low threshold The AuxADC data register $A9 should be read to determine the exact cause. reserved reserved reserved reserved 2014 CML Microsystems Plc Page 47 D/138A/4 Audio Scrambler and Sub-Audio Signalling Processor b3 b2 b1 b0 CMX138A reserved reserved reserved Program Register Ready When set to 1, this bit indicates that the Program Register, $C8 is available for the host to write to it. Cleared by writing to the Programming Register, $C8. Bits 2 to 15 of the Status register are cleared to '0' after the Status register is read. Detection of the DCS turn off tone and removal of the DCS code are both flagged as DCS events in the Status register, not as CTCSS events. The data in this register is not valid if bit 5 of the Power-Down Control register, $C0 is set to 1. 9.1.16 Programming – $C8 write 15 14 13 12 11 10 9 8 7 Program Block Address 6 5 4 3 2 1 0 4 3 2 1 0 Program Block Data See section 9.2 for a definition of programming block operation. 9.1.17 Scrambler Inversion Frequency – $CB write 15 14 0 0 13 12 11 10 9 8 7 6 5 Scrambler Inversion Frequency Bits 13-0 set the inversion frequency of the audio scrambler. By default this is set to 3300Hz with the value $2333. The value of this field can be calculated by: V= ( finv / 0.7324 ) *2. Other common values are: finv 3000 3100 3200 3300 3400 $CB register (hex) 2000 2111 2222 default 2333 2444 Note that this register can be changed whilst in Rx or Tx mode. 9.1.18 Tone Status - $CC read 15 14 13 12 Tone Detected 11 10 9 8 x x x 7 6 5 4 3 2 1 0 Detected DCS or CTCSS code This word holds the current status of the CMX138A sub-audio and In-band tone sections. This word should be read by the host after an interrupt caused by a DCS, CTCSS or In-band tone event. In Tx mode this register will be cleared to '0'. b15-11 Detected In-band frequency; identifies the frequency by its position in Table 6 In-band Tone. A change in the state of bits 15 to 11 will cause bit 13 of the Status register ($C6), ‘In-band State Change’, to be set to '1'. b10-8 reserved b7–0 Detected DCS or CTCSS code, identifies the detected sub-audio tone by its position in Table 3 DCS Codes and CTCSS Tones. 2014 CML Microsystems Plc Page 48 D/138A/4 Audio Scrambler and Sub-Audio Signalling Processor CMX138A 9.1.19 Audio Tone - $CD: 16-bit write 15 14 13 12 11 10 9 8 7 6 5 4 0 0 0 0 Audio Tone 0 0 1 0 Audio Tone Level 0 1 0 0 Voice Level 0 1 1 0 Output1 Fine Gain (also see P4.2) 1 0 0 0 Output2 Fine Gain (also see P4.3) 1 0 1 0 Tx Voice level multiplier 1 0 1 1 reserved 1 1 0 0 reserved 1 1 0 1 Tx Sub-audio level 1 1 1 0 reserved 1 1 1 1 reserved 3 2 1 0 All other values reserved Bits 15-12 determine how the remaining bit fields will be interpreted: 0000b: When the appropriate bits of the Mode Control register ($C1, b10) are set an audio tone will be generated with the frequency set by bits (11-0) of this register in accordance with the formula below. If bits 11-0 are programmed with '0' no tone (i.e. Vbias) will be generated when the Audio Tone is enabled. Frequency = Audio Tone (i.e. 1Hz per LSB) The Audio Tone frequency should only be set to generate frequencies from 300Hz to 3000Hz. The host should disable other Audio band signalling and set the correct audio routing before generating an audio tone and re-enable signalling and audio routing on completion of the audio tone. The timing of intervals between these actions is controlled by the host µC. This register may be written to whilst the audio tone is being generated, any change in frequency will take place after the end of the C-BUS write to this register. This allows complex sequences (e.g. ring or alert tunes) to be generated for the local speaker (Tx or Rx via the AUDIO pin) or transmitted signal (Tx via the MOD pins). 0010b: The Audio Tone Level may be attenuated by the value written to b11-0. The default value of $FFF is equivalent to x1. Note that this adjustment will also affect the In-Band tone generator. This register operates in parallel with P1.0, but allows the level to be adjusted “on-the-fly” without needing to drop back into Idle mode. 0100b: In Rx mode, the Voice Level may be attenuated by the value written to b11-0. The default value of $FFF is equivalent to x1. Note that this adjustment will only affect signals in the Voice processing path as enabled by Mode Control register ($C1, b14) in Rx. This allows the Voice level to be adjusted “on-the-fly” and in conjunction with the Audio Output attenuator ($B0, b3-0), offers a “fine gain” volume control. Approximate values for 0.2dB steps are shown in Table 9. 2014 CML Microsystems Plc Page 49 D/138A/4 Audio Scrambler and Sub-Audio Signalling Processor b11-0 Value (hex) FFF F90 F40 EE0 EA0 E50 DE0 DA0 CMX138A Attenuation (dB) 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 b11-0 Value (hex) D50 CF0 CB0 C60 C20 BF0 BA0 B60 Attenuation (dB) 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 Table 9 Voice Level Attenuation 0110b: The Output1 (AUDIO) level may be attenuated by the value written to b11-0. The default value of $FFF is equivalent to x1. This register operates in parallel with P4.2, but allows the level to be adjusted “on-the-fly” without needing to drop back into Idle mode. b11-0 Value (hex) FFF FA2 F47 EEE E97 E42 DEF D9D D4E D01 Attenuation (dB) 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 b11-0 Value (hex) CB5 C6B C22 BDC B97 B53 B11 AD1 AB1 Attenuation (dB) 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.5 Table 10 Voice Level Attenuation Gain = 20 x log(OG / 4095)dB. OG is the unsigned integer value in the ‘Output Fine Gain’ field. (Please note that differences between the calculated values and measured levels are due to truncation of the programmed values). 1000b: The Output2 (MOD) level may be attenuated by the value written to b11-0. The default value of $FFF is equivalent to x1. This register operates in parallel with P4.3, but allows the level to be adjusted “on-the-fly” without needing to drop back into Idle mode. Also, see Table 10. 1010b: This sets the value of the Tx Voice level multiplier at the output of the Tx limiter stage. This can be useful in situations where it has been necessary to use a small limiting threshold and still maintain an acceptable level at the MOD outputs. The default state is x1. b2 b1 b0 Tx Voice Level Multiplier 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 x1 x2 x4 x8 x16 x32 1101b: 2014 CML Microsystems Plc Page 50 D/138A/4 Audio Scrambler and Sub-Audio Signalling Processor CMX138A The Sub- Audio Tone Level may be attenuated by the value written to b11-0. The default value of $FFF is equivalent to x1. This register operates in parallel with P2.0, but allows the level to be adjusted “on-the-fly” without needing to drop back into Idle mode. 2014 CML Microsystems Plc Page 51 D/138A/4 Audio Scrambler and Sub-Audio Signalling Processor CMX138A 9.1.20 Interrupt Mask - $CE write 15 14 13 12 IRQ 0 Rx in 0 Bit 15 14 13 12 11 10 8 7 6 5 4 3 2 1 0 Value 1 0 0 1 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 1 0 11 10 CTCSS DCS 9 0 8 Aux ADC 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 PRG Function Enable selected interrupts Disable all interrupts (IRQN pin not activated) reserved Enable interrupt when a change to a In-band tone is detected Disabled reserved Enable interrupt when a change to CTCSS tone is detected Disabled Enable interrupt on a change in the detect status of the DCS decoder Disabled Enable interrupt when the AuxADC status changes Disabled reserved reserved reserved reserved reserved reserved reserved Enable interrupt when Prog Flag bit of the Status register changes from '0' to '1' (see Programming register $C8) Disabled To minimise the processing load on the host µC, it is advisable to only enable the interrupts that are relevant for any given operational mode. 9.1.21 Reserved - $CF write This C-BUS address is allocated for production testing and must not be accessed in normal operation. 2014 CML Microsystems Plc Page 52 D/138A/4 Audio Scrambler and Sub-Audio Signalling Processor 9.2 CMX138A Programming Register Operation In order to support radio systems that may not comply with the default settings of the CMX138A, a set of program register blocks is available to customise the features of the device. It is envisaged that these blocks will only be written to following a power-on of the device and hence can only be accessed while the device is in Idle mode. Access to these blocks is via the Programming register ($C8). All other interrupt sources should be disabled while loading the program register blocks. The Programming register should only be written to when the Programming Flag bit (bit 0) of the Status register is set to 1 and the Rx and Tx modes are disabled (bits 0 and 1 of the Mode Control register both '0'). The Programming Flag is cleared when the Programming register is written to by the host. When the corresponding programming action has been completed (normally within 250µs) the CMX138A will set the flag back to 1 to indicate that it is now safe to write the next programming value. The Programming register must not be written to while the Programming Flag bit is 0. Programming is performed by writing a sequence of 16-bit words to the Programming register in the order shown in the following tables. Writing data to the Programming register MUST be performed in the order shown for each of the blocks, however the order in which the blocks are written is not critical. If later words in a block do not require updating the user may stop programming that block when the last change has been performed. e.g: If only 'Fine Output Gain 1' needs to be changed the host will need to write to P4.0, P4.1 and P4.2 only. The user must not exceed the defined word counts for each block. P4.8 is allocated for production testing and must not be accessed in normal operation. The high order bits of each word define which block the word belongs to, and if it is the first word of that block: Bit 15 1 0 x x x x x 2014 CML Microsystems Plc Bit 14 x x 1 1 1 1 0 Bit 13 x x 0 0 1 1 Bit 12 x x 0 1 0 1 Write to Bit 11 – Bit 0 st 1 data for each block nd 2 and following data Write to block 0 (12 bit words) Write to block 1 (12 bit words) Write to block 2 (12 bit words) Write to block 3 (12 bit words) block 4 (14 bit words) Page 53 D/138A/4 Audio Scrambler and Sub-Audio Signalling Processor 9.2.1 Bit: 9.2.2 CMX138A Program Block 0 – reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 0 Program Block 1 – In-band Tone Setup: Bit: 15 14 13 12 P1.0 1 1 0 1 P1.1 0 1 0 1 P1.2 0 1 0 1 Default values: $C8 (P1.0) P1.0: P1.1: P1.2 11 10 9 0 Audio Band Tones Tx Level 0 0 Emph In-band Tone Detect Bandwidth Audio Band Detect Threshold User Programmable In-band Tone $800 $009 $942 (1750Hz) Audio Band Tones Tx Level Bit: 15 14 13 12 P1.0 1 1 0 1 11 10 9 8 7 6 5 4 3 2 1 Audio Band Tones/data Tx Level 0 Emph Bits 11 (MSB) to 1 (LSB) set the transmitted In-band tone, Audio Tone (pk-pk) with a resolution of AVDD/2048 per LSB (1.611mV per LSB at AVDD =3.3V). Valid range for this value is 0 to 1536 – use with care as higher values may result in signal “clipping”. Bit 0 controls In-band tone de-emphasis. When In-band tones are enabled in the Mode Control register ($C1), de/pre-emphasis is enabled in the Audio Control register ($C2) and this bit (b0) is set to '1'; signals going to the In-band tone detector are de-emphasised in accordance with Figure 7 of the datasheet. This combination of settings should only be used in Rx mode. If this bit is set, then in Tx mode, the user is advised to clear the de/pre-emphasis bit in the Audio Control register ($C2). $C8 (P1.1) Bit: P1.1 15 0 In-band tone Detect Bandwidth and Audio Band Detect Threshold 14 1 13 0 12 1 11 0 10 9 0 8 7 6 5 4 3 2 1 0 In-band Tone Detect Bandwidth Audio Band Detect Threshold The ‘detect threshold’ bits (bits 9 to 4) set the minimum In-band tone signal level that will be detected. The levels are set according to the formula: Minimum Level = Detect Threshold 3.993mV rms at AVDD = 3.3V The In-band tone detected bandwidth is set in accordance with the following table: Bit 3 1 1 Recommended for EEA 1 1 $C8 (P1.2) Bit: P1.2 Bit 2 0 0 0 0 Bit 1 0 0 1 1 BANDWIDTH Will Decode Will Not Decode ±1.1% ±2.4% ±1.3% ±2.7% ±1.6% ±2.9% ±1.8% ±3.2% Bit 0 0 1 0 1 User-Programmable In-band Tone 15 14 13 12 0 1 0 1 11 10 9 8 7 6 5 4 3 2 1 0 Programmable In-band Tone N (see below) R (see below) This word set the programmable In-band tone used in transmit and receive. The frequency is set in bits 11-0 according to the formula: 2014 CML Microsystems Plc Page 54 D/138A/4 Audio Scrambler and Sub-Audio Signalling Processor CMX138A N = Integer part of (0.042666 x frequency) R = (0.042666 x frequency - N) x 6000 / frequency (round to nearest integer). Example: For 1010Hz, N = 43, R = 1. The programmed tones must only be set to frequencies from 288Hz to 3000Hz (R MUST NOT exceed 31 decimal). 9.2.3 Program Block 2 – CTCSS and DCS Setup Bit: 15 14 13 12 P2.0 1 1 1 0 P2.1 0 1 1 0 P2.2 0 1 1 0 User Defined DCS Code bits 11 – 0 P2.3 0 1 1 0 User Defined DCS Code bits 23/22 – 12 P2.4 0 1 1 0 P2.5 0 1 1 0 P2.6 0 1 1 0 Default values: $C8 (P2.0) P2.0 P2.1 P2.2 11 10 9 8 7 6 5 4 3 2 1 0 CTCSS and DCS Tx Level DCS 24 0 CTCSS Detect Bandwidth CTCSS and DCS Detect Threshold User Defined CTCSS code N User Defined CTCSS Code R Sub-audio Drop-out Time 0 reserved $800 $008 $000 P2.3 P2.4 P2.5 P2.6 $000 $000 $000 $000 CTCSS and DCS TX LEVEL Bit: 15 14 13 12 P2.0 1 1 1 0 11 10 9 8 7 6 5 4 3 2 1 0 CTCSS and DCS Level Bits 11 (MSB) to 0 (LSB) set the transmitted CTCSS or DCS sub-audio signal level (pk-pk) with a resolution of AVDD/16384 per LSB (0.201mV per LSB at AVDD =3.3V, giving a range 0 to 824.8mV pk-pk). $C8 (P2.1) Bit: P2.1 15 0 CTCSS TONE BW AND LEVEL 14 1 13 1 12 11 0 DCS 24 10 0 9 8 7 6 5 4 CTCSS and DCS Detect Threshold 3 2 1 0 CTCSS Detect Bandwidth Bit 11, DCS 24: When this bit is set to ‘1’ 24 bit DCS codes are transmitted and decoded. When this bit is cleared to '0' 23 bit codes are used. The ‘detect threshold’ bits (bits 9 to 4) set the minimum CTCSS or DCS signal level that will be detected. The levels are set according to the formula: CTCSS Minimum Level = Detect Threshold 2.2mV rms at AVDD DCS Minimum Level = Detect Threshold 6.22mV pk-pk at AVDD 2014 CML Microsystems Plc Page 55 = 3.3V or = 3.3V D/138A/4 Audio Scrambler and Sub-Audio Signalling Processor CMX138A The CTCSS detected tone bandwidth is set in accordance with the following table: Bit 3 Bit 2 Bit 1 Bit 0 0 0 1 1 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 Recommended for use with TM split tones and Tone Clone Recommended for CTCSS $C8 (P2.2-3) BANDWIDTH Will Decode Will Not Decode ±0.5% ±0.8% ±1.1% ±1.3% ±1.6% ±1.8% ±1.8% ±2.1% ±2.4% ±2.7% ±2.9% ±3.2% DCS CODE (LOWER) and DCS CODE (UPPER) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 P2.2 0 1 1 0 DCS Data (bits 11-0) P2.3 0 1 1 0 DCS Data (bits 23/22-12) 3 2 1 0 These words set the User Defined DCS code to be transmitted or searched for. The least significant bit (bit 0) of the DCS code is transmitted or compared first and the most significant bit is transmitted or compared last. Note that DCS Data bit 23 is only used when bit 11 (DCS 24) of P2.1 is set to ‘1’. $C8 (P2.4) User Defined CTCSS Tone Bit: 15 14 13 12 P2.4 0 1 1 0 11 10 9 8 7 6 5 User Defined CTCSS code N 4 3 2 1 0 User Defined CTCSS Code R Calculate the values of N and R for the desired CTCSS frequency by: N = integer (0.24 * User Frequency) R = round (((0.24 * User Frequency) – N) * 3000 / User Frequency) + 0.5 Eg: for 150.1Hz, N=36, R=1 so P2.4 = $6901 $C8 (P2.5) Sub-audio Drop Out Time Bit: 15 14 13 12 P2.5 0 1 1 0 11 10 9 8 7 6 5 4 Sub-audio Drop Out Time 3 2 1 0 0 The Sub-audio Drop Out Time defines the time that the sub-audio signal detection can drop out before loss of sub-audio is asserted. The period is set according to the formula: Time = Sub-audio Drop Out Time 8.0ms [range 0 to 120ms] The setting of this register defines the maximum drop out time that the device can tolerate. The setting of this register also determines the de-response time, which is typically 90ms longer than the programmed drop out time. $C8 (P2.6) Reserved – do not access Bit: 15 14 13 12 P2.6 0 1 1 0 2014 CML Microsystems Plc 11 10 9 8 7 6 5 4 3 2 1 0 reserved – set to $000 Page 56 D/138A/4 Audio Scrambler and Sub-Audio Signalling Processor CMX138A 9.2.4 Program Block 3 – AuxDAC, RAMDAC and Clock Control: This block is divided into two sub-blocks to facilitate loading the RAMDAC buffer. Set bit 15 to restart a loading sequence. If bit 10 is set then loading the first ten locations will be skipped. If bit 10 is clear, the first ten locations must be loaded before continuing to the RAMDAC load. The Internal clk dividers only require modification if a non-standard XTAL frequency is used (see Table 2). Bit: 15 14 13 12 11 10 P3.0 1 1 1 1 0 0 AuxADC Average Counter P3.1 0 1 1 1 0 0 Reserved – set to 000 P3.2 0 1 1 1 0 0 GP Timer value in Idle mode P3.3 0 1 1 1 0 0 VCO output and AUX clk divide in Idle mode P3.4 0 1 1 1 0 0 Ref clk divide in Rx or Tx mode P3.5 0 1 1 1 0 0 PLL clk divide in Rx or Tx mode P3.6 0 1 1 1 0 0 VCO output and AUX clk divide in Rx or Tx mode P3.7 0 1 1 1 0 0 Internal ADC / DAC clk divide in Rx or Tx mode P3.8 0 1 1 1 0 0 AuxADC Internal Control 1 P3.9 0 1 1 1 0 0 AuxADC Internal Control 2 P3.10 0 1 1 1 0 0 AuxADC Internal Control 3 P3.11 1 1 1 1 0 1 User Defined RAMDAC data 0 P3.12 0 1 1 1 0 1 User Defined RAMDAC data xx P3.74 0 1 1 1 0 1 User Defined RAMDAC data 63 Default Values: P3.0 P3.1 P3.2 - P3.7: P3.8 P3.9 P3.10 P3.11 - P3.74: 9 8 7 6 5 4 3 2 1 0 $000 $000 see Table 2 $000 - do not change this value $101 - do not change this value $002 - do not change this value see Table 11 Table 11 RAMDAC Values Default DAC RAM Contents After Reset (hexadecimal) 0 000 16 09A 32 20C 48 376 1 001 17 0AD 33 226 49 387 2 003 18 0C1 34 23F 50 397 2014 CML Microsystems Plc 3 006 19 0D5 35 258 51 3A6 4 00A 20 0EA 36 271 52 3B4 5 010 21 100 37 28A 53 3C1 6 017 22 116 38 2A2 54 3CC 7 01F 23 12D 39 2BA 55 3D7 Page 57 8 028 24 145 40 2D2 56 3E0 9 033 25 15D 41 2E9 57 3E8 10 03E 26 175 42 2FF 58 3EF 11 04B 27 18E 43 315 59 3F5 12 059 28 1A7 44 32A 60 3F9 13 068 29 1C0 45 33E 61 3FC 14 078 30 1D9 46 352 62 3FE 15 089 31 1F3 47 365 63 3FF D/138A/4 Audio Scrambler and Sub-Audio Signalling Processor 9.2.5 CMX138A Program Block 4 – Gain and Offset Setup: Bit: 15 14 P4.0 1 0 Fine Input Gain P4.1 0 0 reserved - clear to '0' P4.2 0 0 Fine Output Gain 1 - AUDIO P4.3 0 0 Fine Output Gain 2 - MOD P4.4 0 0 Output 1 Offset Control - AUDIO P4.5 0 0 Output 2 Offset Control - MOD P4.6 0 0 Ramp Rate Control P4.7 0 0 Limiter Setting (all '1' s = VBIAS +/- AVDD / 2) P4.8 0 0 reserved P4.9 0 0 Audio Filter Sequence P4.10 0 0 reserved P4.11 0 0 Input AGC threshold level Default values: P4.0 P4.1 P4.2 P4.3 P4.4 P4.5 $C8 (P4.0) 13 12 11 10 $8000 $0000 $0000 $0000 $0000 $0000 9 8 7 P4.6 P4.7 P4.8 P4.9 P4.10 P4.11 6 5 4 3 2 1 0 $0000 $3FFF $119A $004B $0608 $0FFF Fine Input Gain Bit: 15 14 P4.0 1 0 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Fine Input Gain (unsigned integer) Gain = 20 log([32768-IG]/32768)dB. IG is the unsigned integer value in the ‘Fine Input Gain’ field. Fine input gain adjustment should be kept within the range 0 to -3.5dB. This adjustment occurs after the coarse input gain adjustment (register $B0). This setting affects both MIC and DISC inputs. $C8 (P4.1) Reserved Bit: 15 14 P4.1 0 0 13 12 11 10 9 8 7 6 5 4 3 2 1 0 4 3 2 1 0 reserved - clear to '0' This register is reserved and should be cleared to '0'. $C8 (P4.2-3) Fine Output Gain 1 and Fine Output Gain 2 Bit: 15 14 P4.2 0 0 13 12 11 10 Fine Output Gain 1 – AUDIO (unsigned integer) 9 8 7 6 5 P4.3 0 0 Fine Output Gain 2 – MOD (unsigned integer) Gain = 20 log([32768-OG]/32768)dB. OG is the unsigned integer value in the ‘Fine Output Gain’ field. Fine output gain adjustment should be kept within the range 0dB to -3.5dB ($000 to $2A73). This adjustment occurs before the coarse output gain adjustment (register $B1). Alteration of Fine Output Gain 1 will affect the gain of the AUDIO output, and Fine Output Gain 2 will affect the MOD output. 2014 CML Microsystems Plc Page 58 D/138A/4 Audio Scrambler and Sub-Audio Signalling Processor b13-0 Value (hex) 0 2EA 5C3 88B B43 DEB 1084 130E 1589 17F5 CMX138A Attenuation (dB) 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 b13-0 Value (hex) 1A53 1CA4 1EE7 211D 2346 2562 2772 2976 2A74 Attenuation (dB) 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.5 Table 12 Voice Level Attenuation (Please note that differences between the calculated values and measured levels are due to truncation of the programmed values). 2014 CML Microsystems Plc Page 59 D/138A/4 Audio Scrambler and Sub-Audio Signalling Processor $C8 (P4.4-5) CMX138A Output 1 Offset and Output 2 Offset Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 P4.4 0 0 2’s Complement Offset for Output 1 (AUDIO), Resolution = AV DD / 65536 per LSB P4.5 0 0 2’s Complement Offset for Output 2 (MOD), Resolution = AV DD / 65536 per LSB The Programmed value is subtracted from the output signal. Can be used to compensate for inherent offsets in the output path via AUDIO (Output 1 Offset) and MOD (Output 2 Offset). It is recommended that the offset correction is kept within the range +/-50mV. This adjustment occurs before the coarse output gain adjustment (register $B1), therefore an alteration to the latter register will require a compensation to be made to the output offsets. $C8 (P4.6) Ramp Rate Control Bit: 15 14 P4.6 0 0 13 12 11 10 9 8 7 6 Ramp Rate Up Control (RRU) 5 4 3 2 1 0 Ramp Rate Down Control (RRD) The MOD ramp-up and ramp-down rates can be independently programmed and enabled (via bits 0,1 of register $A7). The ramp rates should be programmed before ramping any outputs. Time to ramp-up to full gain = Time to ramp down to zero gain = (1 + RRU) 1.333ms (1 + RRD) 1.333ms Ramp up starts from when the transmit mode starts (Mode Control Register bit 1 set = ‘1’). Ramp down starts from when transmit mode is turned off (Mode Control Register bit 1 cleared = ‘0’). $C8 (P4.7) Transmit Limiter Control Bit: 15 14 P4.7 0 0 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Limiter Setting, Resolution = AVDD / 16384 per LSB This unsigned number sets the clipping point (maximum deviation from the centre value) for the MOD output. The maximum setting ($3FFF) is VBIAS (AVDD/2) i.e. output limited from 0 to AVDD. The limiter is set to maximum following a C-BUS Reset or a Power-Up Reset. The levels of internally generated signals may need to be adjusted by setting appropriate transmit levels to avoid un-intentional limiting. The limiter is active whenever either of the 12.5 or 25kHz Channel filters are selected (both in Rx or Tx). $C8 (P4.8) Reserved Bit: 15 14 P4.8 0 0 13 12 11 10 9 8 7 6 5 4 3 2 1 0 4 3 2 1 0 reserved – set to $119A Reserved – set to $119A $C8 (P4.9) Audio Filter sequence Bit: 15 14 13 12 P4.9 0 0 lim src 11 10 9 8 Input AGC 7 6 Pre-emp 5 Comp Scramble 300Hz b13 selects the hard limiter in the audio processing path when set to 1, instead of the default soft Limiter. b12 sets the source of the reference signal when InputAGC function is active. 0 = Audio Input 1 = Pre-emphasis output b11-8 control the hardware InputAGC function and its release timer for Voice/Audio signals on Input 1 in 64ms steps: 2014 CML Microsystems Plc Page 60 D/138A/4 Audio Scrambler and Sub-Audio Signalling Processor 0000 0001 0010 0011 0100 0101 ---1111 CMX138A InputAGC off InputAGC on, release time = 64ms InputAGC on, release time = 128ms InputAGC on, release time = 196ms InputAGC on, release time = 256ms InputAGC on, release time = 320ms -------------------------InputAGC on, release time = 960ms b7-0 set the order of the Audio Filter processing. This feature can be used to optimise the signal to noise performance of particular radio hardware designs. Each filter/process block can be specified in any order. Each two-bit field specifies the order in which the process will be executed in Tx mode, therefore it is imperative that each set of bit fields be different. The reverse sequence is used in Rx mode. The voice filter and soft limiter will always be implemented as the final block in the Tx sequence. The default settings are: o Pre-emphasis: 01 (pre-emphasis in position 1) o Compandor: 00 (Compandor in position 0) o Scramble: 10 (Scrambler in position 2) o 300Hz HPF: 11 (HPF in position 3) which will implement the line-up as shown in Figure 16 and Figure 17. Compress (optional) Audio in Pre-emph (optional) Scrambler (optional) Voice LPF & Soft Limiter 300Hz Filter + CTCSS Figure 16 Default Tx Audio Filter Line-up Discrim Voice LPF De-scrambler (optional) 300Hz Filter De-emph (optional) Expander (optional) Audio Figure 17 Default Rx Audio Filter Line-up $C8 (P4.10) Reserved Bit: 15 14 P4.10 0 0 13 12 11 10 9 8 7 6 5 4 3 2 1 0 4 3 2 1 0 reserved – set to $0608 Reserved – set to $0608 $C8 (P4.11) Input AGC Threshold Level Bit: 15 14 P4.11 0 0 13 12 11 10 9 8 7 6 5 Threshold Level This unsigned hex number sets the threshold level for the Input AGC function. Default is $0FFF = VBIAS AVDD/4. 2014 CML Microsystems Plc Page 61 D/138A/4 Audio Scrambler and Sub-Audio Signalling Processor CMX138A 9.2.6 Initialisation of the Programming Register Blocks: Removal of the Signal Processing block from reset (Power-Down register $C0 b5 1 0), with the Protect Bit (Power-Down register $C0 b4 = 0) kept low, will cause all of the Programming register words (P0 – P4) to be reset to their default values. 2014 CML Microsystems Plc Page 62 D/138A/4 Audio Scrambler and Sub-Audio Signalling Processor CMX138A 10 Application Notes 11 Performance Specification 11.1 Electrical Performance 11.1.1 Absolute Maximum Ratings Exceeding these maximum ratings can result in damage to the device. Supply: DVDD - DVSS AVDD - AVSS Voltage on any pin to DVSS Voltage on any pin to AVSS Current into or out of any power supply pin (excluding VBIAS) i.e. VDEC, AVDD, AVSS, DVDD, DVSS Current into or out of any other pin Voltage differential between power supplies: DVDD and AVDD DVSS and AVSS E1 Package (28-pin TSSOP) Total Allowable Power Dissipation at Tamb = 25°C … Derating Storage Temperature Operating Temperature Min. 0.3 0.3 0.3 0.3 30 Max. 4.5 4.5 DVDD + 0.3 AVDD + 0.3 +30 Unit V V V V mA 20 +20 mA 0 0 0.3 50 V mV Min. – – 55 40 Max. 1100 11.1 +125 +85 Unit mW mW/°C °C °C Min. Max. Unit 3.0 3.0 2.25 40 3.0 3.0 3.6 3.6 2.75 +85 12.288 24.576 V V V °C MHz MHz 11.1.2 Operating Limits Correct operation of the device outside these limits is not implied. Notes Supply Voltage: DVDD – DVSS AVDD – AVSS VDEC – DVSS Operating Temperature XTAL/CLK Frequency (using a Xtal) XTAL/CLK Frequency (using an external clock) Notes: 11 12 12 11 11 Nominal XTAL/CLK frequency is 6.144MHz. The VDEC supply is automatically created from DVDD by the on-chip voltage regulator. 2014 CML Microsystems Plc Page 63 D/138A/4 Audio Scrambler and Sub-Audio Signalling Processor CMX138A 11.1.3 Operating Characteristics For the following conditions unless otherwise specified: External components as recommended in Figure 2. Maximum load on digital outputs = 30pF. Xtal Frequency = 6.144MHz 0.01% (100ppm); Tamb = 40°C to +85°C. AVDD = DVDD = 3.0V to 3.6V. Reference Signal Level = 308mV rms at 1kHz with AVDD = 3.3V. Signal levels track with supply voltage, so scale accordingly. Input stage gain = 0dB. Output stage attenuation = 0dB. DC Parameters Notes 21 22 Typ. Max. Unit – 35 120 µA – 4 – µA – 1.0 – mA – 35 – µA – 7.0 – mA – 3.2 – mA – 8.5 – mA – 3.3 – mA – 538 – µA – – 290 20 – – µA µA – – 215 4 – – µA µA 21 Supply Current All Powersaved AIDD + DIDD (AVDD = 3.3V, DVDD = 3.3V, VDEC = 2.5V) AIDD only (AVDD = 3.3V) IDLE Mode AIDD + DIDD (AVDD = 3.3V, DVDD = 3.3V, VDEC = 2.5V) AIDD only (AVDD = 3.3V) Rx Mode AIDD + DIDD (AVDD = 3.3V, DVDD = 3.3V, VDEC = 2.5V) AIDD only (AVDD = 3.3V) Tx Mode AIDD + DIDD (AVDD = 3.3V, DVDD = 3.3V, VDEC = 2.5V) AIDD only (AVDD = 3.3V) Additional Current for Auxiliary System Clock (output running at 6.144MHz) DIDD (DVDD = 3.3V, VDEC = 2.5V) Additional Current for Auxiliary ADC AIDD (AVDD = 3.3V) DIDD (DVDD = 3.3V, VDEC = 2.5V) Additional Current for Auxiliary DAC AIDD (AVDD = 3.3V) DIDD (DVDD = 3.3V, VDEC = 2.5V) Notes: Min. 22 22 22 Tamb = 25°C, not including any current drawn from the device pins by external circuitry. System clocks, auxiliary circuits, audio scrambler, compander and pre/de-emphasis disabled, but all other digital circuits (including the Main Clock PLL) enabled. A single analogue path is enabled through the device. 2014 CML Microsystems Plc Page 64 D/138A/4 Audio Scrambler and Sub-Audio Signalling Processor CMX138A DC Parameters (continued) Notes Min. Typ. Max. Unit 70% – – 40 – – – – – 30% 40 – DVDD DVDD µA µA C-BUS Interface and Logic Inputs Input Logic ‘1’ Input Logic ‘0’ Input Leakage Current (Logic ‘1’ or ‘0’) Input Capacitance 70% – 1.0 – – – – – – 30% 1.0 7.5 DVDD DVDD µA pF C-BUS Interface and Logic Outputs Output Logic ‘1’ (IOH = 120µA) (IOH = 1mA) Output Logic ‘0’ (IOL = 360µA) (IOL = -1.5mA) “Off” State Leakage Current IRQN (Vout = DVDD) REPLY_DATA (output HiZ) 90% 80% – – – 1.0 1.0 – – – – – – – – – 10% 15% 10 +1.0 +1.0 DVDD DVDD DVDD DVDD µA µA µA – – ±2% 22 – – AVDD k 25 XTAL/CLK Input Logic ‘1’ Input Logic ‘0’ Input Current (Vin = DVDD) Input Current (Vin = DVSS) VBIAS Output Voltage Offset wrt AVDD/2 (IOL < 1A) Output impedance Notes: 25 26 26 Characteristics when driving the XTAL/CLK pin with an external clock source. Applies when utilising VBIAS to provide a reference voltage to other parts of the system. When using VBIAS as a reference, VBIAS must be buffered. VBIAS must always be decoupled with a capacitor as shown in Figure 2. 2014 CML Microsystems Plc Page 65 D/138A/4 Audio Scrambler and Sub-Audio Signalling Processor CMX138A AC Parameters XTAL/CLK Input ‘High’ pulse width ‘Low’ pulse width Input impedance (at 6.144MHz) Powered-up Resistance Capacitance Powered-down Resistance Capacitance Xtal start up (from powersave) Auxiliary System Clk Output XTAL/CLK input to CLOCK_OUT timing: (in high to out high) (in low to out low) ‘High’ pulse width ‘Low’ pulse width Notes Min. Typ. Max. Unit 31 31 15 15 – – – – ns ns – – – – – 150 20 300 20 20 – – – – – k pF k pF ms – – 76 76 15 15 81.38 81.38 – – 87 87 ns ns ns ns – 30 – ms – – 80 > 10 – – – 80% – M AVDD k – – 80 1.0 – – dB MHz 36 37 0.5 0 +0.5 dB 37 1.0 0 +1.0 dB 32 32 33 33 VBIAS Start up time (from powersave) Microphone, Discriminator Inputs (MIC, DISC) Input Impedance Maximum Input Level (pk-pk) Load resistance (feedback pins) Amplifier Open Loop Voltage gain (I/P = 1mV rms at 100Hz) Unity Gain Bandwidth Programmable Input Gain Stage Gain (at 0dB) Cumulative Gain Error (wrt attenuation at 0dB) Notes: 31 32 33 34 35 36 37 34 35 Timing for an external input to the XTAL/CLK pin. XTAL/CLK input driven by an external source. 6.144MHz XTAL fitted and 6.144MHz output selected. With no external components connected, measured at dc. Centered about AVDD/2; after multiplying by the gain of input circuit (with external components connected). Gain applied to signal at output of buffer amplifier: DISCFB, or MICFB Design value. Overall attenuation input to output has a tolerance of 0dB ±1.0dB 2014 CML Microsystems Plc Page 66 D/138A/4 Audio Scrambler and Sub-Audio Signalling Processor AC Parameters Modulator Output and Audio Output (MOD, AUDIO) Power-up to Output Stable Modulator Attenuator Attenuation (at 0dB) Cumulative Attenuation Error (wrt attenuation at 0dB) Output Impedance Enabled Disabled Output Current Range (AVDD = 3.3V) Output Voltage Range Load Resistance Audio Attenuator Attenuation (at 0dB) Cumulative Attenuation Error (wrt attenuation at 0dB) Output Impedance Enabled Disabled Output Current Range (AVDD = 3.3V) Output Voltage Range Load Resistance Notes: 41 42 43 44 CMX138A Notes Min. Typ. Max. Unit 41 – 50 100 µs 43 1.0 0 +1.0 dB 1.0 – – – 0.5 300 0 6 200 – – – +1.0 – – ±3.5 AVDD –0.5 – dB k mA V 1.0 0 +1.0 dB 1.0 – – – 0.5 300 0 6 200 – – – +1.0 – – ±3.5 AVDD –0.5 – dB k mA V 42 42 44 43 42 42 44 Power-up refers to issuing a C-BUS command to turn on an output These limits apply only if VBIAS is on and stable. At power supply switch-on, the default state is for all blocks, except the XTAL and C-BUS interface, to be in placed in powersave mode. Small signal impedance, at 1kHz, AVDD = 3.3V and Tamb = 25°C. With respect to the signal at the feedback pin of the selected input port. Centred about AVDD/2; with respect to the output driving a 20k load to AVDD/2. 2014 CML Microsystems Plc Page 67 D/138A/4 Audio Scrambler and Sub-Audio Signalling Processor AC Parameters (cont.) Auxiliary Signal Inputs (Aux ADC) Source Output Impedance Auxiliary 10 Bit ADC Resolution Maximum Input Level (pk-pk) Conversion Time Input Impedance Resistance Capacitance Zero Error Integral Non-linearity Differential Non-linearity Auxiliary 10 Bit DAC Resolution Maximum Output Level (pk-pk), no load Zero Error Resistive Load Integral Non-linearity Differential Non-linearity Notes: 51 52 53 54 55 56 57 CMX138A Notes Min. Typ. Max. Unit 51 – – 24 k 55 54 52 – – – 10 – 62.4 – 80% – Bits AVDD µs 56 – – 0 – – 100 5 – – – – – ±20 ±4 ±2 k pF mV LSBs LSBs – 80% 0 5 – – 10 – – – – – – – ±10 – ±4 ±2 Bits AVDD mV k LSBs LSBs 53 55 54 57 53 Denotes output impedance of the driver of the auxiliary input signal, to ensure <1 bit additional error under nominal conditions. With an auxiliary clock frequency of 6.144MHz. Guaranteed monotonic with no missing codes. Centred about AVDD/2. Designed for 10-bit accuracy, but only 8-bit accuracy is guaranteed Input offset from a nominal VBIAS input, which produces a $0200 ADC output. Output offset from a $0200 DAC input, measured wrt a nominal VBIAS output. 2014 CML Microsystems Plc Page 68 D/138A/4 Audio Scrambler and Sub-Audio Signalling Processor CMX138A 11.1.4 Parametric Performance For the following conditions unless otherwise specified: External components as recommended in Figure 2. Maximum load on digital outputs = 30pF. Xtal Frequency = 6.144MHz 0.01% (100ppm); Tamb = 40°C to +85°C. AVDD = DVDD = 3.0V to 3.6V. Reference Signal Level = 308mVrms at 1kHz with AVDD = 3.3V. Signal levels track with supply voltage, so scale accordingly. Input stage gain = 0dB, Output stage attenuation = 0dB. AC Parameters (cont.) CTCSS Detector Sensitivity Response Time De-response Time Dropout Immunity Frequency Range In-band Tone Detector Sensitivity Response Time De-response Time Drop-out Immunity Frequency Range DCS Decoder Sensitivity Bit-Rate Sync Time Notes: 71 72 73 74 75 Notes (Pure Tone) (Composite Signal) (Composite Signal) (Pure Tone) (Good Signal) (Good Signal) 74 71 72 72, 75 75 74 73 (In-band tone) 74 71 Min. Typ. Max. Unit – 190 – – 60 26 220 240 160 – – 250 – – 260 dB ms ms ms Hz – – – – 288 26 29 – – – – – 50 20 3000 dB ms ms ms Hz 44 – – 2 – – mVpk-pk edges Sub-Audio Detection Level threshold set to 15.4mV rms (CTCSS) or 44mV pk-pk (DCS). Composite signal = 308mVrms at 1kHz + 75mVrms Noise + 31mV rms Sub-Audio signal. Noise bandwidth = 5kHz Band Limited Gaussian. For Sub-Audio signals above 100Hz. Signals below 100Hz will take longer to detect. In-band Tone Detection Level threshold set to 16mV rms. Detection and decoding involve statistical processes which can, on occasion, result in figures outside the limits quoted. With sub-audio dropout time (P2.5) set to = 120ms. The typical dropout immunity is approximately 40ms more than the programmed dropout immunity. The typical deresponse time is approximately 90ms longer than the programmed dropout immunity. See section 9.2.3 P2.5. 2014 CML Microsystems Plc Page 69 D/138A/4 Audio Scrambler and Sub-Audio Signalling Processor AC Parameters (cont.) CMX138A Min. Typ. Max. Unit – – – – 4.0 13 100 2:1 – – – – ms ms mVrms 81 82 60.0 – 1.0 – – – 0 2.0 260 ±0.3 +1.0 4.0 Hz % dB % In-band Tone Encoder Frequency Range Tone Frequency Accuracy Tone Amplitude Tolerance Total Harmonic Distortion 83 82 288 – 1.0 – – – 0 2.0 3000 ±0.3 +1.0 4.0 Hz % dB % DCS Encoder Bit Rate Amplitude Tolerance 81 – 1.0 134.4 0 – +1.0 bps dB Audio Compandor Attack Time Decay Time 0dB Point Compression/Expansion ratio CTCSS Encoder Frequency Range Tone Frequency Accuracy Tone Amplitude Tolerance Total Harmonic Distortion Notes: 81 82 83 84 Notes 84 AVDD = 3.3V and Tx Sub-Audio Level set to 88mV p-p (31mV rms). Measured at MOD output. AVDD = 3.3V and Tx Audio Level set to 871mV p-p (308mV rms). AVDD = 3.3V. 2014 CML Microsystems Plc Page 70 D/138A/4 Audio Scrambler and Sub-Audio Signalling Processor AC Parameters (cont.) Analogue Channel Audio Filtering Pass-band (nominal bandwidth): Received Audio 12.5kHz Channel Transmitted Audio 25kHz Channel Transmitted Audio Pass-band Gain (at 1.0kHz) Pass-band Ripple (wrt gain at 1.0kHz) Stop-band Attenuation Residual Hum and Noise (Tx path) Residual Hum and Noise (Rx path) Pre-emphasis De-emphasis Audio Scrambler Inversion Frequency Pass-band (assuming 3300Hz inversion frequency) Audio Expandor Input Signal Range Notes: 91 92 93 94 95 96 97 98 99 CMX138A Notes Min. Typ. Max. Unit 91 92 93 96 96 300 300 300 – 2.0 33.0 – – – – – 0 0 – 53.7 74.8 3300 2550 3000 – +0.5 – – – Hz Hz Hz dB dB dB dBm dBm 94 95 – – +6 6 – – dB/oct dB/oct 98 99 2632 300 3300 – 3496 3000 Hz Hz 97 – – 0.55 Vrms The receiver audio filter complies with the characteristic shown in Figure 6. The high pass filtering removes sub-audio components from the audio signal. The 12.5kHz channel filter complies with the characteristic shown in Figure 9. The 25kHz channel filter complies with the characteristic shown in Figure 8. The pre-emphasis filter complies with the characteristic shown in Figure 10. The de-emphasis filter complies with the characteristic shown in Figure 7. Psophometric weighting; pre/de-emphasis, compandor and 25kHz channel filter selected. AVDD = 3.3V. Use of a scrambler inversion frequency other than 3300Hz will shift the scrambled voice signal outside the audio band, so that some of the signal will be lost in the channel filter. The result is that the descrambled voice signal will have a restricted bandwidth. The limits quoted are subjective and relate to the onset of a loss of speech intelligibility. -6dB points. 2014 CML Microsystems Plc Page 71 D/138A/4 Audio Scrambler and Sub-Audio Signalling Processor CMX138A 11.2 C-BUS Timing Figure 18 C-BUS Timing C-BUS Timing tCSE CSN Enable to SCLK high time tCSH Last SCLK high to CSN high time tLOZ SCLK low to RDATA Output Enable Time tHIZ CSN high to RDATA high impedance tCSOFF CSN high time between transactions tNXT Inter-byte time tCK SCLK cycle time tCH SCLK high time tCL SCLK low time tCDS CDATA setup time tCDH CDATA hold time tRDS RDATA setup time tRDH RDATA hold time Notes Min. 100 100 0.0 – 1.0 200 200 100 100 75 25 50 0 Typ. – – – – – – – – – – – – – Max. – – – 1.0 – – – – – – – – – Unit ns ns ns µs µs ns ns ns ns ns ns ns ns Notes: 1. Depending on the command, 1 or 2 bytes of CDATA are transmitted to the peripheral MSB (Bit 7) first, LSB (Bit 0) last. RDATA is read from the peripheral MSB (Bit 7) first, LSB (Bit 0) last. 2. Data is clocked into the peripheral on the rising SCLK edge. 3. Commands are acted upon at the end of each command (rising edge of CSN). 4. To allow for differing µC serial interface formats C-BUS compatible ICs are able to work with SCLK pulses starting and ending at either polarity. 5. Maximum 30pF load on IRQN pin and each C-BUS interface line. These timings are for the latest version of C-BUS and allow faster transfers than the original C-BUS timing specification. The CMX138A can be used in conjunction with devices that comply with the slower timings, subject to system throughput constraints. 2014 CML Microsystems Plc Page 72 D/138A/4 Audio Scrambler and Sub-Audio Signalling Processor CMX138A 11.3 Packaging Figure 19 Mechanical Outline of 28-pin TSSOP (E1) Order as part no. CMX138AE1 As package dimensions may change after publication of this datasheet, it is recommended that you check for the latest Packaging Information from the Datasheets page of the CML website: [www.cmlmicro.com]. Handling precautions: This product includes input protection, however, precautions should be taken to prevent device damage from electro-static discharge. CML does not assume any responsibility for the use of any circuitry described. No IPR or circuit patent licences are implied. CML reserves the right at any time without notice to change the said circuitry and this product specification. CML has a policy of testing every product shipped using calibrated test equipment to ensure compliance with this product specification. Specific testing of all circuit parameters is not necessarily performed. 2014 CML Microsystems Plc Page 73 D/138A/4