Precision Analog Microcontroller, 12-Bit Analog I/O, Large Memory, ARM7TDMI MCU with Enhanced IRQ Handler ADuC7124/ADuC7126 Silicon Anomaly This anomaly list describes the known bugs, anomalies, and workarounds for the ADuC7124/ADuC7126 MicroConverter® Revision B silicon. The anomalies listed apply to all ADuC7124/ADuC7126 packaged material branded as follows: First Line Third Line ADuC7124 or ADuC7126 B30 Analog Devices, Inc., is committed, through future silicon revisions, to continuously improve silicon functionality. Analog Devices tries to ensure that these future silicon revisions remain compatible with your present software/systems by implementing the recommended workarounds outlined here. ADuC7124/ADuC7126 FUNCTIONALITY ISSUES Silicon Revision Identifier B Kernel Revision Identifier 30 Chip Marking All silicon branded B30 Silicon Status Released Anomaly Sheet Rev. B No. of Reported Anomalies 7 Silicon Status Released Anomaly Sheet Rev. B No. of Reported Anomalies 2 ADuC7124/ADuC7126 PERORMANCE ISSUES Silicon Revision Identifier B Rev. B Kernel Revision Identifier 30 Chip Marking All silicon branded B30 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2011-2014 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADuC7124/ADuC7126 Silicon Anomaly FUNCTIONALITY ISSUES Table 1. ADC Conversion—CONVSTART Edge Trigger Mode [er001] Background Issue Workaround Related Issues ADC conversion can be set as CONVSTART falling edge trigger mode by setting ADCCON Bit 13 and with ADCCON[2:0] = 000. Clearing ADCCON Bit 13 enables CONVSTART high level trigger mode. ADC conversion by CONVSTART edge trigger mode is not reliable. Configure CONVSTART through one PLA flip-flop with ULCK as its clock. This ensures that the ADC is triggered by CONVSTART when its pulse width is more than 25 ns. This will be fixed in the next revision. None. Table 2. ADC Conversion—PLA Edge Trigger Mode [er002] Background Issue Workaround Related Issues The ADC conversion can be set as PLA rising edge trigger mode by setting ADCCON Bit 13 and with ADCCON[2:0] = 101. Clearing ADCCON Bit 13 enables PLA low level trigger mode. ADC conversion by PLA edge trigger mode is not reliable. Configure the PLA element output through another PLA flip-flop with ULCK as its clock. This ensures that the ADC is triggered by the PLA edge when CD is less than 5. This will be fixed in the next revision. None. Table 3. Disabling I2C Interface in Slave Mode When a Transfer Is in Progress [er003] Background Issue Workaround Related Issues The I2CSEN bit (Bit 0 in the I2CxSCON register) enables/disables the I2C slave interface. The I2CSBUSY bit (Bit 6 in the I2CxSSTA register) indicates whether the I2C slave interface is busy. If I2C slave mode is enabled (I2CxSCON Bit 0 = 1) and a transfer is in progress with the master, do not clear I2CxSCON Bit 0 to 0 to disable the I2C slave interface until the I2C busy bit, I2CSBUSY (Bit 6 of I2CxSSTA), is cleared. When I2CxSCON Bit 0 is cleared to 0 and I2CSBUSY is still set, the ADuC7124/ADuC7126 may drive the SDAx pins low indefinitely. When this condition occurs, the ADuC7124/ADuC7126 do not release the SDAx pins unless a hardware reset condition occurs. When disabling I2C slave mode by writing to the I2CSEN bit (Bit 0 in the I2CxSCON register), first set the I2CMEN bit (Bit 0 in the I2CxMCON register) = 1 to enable master mode. Then disable the slave mode by clearing the I2CSEN bit. Finally, clear the I2CMEN bit. None. Table 4. Operation of SPI in Slave Mode [er004] Background Issue Workaround Related Issues When in SPI slave mode, the ADuC7124/ADuC7126 expect the number of clock pulses from the master to be divisible by 8 when the chip select (CS) pin is low. The internal bit shift counter within the ADuC7124/ADuC7126 is not reset when the chip select pin is deasserted. If the number of clocks from the master is not divisible by 8 when the chip select is active, incorrect data may be received or transmitted by the ADuC7124/ADuC7126 because the bit shift counter will not be at 0 for future transfers. The internal bit shift counter for the transmit or receive buffers can only be reset by a hardware, software, or watchdog reset. Always ensure that the number of SPI clocks is divisible by 8 when the ADuC7124/ADuC7126 chip select is active. None. Rev. B | Page 2 of 5 Silicon Anomaly ADuC7124/ADuC7126 Table 5. Timer0 in Periodic Mode with Internal 32 kHz Clock [er005] Background Issue Workaround Related Issues In periodic mode, the internal counter decrements/increments from the value in the load register (T0LD MMR) until zero/full scale and starts again at the value stored in the load register. The value of a counter can be read at any time by accessing its value register (T0VAL). The first timer interrupt occurs only after a full 16-bit countdown. After the countdown, the T0LD value is copied into T0VAL as expected. This issue occurs only when the 32 kHz oscillator is serving as the timer source. None. None. Table 6. I2C Slave Not Releasing the Bus [er006] Background Issue Workaround Related Issues When an I2C read request happens, if the slave’s Tx FIFO is empty, the slave should NACK the masters’ request. Then it should release the bus, allowing the master to generate a stop condition. If the slave’s Tx FIFO is loaded with a byte who’s MSB is 0 just on the rising edge of SCL for the ACK/NACK, the slave will pull the SDA low and hold the line until the device is reset. Make sure the Tx FIFO is always loaded on time by preloading Tx FIFO in the preceding RX interrupt. None. Table 7. I2C Clock Stretch Issue [er007] Background Issue Workaround Related Issues Clock stretching is a feature that allows a device to halt the I2C bus temporarily by holding SCL low. Bit 6 of the I2CxSCON register enables clock stretching in slave mode. Bit 3 of the I2CxMCON register enables clock stretching in master mode. Writing to I2CxSCON Bit 6 or to I2CxMCON Bit 3 on the rising edge of SCL can cause a glitch that may be interpreted by other devices as a real clock edge and might hang the bus. Do not enable clock stretching. None. Rev. B | Page 3 of 5 ADuC7124/ADuC7126 Silicon Anomaly PERFORMANCE ISSUES Table 8. ADC and DAC Reference Selection Limitation [pr001] Background Issue Workaround Related Issues The ADuC7124/ADuC7126 provide an on-chip band gap reference of 2.5 V, which can be used for the ADC and DACs. This internal reference also appears on the VREF pin. When using the internal reference, a 0.47 µF capacitor must be connected from the external VREF pin to AGND to ensure stability and fast response during ADC conversions. When REFCON = 0x00 is set, the internal 2.5 V reference is unstable; that is, when the ADC uses the external reference (REFCON = 0x00) and the DACs use the internal 2.5 V reference (DACxCON[1:0] = 10), the DAC output is unstable. Set REFCON = 0x00 for the ADC to use the external reference, and set DACxCON[1:0] = 01 for the DACs to use a different external reference from DACREF. None. Table 9. JTAG Clock Limitation [pr002] Background Issue Workaround Related Issues The JTAG clock speed is limited. JTAG speed requires TCK < UCLK/(2CD × 6); that is, TCK should be changed according to how the CD (CPU clock divider) bits are set. If TCK is greater than the limitation, the JTAG cannot download until the power-on reset (POR) is at the correct TCK speed. The JTAG clock speed must be set up manually. The default kernel setting for the CPU clock is CD = 3 (5.22 MHz). Therefore, a JTAG clock speed limitation of 800 kHz or less must be maintained. None. Rev. B | Page 4 of 5 Silicon Anomaly ADuC7124/ADuC7126 SECTION 1. ADuC7124/ADuC7126 FUNCTIONALITY ISSUES Reference Number er001 er002 er003 er004 er005 er006 er007 Description ADC conversion—CONVSTART edge trigger mode ADC conversion—PLA edge trigger mode Disabling I2C interface in slave mode when a transfer in progress Operation of SPI in slave mode Timer0 in periodic mode with an internal 32 kHz clock I2C slave not releasing the bus I2C clock stretch issue Status Open Open Open Open Open Open Open SECTION 2. ADuC7124/ADuC7126 PERFORMANCE ISSUES Reference Number pr001 pr002 Description ADC and DAC reference selection limitation JTAG clock limitation I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2011-2014 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. S09861-0-9/14(B) Rev. B | Page 5 of 5 Status Open Open