ISSI IS62WV5128DALL-55BI 512k x 8 low voltage, ultra low power cmos static ram Datasheet

IS62WV5128DALL/DBLL, IS65WV5128DALL/DBLL
512K x 8 LOW VOLTAGE,
FEBRUARY 2012
ULTRA LOW POWER CMOS STATIC RAM FEATURES
DESCRIPTION
The ISSI IS62WV5128DALL / IS62WV5128DBLL are • High-speed access time: 35, 45, 55 ns
high-speed, 4M bit static RAMs organized as 512K words
by 8 bits. It is fabricated using ISSI's high-performance
CMOS technology. This highly reliable process coupled
with innovative circuit design techniques, yields highperformance and low power consumption devices.
• CMOS low power operation
36 mW (typical) operating
9 µW (typical) CMOS standby
• TTL compatible interface levels
When CS1 is HIGH (deselected) the device assumes
a standby mode at which the power dissipation can be
reduced down with CMOS input levels.
• Single power supply 1.65V – 2.2V Vdd (IS62WV5128DALL)
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs. The active LOW Write Enable
(WE) controls both writing and reading of the memory.
2.3V – 3.6V Vdd (IS62WV5128DBLL)
• Fully static operation: no clock or refresh
required
• Three state outputs
• Industrial and Automotive temperature support
The IS62WV5128DALL and IS62WV5128DBLL are
packaged in the JEDEC standard 32-pin TSOP (TYPE
I), 32-pin sTSOP (TYPE I), 32-pin TSOP (Type II), 32-pin
SOP and 36-pin mini BGA.
• Lead-free available
FUNCTIONAL BLOCK DIAGRAM
A0-A18
DECODER
512K x 8
MEMORY ARRAY
VDD
GND
I/O
DATA
CIRCUIT
I/O0-I/O7
CS1
OE
COLUMN I/O
CONTROL
CIRCUIT
WE
Copyright © 2012 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications
unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
02/09/2012
1
IS62WV5128DALL/DBLL, IS65WV5128DALL/DBLL
PIN DESCRIPTIONS
A0-A18
CS1
OE
WE
I/O0-I/O7
NC
Vdd
GND
Address Inputs
Chip Enable 1 Input
Output Enable Input
Write Enable Input
Input/Output
No Connection
Power
Ground
36-pin mini BGA (B) (6mm x 8mm)
(Package Code B)
1
2
3
4
5
6
A
A0
A1
NC
A3
A6
A8
B
I/O4
A2
WE
A4
A7
I/O0
C
I/O5
NC
A5
D
GND
VDD
E
VDD
GND
F
I/O6
G
I/O7
H
A9
I/O1
A18
A17
I/O2
OE
CS1
A16
A15
I/O3
A10
A11
A12
A13
A14
2 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A
02/09/2012
IS62WV5128DALL/DBLL, IS65WV5128DALL/DBLL
PIN DESCRIPTIONS
A0-A18 Address Inputs
CS1
Chip Enable 1 Input
OE
Output Enable Input
WE
Write Enable Input
I/O0-I/O7 Input/Output
Vdd
Power
GND
Ground
PIN CONFIGURATION
32-pin TSOP (TYPE I), (Package Code T)
32-pin sTSOP (TYPE I) (Package Code H)
A11
A9
A8
A13
WE
A18
A15
VDD
A17
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CS1
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3
32-pin SOP (Package Code Q)
32-pin TSOP (TYPE II) (Package Code T2)
A17
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
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Rev. A
02/09/2012
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VDD
A15
A18
WE
A13
A8
A9
A11
OE
A10
CS1
I/O7
I/O6
I/O5
I/O4
I/O3
3
IS62WV5128DALL/DBLL, IS65WV5128DALL/DBLL
TRUTH TABLE
Mode
Not Selected
(Power-down)
Output Disabled
Read
Write
WE
X
H
H
L
CS1
H
L
L
L
I/O Operation
High-Z OE
X
H
L
X
Vdd Current
Isb1, Isb2
High-Z
Dout
Din
Icc
Icc
Icc
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Vterm
Vdd
Tstg
Pt
Parameter
Terminal Voltage with Respect to GND
Vdd Relates to GND
Storage Temperature
Power Dissipation
Value
–0.5 to Vdd + 0.5
–0.3 to 4.0
–65 to +150
1.0
Unit
V
V
°C
W
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
CAPACITANCE(1,2)
Symbol
Cin
CI/O
Parameter
Input Capacitance
Input/Output Capacitance
Conditions
Vin = 0V
Vout = 0V
Max.
6
8
Unit
pF
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: Ta = 25°C, f = 1 MHz, Vdd = 3.3V.
4 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A
02/09/2012
IS62WV5128DALL/DBLL, IS65WV5128DALL/DBLL
AC TEST CONDITIONS
Parameter
Unit
Unit
(2.3V-3.6V)
(3.3V + 5%)
Input Pulse Level
0.4V to Vdd - 0.3V
0.4V to Vdd - 0.3V
Input Rise and Fall Times
1V/ ns
1V/ ns
Input and Output Timing
VDD /2
VDD + 0.05
and Reference Level (VRef) 2
Output Load
See Figures 1 and 2
See Figures 1 and 2
R1 ( Ω )
1005
1213
R2 ( Ω )
820
1378
Vtm (V)
3.0V
3.3V
Unit
(1.65V-2.2V)
0.4V to Vdd - 0.3V
1V/ ns
0.9V
See Figures 1 and 2
13500
10800
1.8V
AC TEST LOADS
R1
R1
VTM
VTM
OUTPUT
OUTPUT
30 pF
Including
jig and
scope
R2
Figure 1.
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Rev. A
02/09/2012
5 pF
Including
jig and
scope
R2
Figure 2.
5
IS62WV5128DALL/DBLL, IS65WV5128DALL/DBLL
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Vdd = 3.3V + 5%
Symbol
Voh
Vol
Vih
Vil
Ili
Ilo
Parameter
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage(1)
Input Leakage
Output Leakage
Test Conditions
Vdd = Min., Ioh = –1 mA
Vdd = Min., Iol = 2.1 mA
Min.
2.4
—
2
–0.3
–1
–1
GND ≤ Vin ≤ Vdd
GND ≤ Vout ≤ Vdd, Outputs Disabled
Max.
—
0.4
Vdd + 0.3
0.8
1
1
Unit
V
V
V
V
µA
µA
Max.
—
0.4
Vdd + 0.3
0.8
1
1
Unit
V
V
V
V
µA
µA
Note:
1. Vil (min.) = –0.3V DC; Vil (min.) = –2.0V AC (pulse width < 10 ns). Not 100% tested.
Vih (max.) = Vdd + 0.3V DC; Vih (max.) = Vdd + 2.0V AC (pulse width < 10 ns). Not 100% tested.
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Vdd = 2.3V-3.6V
Symbol
Voh
Vol
Vih
Vil
Ili
Ilo
Parameter
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage(1)
Input Leakage
Output Leakage
Test Conditions
Vdd = Min., Ioh = –1.0 mA
Vdd = Min., Iol = 2.1 mA
Min.
1.8
—
2.0
–0.3
–1
–1
GND ≤ Vin ≤ Vdd
GND ≤ Vout ≤ Vdd, Outputs Disabled
Note:
1. Vil (min.) = –0.3V DC; Vil (min.) = –2.0V AC (pulse width < 10 ns). Not 100% tested.
Vih (max.) = Vdd + 0.3V DC; Vih (max.) = Vdd + 2.0V AC (pulse width < 10 ns). Not 100% tested.
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Vdd = 1.65V-2.2V
Symbol
Voh
Vol
Vih
Vil(1)
Ili
Ilo
Parameter
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Leakage
Output Leakage
Test Conditions
Ioh = -0.1 mA
Iol = 0.1 mA
Vdd
1.65-2.2V
1.65-2.2V
1.65-2.2V
1.65-2.2V
GND ≤ Vin ≤ Vdd
GND ≤ Vout ≤ Vdd, Outputs Disabled
Min.
1.4
—
1.4
–0.2
–1
–1
Max.
—
0.2
Vdd + 0.2
0.4
1
1
Unit
V
V
V
V
µA
µA
Note:
1. Vil (min.) = –0.3V DC; Vil (min.) = –2.0V AC (pulse width < 10 ns). Not 100% tested.
Vih (max.) = Vdd + 0.3V DC; Vih (max.) = Vdd + 2.0V AC (pulse width < 10 ns). Not 100% tested.
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02/09/2012
IS62WV5128DALL/DBLL, IS65WV5128DALL/DBLL
OPERATING RANGE (Vdd)
Range
Ambient Temperature
Commercial
0°C to +70°C
Industrial
–40°C to +85°C
Automotive
–40°C to +125°C
Vdd
1.65V-2.2V
1.65V-2.2V
1.65V-2.2V
Speed
45ns
55ns
55ns
Vdd (45 ns)
2.3V-3.6V
2.3V-3.6V
Vdd (35 ns)
3.3V+5%
3.3V+5%
OPERATING RANGE (Vdd)
Range
Ambient Temperature
Commercial
0°C to +70°C
Industrial
–40°C to +85°C
OPERATING RANGE (Vdd)
Range
Automotive
Ambient Temperature
–40°C to +125°C
Vdd (45 ns)
2.3V-3.6V
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-35
Symbol Parameter
Test Conditions
Min. Max.
Icc
Vdd Dynamic Operating
Vdd = Max.,
Com.
—
20
Supply Current
Iout = 0 mA, f = fmax
Ind.
—
25
CE = Vil
Auto.
—
30
Vin ≥ Vdd – 0.3V, or
typ.(2) 10
Vin ≤ 0.4V
Icc1
Operating
Vdd = Max.,
Com.
—
3
Supply Current
Iout = 0 mA, f = 0
Ind.
—
3
CE = Vil
Auto.
—
3
Vin ≥ Vdd – 0.3V, or
Vin ≤ 0.4V
Isb2
CMOS Standby
Vdd = Max.,
Com.
—
5
Current (CMOS Inputs)
CE ≥ Vdd – 0.2V,
Ind.
—
10
Vin ≥ Vdd – 0.2V, or
Auto.
—
30
Vin ≤ 0.2V, f = 0
typ.(2) 2
-45
Min. Max.
—
15
—
20
—
25
-55
Min. Max.
—
15
—
20
—
25
Unit
mA
—
—
—
3
3
3
—
—
—
3
3
3
mA
—
—
—
5
10
30
—
—
—
5
10
30
µA
Note:
1. At f = fmax, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2. Typical values are measured at Vdd = 3.0V, Ta = 25oC and not 100% tested.
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Rev. A
02/09/2012
7
IS62WV5128DALL/DBLL, IS65WV5128DALL/DBLL
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
35 ns 45 ns 55 ns
Symbol
Parameter
Min. Max.
Min. Max.
Min. Max. Unit
trc
taa
toha
tacs1
tdoe
thzoe(2)
tlzoe(2)
thzcs1
tlzcs1
Read Cycle Time
35
—
45
—
55
—
ns
Address Access Time
—
35
—
45
—
55
ns
Output Hold Time
10
—
10
—
10
—
ns
CS1 Access Time
—
35
—
45
—
55
ns
OE Access Time
—
10
—
20
—
25
ns
OE to High-Z Output
—
10
—
15
—
20
ns
OE to Low-Z Output
3
—
5
—
5
—
ns
CS1 to High-Z Output
0
10
0
15
0
20
ns
CS1 to Low-Z Output
5
—
10
—
10
—
ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V/1.5V, input pulse levels of 0.4 to
Vdd-0.2V/Vdd-0.3V and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
AC WAVEFORMS
READ CYCLE NO. 1(1,2) (Address Controlled) (CS1 = OE = Vil, WE = Vih)
tRC
ADDRESS
tAA
tOHA
DOUT
PREVIOUS DATA VALID
tOHA
DATA VALID
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02/09/2012
IS62WV5128DALL/DBLL, IS65WV5128DALL/DBLL
AC WAVEFORMS
READ CYCLE NO. 2(1,3) (CS1, OE Controlled)
tRC
ADDRESS
tAA
tOHA
OE
tDOE
CS1
tHZOE
tLZOE
tACS1
tLZCS1
DOUT
HIGH-Z
tHZCS
DATA VALID
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CS1= Vil. WE=Vih.
3. Address is valid prior to or coincident with CS1 LOW transition.
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Rev. A
02/09/2012
9
IS62WV5128DALL/DBLL, IS65WV5128DALL/DBLL
WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range)
35ns 45ns 55 ns
Symbol
Parameter
Min. Max. Min.Max. Min. Max. Unit
twc
Write Cycle Time
35
—
45
—
55
—
ns
tscs1
CS1 to Write End
25
—
35
—
45
—
ns
taw
Address Setup Time to Write End
25
—
35
—
45
— ns
tha
Address Hold from Write End
0
—
0
—
0
— ns
tsa
Address Setup Time
0
—
0
—
0
—
ns
tpwe
WE Pulse Width
25
—
35
—
40
—
ns
tsd
Data Setup to Write End
20
—
20
—
25
— ns
thd
Data Hold from Write End
0
—
0
—
0
—
­ns
(3)
thzwe
WE LOW to High-Z Output
—
10
—
20
—
20 ns
tlzwe(3)
WE HIGH to Low-Z Output
3
—
5
—
5
—
ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V/1.5V, input pulse levels of 0.4V to
Vdd-0.2V/Vdd-0.3V and output loading specified in Figure 1.
2. The internal write time is defined by the overlap of CS1 LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the write.
3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
AC WAVEFORMS
WRITE CYCLE NO. 1 (CS1 Controlled, OE = HIGH or LOW)
tWC
ADDRESS
tHA
tSCS1
CS1
tAW
tPWE
WE
tSA
DOUT
DATA UNDEFINED
tHZWE
tLZWE
HIGH-Z
tSD
DIN
tHD
DATA-IN VALID
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02/09/2012
IS62WV5128DALL/DBLL, IS65WV5128DALL/DBLL
WRITE CYCLE NO. 2 (WE Controlled: OE is HIGH During Write Cycle)
tWC
ADDRESS
OE
tHA
tSCS1
CS1
tAW
tPWE
WE
tSA
DOUT
tHZWE
tLZWE
HIGH-Z
DATA UNDEFINED
tSD
DIN
tHD
DATA-IN VALID
WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle)
tWC
ADDRESS
OE
tHA
tSCS1
CS1
tAW
tPWE
WE
tSA
DOUT
DATA UNDEFINED
tHZWE
tLZWE
HIGH-Z
tSD
DIN
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Rev. A
02/09/2012
tHD
DATA-IN VALID
11
IS62WV5128DALL/DBLL, IS65WV5128DALL/DBLL
DATA RETENTION SWITCHING CHARACTERISTICS
Symbol
Vdr
Idr
tsdr
trdr
Parameter
Vdd for Data Retention
Data Retention Current
Data Retention Setup Time
Recovery Time
Test Condition
See Data Retention Waveform
Vdd = 1.2V, CS1 ≥ Vdd – 0.2V
Com.
Ind.
Auto.
typ.(1)
See Data Retention Waveform
See Data Retention Waveform
Min.
1.2
—
—
—
1
0
trc
Max.
3.6
3
7
20
Unit
V
µA
—
—
ns
ns
Note: 1. Typical values are measured at Vdd = 3.0V, Ta = 25oC and not 100% tested.
DATA RETENTION WAVEFORM (CS1 Controlled)
tSDR
Data Retention Mode
tRDR
VDD
VDR
CS1
GND
CS1 ≥ VDD - 0.2V
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02/09/2012
IS62WV5128DALL/DBLL, IS65WV5128DALL/DBLL
ORDERING INFORMATION
IS62WV5128DALL (1.65V-2.2V)
Industrial Range: –40°C to +85°C
Speed (ns)
55
55
55
55
Order Part No.
IS62WV5128DALL-55TI
IS62WV5128DALL-55TLI
IS62WV5128DALL-55T2I
IS62WV5128DALL-55T2LI
IS62WV5128DALL-55HI
IS62WV5128DALL-55HLI
IS62WV5128DALL-55BI
IS62WV5128DALL-55BLI
Package
TSOP, TYPE I (8 x 20 mm)
TSOP, TYPE I, Lead-free (8 x 20 mm)
TSOP, TYPE II
TSOP, TYPE II, Lead-free
sTSOP, TYPE I (8 x 13.4 mm)
sTSOP, TYPE I, Lead-free (8 x 13.4 mm)
mini BGA (6mmx8mm)
mini BGA (6mmx8mm), Lead-free
ORDERING INFORMATION
IS62WV5128BLL (2.3V - 3.6V)
Industrial Range: –40°C to +85°C
Speed (ns)
45
45
45
45
45
45
45
45
45
Order Part No.
IS62WV5128DBLL-45TI
IS62WV5128DBLL-45TLI
IS62WV5128DBLL-45QLI
IS62WV5128DBLL-45T2I
IS62WV5128DBLL-45T2LI
IS62WV5128DBLL-45HI
IS62WV5128DBLL-45HLI
IS62WV5128DBLL-45BI
IS62WV5128DBLL-45BLI
Package
TSOP, TYPE I (8 x 20 mm)
TSOP, TYPE I, Lead-free (8 x 20 mm)
SOP, Lead-free
TSOP, TYPE II
TSOP, TYPE II, Lead-free
sTSOP, TYPE I (8 x 13.4 mm)
sTSOP, TYPE I, Lead-free (8 x 13.4 mm)
mini BGA (6mmx8mm)
mini BGA (6mmx8mm), Lead-free
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
02/09/2012
13
IS62WV5128DALL/DBLL, IS65WV5128DALL/DBLL
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02/09/2012
IS62WV5128DALL/DBLL, IS65WV5128DALL/DBLL
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
02/09/2012
15
IS62WV5128DALL/DBLL, IS65WV5128DALL/DBLL
16 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A
02/09/2012
IS62WV5128DALL/DBLL, IS65WV5128DALL/DBLL
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
02/09/2012
17
08/12/2008
Package Outline
1. CONTROLLING DIMENSION : MM .
2. Reference document : JEDEC MO-207
NOTE :
IS62WV5128DALL/DBLL, IS65WV5128DALL/DBLL
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02/09/2012
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