IRF IRS2500SPBF Transition mode pfc control ic Datasheet

February 22, 2012
IRS2500S
TRANSITION MODE PFC CONTROL IC
Features
•
•
•
•
•
•
•
•
•
•
•
•
PFC Control IC
Boost or Flyback Converter Modes
Critical-conduction / Transition mode
operation
Over-current protection
Static and Dynamic DC bus overvoltage
protection
Micropower startup (<50μA)
Low quiescent current (2.5mA)
Latch immunity and ESD protection
Wide range PFC for universal AC line input
Low THD
Open load Over voltage protection
Noise immunity
Typical Applications
•
•
•
Product Summary
Topology
Boost / Flyback
Io+ & I o- (typical)
500 / 500 mA
tr & tf (typical)
60 / 30 nS
Packages
8-Lead SOIC
Switched Mode Power Supplies
Electronic Ballasts
LED Drivers
Typical Connection Diagram
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© 2012 International Rectifier
IRS2500S
Table of Contents
Page
Description
3
Qualification Information
5
Absolute Maximum Ratings
6
Recommended Operating Conditions
6
Electrical Characteristics
7
Functional Block Diagram
9
Input/Output Pin Equivalent Circuit Diagram
10
Lead Definitions
11
Lead Assignments
11
Application Information and Additional Details
12
Package Details
19
Tape and Reel Details
20
Part Marking Information
21
Ordering Information
22
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© 2012 International Rectifier
2
IRS2500S
Description
The IRS2500 is a fully integrated, fully protected PFC SMPS control IC designed to drive Boost or Flyback
switching regulators providing high power factor. Typical applications are PFC pre-regulators for SMPS and
electronic ballasts for fluorescent or HID lighting as well as single stage Flyback converters widely used in
low power LED drivers. The IRS2500 is pin compatible with most industry standard critical conduction or
transition mode PFC control IC with additional improvements to increase performance. The PFC circuitry
provides high PF, low THD and stable DC bus regulation over a wide line/load range. The IRS2500
protection features include cycle by cycle over-current protection and output over voltage protection.
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IRS2500S
Typical Application Diagram
DBUS
DIN
RPU
RSH
RS
DVCC
IC2
VREG
T1
OUT+
+5V
CVCC
RIN
RV1
RZX
CIN
RFB1
INV
1
COMP
CCOMP
AC
Line
Input
CVREG
IC1
VDC
OC
2
3
4
8
IRS2500
BR1
7
6
5
VCC
CVOUT
OUT
RD1
COM
ZX
RPFC
RPD
IC3A
RFB2
RD2
RVFB
CVFB
MPFC
CF
RDC
OUTRV2
RF
RII
IC3B
ROC
RI
CF
RD3
RIFB
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CIFB
© 2012 International Rectifier
4
IRS2500S
†
Qualification Information
Qualification Level
Moisture Sensitivity Level
Machine Model
ESD
IC Latch-Up Test
RoHS Compliant
Human Body Model
Industrial††
Comments: This family of ICs has passed JEDEC’s Industrial
qualification. IR’s Consumer qualification level is granted by
extension of the higher Industrial level.
MSL2††† 260°C
(per IPC/JEDEC J-STD-020)
Class B
(per JEDEC standard JESD22-A115)
Class 2
(per EIA/JEDEC standard EIA/JESD22-A114)
Class I, Level A
(per JESD78)
Yes
†
††
Qualification standards can be found at International Rectifier’s web site http://www.irf.com/
Higher qualification ratings may be available should the user have such requirements. Please contact
your International Rectifier sales representative for further information.
††† Higher MSL ratings may be available for the specific package types listed here. Please contact your
International Rectifier sales representative for further information.
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© 2012 International Rectifier
5
IRS2500S
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All
voltage parameters are absolute voltages referenced to COM, all currents are defined positive into any lead.
The thermal resistance and power dissipation ratings are measured under board mounted and still air
conditions.
Symbol
VCC
Definition
Supply Voltage
†
Min.
Max.
-0.3
VCLAMP
Unit
s
VOUT
Gate Driver Output Voltage
-0.3
VCC + 0.3
V
IOMAX
Maximum allowable output current (OUT) due to external
power transistor miller effect
-500
500
mA
0
25
mA
-0.3
VCC + 0.3
ICC
VCOMP
VOC
VVBUS
VCC current
COMP Pin Voltage
OC Pin Voltage
VBUS Pin Voltage
VDC
VDC Pin Voltage
VZX
ZX Pin Voltage
ICOMP
V
-0.3
7.0
-5
5
mA
COMP Pin Current
IZX
ZX Pin Current
IOC
OC Pin Current
PD
Package Power Dissipation @ TA ≤ +25ºC
---
0.625
W
Thermal Resistance, Junction to Ambient
---
128
ºC/W
TJ
Junction Temperature
-55
150
TS
Storage Temperature
-55
150
TL
Lead Temperature (soldering, 10 seconds)
---
300
Min.
VCCUV+
Max.
VCLAMP
0
10
-1
1
-25
125
RθJA
ºC
Recommended Operating Conditions
For proper operation the device should be used within recommended conditions.
Definition
Symbol
†:
†
VCC
Supply Voltage
ICC
VCC Supply Current
IOC
OC Pin Current
IZX
ZX Pin Current
TJ
Junction Temperature
Units
V
mA
ºC
This IC contains a zener clamp structure between the chip VCC and COM which has a nominal breakdown voltage of 20V. This
supply pin should not be driven by a DC, low impedance power source greater than the VCLAMP specified in the Electrical
Characteristics section.
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© 2012 International Rectifier
6
IRS2500S
Electrical Characteristics
VCC = 14 V +/- 0.25 V, COUT=1000 pF, CVCC=0.1 μF, TA=25 °C unless otherwise specified.
Symbol
Supply Characteristics
Definition
Min
Typ
Max
11.5
12.5
13.5
9.5
10.5
11.5
1.5
2.0
3.0
Units
Test Conditions
VUVHYS
VCC Supply Undervoltage Positive Going
Threshold
VCC Supply Undervoltage Negative Going
Threshold
VCC Supply Undervoltage Lockout
Hysteresis
IQCCUV
UVLO Mode VCC Quiescent Current
---
30
---
uA
VCC Supply Current
---
2.3
5.0
mA
VCC Zener Clamp Voltage
---
20.0
---
V
---
10
---
---
-23
---
---
6.0
---
---
0.25
---
---
0
---
Input bias current
---
---
-1
uA
VBUS=0 to 3V
Gv
Voltage gain
60
80
---
dB
Open loop
GB
Bandwidth
---
1
---
MHz
2.46
2.5
2.54
VCCUV+
VCCUV-
ICC
VCLAMP
VCC = 8V
VBUS=2.5V
PFC off time =
5us
ICC = 10mA
Error Amplifier Characteristics
ICOMP
SOURCE
ICOMP
SINK
COMP Pin Error Amplifier Output Current
Sourcing
COMP Pin Error Amplifier Output Current
Sinking
Error Amplifier Output Voltage Swing (high
VCOMPOH
state)
Error Amplifier Output Voltage Swing (low
VCOMPOL
state)
VCOMPFL Error Amplifier Output Voltage in Fault
T
Mode
IVBUS
mA
V
VVBUS = 2.4V
VCOMP=4.0V
VVBUS = 2.6V
VCOMP=4.0V
VBUS=2.0V
ICOMP=-0.5mA
VBUS=3.0V
ICOMP=+0.5mA
VBUS=3.0V
Control Characteristics
VVBUS
VBUS Internal Reference Voltage
VZX+
ZX Pin Threshold Voltage (Arm)
---
1.6
---
VZX-
ZX Pin Threshold Voltage (Trigger)
---
0.7
---
VZXclamp ZX pin Clamp Voltage (high state)
---
5.2
---
VDCclamp VDC pin Clamp Voltage
---
5.2
---
tBLANK
VCOMP = 4.0V
V
IZX = 1mA
IDC = 1mA
OC pin current-sensing blank time
---
320
---
ns
PFC Watch-dog Pulse Interval
---
400
---
us
tONMIN
PFC Minimum ON time
---
0.3
---
us
tONMAX
PFC Maximum ON Time
10
50
---
us
tWD
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VBUS=2.5V
VCOMP=4.0V
ZX = 0,VCOMP =
4.0V
ZX = 0,VCOMP =
0.25V
ZX = 0,VCOMP =
6.0V,
VDC = 2V
© 2012 International Rectifier
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IRS2500S
Electrical Characteristics (cont’d)
VCC = 14V +/- 0.25V, COUT = 1000pF,
VCOMP = VOC = VBUS = VZX = 0V, TA=25C unless otherwise specified.
Protection Circuitry Characteristics
VOCTH
VVBUSOV
VVBUSOV
HYS
ICOMPOV+
ICOMPOV-
OC Pin Over-current Sense Threshold
VBUS Over-voltage Comparator
Threshold
VBUS Over-voltage Comparator
Hysteresis
Dynamic Over-voltage detection
threshold
0.93
1.1
1.22
V
2.7
50
100
150
30
Dynamic Over-voltage detection reset
mV
Guaranteed by
design
Guaranteed by
design
uA
8
Gate Driver Output Characteristics
VOL
Low-Level Output Voltage
---
0
100
mV
IO = 0
VOH
High-Level Output Voltage
---
0
11
V
IO = 0
tr
Turn-On Rise Time
---
60
110
tf
Turn-Off Fall Time
---
30
70
I0+
Source Current
---
500
---
I0-
Sink Current
---
500
---
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ns
mA
© 2012 International Rectifier
8
IRS2500S
Functional Block Diagram
VCC
OC 4
VOCTH
COM
6
8
Blank Time
UVLO
VBUS 1
VCLAMP
OVP
VVBUS
VCC
VVBUSOV
7
COMP 2
VDC
ON TIME
MODULATOR
3
S
Q
R
Q
VDCCLAMP
S
Q
OUT
Watchdog
Timer
R1
R2 Q
ZX 5
VZXCLAMP
VZX
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© 2012 International Rectifier
9
IRS2500S
Input/Output Pin Equivalent Circuit Diagrams
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© 2012 International Rectifier
10
IRS2500S
Lead Definitions
Symbol
VBUS
COMP
VDC
OC
ZX
COM
OUT
VCC
Description
DC Bus Sensing Input
PFC Error Amplifier Compensation
Full Wave Voltage Input
PFC Current Sensing Input
PFC Zero-Crossing Detection
IC Power & Signal Ground
Gate Drive Output
Logic & Low-Side Gate Driver Supply
VBUS
COMP
VDC
OC
1
2
3
4
IRS2500
Lead Assignments
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8
7
6
5
VCC
OUT
COM
ZX
© 2012 International Rectifier
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IRS2500S
When the switch MPFC is turned on, the inductor
LPFC is connected between the rectified line input
(+) and (-) causing the current in LPFC to increase
linearly. When MPFC is turned off, LPFC is
connected between the rectified line input (+) and
the DC bus capacitor CBUS through diode DPFC.
The stored energy in LPFC is transferred to the
output, supplying a current into CBUS. MPFC is
turned on and off at a high frequency and the
voltage on CBUS charges up to a specified voltage.
The voltage feedback loop of the IRS2500
regulates the output to the desired voltage by
continuously monitoring the DC output and
adjusting the on-time of MPFC accordingly. If the
output voltage is too high, the on-time is decreased
and if it is too low, the on-time is increased. This
negative feedback control loop operates with a slow
loop speed and a low loop gain such that the
average inductor current smoothly follows the lowfrequency line input voltage to obtain high power
factor and low THD.
The loop speed is intentionally slow with respect to
the AC line frequency so that there is no
appreciable change in the on time during a single
line half cycle. This allows the current to follow
shape of the sinusoidal voltage.
Application Information and Additional
Details
Power factor correction is required in many
electrical appliances in order to minimize reactive
current losses in AC power transmission lines. The
degree to which an electronic circuit matches an
ideal purely resistive load is measured by the phase
shift (displacement) between the input voltage and
input current and the amount of current waveform
distortion. In other words how well the shape of the
input current waveform matches the shape of the
sinusoidal input voltage.
The power factor (PF) is defined as the ratio
between real power and apparent power with the
maximum value of 1.0 representing a totally
resistive load where the current waveform shape
matches the voltage waveform shape exactly. The
distortion of the input current waveform is quantified
by the total harmonic distortion (THD), which is the
sum of all harmonic content of the waveform
expressed as a percentage.
An ideal power factor of 1.0 corresponds to zero
phase shift and a THD of 0% representing a purely
sinusoidal input current waveform in phase with the
line voltage. The lower the power factor the more
current is needed to supply the same power to the
load, which results is higher conduction losses in
transmission lines. For this reason it is desirable to
have a high PF and a low THD. To achieve this, the
IRS2500 implements an active power factor
correction (PFC) circuit.
The control method implemented in the IRS2500
may be used in a Boost converter (Figure 8) or a
low power single stage Flyback converter for small
power supplies or LED drivers. The IRS2500
operates in critical-conduction mode (CrCM), also
known as transition mode. This means that during
each switching cycle of the PFC MOSFET, the
circuit waits until the inductor current discharges to
zero before turning the PFC MOSFET on again.
The PFC MOSFET is turned on and off at a much
higher frequency (>10KHz) than the line input
frequency (50 to 60Hz).
LPFC
(+)
DPFC
V, I
t
Figure 9: Sinusoidal line input voltage (solid line),
triangular PFC Inductor current and smoothed
sinusoidal line input current (dashed line) over one
half-cycle of the AC line input voltage.
Corrections to the output voltage therefore require
several line cycles. With a fixed on-time, and an offtime determined by the inductor current discharging
to zero, the result is a system where the switching
frequency is free-running and constantly changing
from a high frequency near the zero crossing of the
AC input line voltage, to a lower frequency at the
peaks (Figure 9).
When the line input voltage is low (near the zero
crossing), the inductor current will increase only a
small amount and the discharge time will be short
resulting in a high switching frequency. When the
input line voltage is high (near the peak), the
inductor current will charge up to a much higher
DC Bus
+
MPFC
CBUS
(-)
Figure 8: Boost converter circuit.
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© 2012 International Rectifier
12
IRS2500S
level and the discharge time will be longer giving a
lower switching frequency.
The PFC control circuit of the IRS2500 (Figure
10) includes six control pins: VBUS, COMP, ZX,
OUT, VDC and OC. The VBUS pin measures the
DC bus voltage through an external resistor voltage
divider. The COMP pin voltage determines the ontime of MPFC and sets the feedback loop response
speed with an external RC integrator. The ZX pin
detects when the inductor current discharges to
zero each switching cycle using a secondary
winding from the PFC inductor. The OUT pin is the
low-side gate driver output for the external
MOSFET, MPFC. The VDC pin senses the line
input cycle providing phase information to control
the on time modulation described in the next
section. The OC pin senses the current flowing
through MPFC and performs cycle-by-cycle overcurrent protection.
VBUS 1
VCC
2.75
5.1V
RZX
CBUS
MPFC
OC
COM
ROC
RVBUS
RDC
(-)
Figure 10:
RS4
2.0V
The off-time of MPFC is determined by the time it
takes the LPFC current to discharge to zero. The
zero current level is detected by a secondary
winding on LPFC that is connected to the ZX pin
through an external current limiting resistor RZX. A
positive-going edge exceeding the internal
threshold VZX+ signals the beginning of the offtime. A negative-going edge on the ZX pin falling
below VZX- will occur when the LPFC current
discharges to zero, which signals the end of the offtime and MPFC is turned on again (Figure 12). The
ZX pin is internally biased to ensure that the voltage
detected from the inductor drops fully to zero before
triggering the next PWM cycle. A wide hysteresis
prevents false triggering by ringing oscillations.
The cycle repeats itself indefinitely until the
IRS2500 is disabled through an over-voltage
condition on the DC bus or if the negative transition
of ZX pin voltage does not occur. Should the
negative edge on the ZX pin not occur, MPFC will
remain off until the watch-dog timer forces a turn-on
of MPFC for an on-time duration programmed by
the voltage on the COMP pin. The watch-dog
pulses occur every 300-400us (tWD) indefinitely
until a correct positive and negative-going signal is
detected at the ZX pin and normal operation is
resumed. Should the OC pin voltage exceed the
VOCTH over-current threshold during the on-time
the gate drive output will turn off. The circuit will
then wait for a negative-going transition on the ZX
pin or a forced turn-on from the watch-dog timer to
turn the output on again.
ZX
COMP
OC
1.2V
Figure 11: IRS2500 detailed PFC control circuit.
RVBUS2
RPFC
4
WATCH
DOG
TIMER
M2
COMP3
ZX 5
RIN
OUT
OUT
R Q
S Q
R1
R2 Q
RVBUS1
PFC
Control
7
Q
On Time
Modulator
C1
DFPC
VDC
S
M1
VDC 3
LPFC
CCOMP
RS3
COMP5
COMP 2
(+)
VBUS
COMP4
2.5V
IRS2500 simplified PFC control
circuit.
The VBUS pin is compared with a fixed internal
2.5V reference voltage for regulating the DC output
voltage (Figure 11). The feedback loop error
amplifier increases or decreases the COMP pin
voltage. The resulting voltage on the COMP pin
sets the threshold for the charging of the internal
timing capacitor (C1, Figure 11) and therefore
determines the on-time of MPFC.
The error amplifier operates at a slow loop speed
preventing rapid changes in PWM duty cycle during
a single input line cycle. This prevents distortion
achieving high power factor and low THD.
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© 2012 International Rectifier
13
IRS2500S
ILPFC
ILPFC
...
OUT
0
...
OUT
pin
0
ZX
near peak region of
rectified AC line
...
VOCTH
OC
near zero-crossing region
of rectified AC line
Figure 13: On-time modulation circuit timing
diagram.
...
Output Over-voltage Protection
The IRS2500 incorporates both static and dynamic
overvoltage protection. Static over voltage
protection monitors the feedback voltage at the
VBUS pin and disables the gate drive output if this
voltage exceeds the target voltage by 8%. This is
activated by an internal comparator set to detect a
threshold of 2.7V, which is 8% above the regulation
threshold of 2.5V.
However, under startup condition or when a load is
removed from the output the error amplifier output
voltage at the COMP pin swings low. Since the
compensation capacitor CCOMP is connected from
this output back to the VBUS input a current will
flow during the COMP voltage transition. This pulls
down the VBUS voltage, which allows the output
voltage to exceed the desired regulation level
during the transition and results in an overshoot
before the voltage at the VBUS input exceeds the
regulation threshold.
In order to compensate for this effect, the IRS2500
includes dynamic detection of the error amplifier
output current. During a swing in the negative
direction the error amplifier output current peaks at
a much high level than the level during steady state
operation. This higher current is internally detected
and triggers the overvoltage protection circuitry
disabling the PWM output until the error amplifier
output has settled to a new level. This prevents the
output voltage from overshooting the desired level
by a significant amount under the transient
conditions described. For this reason the loop
should be designed such that voltage ripple at
COMP is minimized during steady state operation.
Figure 12: Inductor current, OUT pin, ZX pin and
OC pin timing diagram.
On-time Modulation Circuit
A fixed on-time of MPFC over an entire cycle of the
line input voltage produces a peak inductor current
which naturally follows the sinusoidal shape of the
line input voltage. The smoothed, averaged line
input current is in phase with the line input voltage
for high power factor but a high total harmonic
distortion (THD), as well as individual higher
harmonics, of the current are still possible. This is
mostly due to cross-over distortion of the line
current near the zero-crossings of the line input
voltage. To achieve low harmonics that are
acceptable for compliance with international
standards and general market requirements, an
additional on-time modulation circuit has been
added to the PFC control. This circuit dynamically
increases the on-time of MPFC as the line input
voltage nears the zero-crossings (Figure 13). This
causes the peak LPFC current, and therefore the
smoothed line input current, to increase near the
zero-crossings of the line input voltage. This
reduces the amount of cross-over distortion in the
line input current which reduces the THD and
higher harmonics. The on time modulation function
is controlled via the VDC input. The full wave
rectified voltage from the bridge rectifier is divided
down by RIN and RDC to provide an input with a
peak voltage of approximately 1V at 90VAC input
and 3V at 277VAC. CDC is added to remove noise
from the signal, the value is typically 10nF. The on
time modulation function is not required in some
applications. In such cases the VDC input should
be tied to VCC through a 10K resistor.
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© 2012 International Rectifier
14
IRS2500S
PCB Layout Guidelines
For correct operation of the IRS2500, the PCB
should be designed to avoid noise coupling to the
control inputs and ground loops. By following the
recommendations listed here potential issues will be
avoided:
1. The circuit signal and power grounds should be
joined together at one point only. The signal ground
should be a star point located close to the COM pin
of the IRS2500.
2. The point at which the signal ground is connected
to the power ground is recommended to be at the
current sense resistor (ROC) ground.
3. A 0.1μF noise decoupling capacitor should be
located between the VCC and COM pins of the
IRS2500 located as close to the IC as possible.
Figure 14: Layout Example
4. All traces to the VBUS input should be as short as
possible. This means that resistors and capacitors
that are connected to this input should be located as
close to the IRS2500 as possible. The voltage
feedback divider resistor connected to COM should
be connected to a signal ground close to the COM
pin.
Figure 14 shows a layout where the IRS2500 is
located on the bottom side of the PCB. The bottom
side traces are shown in red and the top side traces
in pale blue. The circuit power ground can be seen
at the C2 GND node with the signal ground star
point is located at the junction between RPFC6 and
CPFC4 to the left of the IRS2500 (IC1). (Note that
the component designators in this example are
different from those used in the datasheet
schematics)
The traces from IC1 pin 6, RPFC3 and CPFC1 (the
VDC divider low side) all run directly to the star
point without crossing any other grounds. The
signal ground is connected to the power ground at
the current sense resistor. A large trace can be
seen running from the star point off the left to where
the MOSFET is situated (not shown). This is the
single point where the signal and power grounds
are connected. The VCC supply decoupling
capacitor shown in this example is CPFC4, which is
located very close to the IRS2500 and grounded
directly to the signal ground star point.
Traces leading to pin 1 (VBUS) are all short and
components connected to pin 1 (RPFC5, RPFC6
and RPFC7) are all located close to IC1. There are
no traces connected to high voltage switching
nodes located anywhere close to pin 1.
The board layout shown in figure 14 complies with
all of the guidelines stated enabling optimum
operation of the IRS2500.
5. Traces carrying high voltage switching signals
such as those connected to the MOSFET drain or
gate drive signals should not be located close to
traces connected directly to the VBUS input.
6. The divider network resistor (RDC) and filter
capacitor (CDC) connected to the VDC input of the
IRS2500 should be located as closely to the IC as
possible with the grounded end connected to the
circuit signal ground.
7. The compensation capacitor CCOMP should be
located close to the IRS2500 with short traces
leading to the VBUS and COMP pins.
8. The over current detection filter resistor (ROC)
and capacitor (COC) should be located as close to
the IRS2500 as possible with COC connected to the
circuit signal ground.
9. The zero crossing detection resistor should be
located close to the IRS2500 if possible to prevent
possible noise appearing at this input.
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© 2012 International Rectifier
15
IRS2500S
PFC Design Equations (for Boost Converter)
Step1: Calculate PFC inductor value:
LPFC =
2
(VBUS − 2 ⋅ VACMIN ) ⋅VAC MIN
⋅η
2 ⋅ f MIN ⋅ POUT ⋅VBUS
[Henries]
(1)
where,
VBUS
VAC MIN
η
f MIN
POUT
=
=
=
=
=
DC bus voltage
Minimum rms AC input voltage
PFC efficiency (typically 0.95)
Minimum PFC switching frequency at minimum AC input voltage
Ballast output power
Step 2: Calculate peak PFC inductor current:
i PK =
2 ⋅ 2 ⋅ POUT
VAC MIN ⋅η
[Amps Peak]
(2)
Note: The PFC inductor must not saturate at i PK over the specified ballast operating temperature range. Proper core sizing
and air-gapping should be considered in the inductor design.
Step 3: Calculate PFC over-current resistor ROC value:
ROC =
VOCTH
i PK
[Ohms]
where VOCTH = 1.1V
(3)
Step 4: Calculate start-up resistor RVCC value:
RVCC =
VAC MIN
+ 10
PK
[Ohms]
IQCCUV
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(4)
© 2012 International Rectifier
16
IRS2500S
14
2.5
VCCUV+
12
2
VCCUV‐
ICC ( mA)
VCCUV (+/‐)
10
8
6
4
1.5
1
0.5
2
0
0
‐25
‐25
0
25
50
75
100
0
25
50
75
100
125
125
TEMP C
TEMP C
Graph 2: ICC vs. Temperature
Graph 1: VCCUV+ vs. Temperature
22
120
21.8
21.6
100
VCLAMP (V)
IQCCUV (uA)
21.4
80
60
40
21.2
21
20.8
20.6
20.4
20
20.2
0
20
‐25
0
25
50
75
100
125
‐25
0
25
50
75
100
125
TEMP C
TEMP C
Graph 4: VCLAMP vs. Temperature
Graph 3: IQCCUV vs. Temperature
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© 2012 International Rectifier
17
IRS2500S
500
450
WATCH DOG INTERVAL (us)
3
2.9
2.8
VBUS (V)
2.7
2.6
2.5
2.4
2.3
2.2
2.1
400
350
300
250
200
150
100
50
2
0
‐25
0
25
50
75
100
125
‐25
0
25
50
75
100
125
TEMP C
TEMP C
Graph 6: Watch dog interval vs. Temperature
Graph 5: VBUS reference vs. Temperature
50
49
PFC Ton max (US)
48
47
46
45
44
43
42
41
40
‐25
0
25
50
75
100
125
TEMP C
Graph 7: PFC Ton max (us)
Package Details
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© 2012 International Rectifier
18
IRS2500S
www.irf.com
© 2012 International Rectifier
19
IRS2500S
Tape and Reel Details
LOADED TAPE FEED DIRECTION
A
B
H
D
F
C
NOTE : CONTROLLING
DIM ENSION IN M M
E
G
CARRIER TAPE DIMENSION FOR
Metric
Code
Min
Max
A
7.90
8.10
B
3.90
4.10
C
11.70
12.30
D
5.45
5.55
E
6.30
6.50
F
5.10
5.30
G
1.50
n/a
H
1.50
1.60
8SOICN
Imperial
Min
Max
0.311
0.318
0.153
0.161
0.46
0.484
0.214
0.218
0.248
0.255
0.200
0.208
0.059
n/a
0.059
0.062
F
D
C
B
A
E
G
H
REEL DIMENSIONS FOR 8SOICN
Metric
Code
Min
Max
A
329.60
330.25
B
20.95
21.45
C
12.80
13.20
D
1.95
2.45
E
98.00
102.00
F
n/a
18.40
G
14.50
17.10
H
12.40
14.40
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Imperial
Min
Max
12.976
13.001
0.824
0.844
0.503
0.519
0.767
0.096
3.858
4.015
n/a
0.724
0.570
0.673
0.488
0.566
© 2012 International Rectifier
20
IRS2500S
Part Marking Information
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© 2012 International Rectifier
21
IRS2500S
Ordering Information
Standard Pack
Base Part Number
Package Type
Complete Part Number
Form
IRS2500
SOIC8
Quantity
Tube/Bulk
95
IRS2500SPBF
Tape and Reel
2500
IRS2500STRPBF
The information provided in this document is believed to be accurate and reliable. However, International Rectifier assumes no
responsibility for the consequences of the use of this information. International Rectifier assumes no responsibility for any infringement
of patents or of other rights of third parties which may result from the use of this information. No license is granted by implication or
otherwise under any patent or patent rights of International Rectifier. The specifications mentioned in this document are subject to
change without notice. This document supersedes and replaces all information previously supplied.
For technical support, please contact IR’s Technical Assistance Center
http://www.irf.com/technical-info/
WORLD HEADQUARTERS:
233 Kansas St., El Segundo, California 90245
Tel: (310) 252-7105
www.irf.com
© 2012 International Rectifier
22
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