ETC 73K324BL

73K324BL
V.22bis/V.22/V.21/V.23 Bell 212A
Single-Chip Modem w/Integrated Hybrid
April 2000
DESCRIPTION
FEATURES
The 73K324BL is a highly integrated single-chip
modem IC which provides the functions needed to
construct a V.22bis compatible modem, capable of
2400 bps full-duplex operation over dial-up lines. The
73K324BL is an enhancement of the 73K324L singlechip modem which adds the hybrid hook switch
control, and driver to the 73K324L. The 73K324BL
integrates analog, digital, and switched-capacitor
array functions on a single chip, offering excellent
performance and a high level of functional integration
in a 32-Lead PLCC and 44-Lead TQFP package.
•
Includes features of 73K324L single-chip
modem
•
On chip 2-wire/4-wire hybrid driver and off
hook relay buffer
•
One-chip multi-mode V.22bis/V.22/V.21/V.23
and Bell 212A compatible modem data pump
•
FSK (300/1200 bps), DPSK (600, 1200 bps), or
QAM (2400 bps) encoding
•
Semi-
The 73K324BL operates from a single +5 V supply for
low power consumption.
Software compatible with other
conductor K-Series one-chip modems
•
micro-
The 73K324BL is designed to appear to the systems
designer as a microprocessor peripheral, and will
easily interface with popular single-chip microprocessors (80C51 typical) for control of modem
functions through its 8-bit multiplexed address/data
bus or via an optional serial control bus. An ALE
control simplifies address demultiplexing. Data
communications normally occur through a separate
serial port.
Interfaces directly with standard
processors (80C51 typical)
•
•
Parallel or serial bus for control
•
All asynchronous and synchronous operating
modes (internal, external, slave)
(continued)
Selectable
asynch/synch
with
internal
buffer/debuffer and scrambler/descrambler
functions
(continued)
BLOCK DIAGRAM
DTMF,
ANSWER,
GUARD &
CALLING
TONE
GENERATOR
OH
FSK
MODULATOR
BUFFER
SCRAMBLER
DI-BIT/
QUAD-BIT
ENCODER
FIR
PULSE
SHAPER
QAM/
DPSK
MODULATOR
FILTER
EQUALIZER
FILTER
ATTENUATOR
8-BIT
µP
BUS
INTERFACE
TXA1
2W/4W
HYBRID
DEBUFFER
TXD
RXD
DESCRAMBLER
DI-BIT/
QUAD-BIT
DECODER
DIGITAL
SIGNAL
PROCESSOR
RECEIVE
FUNCTIONS
A/D
TONE
DETECTION
PASS
BAND
FILTER
EQUALIZER
FIXED
DEMODULATOR
SERIAL
INTERFACE
TXA2
RXA
FILTER
AGC
ANTI-ALIAS
FILTER
GAIN
BOOST
73K324BL
V.22bis/V.22/V.21/V.23 Bell 212A
Single-Chip Modem w/Integrated Hybrid
DESCRIPTION (continued)
FEATURES (continued)
The 73K324BL is pin and software compatible with
the 73K222BL and 73K224BL, allowing system
upgrades and product differentiation with a single
component change.
The 73K324BL is designed to be a complete V.22bis
compatible modem on a chip. The complete modem
requires only the addition of the phone line interface,
a control microprocessor, and RS-232 level
converter for a typical system. Many functions were
included to simplify implementation of typical modem
designs. In addition to the basic 2400 bps QAM,
600/1200 bps DPSK and 300/1200 bps FSK
modulator/demodulator sections, the device also
includes
synch/asynch
converters,
scrambler/descrambler, call progress tone detect,
DTMF tone generator capabilities and handshake
pattern detectors. Test features such as analog loop,
digital loop, and remote digital loopback are
supported. Internal pattern generators are also
included for self-testing functional Description
2
•
Adaptive
equalization
performance over all lines
•
Programmable transmit attenuation (16 dB, 1
dB
steps),
selectable
receive
boost
(+18 dB)
•
Call
progress,
carrier,
answer
tone,
unscrambled mark, S1, and signal quality
monitors
•
DTMF, answer,
generators
•
Test modes available: ALB, DL, RDL, mark,
space, alternating bit, S1 pattern
•
CMOS technology for low power consumption
(typically 100 mW @ 5 V) with power-down
mode (15 mW @ 5 V)
•
TTL and CMOS compatible inputs and outputs
SCT,
for
and
optimum
guard
tone
73K324BL
V.22bis/V.22/V.21/V.23 Bell 212A
Single-Chip Modem w/Integrated Hybrid
FUNCTIONAL DESCRIPTION
FSK MODULATOR/DEMODULATOR
HYBRID AND RELAY DRIVER
The FSK modulator produces a frequency modulated
analog output signal using two discrete frequencies to
represent the binary data. V.21 mode uses 980 and
1180 Hz (originate, mark and space) or 1650 and
1850 Hz (answer, mark and space) are used in V.21
mode. V.23 mode uses 1300 and 2100 Hz for the
main channel and 390 and 450 Hz for the back
channel. Demodulation involves detecting the
received frequencies and decoding them into the
appropriate binary value. The rate converter and
scrambler/descrambler are automatically bypassed in
the FSK modes.
To make designs more cost effective and space
efficient, the 73K324BL includes the 2-wire to 4-wire
hybrid with sufficient drive to interface directly to the
telecom coupling transformers. In addition, an off
hook relay driver with 40 mA drive capability is also
included to allow use of commonly available
mechanical telecom relays.
QAM MODULATOR/DEMODULATOR
The 73K324BL encodes incoming data into quad-bits
represented by 16 possible signal points with specific
phase and amplitude levels. The base-band signal is
then filtered to reduce intersymbol interference on the
band limited telephone network. The modulator
transmits this encoded data using either a 1200 Hz
(originate mode) or 2400 Hz (answer mode) carrier.
The demodulator, although more complex, essentially
reverses this procedure while also recovering the
data clock from the incoming signal. Adaptive
equalization corrects for varying line conditions by
automatically
changing
filter
parameters
to
compensate for line characteristics.
PASSBAND FILTERS AND EQUALIZERS
High and low band filters are included to shape the
amplitude and phase response of the transmit and
receive signals and provide compromise delay
equalization and rejection of out-of-band signals.
Amplitude and phase equalization are necessary to
compensate for distortion of the transmission line and
to reduce intersymbol interference in the band limited
receive signal. The transmit signal filtering
corresponds to a 75% square root of raised Cosine
frequency response characteristic.
DPSK MODULATOR/DEMODULATOR
ASYNCHRONOUS MODE
The 73K324BL modulates a serial bit stream into
di-bit pairs that are represented by four possible
phase shifts as prescribed by the Bell 212A/V.22
standards. The base-band signal is then filtered to
reduce intersymbol interference on the bandlimited 2wire PSTN line. Transmission occurs on either a 1200
Hz (originate mode) or 2400 Hz carrier (answer
mode).
Demodulation is the reverse of the
modulation process, with the incoming analog signal
eventually decoded into di-bits and converted back to
a serial bit stream. The demodulator also recovers
the clock which was encoded into the analog signal
during modulation. Demodulation occurs using either
a 1200 Hz carrier (answer mode or ALB originate
mode) or a 2400 Hz carrier (originate mode or ALB
answer mode). The 73K324BL use a phase locked
loop coherent demodulation technique that offers
excellent performance. Adaptive equalization is also
used in DPSK modes for optimum operation with
varying line conditions.
The asynchronous mode is used for communication
with asynchronous terminals which may communicate
at 600,1200, or 2400 bps +1%, -2.5% even though
the modem’s output is limited to the nominal bit rate
±.01% in DPSK and QAM modes. When transmitting
in this mode the serial data on the TXD input is
passed through a rate converter which inserts or
deletes stop bits in the serial bit stream in order to
output a signal that is the nominal bit rate ±.01%. This
signal is then routed to a data scrambler and into the
analog modulator where quad-bit/di-bit encoding
results in the output signal. Both the rate converter
and scrambler can be bypassed for handshaking, and
synchronous operation as selected. Received data is
processed in a similar fashion except that the rate
converter now acts to reinsert any deleted stop bits
and output data to the terminal at no greater than the
bit rate plus 1%. An incoming break signal (low
through two characters) will be passed through
without incorrectly inserting a stop bit.
3
73K324BL
V.22bis/V.22/V.21/V.23 Bell 212A
Single-Chip Modem w/Integrated Hybrid
FUNCTIONAL DESCRIPTION (continued)
SERIAL CONTROL INTERFACE MODE
The synch/asynch converter also has an extended
Overspeed mode which allows selection of an output
overspeed range of either +1% or +2.3%. In the
extended overspeed mode, stop bits are output at 7/8
rising edge of TXCLK the normal width.
The serial Command mode allows access to the
73K324BL control and status registers via a serial
control port. In this mode the AD0, AD1, and AD2
lines provide register addresses for data passed
through the AD7 (DATA) pin under control of the RD
and WR lines. A read operation is initiated when the
RD line is taken low. The next eight cycles of EXCLK
will then transfer out eight bits of the selected
addresss location LSB first. A write takes place by
shifting in eight bits of data LSB first for eight
consectuive cycles of EXCLK. WR is then pulsed low
and data transfer into the selected register occurs on
the rising edge of WR.
Both the synch/asynch rate converter and the data
descrambler are automatically bypassed in the FSK
modes.
SYNCHRONOUS MODE
Synchronous operation is possible only in the QAM or
DPSK modes. Operation is similar to that of the
asynchronous mode except that data must be
synchronized to a provided clock and no variation in
data transfer rate is allowable. Serial input data
appearing at TXD must be valid on the rising edge of
TXCLK.
DTMF GENERATOR
The DTMF generator controls the sending of the
sixteen standard DTMF tone pairs. The tone pair sent
is determined by selecting transmit DTMF (bit D4)
and the 4 DTMF bits (D0-D3) of the Tone Register.
Transmission of DTMF tones from TXA is gated by
the transmit enable bit of CR0 (bit D1) as with all
other analog signals.
TXCLK is an internally derived 1200 or 2400 Hz
signal in internal mode and is connected internally to
the RXCLK pin in slave mode. Receive data at the
RXD pin is clocked out on the falling edge of RXCLK.
The asynch/synch converter is bypassed when
synchronous mode is selected and data is transmitted
at the same rate as it is input.
PARALLEL BUS CONTROL INTERFACE MODE
Eight 8-bit registers are provided for control, option
select, and status monitoring. These registers are
addressed with the AD0, AD1, and AD2 multiplexed
address lines (latched by ALE) and appear to a
control microprocessor as seven consecutive memory
locations. Six control registers are read/write memory.
The detect and ID registers are read only and cannot
be modified except by modem response to monitored
parameters.
4
73K324BL
V.22bis/V.22/V.21/V.23 Bell 212A
Single-Chip Modem w/Integrated Hybrid
PIN DESCRIPTION
POWER
NAME
PIN
TYPE
DESCRIPTION
GND
1
I
System ground
VDD
16
I
Power supply input, 5 V ±10% Bypass with 0.1 and 22 µF
capacitors to GND.
VREF
31
O
An internally generated reference voltage. Bypass with 0.1
µF capacitor to ground.
ISET
28
I
Chip current reference. Sets bias current for op-amps. The
chip current is set by connecting this pin to VDD through a
2 MΩ resistor. ISET should be bypassed to GND with a
0.1 µF capacitor.
PARALLEL MICROPROCESSOR CONTROL INTERFACE MODE
ALE
13
I
ADDRESS LATCH ENABLE: The falling edge of ALE latches
the address on AD0-AD2 and the chip select on CS.
5-12
I/O
ADDRESS/DATA BUS: These bi-directional tri-state
multiplexed lines carry information to and from the internal
registers.
CS
23
I
CHIP SELECT: A low on this pin during the falling edge of
ALE allows a read cycle or a write cycle to occur. AD0-AD7
will not be driven and no registers will be written if CS
(latched) is not active. The state of CS is latched on the
falling edge of ALE.
CLK
2
O
OUTPUT CLOCK: This pin is selectable under processor
control to be either the crystal frequency (for use as a
processor clock) or 16 times the data rate for use as a baud
rate clock in DPSK modes only. The pin defaults to the
crystal frequency on reset.
INT
20
O
INTERRUPT: This open drain output signal is used to inform
the processor that a detect flag has occurred. The processor
must then read the Detect Register to determine which detect
triggered the interrupt. INT will stay low until the processor
reads the detect register or does a full reset.
RD
15
I
READ: A low requests a read of the 73K324BL internal
registers. Data can not be output unless both RD and the
latched CS are active or low.
RESET
30
I
RESET: An active high signal on this pin will put the chip into
an inactive state. All Control Register bits (CR0, CR1, tone)
will be reset. The output of the CLK pin will be set to the
crystal frequency. An internal pull-down resistor permits
power-on-reset using a capacitor to VDD.
AD0-AD7
5
73K324BL
V.22bis/V.22/V.21/V.23 Bell 212A
Single-Chip Modem w/Integrated Hybrid
PARALLEL MICROPROCESSOR INTERFACE (continued)
NAME
PIN
TYPE
WR
14
I
DESCRIPTION
WRITE: A low on this informs the 73K324BL that data is
available on AD0-AD7 for writing into an internal register.
Data is latched on the rising edge of WR. No data is written
unless both WR and the latched CS are low.
SERIAL MICROPROCESSOR CONTROL INTERFACE MODE
NAME
PIN
TYPE
AD0-AD2
5-7
I
REGISTER ADDRESS SELECTION: These lines carry
register addresses and should be valid during any read or
write operation.
DATA (AD7)
12
I/O
SERIAL CONTROL DATA: Data for a read/write operation is
clocked in or out on the falling edge of the EXCLK pin. The
direction of data flow is controlled by the RD pin. RD low
outputs data. RD high inputs data.
RD
15
I
READ: A low on this input informs the 73K324BL that data or
status information is being read by the processor. The falling
edge of the RD signal will initiate a read from the addressed
register. The RD signal must continue for eight falling edges
of EXCLK in order to read all eight bits of the referenced
register. Read data is provided LSB first. Data will not be
output unless the RD signal is active.
WR
14
I
WRITE: A low on this input informs the 73K324BL that data
or status information has been shifted in through the DATA
pin and is available for writing to an internal register. The
normal procedure for a write is to shift in data LSB first on the
DATA pin for eight consecutive falling edges of EXCLK and
then to pulse WR low. Data is written on the rising edge of
WR.
NOTE:
DESCRIPTION
The serial control mode is provided by tying ALE high and CS low. In this configuration AD7 becomes
DATA and AD0, AD1 and AD2 become the register address.
6
73K324BL
V.22bis/V.22/V.21/V.23 Bell 212A
Single-Chip Modem w/Integrated Hybrid
DTE USER
NAME
PIN
TYPE
DESCRIPTION
EXCLK
22
I
EXTERNAL CLOCK: This signal is used in synchronous
transmission when the external timing option has been
selected. In the external timing mode the rising edge of
EXCLK is used to strobe synchronous DPSK transmit data
applied to on the TXD pin. Also used for serial control
interface.
RXCLK
26
O
RECEIVE CLOCK: The falling edge of this clock output is
coincident with the transitions in the serial received data
output. The rising edge of RXCLK can be used to latch the
valid output data. RXCLK will be valid as long as a carrier is
present.
RXD
25
O
RECEIVED DATA OUTPUT: Serial receive data is available
on this pin. The data is always valid on the rising edge of
RXCLK when in synchronous mode. RXD will output
constant marks if no carrier is detected.
TXCLK
21
O
TRANSMIT CLOCK: This signal is used in synchronous
transmission to latch serial input data on the TXD pin. Data
must be provided so that valid data is available on the rising
edge of the TXCLK. The transmit clock is derived from
different sources depending upon the synchronization mode
selection. In internal mode the clock is generated internally.
In external mode TXCLK is phase locked to the EXCLK pin.
In slave mode TXCLK is phase locked to the RXCLK pin.
TXCLK is always active.
TXD
24
I
TRANSMIT DATA INPUT: Serial data for transmission is
applied on this pin. In synchronous modes, the data must be
valid on the rising edge of the TXCLK clock. In asynchronous
modes (1200/600 bps or 300/1200 baud) no clocking is
necessary. DPSK data must be 1200/600 bps +1%, -2.5% or
+2.3%, -2.5 % in extended over speed mode.
.
7
73K324BL
V.22bis/V.22/V.21/V.23 Bell 212A
Single-Chip Modem w/Integrated Hybrid
PIN DESCRIPTION (continued)
ANALOG INTERFACE AND OSCILLATOR
NAME
PIN
TYPE
RXA
32
I
Received modulated analog signal input from the telephone
line interface.
TXA1 / TXA 2
18 / 17
O
(differential) Transmit Analog. These pins provide the analog
output signals to be transmitted to the telephone line. The
drivers will differentially drive the impedance of the line
transformer and the line matching resistor. An external hybrid
can also be built using TXA1 as a single ended transmit
signal.
XTL1 / XTL2
3/4
I
These pins are for the internal crystal oscillator requiring a
11.0592 MHz parallel mode crystal. Load capacitors should
be connected from XTL1 and XTL2 to ground. XTL2 can also
be driven from an external clock.
27
O
OFF-HOOK RELAY DRIVER: This signal is an open drain
output capable of sinking 40 mA and is used for controlling a
relay. The output is the complement of the OH register bit in
the ID Register.
OH
DESCRIPTION
.
8
73K324BL
V.22bis/V.22/V.21/V.23 Bell 212A
Single-Chip Modem w/Integrated Hybrid
REGISTER DESCRIPTIONS
of monitored modem status conditions. TR, the tone
control register, controls the DTMF generator,
answer and guard tones and RXD output gate used
in the modem initial connect sequence. CR2 is the
primary DSP control interface and CR3 controls
transmit attenuation and receive gain adjustments.
All registers are read/write except for DR and ID
which are read only. Register control and status bits
are identified below:
Eight 8-bit internal registers are accessible for
control and status monitoring. The registers are
accessed in read or write operations by addressing
the AD0, AD1 and AD2 lines in serial mode, or in
parallel mode. The address lines and CS are latched
by ALE in the parallel mode. Register CR0 controls
the method by which data is transferred over the
phone line. CR1 controls the interface between the
microprocessor and the 73K324BL internal state.
DR is a detect register which provides an indication
REGISTER BIT SUMMARY
ADDRESS
REGISTER
AD-A0
D7
D6
D5
D4
D3
D2
D1
D0
MODULATION
OPTION
MODULATION
TYPE
1
MODULATION
TYPE
0
TRANSMIT
MODE
2
TRANSMIT
MODE
1
TRANSMIT
MODE
0
TRANSMIT
ENABLE
ANSWER/
ORIGINATE
TRANSMIT
PATTERN
1
TRANSMIT
PATTERN
0
ENABLE
DETECT
INTERRUPT
BYPASS
SCRAMBLER
CLK
CONTROL
RESET
TEST MODE
1
TEST MODE
0
RECEIVE
LEVEL
PATTERN
S1 DET
RECEIVE
DATA
UNSCR.
MARK
DETECT
CARRIER
DETECT
SPECIAL
TONE
DETECT
CALL
PROGRESS
DETECT
SIGNAL
QUALITY
CONTROL
REGISTER
0
CR0
000
CONTROL
REGISTER
1
CR1
001
DR
010
TONE
CONTROL
REGISTER
011
RXD
OUTPUT
CONTROL
TRANSMIT
GUARD
TONE
TRANSMIT
ANSWER
TONE
TRANSMIT
DTMF
DTMF 3
TR
DTMF2/
4W/FDX
DTMF1/
EXTENDED
OVERSPEED
DTMF0/
GUARD/
ANSWER
CONTROL
REGISTER
2
100
0
SPECIAL
REGISTER
ACCESS
CALL
INITIALIZE
TRANSMIT
S1
16 WAY
CR2
RESET
DSP
TRAIN
INHIBIT
EQUALIZER
ENABLE
CONTROL
REGISTER
3
CR3
101
TRISTATE
TX/RXCLK
OH
RECEIVE
GAIN
BOOST
TRANSMIT
ATTEN.
3
TRANSMIT
ATTEN.
2
TRANSMIT
ATTEN.
1
TRANSMIT
ATTEN.
0
SPECIAL
REGISTER
SR
101
0
TX BAUD
CLOCK
RX UNSCR.
DATA
0
TXD
SOURCE
SQ
SELECT 1
SQ
SELECT 0
0
ID
REGISTER
ID
110
ID
ID
ID
ID
X
X
X
1
DETECT
REGISTER
NOTE:
TXDALT
When a register containing reserved control bit is written into, the reserved bits must be programmed as
0’s.
X = Undefined, mask in software
9
73K324BL
V.22bis/V.22/V.21/V.23 Bell 212A
Single-Chip Modem w/Integrated Hybrid
REGISTER ADDRESS TABLE
ADDRESS
REGISTER
CONTROL
REGISTER
0
CR0
DATA BIT NUMBER
AD2 - AD0
D7
D6
D5
D4
D3
D2
D1
D0
000
MODULATION
OPTION
MODULATION
TYPE
1
MODULATION
TYPE
0
TRANSMIT
MODE
2
TRANSMIT
MODE
1
TRANSMIT
MODE
0
TRANSMIT
ENABLE
ANSWER/
ORIGINATE
QAM: 0 = 2400 BIT/S
DPSK: 0=1200 BIT/S
1 = 600 BIT/S
FSK: 0 = V.23
1 = V.21
CONTROL
REGISTER
1
CR1
001
TRANSMIT
PATTERN
1
10=QA,
00=DPSK
01=FSK
TRANSMIT
PATTERN
0
00 = TX DATA
01 = TX ALTERNATE
10 = TX MARK
11 = TX SPACE
DETECT
REGISTER
READ ONLY
DR
010
RECEIVE
LEVEL
INDICATOR
0000 = PWR DOWN
0001 = INT SYNCH
0010 = EXT SYNCH
0011 = SLAVE SYNCH
0100 = ASYNCH 8 BITS/CHAR
0101 = ASYNCH 9 BITS/CHAR
0110 = ASYNCH 10 BITS/CHAR
0111 = ASYNCH 11 BITS/CHAR
1X00 = FSK
ENABLE
DETECT
INTERRUPT
0 = DISABLE
1 = ENABLE
S1
PATTERN
DETECT
RECEIVE
DATA
BYPASS
SCRAMBLER
UNSCR.
MARKS
DETECT
TR
011
RXD
OUTPUT
CONTROL
RXD PIN
0 = NORMAL
1 = OPEN
CONTROL
REGISTER
2
CONTROL
REGISTER
3
CR2
CR3
100
101
0
TXDALT
ALTERNATE
TRANSMIT
DATA
SOURCE
SPECIAL
REGISTER
SR
101
0
TRANSMIT
GUARD/
TONE
TRANSMIT
ANSWER
TONE
0 = OFF
1 = ON
0 = OFF
1 = ON
SPECIAL
REGISTER
ACCESS
CALL
INTIALIZE
CLK
CONTROL
CARRIER
DETECT
0 = DATA
CARRIER
1=TX DTMF
TRANSMIT
S1
16 WAY
RECEIVE
GAIN
BOOST
TRANSMIT
ATTEN.
3
0=NORMAL
1=TRISTATE
TX BAUD
CLOCK
OUTPUTS
TXBAUD
CLOCK
0=OH RELAY
0=NO BOOST
DRIVER OPEN 1=18 dB BOOST
1=OH OPEN
DRAIN
DRIVER PULLING
LOW
RX UNSCR.
DATA
CP
TONE
DETECT
0
DTMF1/
EXTENDED
OVERSPEED
DTMF0/
GUARD/
ANSWER/
CALLING/SCT
GUARD:
0-1800 Hz
1-550 Hz
ANSWER: 0-2225 Hz
1-2100 Hz
CALLING: 0-1300 Hz
SCT:
1-900 Hz
TRAIN
INHIBIT
0=ADAPT EQ
ACTIVE
1=ADAPT EQ
FROZEN
TRANSMIT
ATTEN.
1
EQUALIZER
ENABLE
0=ADAPT EQ
IN INIT
1=ADAPT EQ
OK TO ADAPT
TRANSMIT
ATTEN.
0
0000-1111,SETS
TRANSMIT ATTENUATOR
16 dB RANGE
DEFAULT=0100 -10 dBm0
TXD
SOURCE
0=TXD PIN
1=TXALT BIT
OUTPUTS
UNSCR.
DATA
TRANSMIT
ATTEN.
2
SIGNAL
QUALITY
INDICATOR
0=GOOD
1=BAD
RESET
DSP
0=DSP
INACTIVE
1=DSP
ACTIVE
TEST
MODE
0
00 = NORMAL
01 = ANALOG LOOPBACK
10 = REMOTE DIGITAL
LOOPBACK
11 = LOCAL DIGITAL
LOOPBACK
4 BIT CODE FOR 1 OF 16
DUAL TONE COMBINATIONS
0=RX=TX
1=RX=16WAY
OH
ANSWER
TONE
DETECT
DTMF2/
4W/FDX
DTMF3
0=NORMAL
0=ACCESS CR3 0=DSP IN
DEMOD MODE
DOTTING
1=ACCESS
1=DSP IN CALL
1=S1
SPECIAL
PROGRESS
REGISTER
MODE
TRISTATE
TX/RXCLK
TEST
MODE
1
RESET
0 = CONDITION NOT DETECTED
1 = CONDITION DETECTED
TRANSMIT
DTMF
In V.21, V.22, V.22bis
0=ANSWER
1=ORIGINATE
In V.23:
0=BC XMIT
1=MC XMIT
0 = NORMAL
0 = XTAL
0 = NORMAL
1 = BYPASS
1 = 16 X DATA
1 = RESET
SCRAMBLER RATE OUTPUT
AT CLK PIN IN
QAM/DPSK MODE
ONLY
0=SIGNAL
0=NOT PRESENT OUTPUTS
BELOW
1=PATTERN
RECEIVED
THRESHOLD
FOUND
DATA STREAM
1=ABOVE
THRESHOLD
TONE
CONTROL
REGISTER
0 = DISABLE
TXA OUTPUT
1 = ENABLE
TXA OUTPUT
SQ
SELECT 1
SQ
SELECT 0
0
00 10 -5 BER
01 10 -6 BER
10 10 -4 BER
11 10 -3 BER
ID
REGISTER
READ ONLY
10
110
00XX=73K212AL, 322L, 321L
01XX=73K221AL, 302L
10XX=73K222AL, 222BL
1100=73K224L
1110=73K324L
1100=73K224BL
1110=73K324BL
1
1
1
0
0 = Only write zeros to these locations
X = Undefined, mask in software
10
X
X
X
X
73K324BL
V.22bis/V.22/V.21/V.23 Bell 212A
Single-Chip Modem w/Integrated Hybrid
CONTROL REGISTER 0
CR0
000
BIT
D0
D7
D6
MODUL.
OPTION
MODUL.
TYPE 1
NAME
D5
D4
D3
D2
MODUL. TRANSMIT TRANSMIT TRANSMIT
TYPE 0
MODE 2
MODE 1
MODE 0
CONDITION
DESCRIPTION
Answer/
0
D1
D0
TRANSMIT
ENABLE
ANSWER/
ORIGINATE
Selects answer mode (transmit in high band, receive
Originate
in low band) or in V.23 HDX mode, receive at 1200 bps
and transmit at 75 bps.
1
Selects originate mode (transmit in low band, receive in
high band) or in V.23 HDX mode, receive at 1200 bps
and transmit at 75 bps.
Note: This bit works with Tone Register bits D0 and D6
to program special tones detected in the Detect Register.
See Detect and Tone Registers.
D1
Transmit
0
Disables transmit output at TXA1 & TXA2
Enable
1
Enables transmit output at TXA1 & TXA2
Note: Transmit enable must be set to 1 to allow
activation of answer tone or DTMF.
D5,D4
Transmit
D3,D2
Mode
D5 D4 D3 D2
0
0
0
0
Selects Power down mode. All functions disabled except
digital interface.
0
0
0
1
Internal synchronous mode in this mode TXCLK is an
internally derived 600,1200 or 2400 Hz signal. Serial
input data appearing at TXD must be valid on the rising
edge of TXCLK. Receive data is clocked out of RXD on
the falling edge of RXCLK.
0
0
1
0
External synchronous mode. Operation is identical to
internal synchronous, but TXCLK is connected internally
to EXCLK pin, and a 600, 1200 or 2400 Hz clock must be
supplied externally.
0
0
1
1
Slave synchronous mode Same operation as other
synchronous modes TXCLK is connected internally to
the RXCLK pin in this mode.
0
1
0
0
Selects a synchronous mode 8 bits/character (1 start bit,
6 data bits, 1 stop bit).
0
1
0
1
Selects asynchronous mode - 9 bits/character (1 start bit,
7 data bits, 1 stop bit).
0
1
1
0
Selects asynchronous mode - 10 bits/character (1 start
bit, 8 data bits, 1 stop bit).
0
1
1
1
Selects asynchronous mode - 11 bits/character (1 start
bit, 8 data bits, 1 stop bit) or 2 stop bits)..
1
X
0
0
Selects FSK operation.
11
73K324BL
V.22bis/V.22/V.21/V.23 Bell 212A
Single-Chip Modem w/Integrated Hybrid
CONTROL REGISTER 0 (continued)
CR0
000
BIT
D6,D5
D7
D6
MODUL.
OPTION
MODUL.
TYPE 1
NAME
Modulation
Type
D7
Modulation
Option
D5
D4
D3
D2
MODUL. TRANSMIT TRANSMIT TRANSMIT
TYPE 0
MODE 2
MODE 1
MODE 0
CONDITION
DESCRIPTION
D1
D0
TRANSMIT
ENABLE
ANSWER/
ORIGINATE
D6 D5
1
0
QAM
0
0
DPSK
0
1
FSK
0
QAM selects 2400 bps. DPSK selects 1200 bps.
selects 103 mode.
1
DPSK selects 600 bps.
FSK selects V.21 mode.
12
FSK
73K324BL
V.22bis/V.22/V.21/V.23 Bell 212A
Single-Chip Modem w/Integrated Hybrid
CONTROL REGISTER 1
D7
D6
D5
D4
D3
D2
D1
D0
CR0 MODUL. MODUL.
000 OPTION TYPE 1
BIT
NAME
D0, D1
Test Mode
D2
D3
D4
D5
MODUL. TRANSMIT TRANSMIT TRANSMIT TRANSMIT
ANSWER/
TYPE 0
MODE 2
MODE 1
MODE 0
ENABLE
ORIGINATE
CONDITION
DESCRIPTION
D1 D0
0
0
Selects normal operating mode.
0
1
Analog loopback mode. Loops the transmitted analog
signal back to the receiver, and causes the receiver to
use the same carrier frequency as the transmitter. To
squelch the TXA pin, transmit enable bit as well as Tone
Register bit D2 must be low.
1
0
Selects remote digital loopback. Received data is looped
back to transmit data internally, and RXD is forced to a
mark. Data on TXD is ignored.
1 1
Selects local digital loopback. Internally loops TXD back
to RXD and continues to transmit data carrier at TXA pin
Reset
0
Selects Normal Operations
1
Resets modem to power-down state. All Control
Register bits (CR0, CR1, CR2, CR3 and tone) are reset
to zero except CR3 bit D2. The output of the clock pin
will be set to the crystal frequency.
Clock Control
0
Selects 11.0592 MHz crystal echo output at CLK pin.
1
Selects 16 times the data rate output at CLK pin in
DPSK/QAM modes only.
0
Bypass
Selects normal operation. DPSK and QAM data is
Scrambler
passed through scrambler.
1
Selects Scrambler bypass. Bypass DPSK and QAM
data is route around scrambler in the transmit path.
Disables interrupt at INT pin. All interrupts are normally
disabled in power-down mode.
Enables INT output. An interrupt will be generated with a
change in status of DR bits D1- D4 and D6. The answer
tone and call progress detect interrupts are masked
when the TX enable bit is set. Carrier detect is masked
when TXDTMF is activated. All interrupts will be disable
if the device is in power-down mode.
0
Enable Detect
Interrupt
1
D6, D7
Transmit
Pattern
D7 D6
0
0
0
1
1
1
0
1
Selects normal data transmission as controlled by the
state of the TXD pin.
Selects an alternating mar/space transmit pattern for
modem testing and handshaking. Also used for S1
pattern generation (see CR2 bit D4).
Selects a constant mark transmit pattern.
Selects a constant space transmit pattern.
13
73K324BL
V.22bis/V.22/V.21/V.23 Bell 212A
Single-Chip Modem w/Integrated Hybrid
DETECT REGISTER
D7
DR
010
BIT
D0
D1
D2
D6
D5
D4
D3
D2
D1
D0
SIGNAL
CALL
CARR.
SPECIAL
RECEIVE UNSCR.
S1
RECEIVE
QUALITY
PROG.
DETECT
TONES
DATA
MARK
PATTERN
LEVEL
DETECT DETECT INDICATOR
DETECT
DETECT
INDICATOR
NAME
CONDITION
DESCRIPTION
Signal Quality
0
Indicates normal received signal.
Indicator
1
Indicates low received signal quality (above average
error rate). Interacts with Special Register bits D2, D1.
Call Progress
0
No call progress tone detected.
Detect
1
Indicates presence of call progress tones. The call
progress detection circuitry is activated by energy in the
normal 350 to 620 Hz call progress bandwidth.
Special Tone
0
Condition not detected.
Detect
1
Condition detected
CR0 D0
TR D0
CR2 D5
1
0
1
2225 Hz ±10 Hz answer tone detected in V.22bis, V.22
modes.
1
1
1
0
1
X
X
0
0
2100 Hz ±21 Hz answer tone detected in V.22 bis, V.22
modes.
900 Hz SCT tone detected in V.23 mode.
2100 Hz or 2225 Hz answer tone detected in QAM,
DPSK mode
No carrier detected in the receive channel.
Indicated carrier has been detected in the received
channel.
No unscrambled mark.
Indicates detection of unscrambled marks in the received
data. Should be time qualified by software.
Continuously outputs the received data stream. This data
is the same as that output on the RXD pin, but it is not
disabled when RXD is tri-stated.
No S1 pattern being received.
S1 pattern detected. Should be time qualified by
software. S1 pattern is defined as a double di-bit
(001100..) unscrambled 1200 bps DPSK signal. Pattern
must be aligned with baud clock to be detected.
Received signal level below threshold, (typical @ -25 dBm0);
can use receive gain boost (+18 dB).
Received signal above threshold.
D3
Carrier Detect
0
1
D4
Unscrambled
Mark Detect
0
1
D5
Receive Data
D6
S1 Pattern
Detect
0
1
D7
Receive Level
Indicator
0
1
14
73K324BL
V.22bis/V.22/V.21/V.23 Bell 212A
Single-Chip Modem w/Integrated Hybrid
TONE REGISTER
TR
011
D7
D6
D5
D4
D3
D2
D1
D0
RXD
OUTPUT
CONTROL
TRANSMIT
GUARD
TONE
TRANSMIT
ANSWER
TONE
TRANSMIT
DTMF
DTMF
3
DTMF 2/
4-WIRE
FDX
DTMF 1/
EXTENDED
OVERSPEED
DTMF 0/
G.T./ANSW./
CALLING//
SCT
TONE/SEL
BIT
D0, D4,
D5, D6
NAME
DTMF 0/
Guard Tone/
Answer Tone/
Calling/SCT
Tone/
Transmit
Select
D1
DTMF 1/
Extended
Overspeed
D2
DTMF 2/
4 Wire FDX
CONDITION
D6 D5 D4 D0
X X 1 X
DESCRIPTION
D0 interacts with bits D6, D5, and D4 as shown
Transmit DTMF tones (overrides all other functions).
Must be in V.22 mode during DTMF transmission
1
0
0
0
1
0
0
1
Select 1800 HZ guard tone if in V.22bis or V.22 and
Answer mode in CR0.
Select 550 Hz guard tone if in V.22bis or V.22 and
Answer mode in CR0.
Note: Bit D0 also selects the answer tone detected in Originate mode, see
Detect Register Special Tone Detect (bit D2) for details.
1 0 0 0
1300 Hz calling tone will be transmitted if V.22, V.22bis
or V.23 Originate mode is selected in CR0.
X 1 0 0
Transmit 2225 Hz Answer Tone. Must be in DPSK
Answer mode..
X 1 0 1
Transmit 2100 Hz Answer Tone. Must be in DPSK
Answer mode.
1 0 0 1
900 Hz SCT (soft carrier turnoff) tone transmitted in V.23
75 bps Receive mode. (CR0 bit D0 = 1)
D4 D1
D1 interacts with D4 as shown.
0
0
Asynchronous QAM or DPSK +1% -2.5%. (normal)
0
1
Asynchronous QAM or DPSK +2.3% -2.5%. (extended
overspeed)
D4 D2
0
0
Selects 2-wire duplex or half duplex
0
1
D2 selects 4-wire full duplex in the modulation mode
selected. The receive path corresponds receive mode
selected by the ANS/ORIG bit CR0 D0 in terms of high or
low band operation. The transmitter is in the same band
as the receiver, but does not have magnitude filtering or
equalization on its signal as in the receive path.
15
73K324BL
V.22bis/V.22/V.21/V.23 Bell 212A
Single-Chip Modem w/Integrated Hybrid
TONE REGISTER
TR
011
D7
D6
D5
D4
D3
D2
D1
D0
RXD
OUTPUT
CONTROL
TRANSMIT
GUARD
TONE
TRANSMIT
ANSWER
TONE
TRANSMIT
DTMF
DTMF
3
DTMF 2/
4-WIRE
FDX
DTMF 1/
EXTENDED
OVERSPEED
DTMF 0/
ANSWER
GUARD
BIT
D3, D2,
D1, D0
D7
NAME
DTMF 3,
2, 1, 0
RXD Output
Control
CONDITION
D3 D2 D1 D0
0 0 0 01 1 1 1
0
1
DESCRIPTION
D0 interacts with bits D6, D5, and D4 as shown
Programs 1 of 16 DTMF tone pairs that will be
transmitted when TX DTMF and TX enable bit (CR0, bit
D1) is set. Tone encoding is shown below:
KEYBOARD
DTMF CODE
TONES
EQUIVALENT
D3 D2 D1 D0
LOW
HIGH
1
0
0
0
1
697
1209
2
0
0
1
0
697
1336
3
0
0
1
1
697
1477
4
0
1
0
0
770
1209
5
0
1
0
1
770
1336
6
0
1
1
0
770
1477
7
0
1
1
1
852
1209
8
1
0
0
0
852
1336
9
1
0
0
1
852
1477
0
1
0
1
0
941
1336
*
1
0
1
1
941
1209
#
1
1
0
0
941
1477
A
1
1
0
1
697
1633
B
1
1
1
0
770
1633
C
1
1
1
1
852
1633
D
0
0
0
0
941
1633
Enables RXD pin. Receive data will be output on RXD.
Disables RXD pin. The RXD pin reverts to a high
impedance with internal weak pull-up resistor.
NOTE: DTMF0-DTMF2 should be set to an appropriate state after DTMF dialing to avoid unintended operation.
16
73K324BL
V.22bis/V.22/V.21/V.23 Bell 212A
Single-Chip Modem w/Integrated Hybrid
CONTROL REGISTER 2
CR2
100
BIT
D0
D7
D6
D5
D4
D3
D2
D1
D0
0
SPEC
REG
ACCESS
NAME
Equalizer
Enable
CALL
INIT
TRANSMIT
S1
16 WAY
RESET
DSP
TRAIN
INHIBIT
EQUALIZER
ENABLE
CONDITION
0
1
D1
Train Inhibit
0
1
D2
RESET DSP
0
1
D3
16 Way
0
1
D4
Transmit S1
0
1
D5
Call Init
0
1
D6
Special
Register
Access
0
1
D7
Not used at this time
0
DESCRIPTION
The adaptive equalizer is in its initialized state.
The adaptive equalizer is enabled. This bit is used in
handshakes to control when the equalizer should
calculate its coefficients.
The adaptive equalizer is active.
The adaptive equalizer coefficients are frozen.
The DSP is inactive and all variables are initialized.
The DSP is running based on the mode set by other
control bits.
The receiver and transmitter are using the same decision
plane (based on the modulator control mode).
The receiver, independent of the transmitter, is forced
into a 16 point decision plane. Used for QAM
handshaking.
The transmitter when placed in alternating mark/space
mode transmits 0101...... scrambled or not dependent on
the bypass scrambler bit.
When this bit is 1 and only when the transmitter is placed
in alternating mark/space mode by CR1 bits D7, D6, and
in DPSK or QAM, an unscrambled repetitive double di-bit
pattern of 00 and 11 at 1200 bps (S1) is sent
The DSP is set-up to do demodulation and pattern
detection based on the various mode bits. Both answer
tones are detected in demodulation mode concurrently;
TR-D0 is ignored.
The DSP decodes unscrambled mark, answer tone and
call progress tones.
Normal CR3 access.
Setting this bit and addressing CR3 allows access to the
special register (see the special register for details).
Only write zero to this bit.
17
73K324BL
V.22bis/V.22/V.21/V.23 Bell 212A
Single-Chip Modem w/Integrated Hybrid
CONTROL REGISTER 3
CR3
101
D7
D6
TXDALT
TRI-STATE
TX/RXCLK
BIT
D3, D2,
D1,D0
NAME
Transmit
Attenuator
D4
Receive Gain
Boost
D5
OH
D6
Tri-state
TXCLK/RXCLK
TXDALT
D7
D5
D4
D3
D2
D1
D0
TRANSMIT TRANSMIT TRANSMIT TRANSMIT
RECEIVE
ATTEN. 3
ATEN 2
ATTEN. 1
ATTEN. 0
BOOST
ENABLE
CONDITION
DESCRIPTION
D3 D2 D1 D0
0
0
0
0 Sets the attenuation level of the transmitted signal in 1
1
1
1
1 dB steps. The default (D3 - D0 = 0100) is for a transmit
level of -10 dBm0 on the line with the recommended
hybrid transmit gain. The total range is 16 dB.
0
18 dB receive front end boost is not used.
1
Boost is in the path. This boost does not change
reference levels. It is used to extend dynamic range by
compensating for internally generated noise when
receiving weak signals. The receive level detect signal
and knowledge of the hybrid and transmit attenuator
setting will determine when boost should be enabled.
0
Relay driver open.
1
Open drain driver pulling low.
0
TXCLK and RXCLK are driven.
1
TXCLK and RXCLK are tri-stated.
Special Register Alternate TX data source (see Special Register).
Bit D3=1
OH
18
73K324BL
V.22bis/V.22/V.21/V.23 Bell 212A
Single-Chip Modem w/Integrated Hybrid
SPECIAL REGISTER
SR
101
D7
D6
D5
D4
D3
D2
D1
D0
0
TXBAUD
CLOCK
RXUNDSCR
DATA
0
TXD
SOURCE
SIGNAL
QUALITY
LEVEL
SELECT 1
SIGNAL
QUALITY
LEVEL
SELECT 0
0
BIT
D7, D4, D0
D6
NAME
TXBAUD CLK
D5
RXUNDSCR
Data
D3
TXD Source
D2, D1
Signal Quality
Level Select
D2
0
0
1
1
D1
0
1
0
1
DESCRIPTION
Not used at this time. Only write zeros to these bits.
TXBAUD clock is the transmit baud-synchronous clock that can be used to
synchronize the input of arbitrary quad/di-bit patterns. The rising edge of
TXBAUD signals the latching of a baud-worth of data internally. Synchronous
data to be entered via the TXDALT bit, CR3 bit D7, should have data
transitions that start 1/2 bit period delayed from the TXBAUD clock edges.
This bit outputs the data received before going to the descrambler.
This is useful for sending special unscrambled patterns that can be used for signaling.
This bit selects the transmit data source; either the TXD pin if zero or the
TXDALT if this bit is a one. The transmit pattern bits D7 and D6 in CR1
override either of these sources.
The signal quality indicator is a logical zero when the signal received is
acceptable for low error rate reception. It is determined by the value of the
mean squared error (MSE) calculated in the decisioning process when
compared to a given threshold. This threshold can be set to four levels of
error rate. The SQI bit will be low for good or average connections. As the
error rate crosses the threshold setting, the SQI bit will toggle at a 1.66 ms
rate. Toggling will continue until the error rate indicates that the data pump
has lost convergence and a retrain is required. At that point the SQI bit will be
a one constantly. The SQI bit and threshold selection are valid for QAM and
DPSK only and indicates typical error rate.
THRESHOLD VALUE
UNITS
10-5
BER (default)
10-6
BER
10-4
BER
-3
10
BER
NOTE: This register is "mapped" and is accessed by setting CR2 bit D6 to a one and addressing CR3. This
register provides functions to the 73K324BL user that are not necessary in normal communications. Bits
D7-D4 are read only, while D3-D0 are read/write. To return to normal CR3 access, CR2 bit D6 must be
returned to a zero.
19
73K324BL
V.22bis/V.22/V.21/V.23 Bell 212A
Single-Chip Modem w/Integrated Hybrid
ID REGISTER
ID
110
BIT
D7, D6,
D5, D4
D7
D6
D5
D4
D3
D2
D1
D0
ID
ID
ID
ID
X
X
X
X
NAME
Device
Identification
Signature
CONDITION
D7 D6 D5 D4
0
0
X
X
0
1
X
X
1
0
X
X
1
1
0
0
1
1
1
0
DESCRIPTION
Indicates Device:
73K212L, 73K321L or 73K322L
73K221L or 73K302L
73K222L or 73K222BL
73K224L, 73K224BL
73K324L, 73K324BL
20
73K324BL
V.22bis/V.22/V.21/V.23 Bell 212A
Single-Chip Modem w/Integrated Hybrid
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
PARAMETER
RATING
VDD supply voltage
7V
Storage temperature
-65 to 150° C
Soldering temperature (10 s)
260° C
Applied voltage
-0.3 to VDD + 0.3 V
NOTE: All inputs and outputs are protected from static charge using built-in, industry standard protection
devices and all outputs are short-circuit protected.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
CONDITION
MIN
NOM
VDD supply voltage
4.5
5
5.5
V
TA, operating free-air
-40
+85
C
-0.01
+0.01
%
Clock variation
(11.0592 MHz) crystal or external
clock
External components (Refer to application section for placement.)
MAX
UNIT
VREF bypass capacitor
External to GND
0.1
Note 1
µF
Bias setting resistor
1.8
2
ISET bypass capacitor
Placed between VDD and ISET
pins
ISET pin to GND
VDD bypass capacitor 1
External to GND
0.1
Note 1
µF
VDD bypass capacitor 2
External to GND
22
Note 1
µF
XTL1 load capacitor
Depends on crystal characteristics
from pin to GND
40
pF
XTL2 load capacitor
Depends on crystal characteristics
from pin to GND
40
pF
Hybrid loading
see Figure 1
2.2
0.1
MΩ
µF
R1
600
Ω
R2
600
Ω
C1
0.033
µF
NOTE 1: Minimum for optimized system layout; may require higher values for noisy environments.
21
73K324BL
V.22bis/V.22/V.21/V.23 Bell 212A
Single-Chip Modem w/Integrated Hybrid
DC ELECTRICAL CHARACTERISTICS
(TA = -40°C to 85°C, VDD = recommended range unless otherwise noted.)
PARAMETER
CONDITION
IDD, Supply Current
CLK = 11.0592 MHz
IDD1, Active
IDD2, Idle
Digital Inputs
MIN
NOM
MAX
UNIT
Operating with crystal oscillator,
20
27
mA
< 5 pF capacitive load on CLK pin
5
7
mA
0.8
V
2.0
VDD
V
3.0
VDD
V
100
µA
ISET Resistor = 2 MΩ
VIL, Input Low Voltage
VIH, Input High Voltage
All Inputs except Reset
XTL1, XTL2
Reset, XTL1, XTL2
IIH, Input High Current
VI = VDD
IIL, Input Low Current
VI = 0V
Reset Pull-down Current
Reset = VDD
-200
µA
2
50
µA
2.4
VDD
V
0.4
V
-2
-50
µA
Digital Outputs
VOH, Output High Voltage
IO = IOH Min
IOUT = -0.4 mA
VOL, Output Low Voltage
IO = IOUT = 1.6 mA
RXD Tri-State Pull-up Curr.
RXD = GND
OH Output VOL
Capacitance
IOUT = 40 mA
1.4
V
CLK
Maximum permitted load
25
pF
Input Capacitance
All digital inputs
10
pF
22
73K324BL
V.22bis/V.22/V.21/V.23 Bell 212A
Single-Chip Modem w/Integrated Hybrid
FIGURE 1: Analog Interface Hybrid Loading
23
73K324BL
V.22bis/V.22/V.21/V.23 Bell 212A
Single-Chip Modem w/Integrated Hybrid
ELECTRICAL SPECIFICATIONS (continued)
DYNAMIC CHARACTERISTICS AND TIMING
(TA = -40°C to +85°C, VDD = recommended range unless otherwise noted.)
PARAMETER
CONDITION
MIN
Carrier suppression
Measured between TXA1 and
TXA2
35
Output Amplitude
TX Scrambled marks
ATT = 0100 (default)
NOM
MAX
UNIT
QAM/DPSK Modulator
-11.5
dB
-10
-9
dBm0
FSK Modulator/Demodulator
Output Frequency Error
CLK = 11.0592 MHz
-0.31
Transmit Level
ATT = 0100 (default)
transmit dotting pattern
-11.5
TXA output distortion
All products through BPF
Output bias distortion
@ RXD
Dotting pattern measured at RXD
receive level -20 dBm, SNR 20 dB
Output jitter @ RXD
Integrated for 5 seconds
-15
+15
%
Sum of bias distortion and
output jitter
Integrated for 5 seconds
-17
+17
%
-10
-10
+0.20
%
-9
dBm0
-45
dB
+10
%
Answer Tone Generator (2100 or 2225 Hz) Note: Do note use in V.21 when transmitting answer tone.
Output amplitude
ATT = 0100 (default level)
In V.22 mode
Output Distortion
Distortion products in receive band
DTMF Generator
Frequency accuracy
In V.22 mode
Output amplitude
-11.5
-10
-9
dBm0
-40
dB
-0.03
+0.25
%
Low band, ATT = 0100, DPSK mode
-10
-8
dBm0
Output amplitude
High band, ATT = 0100, DPSK mode
-8
-6
dBm0
Twist
High band to low band, DPSK mode
1
3
dB
Receiver Dynamic Range
Refer to performance curves
-43
-3
dBm0
Call Progress Detector
In call init mode
Detect level
460 Hz test signal
-34
0
dBm0
Reject level
460 Hz test signal
-40
dBm0
Delay time
-70 dBm0 to -30 dBm0 step
25
ms
Hold time
-30 dBm0 to -70 dBm0 step
25
ms
2
NOTE: Parameters expressed in dBm0 refer to the following definition:
8 dB loss in the transmit path (TXA1 - TXA2 to the line) in all modes except V.23 back channel
9 dB loss for the V.23 back channel transmit path (TXA1 – TXA2 to the line)
3 dB loss in the receive path from the line to RXA
24
73K324BL
V.22bis/V.22/V.21/V.23 Bell 212A
Single-Chip Modem w/Integrated Hybrid
DYNAMIC CHARACTERISTICS AND TIMING (continued)
PARAMETER
CONDITION
Carrier Detect
Receive gain = On for lower input level measurements
Threshold
All modes
-48
Hysteresis
All modes
2
Delay Time
FSK
DPSK
QAM
Hold Time
FSK
DPSK
QAM
Answer Tone Detectors
MIN
NOM
MAX
UNIT
-43
dBm0
70 dBm0 to -6 dBm0
25
37
ms
70 dBm0 to -40 dBm0
25
37
ms
-70 dBm0 to -6 dBm0
7
17
ms
-70 dBm0 to -40 dBm0
7
17
ms
-70 dBm0 to -6 dBm0
25
37
ms
-70 dBm0 to -40 dBm0
25
37
ms
-6 dBm0 to -70 dBm0
25
37
ms
40 dBm0 to -70 dBm0
15
30
ms
-6 dBm0 to -70 dBm0
20
29
ms
-40 dBm0 to -70 dBm0
14
21
ms
-6 dBm0 to -70 dBm0
25
32
ms
-40 dBm0 to -70 dBm0
18
28
ms
-48
-43
dBm0
DPSK Mode
Detect Level
Detect Time
Call init mode, 2100 or 2225 Hz
6
50
ms
Hold Time
Call init mode, 2100 or 2225 Hz
6
50
ms
Pattern Detectors
DPSK Mode
S1 Pattern
Delay Time
For signals from -6 to -40 dBm0,
10
55
ms
Hold Time
-6 to -40 dBm0, demodulation mode
10
45
ms
Unscrambled Mark
Delay Time
For signals from -6 to -40 call init
10
45
ms
Hold Time
mode
10
45
ms
-22
-28
dBm0
7
ms
Receive Level Indicator
Detect On
Valid after Carrier Detect
DPSK Mode
1
25
4
73K324BL
V.22bis/V.22/V.21/V.23 Bell 212A
Single-Chip Modem w/Integrated Hybrid
DYNAMIC CHARACTERISTICS AND TIMING (continued)
PARAMETER
CONDITION
MIN
NOM
MAX
UNIT
-22
-6
dBm0
-0.15
+0.15
dB
1.5
mVrms
Transmit Attenuator
Range of Transmit Level
Default ATT=0100 (-10 dBm0) 1111-0000
Step Accuracy
Clock Noise
TXA pins; 153.6 kHz
Carrier Offset
Capture Range
Recovered Clock
Originate or Answer
±5
Capture Range
% of frequency (originate or
answer)
-0.02
Hz
+0.02
%
Guard Tone Generator
Tone Accuracy
Tone Level
550 Hz
+1.2
1800 Hz
-0.8
%
550 Hz
-4.5
-3.0
-1.5
(Below QAM/DPSK Output)
1800 Hz
-7.5
-6.1
-4.5
dB
Harmonic Distortion
550 Hz
-50
dB
(700 to 2900 Hz)
1800 Hz
-50
dB
26
dB
73K324BL
V.22bis/V.22/V.21/V.23 Bell 212A
Single-Chip Modem w/Integrated Hybrid
DYNAMIC CHARACTERISTICS AND TIMING (continued)
PARAMETER
CONDITION
TIMING (Refer to Timing Diagrams)
*
TAL
CS/Address setup before ALE Low
12
ns
CS hold after ALE Low
0
ns
CS
TLA
AD0-AD7
MIN
NOM
MAX
UNIT
Address hold after ALE Low
10
ns
TLC
ALE Low to RD/WR Low
10
ns
TCL
RD/WR Control to ALE High
0
ns
TRD
Data out from RD Low
0
TLL
ALE width
15
TRDF
Data float after RD High
TRW
RD width
50
ns
TWW
WR width
50
ns
TDW
Data setup before WR High
15
ns
TWD
Data hold after WR High
12
ns
TCKD
Data out after EXCLK Low
TCKW (serial mode)
WR after EXCLK Low
150
ns
TDCK (serial mode)
Data setup before EXCLK Low
150
ns
TAC (serial mode)
Address setup before control**
50
ns
TCA (serial mode)
Address hold after control**
50
ns
TWH (serial mode)
Data Hold after EXCLK
20
70
ns
ns
50
200
ns
ns
* All timing parameters are targets and not guaranteed.
** Control for setup is the falling edge of RD or WR. Control for hold is the falling edge of RD or the rising edge of
WR.
NOTE:
Asserting ALE, CS, and RD or WR concurrently can cause unintentional register accesses. When
using non-8031 compatible processors, care must be taken to prevent this from occurring when
designing the interface logic.
27
73K324BL
V.22bis/V.22/V.21/V.23 Bell 212A
Single-Chip Modem w/Integrated Hybrid
TIMING DIAGRAMS
TLL
ALE
TLC
RD
TRW
TCL
TLC
WR
TRD
TLA
TWW
TRDF
TWD
TAL
AD0-AD7
TDW
ADDRESS
READ DATA
ADDRESS
WRITE DATA
CS
FIGURE 2: Bus Timing Diagram (Parallel Control Mode)
EXCLK
RD
TAC
AD0-AD2
TCA
ADDRESS
TRD
D0
DATA
TRDF
TCKD
D1
D2
D3
D4
D5
D6
D7
FIGURE 3: Read Timing Diagram (Serial Control Mode)
EXCLK
TWW
WR
TCKW
AD0-AD2
ADDRESS
TDCK
DATA
TAC
D0
TWH
D1
D2
D3
D4
D5
D6
FIGURE 4: Write Timing Diagram (Serial Control Mode)
28
D7
TCA
73K324BL
V.22bis/V.22/V.21/V.23 Bell 212A
Single-Chip Modem w/Integrated Hybrid
APPLICATIONS INFORMATION
The 73K324BL can be used in either of two control
interface configurations: one for a parallel
multiplexed address/data interface, and one for a
serial interface. The parallel method is intended for
use with 8039/48 or 8031/51 compatible
microcontrollers from Intel or many other
manufacturers. The serial interface mode can be
used with other microcontrollers or in applications
where only a limited number of port lines are
available or the application does not lend itself to a
multiplexed address/data interface.
GENERAL CONSIDERATIONS
Figure 5 shows the basic circuit diagram for a
73K324BL modem integrated circuit designed to be
used in conjunction with a control processor, a
UART or RS-232 serial data interface, and a DAA
phone line interface to function as a typical
intelligent modem. The K-Series ICs interface
directly with Intel 8048 and 80C51 microprocessors
for control and status monitoring purposes. A typical
DAA arrangement is shown in Figure 5. This
diagram is for reference only and does not represent
a production-ready modem design.
In most applications the controller will monitor the
serial data for commands from the DTE and the
received data for break signals from the far end
modem. In this way, commands to the modem are
sent over the same line as the transmitted data. In
other applications the RS-232 interface handshake
lines are used for modem control.
RING DETECT
+5
TX DATA
RX DATA
+
2 MΩ
1 µF
1
2
3
11.0592 MHz
4
5
6
7
CONTROL
INTERFACE
CLK
XTL1
XTL2
AD0
AD1
AD2
AD3
AD4
10 AD5
11 AD6
8
9
ADR/DATA BUS
12 AD7
13 ALE
14 WR
15 RD
µC ALE
µC WR
µC RD
+5
16 VDD
+
10 µF
GND
32
RXA
31
VREF
RESET 30
29
N/C
28
ISET
27
OH
26
RXCLK
25
RXD
24
TXD
23
CS
0.1 µF
0.1 µF
22
EXCLK
21
TXCLK
INT 20
19
N/C
18
TXA1
TXA2 17
RING
DETECTOR
8.2 K
HOOK
RELAY
600 Ω
+5
FUSE
1
2
3
4
0.033 µF 600 Ω
1:1
TYP.
TRANSFORMER
0.1 µF
RXCLK
TXCLK
EXCLK
CHIP SELECT
FIGURE 5: Typical 73K324BL DAA Circuit
29
TRANSIENT
SUPPRESSOR
RJ - 11
73K324BL
V.22bis/V.22/V.21/V.23 Bell 212A
Single-Chip Modem w/Integrated Hybrid
APPLICATIONS INFORMATION (continued)
DESIGN CONSIDERATIONS
DIRECT ACCESS ARRANGEMENT (DAA)
Semiconductor's one-chip modem products
include all basic modem functions. This makes
these devices adaptable for use in a variety of
applications, and as easy to control as
conventional digital bus peripherals.
The DAA (Direct Access Arrangement) required for the
73K324BL consists of an impedance matching
resistor, telecom coupling transformer, ring detection
and fault protection circuitry.
Unlike digital logic circuitry, modem designs must
properly contend
with
precise frequency
tolerances and very low level analog signals, to
ensure acceptable performance. Using good
analog circuit design practices will generally result
in a sound design. Following are additional
recommendations that should be taken into
consideration when starting new designs.
The transformer specifications must comply with the
PTT requirements of the country in which the modem
is being operated. Transformers designed specifically
for use with the telephone network should be used.
These may present a DC load to the network
themselves (a “wet” transformer) or they may require
AC coupling with a DC load provided by additional
devices (a “dry” transformer). A dry transformer will
generally provide higher performance and smaller size
than a wet transformer. A wet transformer allows a
simpler design, but must not saturate with the worst
case DC current passing through it or distortion and
poor performance will result.
CRYSTAL OSCILLATOR
The K-Series crystal oscillator requires a parallel
mode (anti-resonant) crystal that operates at
11.0592 MHz. It is important that this frequency be
maintained to within ±0.01% accuracy over all
operating conditions.
The protection circuitry typically consists of a transient
suppression device and current limiter to protect the
user and the telephone network from hazardous
voltages that can be present under fault conditions.
The transient suppresser may be a MOV (metal oxide
varistor), Sidactor (Teccor Electronics Inc.), spark gap
device , or avalanche diode. Some devices clamp the
transient to their specified break down voltage and
others go into low impedance crowbar state. The latter
require that the fault current cease before they can
return to their inactive state.
In order for a parallel mode crystal to operate
correctly and to specification, it must have a
capacitor connected to the junction of each of the
crystal and internal inverter connections,
terminated to ground. The values of these
capacitors depend primarily on the crystal’s
characteristics, and to a lesser degree on the
internal inverter circuit. The values used affect the
accuracy and start up characteristics of the
oscillator.
Current limiting devices can consist of a resistor,
Raychem PolySwitch resettable fuse, or slow blow
fuse that can withstand the transient tests without
permanent damage or replacement.
LAYOUT CONSIDERATIONS
Good analog/digital design rules must be used to
control system noise in order to obtain highest
performance in modem designs. The more digital
circuitry present on the PC board, the more this
attention to noise control is needed. The modem
should be treated as a high performance analog
device. A 22 µF electrolytic capacitor in parallel
with a 0.1 µF ceramic capacitor between VDD and
GND is recommended. Liberal use of ground
planes and larger traces on power and ground are
also highly favored. High speed digital circuits tend
to generate a significant amount of EMI (ElectroMagnetic Interference) which must be minimized
in order to meet regulatory agency limitations.
Ring detection circuitry is not required by the FCC, but
may be required by the application. The ring detector
usually consists of an optoisolator, capacitor, and
resistor to present the proper AC load to the network
to meet the REN (Ring Equivalency Number)
regulations of FCC Part 68. The K-Series Design
Manual contains detailed information on the design of
a ring detect circuits as well as the other topics
concerning the DAA.
30
73K324BL
V.22bis/V.22/V.21/V.23 Bell 212A
Single-Chip Modem w/Integrated Hybrid
BER VS. S/N
To accomplish this, high speed digital devices should
be locally bypassed, and the telephone line interface
and K-Series device should be located close to each
other near the area of the board where the phone line
connection is accessed. To avoid problems, power
supply and ground traces should be routed separately
to the analog and digital functions on the board, and
digital signals should not be routed near low level or
high impedance analog traces. The analog and digital
grounds should only connect at one point near the KSeries device ground pin to avoid ground loops. The
K-Series modem ICs should have both high frequency
and low frequency bypassing as close to the package
as possible.
This test measures the ability of the modem to
operate over noisy lines with a minimum of datatransfer errors. Since some noise is generated in
the best of dial-up lines, the modem must operate
with the lowest S/N ratio possible. Better modem
performance is indicated by test curves that are
closest to the BER axis. A narrow spread between
curves representing the four line parameters
indicates minimal variation in performance while
operating over a range of operating conditions.
Typically, a DPSK modem will exhibit better BER
performance test curves receiving in the low band
than in the high band.
MODEM PERFORMANCE
CHARACTERISTICS
BER VS. RECEIVE LEVEL
This test measures the dynamic range of the
modem. Because signal levels vary widely over
dial-up lines, the widest possible dynamic range is
desirable. The minimum Bell specification calls for
36 dB of dynamic range. S/N ratios are held
constant at the indicated values while the receive
level is lowered from a very high to very low signal
levels. The width of the “bowl” of these curves,
taken at the BER point, is the measure of dynamic
range.
The curves presented here define modem IC
performance under a variety of line conditions while
inducing disturbances that are typical of those
encountered during data transmission on public
service telephone lines. Test data was taken using an
TAS “1200” modem test set and line simulator,
operating under computer control. All tests were run
full-duplex, using a standard off-the-shelf modem as
the reference modem. A 511 pseudo-random-bit
pattern was used for each data point. Noise was Cmessage weighted and all signal-to-noise (S/N) ratios
reflect total power measurements similar to the CCITT
V.56 measurement specification. The individual tests
are defined as follows.
31
73K324BL
V.22bis/V.22/V.21/V.23 Bell 212A
Single-Chip Modem w/Integrated Hybrid
73K324BL BER vs S/N-DPSK LOW BAND
73K324BL BER vs S/N-DPSK HIGH BAND
10 -2
10 -2
HIGH BAND RECEIVE
-30 dBm
DPSK OPERATION
1200 BIT/S
LOW BAND RECEIVE
-30 dBm
DPSK OPERATION
1200 BIT/S
10 -3
10 -3
10
C1, 3002, FLAT
BIT ERROR RATE
BIT ERROR RATE
3002
-4
10
-4
C1, C2, FLAT
10 -5
10 -5
C2
10 -6
10 -6
4
6
8
12
10
14
4
16
6
8
73K324BL
BER VS S/N-QAM-LOW BAND
14
73K324BL
BER VS S/N-QAM-HIGH BAND
10 -2
10 -2
HIGH BAND RECEIVE
-30 dBm
QAM OPERATION
2400 BIT/S
HIGH BAND RECEIVE
-30 dBm
QAM OPERATION
2400 BIT/S
C1
C1
10 -3
10 -3
FLAT
BIT ERROR RATE
FLAT
BIT ERROR RATE
12
10
SIGNAL TO NOISE (dB)
SIGNAL TO NOISE (dB)
C2
10 -4
3002
10 -5
C2
10 -4
3002
10 -5
10 -6
10 -6
8
10
12
14
16
18
20
8
SIGNAL TO NOISE (dB)
10
12
14
16
SIGNAL TO NOISE (dB)
32
18
20
16
73K324BL
V.22bis/V.22/V.21/V.23 Bell 212A
Single-Chip Modem w/Integrated Hybrid
MECHANICAL SPECIFICATIONS
32-Lead PLCC
0.453 (11.51)
0.449 (11.40)
0.023
0.029
0.140 (3.56)
0.123 (3.12)
PIN NO. 1 IDENT.
0.595 (15.11)
0.585 (14.86)
0.553 (14.05)
0.549 (13.94)
0.095 (2.41)
0.078 (1.98)
0.050
0.013
0.021
0.300 REF
(7.62 REF)
0.430 (10.92)
0.390 (9.91)
0.026
0.032
0.400 REF
(10.16 REF)
0.530 (13.46)
0.490 (12.45)
0.495 (12.57)
0.485 (12.32)
44-Lead TQFP
16.0 BSC (0.630)
16.0 BSC (0.630)
INDEX
1
14.0 BSC (0.552)
1.35 (0.053)
1.45 (0.057)
0.09 (0.035)
0.20 (0.008)
0.42 (0.0165) Typ.
1.00 (0.0394) Typ.
33
0.60 (0.024) Typ.
0.045 (1.140)
0.020 (0.508)
73K324BL
V.22bis/V.22/V.21/V.23 Bell 212A
Single-Chip Modem w/Integrated Hybrid
PACKAGE PIN DESIGNATIONS
CAUTION: Use handling procedures necessary for
a static sensitive component.
XTAL1
CLK
GND
RXA
VREF
4
3
2
1
32
31
RESET
XTAL2
(Top View)
AD2
7
27
OH
AD3
8
26
RXCLK
AD4
9
25
RXD
AD5
10
24
TXD
AD6
11
23
CS
DATA/AD7
12
22
EXCLK
ALE
13
TXCLK
14
15
16
17
18
19
21
20
INT
ISET
N/C
28
TXA1
6
TXA2
AD1
VDD
30
29
RD
5
WR
AD0
N/C
32-Lead PLCC
73K324BL-IH
44-Lead TQFP
73K324BL-IGT
ORDERING INFORMATION
PART DESCRIPTION
ORDER NUMBER
PACKAGING MARK
73K324BL
32-Lead PLCC
73K324BL-IH
73K324BL-IH
73K324BL
44-Lead TQFP
73K324BL-IGT
73K324BL-IGT
No responsibility is assumed by TDK Semiconductor Corporation for use of this product nor for any infringements of patents and trademarks
or other rights of third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of TDK
Semiconductor Corporation. TDK Semiconductor Corporation reserves the right to make changes in specifications at any time without notice.
Accordingly, the reader is cautioned to verify that the data sheet is current before placing orders.
TDK Semiconductor Corporation, 2642 Michelle Dr., Tustin, CA 92780-7019, (714) 508-8800, FAX: (714) 508-8877
Protected by the following Patents (4,691,172) (4,777,453)
© 1996 TDK Semiconductor Corporation
04/24/00 – rev. D
34