FAIRCHILD 74ALVC16500

Revised October 2001
74ALVC16500
Low Voltage 18-Bit Universal Bus Transceivers
with 3.6V Tolerant Inputs and Outputs
General Description
Features
The ALVC16500 is an 18-bit universal bus transceiver
which combines D-type latches and D-type flip-flops to
allow data flow in transparent, latched, and clocked modes.
■ 1.65V–3.6V VCC supply operation
Data flow in each direction is controlled by output-enable
(OEAB and OEBA), latch-enable (LEAB and LEBA), and
clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the
device operates in the transparent mode when LEAB is
HIGH. When LEAB is LOW, the A data is latched if CLKAB
is held at a HIGH or LOW logic level. If LEAB is LOW, the A
bus data is stored in the latch/flip-flop on the HIGH-to-LOW
transition of CLKAB. When OEAB is HIGH, the outputs are
active. When OEAB is LOW, the outputs are in a highimpedance state.
Data flow for B to A is similar to that of A to B but uses
OEBA, LEBA, and CLKBA. The output enables are complementary (OEAB is active HIGH and OEBA is active
LOW).
The ALVC16500 is designed for low voltage (1.65V to
3.6V) VCC applications with I/O capability up to 3.6V.
■ 3.6V tolerant inputs and outputs
■ tPD (A to B, B to A)
3.4 ns max for 3.0V to 3.6V VCC
4.0 ns max for 2.3V to 2.7V VCC
7.0 ns max for 1.65V to 1.95V VCC
■ Power-off high impedance inputs and outputs
■ Supports live insertion/withdrawal (Note 1)
■ Uses patented noise/EMI reduction circuitry
■ Latchup conforms to JEDEC JED78
■ ESD performance:
Human body model > 2000V
Machine model >200V
Note 1: To ensure the high-impedance state during power up or power
down, OEBA should be tied to VCC through a pull-up resistor and OEAB
should be tied to GND through a pull-down resistors; the minimum value of
the resistor is determined by the current-sourcing capability of the driver.
The 74ALVC16500 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintaining low CMOS power dissipation.
Ordering Code:
Order Number
Package Number
Package Description
74ALVC16500MTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
© 2001 Fairchild Semiconductor Corporation
DS500684
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74ALVC16500 Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs
October 2001
74ALVC16500
Connection Diagram
Pin Descriptions
Pin Names
Description
OEAB
Output Enable Input for A to B Direction
(Active HIGH)
OEBA
Output Enable Input for B to A Direction
(Active LOW)
LEAB, LEBA
Latch Enable Inputs
CLKAB,
CLKBA
Clock Inputs
A1–A18
Side A Inputs or 3-STATE Outputs
B1–B18
Side B Inputs or 3-STATE Outputs
Function Table (Note 2)
Inputs
Outputs
OEAB
LEAB
CLKAB
An
Bn
L
X
X
X
Z
H
H
X
L
L
H
H
X
H
H
H
L
↓
L
L
H
L
↓
H
H
H
L
H
X
B0 (Note 3)
H
L
L
X
B0 (Note 4)
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial (HIGH or LOW, inputs may not float)
Z = High Impedance
Note 2: A-to-B data flow is shown; B-to-A flow is similar but uses OEBA,
LEBA and CLKBA. OEBA is active LOW.
Note 3: Output level before the indicated steady-state input conditions
were established.
Note 4: Output level before the indicated steady-state input conditions
were established, provided that CLKAB was LOW before LEAB went LOW.
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2
74ALVC16500
Logic Diagram
3
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74ALVC16500
Absolute Maximum Ratings(Note 5)
Recommended Operating
Conditions (Note 7)
−0.5V to +4.6V
Supply Voltage (VCC)
−0.5V to 4.6V
DC Input Voltage (VI)
Output Voltage (VO) (Note 6)
Power Supply
−0.5V to VCC +0.5V
Operating
DC Input Diode Current (IIK)
VI < 0V
−50 mA
0V to VCC
Output Voltage (VO)
DC Output Diode Current (IOK)
0V to VCC
Free Air Operating Temperature (TA)
VO < 0V
−50 mA
−40°C to +85°C
Minimum Input Edge Rate (∆t/∆V)
VIN = 0.8V to 2.0V, VCC = 3.0V
DC Output Source/Sink Current
±50 mA
(IOH/IOL)
±100 mA
Supply Pin (ICC or GND)
10 ns/V
Note 5: The Absolute Maximum Ratings are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation.
DC VCC or GND Current per
Storage Temperature Range (TSTG)
1.65V to 3.6V
Input Voltage (VI)
−65°C to +150°C
Note 6: IO Absolute Maximum Rating must be observed.
Note 7: Floating or unused control inputs must be held HIGH or LOW.
DC Electrical Characteristics
Symbol
VIH
VIL
VOH
VOL
Parameter
Conditions
HIGH Level Input Voltage
LOW Level Input Voltage
HIGH Level Output Voltage
LOW Level Output Voltage
VCC
(V)
Min
1.65 - 1.95
0.65 x VCC
2.3 - 2.7
1.7
2.7 - 3.6
2.0
Max
V
1.65 - 1.95
0.35 x VCC
2.3 - 2.7
0.7
2.7 - 3.6
0.8
IOH = 100 µA
1.65 - 3.6
IOH = −4 mA
1.65
1.2
IOH = −6 mA
2.3
2.0
IOH = −12 mA
2.3
1.7
2.7
2.2
V
VCC - 0.2
V
3.0
2.4
IOH = −24 mA
3.0
2
IOL = 100 µA
1.65 - 3.6
0.2
1.65
0.45
IOL = 6 mA
2.3
0.4
IOL = 12 mA
2.3
0.7
2.7
0.4
IOL = 24 mA
3.0
0.55
IOL = 4 mA
Units
V
II
Input Leakage Current
0 ≤ VI ≤ 3.6V
3.6
±5.0
µA
IOZ
3-STATE Output Leakage
0 ≤ VO ≤ 3.6V
3.6
±10
µA
ICC
Quiescent Supply Current
VI = VCC or GND, IO = 0
3.6
40
µA
∆ICC
Increase in ICC per Input
VIH = VCC − 0.6V
3 - 3.6
750
µA
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TA = −40°C to +85°C, RL = 500Ω
Symbol
CL = 50 pF
Parameter
VCC = 3.3V ± 0.3V
Min
fMAX
Maximum Clock Frequency
tPHL, tPLH
Propagation Delay
Bus to Bus
tPHL, tPLH
Propagation Delay
Clock to Bus
tPHL, tPLH
Propagation Delay
Max
250
CL = 30 pF
VCC = 2.7V
Min
VCC = 2.5V ± 0.2V
Max
200
Min
VCC = 1.8V ± 0.15V
Max
Min
200
Units
Max
100
MHz
1.1
3.4
1.3
4.0
0.8
3.5
1.5
7.0
ns
1.1
4.7
1.3
5.8
0.8
5.3
1.5
9.8
ns
1.1
4.3
1.3
5.4
0.8
4.9
1.5
9.8
ns
tPZL, tPZH
Output Enable Time
1.1
4.3
1.3
5.4
0.8
4.9
1.5
9.8
ns
tPLZ, tPHZ
Output Disable Time
1.1
4.2
1.3
4.7
0.8
4.2
1.5
7.6
ns
tW
Pulse Width
1.5
1.5
1.5
4.0
tS
Setup Time
1.5
1.5
1.5
2.5
ns
tH
Hold Time
1.0
1.0
1.0
1.0
ns
LE to Bus
ns
Capacitance
Symbol
Parameter
Conditions
TA = +25°C
VCC
Typical
Units
CIN
Input Capacitance
VI = 0V or VCC
3.3
6
pF
COUT
Output Capacitance
VI = 0V or VCC
3.3
7
pF
CPD
Power Dissipation Capacitance
3.3
20
2.5
20
Outputs Enabled f = 10 MHz, CL = 50 pF
5
pF
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74ALVC16500
AC Electrical Characteristics
74ALVC16500
AC Loading and Waveforms
TABLE 1. Values for Figure 1
TEST
SWITCH
tPLH, tPHL
Open
tPZL, tPLZ
VL
tPZH, tPHZ
GND
FIGURE 1. AC Test Circuit
TABLE 2. Variable Matrix
(Input Characteristics: f = 1 MHz; tr = tf = 2ns; Z0 = 50Ω
Symbol
VCC
3.3V ± 0.3V
2.7V
2.5V ± 0.2V
1.8V ± 0.15V
Vmi
1.5V
1.5V
VCC/2
VCC/2
Vmo
1.5V
1.5V
VCC/2
VCC/2
VX
VOL + 0.3V
VOL + 0.3V
VOL + 0.15V
VOL + 0.15V
VY
VOH − 0.3V
VOH − 0.3V
VOH − 0.15V
VOH − 0.15V
VL
6V
6V
VCC*2
VCC*2
FIGURE 2. Waveform for Inverting
and Non-inverting Functions
FIGURE 3. 3-STATE Output High Enable
and Disable Times for Low Voltage Logic
FIGURE 4. 3-STATE Output Low Enable
and Disable Times for Low Voltage Logic
FIGURE 5. Propagation Delay, Pulse Width
and trec Waveforms
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FIGURE 6. Setup Time, Hold Time
and Recovery Time for Low Voltage Logic
6
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD56
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
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74ALVC16500 Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs
Physical Dimensions inches (millimeters) unless otherwise noted