SCLS599 − NOVEMBER 2004 D Qualification in Accordance With D D D D D D D D D D OR PW PACKAGE (TOP VIEW) AEC-Q100† Qualified for Automotive Applications Customer-Specific Configuration Control Can Be Supported Along With Major-Change Approval Wide Operating Voltage Range of 2 V to 6 V Outputs Can Drive up to Ten LSTTL Loads Low Power Consumption, 80-µA Max ICC Typical tpd = 14 ns ±4-mA Output Drive at 5 V Low Input Current of 1 µA Max Allow Design of Either RC- or Crystal-Oscillator Circuits QL QM QN QF QE QG QD GND 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC QJ QH QI CLR CLKI CLKO CLKO † Contact factory for details. Q100 qualification data available on request. description/ordering information The SN74HC4060 device consists of an oscillator section and 14 ripple-carry binary counter stages. The oscillator configuration allows design of either RC- or crystal-oscillator circuits. A high-to-low transition on the clock (CLKI) input increments the counter. A high level at the clear (CLR) input disables the oscillator (CLKO goes high and CLKO goes low) and resets the counter to zero (all Q outputs low). ORDERING INFORMATION ORDERABLE PART NUMBER PACKAGE‡ TA SOIC − D Reel of 2500 TOP-SIDE MARKING SN74HC4060QDRQ1 HC4060Q −40°C to 125°C TSSOP − PW Reel of 2000 SN74HC4060QPWRQ1 HC4060Q ‡ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE (each buffer) INPUTS FUNCTION CLK CLR ↑ L No change ↓ L Advance to next stage X H All outputs L Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2004, Texas Instruments Incorporated ! " #$%! " &$'(#! )!%* )$#!" # ! "&%##!" &% !+% !%" %," "!$%!" "!)) -!.* )$#! &#%""/ )%" ! %#%""(. #($)% !%"!/ (( &%!%"* POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SCLS599 − NOVEMBER 2004 logic diagram (positive logic) R R T CLR R T R T 4 6 QF QG R T 14 R T 13 QH T R T 15 QI QJ R T T 1 2 3 QL QM QN 12 R R T 9 CLKI R 11 10 R T R T R T T CLKO CLKO 7 5 QD QE absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SCLS599 − NOVEMBER 2004 recommended operating conditions (see Note 3) VCC VIH VI VO ∆t/∆v NOM MAX 2 5 6 Supply voltage VCC = 2 V VCC = 4.5 V High-level input voltage 3.15 V 0.5 1.35 V 1.8 Input voltage 0 Output voltage VCC VCC 0 VCC = 2 V VCC = 4.5 V Input transition rise/fall time V 4.2 VCC = 4.5 V VCC = 6 V Low-level input voltage UNIT 1.5 VCC = 6 V VCC = 2 V VIL MIN V V 1000 500 ns VCC = 6 V 400 TA Operating free-air temperature −40 125 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER All outputs TEST CONDITIONS VI = VIH or VIL, IOH = −20 µA VOH Q outputs All outputs VI = VIH or VIL IOH = −4 mA IOH = −5.2 mA II ICC Ci MAX TA = −40°C TO 125°C TA = −40°C TO 85°C MIN MIN MIN TYP 2V 1.9 1.998 1.9 1.9 4.5 V 4.4 4.499 4.4 4.4 6V 5.9 5.999 5.9 5.9 4.5 V 3.98 4.3 3.7 3.84 6V 5.48 5.8 MAX 5.2 UNIT MAX V 5.34 2V 0.002 0.1 0.1 0.1 0.001 0.1 0.1 0.1 VI = VIH or VIL, IOL = 20 µA 4.5 V 6V 0.001 0.1 0.1 0.1 4.5 V 0.17 0.26 0.4 0.33 VI = VIH or VIL IOL = 4 mA IOL = 5.2 mA 6V 0.15 0.26 0.4 0.33 6V ±0.1 ±100 ±1000 ±1000 nA 8 160 80 µA 10 10 10 pF VOL Q outputs TA = 25°C VCC VI = VCC or 0 VI = VCC or 0, IO = 0 6V 2 V to 6 V POST OFFICE BOX 655303 3 • DALLAS, TEXAS 75265 V 3 SCLS599 − NOVEMBER 2004 timing requirements over recommended operating free-air temperature range (unless otherwise noted) VCC fclock Clock frequency CLKI high or low tw Pulse duration CLR high tsu Setup time, CLR inactive before CLKI↓ TA = 25°C TA = −40°C TO 125°C TA = −40°C TO 85°C MIN MIN MIN MAX MAX 2V 5.5 3.7 4.3 4.5 V 28 19 22 6V 33 22 25 2V 90 135 115 4.5 V 18 27 23 6V 15 23 20 2V 90 135 115 4.5 V 18 27 23 6V 15 23 20 2V 160 240 200 4.5 V 32 48 40 6V 27 41 34 UNIT MAX MHz ns ns switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) fmax tpd CLKI tPHL CLR tt QD Any Q Any TA = 25°C VCC MAX TA = −40°C TO 125°C TA = −40°C TO 85°C MIN MIN MIN TYP MAX 2V 5.5 10 3.7 4.3 4.5 V 28 45 19 22 6V 33 53 22 25 UNIT MAX MHz 2V 240 490 735 615 4.5 V 58 98 147 123 6V 42 83 125 105 2V 66 140 210 175 4.5 V 18 28 42 35 6V 14 24 36 30 2V 28 75 110 95 4.5 V 8 15 22 19 6V 6 30 19 16 ns ns ns operating characteristics, TA = 25°C PARAMETER Cpd 4 TEST CONDITIONS Power dissipation capacitance No load POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TYP 88 UNIT pF SCLS599 − NOVEMBER 2004 PARAMETER MEASUREMENT INFORMATION From Output Under Test Test Point CL = 50 pF (see Note A) Reference Input 0V tsu Data Input LOAD CIRCUIT Input 50% 0V tPLH In-Phase Output 90% 50% 10% 90% tPHL 90% VCC 50% 10% 0 V 90% tr tf VOLTAGE WAVEFORMS SETUP AND INPUT RISE AND FALL TIMES tPHL 90% tr Out-of-Phase Output 50% 10% VCC 50% VCC 50% VOH 50% 10% VOL tf tf 50% 10% 50% 50% 0V tPLH 50% 10% VCC High-Level Pulse VOH 90% VOL tr tw VCC Low-Level Pulse VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES 50% 50% 0V VOLTAGE WAVEFORMS PULSE DURATIONS NOTES: A. CL includes probe and test-fixture capacitance. B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. C. For clock inputs, fmax is measured when the input duty cycle is 50%. D. The outputs are measured one at a time, with one input transition per measurement. E. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SCLS599 − NOVEMBER 2004 CONNECTING AN RC-OSCILLATOR CIRCUIT TO THE SN74HC4060 DEVICE The SN74HC4060 device consists of an oscillator section and 14 ripple-carry binary counter stages. The oscillator configuration allows design of either RC- or crystal-oscillator circuits. When an RC-oscillator circuit is implemented, two resistors and a capacitor are required. The components are attached to the terminals as shown: 1 2 16 15 3 4 14 13 5 6 12 11 7 10 8 9 R2 R1 C To determine the values of capacitance and resistance necessary to obtain a specific oscillator frequency (f), use this formula: f+ 1 R2 2(R1)(C)ǒ0.405 ) 0.693Ǔ R1)R2 If R2 > > R1 (i.e., R2 = 10R1), the above formula simplifies to: f + 0.455 RC 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. 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