PRELIMINARY Integrated Circuit Systems, Inc. ICS85222-02 1-TO-2 LVCMOS / LVTTL-TODIFFERENTIAL HSTL TRANSLATOR GENERAL DESCRIPTION FEATURES The ICS85222-02 is a 1-to-2 LVCMOS / LVTTLto-Differential HSTL translator and a member of HiPerClockS™ the HiPerClocks™ family of High Performance Clock Solutions from ICS. The ICS85222-02 has one single ended clock input. The single ended clock input accepts LVCMOS or LVTTL input levels and translates them to HSTL levels. The small outline 8-pin SOIC package makes this device ideal for applications where space, high performance and low power are important. • Two differential HSTL outputs ICS • One LVCMOS/LVTTL clock input • CLK input can accept the following input levels: LVCMOS or LVTTL • Maximum output frequency: 350MHz • Part-to-part skew: TBD • Propagation delay: 1ns (typical) • VOH: 1.4V (maximum) • Full 3.3V operating supply voltage • 0°C to 70°C ambient operating temperature • Industrial temperature information available upon request • Available in both standard and lead-free RoHS compliant packages BLOCK DIAGRAM PIN ASSIGNMENT Q0 CLK Pullup Q0 nQ0 Q1 nQ1 nQ0 Q1 nQ1 1 2 3 4 8 7 6 5 VDD CLK nc GND ICS85222-02 8-Lead SOIC 3.90mm x 4.92mm x 1.37mm body package M Package Top View The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 85222AM-02 www.icst.com/products/hiperclocks.html REV. A JANUARY 25, 2006 1 PRELIMINARY Integrated Circuit Systems, Inc. ICS85222-02 1-TO-2 LVCMOS / LVTTL-TODIFFERENTIAL HSTL TRANSLATOR TABLE 1. PIN DESCRIPTIONS Number Name 1, 2 Q0, nQ0 Output Type Description 3, 4 Q1, nQ1 Output Differential output pair. HSTL interface levels. 5 GN D Power Power supply ground. 6 CLK Input 7 nc Unused Differential output pair. HSTL interface levels. Pullup LVCMOS / LVTTL clock input. No connect. Power Positive supply pin. 8 VDD NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. NOTE: Unused output pairs must be terminated. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 kΩ 85222AM-02 www.icst.com/products/hiperclocks.html 2 REV. A JANUARY 25, 2006 PRELIMINARY Integrated Circuit Systems, Inc. ICS85222-02 1-TO-2 LVCMOS / LVTTL-TODIFFERENTIAL HSTL TRANSLATOR ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, IO Continuous Current Surge Current 50mA 100mA Package Thermal Impedance, θJA 112.7°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions VDD Positive Supply Voltage IDD Power Supply Current Minimum Typical Maximum 3.135 3. 3 3.465 90 Units V mA TABLE 3B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter VIH Input High Voltage Test Conditions VIL Input Low Voltage IIH Input High Current CLK VDD = VIN = 3.465V IIL Input Low Current CLK VDD = 3.465, VIN = 0V Minimum Maximum Units 2 Typical VDD + 0.3 V -0.3 0.8 V 5 µA -150 µA TABLE 3C. HSTL DC CHARACTERISTICS, VDD = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VOH Output High Voltage; NOTE 1 1 1.4 V VOL Output Low Voltage; NOTE 1 0 0.4 V VSWING Peak-to-Peak Output Voltage Swing 0.6 1.4 V Maximum Units 350 MHz NOTE 1: Outputs terminated with 50Ω to GND. TABLE 4. AC CHARACTERISTICS, VDD = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter fMAX Output Frequency tPD Propagation Delay; NOTE 1 t sk(pp) Par t-to-Par t Skew; NOTE 2, 3 tR / tF Output Rise/Fall Time Test Conditions Minimum 20% to 80% Typical 1.0 ns TBD ps 375 ps odc Output Duty Cycle 50 % NOTE 1: Measured from VDD/2 of the input to the differential output crossing point. NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. 85222AM-02 www.icst.com/products/hiperclocks.html 3 REV. A JANUARY 25, 2006 PRELIMINARY Integrated Circuit Systems, Inc. ICS85222-02 1-TO-2 LVCMOS / LVTTL-TODIFFERENTIAL HSTL TRANSLATOR PARAMETER MEASUREMENT INFORMATION 3.3V ± 5% PART 1 nQx VDD Qx SCOPE Qx PART 2 nQy HSTL Qy nQx tsk(pp) GND 0V 3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT PART-TO-PART SKEW VDD CLK 80% 80% 2 VSW I N G Clock Outputs nQ0, nQ1 20% 20% Q0, Q1 tR tF tPD OUTPUT RISE/FALL TIME PROPAGATION DELAY nQ0, nQ1 Q0, Q1 t PW t odc = PERIOD t PW x 100% t PERIOD OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD 85222AM-02 www.icst.com/products/hiperclocks.html 4 REV. A JANUARY 25, 2006 PRELIMINARY Integrated Circuit Systems, Inc. ICS85222-02 1-TO-2 LVCMOS / LVTTL-TODIFFERENTIAL HSTL TRANSLATOR APPLICATION INFORMATION RECOMMENDATIONS FOR UNUSED OUTPUT PINS OUTPUTS: HSTL OUTPUT All unused HSTL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. 85222AM-02 www.icst.com/products/hiperclocks.html 5 REV. A JANUARY 25, 2006 PRELIMINARY Integrated Circuit Systems, Inc. ICS85222-02 1-TO-2 LVCMOS / LVTTL-TODIFFERENTIAL HSTL TRANSLATOR POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS85222-02. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS85222-02 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • • Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 90mA = 311.85mW Power (outputs)MAX = 73.8mW/Loaded Output pair If all outputs are loaded, the total power is 2 * 73.8mW = 147.6mW Total Power_MAX (3.465V, with all outputs switching) = 121.3mW + 147.6mW = 459.5mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total device power dissipation (example calculation is in Section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 103.3°C/W per Table 5 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: 70°C + 0.460W * 103.3°C/W = 117.5°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 5. THERMAL RESISTANCE θJA FOR 8-PIN SOIC, FORCED CONVECTION θJA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 153.3°C/W 112.7°C/W 128.5°C/W 103.3°C/W 115.5°C/W 97.1°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. 85222AM-02 www.icst.com/products/hiperclocks.html 6 REV. A JANUARY 25, 2006 PRELIMINARY Integrated Circuit Systems, Inc. ICS85222-02 1-TO-2 LVCMOS / LVTTL-TODIFFERENTIAL HSTL TRANSLATOR 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. HSTL output driver circuit and termination are shown in Figure 1. VDD Q1 VOUT RL 50Ω FIGURE 1. HSTL DRIVER CIRCUIT AND TERMINATION To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load. Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = (V /R ) * (V OH_MIN Pd_L = (V OL_MAX L -V DD_MAX /R ) * (V L DD_MAX ) OH_MIN -V ) OL_MAX Pd_H = (1V/50Ω) * (3.465V - 1V) = 49.3mW Pd_L = (0.4V/50Ω) * (3.465V - 0.4V) = 24.52mW Total Power Dissipation per output pair = Pd_H + Pd_L = 73.8mW 85222AM-02 www.icst.com/products/hiperclocks.html 7 REV. A JANUARY 25, 2006 PRELIMINARY Integrated Circuit Systems, Inc. ICS85222-02 1-TO-2 LVCMOS / LVTTL-TODIFFERENTIAL HSTL TRANSLATOR RELIABILITY INFORMATION TABLE 6. θJAVS. AIR FLOW TABLE 8 LEAD SOIC θJA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 153.3°C/W 112.7°C/W 128.5°C/W 103.3°C/W 115.5°C/W 97.1°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS85222-02 is: 411 85222AM-02 www.icst.com/products/hiperclocks.html 8 REV. A JANUARY 25, 2006 PRELIMINARY Integrated Circuit Systems, Inc. PACKAGE OUTLINE - M SUFFIX ICS85222-02 1-TO-2 LVCMOS / LVTTL-TODIFFERENTIAL HSTL TRANSLATOR FOR 8 LEAD SOIC TABLE 7. PACKAGE DIMENSIONS SYMBOL Millimeters MINIMUM N A MAXIMUM 8 1.35 1.75 A1 0.10 0.25 B 0.33 0.51 C 0.19 0.25 D 4.80 5.00 E 3.80 4.00 e 1.27 BASIC H 5.80 6.20 h 0.25 0.50 L 0.40 1.27 α 0° 8° Reference Document: JEDEC Publication 95, MS-012 85222AM-02 www.icst.com/products/hiperclocks.html 9 REV. A JANUARY 25, 2006 PRELIMINARY Integrated Circuit Systems, Inc. ICS85222-02 1-TO-2 LVCMOS / LVTTL-TODIFFERENTIAL HSTL TRANSLATOR TABLE 8. ORDERING INFORMATION Part/Order Number Marking Package Shipping Package Temperature ICS85222AM-02 85222A02 8 Lead SOIC tube 0°C to 70°C ICS85222AM-02T 85222A02 8 Lead SOIC 2500 tape & reel 0°C to 70°C ICS85222AM-02LF TBD 8 Lead "Lead-Free" SOIC tube 0°C to 70°C ICS85222AM-02LFT TBD 8 Lead "Lead-Free" SOIC 2500 tape & reel 0°C to 70°C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. The aforementioned trademark, HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 85222AM-02 www.icst.com/products/hiperclocks.html 10 REV. A JANUARY 25, 2006