Product Specification PE926C31 Product Description The PE926C31 is a high performance monolithic CMOS RS-422 line driver. Its operating supply range is 3.0 to 3.6 V, with an output signal overvoltage range of 0 – 6 V. The PE26C31 offers higher speed and lower power than other RS-422 driver types. It is packaged in a flat pack and is ideal for space applications. The PE926C31 is manufactured in Peregrine’s patented Ultra Thin Silicon (UTSi®) CMOS process, offering the performance of GaAs with the economy and integration of conventional CMOS. Quad RS-422 Differential Line Driver Radiation Hardened Features • High-speed operation: < 10 nS typical • Low power: < 150 uA typical (unloaded) • 3.3 V operation • Standard packaging: 16-lead flat pack • SEL Immune UTSi CMOS-on-sapphire • SEU <10-10 errors / bit-day • 300 Krad Total Dose Figure 1. Package Drawing Document No. 70-0157-01 │ www.psemi.com ©2005 Peregrine Semiconductor Corp. All rights reserved. Page 1 of 7 PE926C31 Product Specification Figure 2. Pin Configuration (Top View) Table 2. Recommended Operating Conditions Symbol A 1 16 V+ AQ+ 2 15 D AQ- 3 E+ 4 BQ- 14 PE926C31 DQ+ 13 DQ- 5 12 E- BQ+ 6 11 CQ- B 7 10 CQ+ V- 8 9 Parameter/Conditions Min Max Units V+ Supply voltage 3.0 3.6 V TOP Operating temperature range -55 125 °C VIN Maximum input voltage 0 Vdd V VOUT Maximum output voltage 0 Vdd V IOUT Maximum output current -50 50 mA Electrostatic Discharge (ESD) Precautions C Table 1. Pin Descriptions Latch-Up Avoidance Pin No. Pin Name 1 A 2 AQ+ Channel A Noninverting Ouput 3 AQ- Channel A Inverting Output 4 E+ Enable, active high 5 BQ- Channel B Inverting Output 6 BQ+ Channel B Noninverting Output 7 B Channel B Input 8 V- Ground Pin 9 C Channel C Input 10 CQ+ Channel C Noninverting Output 11 CQ- Channel C Inverting Ouput 12 E- 13 DQ- Channel D Inverting Output 14 DQ+ Channel D Noninverting Output 15 D Channel D Input 16 V+ Supply Pin Description Unlike conventional CMOS devices, UltraCMOS™ devices are immune to latch-up. Channel A Input Enable, active low ©2005 Peregrine Semiconductor Corp. All rights reserved. Page 2 of 7 When handling this UTSi device, observe the same precautions that you would use with other ESD-sensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the rating specified in Table 2. Device Functional Considerations The PE926C31 operates at high switching speeds. In order to obtain maximum performance, it is crucial that pin 16 be supplied with a bypass capacitor to ground (pin 8). Table 3. Truth Table E+ E- Data Q+ Q- L H X Z Z H X L L H X L H X H H L X L Document No. 70-0157-01 │ UltraCMOS™ RFIC Solutions PE926C31 Product Specification Table 4. Electrical Specifications -55° C < Tcase < 125° C, 3.0 V < V+ < 3.6 V, PreRad, unless otherwise specified Param Description Conditions Pin(s) VD1 Output Differential Voltage No load AQ+, AQ-, BQ+, BQ-, CQ+, CQ-, DQ+, DQ- Min Typ (V+) -0.3 (V+) VD2 Output Differential Voltage DVD2 RL=100 Ω, Fig DC1 1.9 2.3 Output Differential Voltage Change IOUT 0 – 20mA, Fig DC1 -0.4 0 0.4 V VCM Common Mode Voltage RL=100 Ω, Fig DC1 1.5 2.0 V DVCM Common Mode Voltage Change RL=100 Ω, Fig DC1 -0.4 0 0.4 V IOZH Tristate Output Leakage (H) VOUT = V+, disabled -5 -0.1 IOZL Tristate Output Leakage (L) VOUT = 0.0 V, disabled IOSC Output Short Circuit Current VOUT = 0.0 V, Enabled Q=H IOFFH Output Leakage Current (H) VOUT=6.0V,V+ and all inputs = 0.0V IOFFL Output Leakage Current (L) VOUT=-0.25V,V+ and all inputs = 0.0V -100 -1 uA VOH Output High Voltage Iout=-20mA 2.0 2.4 V VOL Output Low Voltage Iout=20mA VIH Input threshold H Vdd=3.6V (VIHMIN=0.7*VDD) A, B, C, D, E+, E- VIL Input Threshold L Vdd=3.0V (VILMAX=0.3*VDD) A, B, C, D, E+, E- IIH Input Lkg Current A, B, C, D, E+, E- IIL Input Lkg Current VIKL Input Clamp Diode Voltage VIKH ICC Notes: -30 Max (V+) +0.6 Units V V uA 0.1 5 uA -70 -100 mA 1 100 uA 0.1 0.5 2.5 V V 0.9 V -1 1 uA A, B, C, D, E+, E- -1 1 uA IIN=-20 mA A, B, C, D, E+, E- -1.5 Input Clamp Diode Voltage IIN=20 mA A, B, C, D, E+, E- (V+) + 1.5 V µ Supply Current No load, Inputs = 0 V or V+ V+ 120 uA 150 uA 1. “Line” pins refer to AQ-, AQ+, BQ-, BQ+, CQ-, CQ+, DQ-, DQ+, differential outputs 2. “Digital Input” or “Enable” pins refer to E+, E3. “Digital Input” pins refer to A, B, C, D Document No. 70-0157-01 │ www.psemi.com ©2005 Peregrine Semiconductor Corp. All rights reserved. Page 3 of 7 PE926C31 Product Specification Table 5. Post-Irradiation DC Electrical Specifications Tcase = 25° C, 3.0 V < V+ < 3.6 V, 300 KRad, unless otherwise specified Param Description Conditions Pin(s) VD1 Output Differential Voltage No load VD2 Output Differential Voltage RL=100 Ω, Fig DC1 AQ+, AQ-, BQ+, BQ-, CQ+, CQ-, DQ+, DQ- DVD2 Output Differential Voltage Change IOUT 0 – 20mA, Fig DC1 VCM Common Mode Voltage RL=100 Ω, Fig DC1 DVCM Common Mode Voltage Change RL=100 Ω, Fig DC1 IOZH Tristate Output Leakage (H) VOUT = V+, disabled IOZL Tristate Output Leakage (L) VOUT = 0.0 V, disabled IOSC Output Short Circuit Current VOUT = 0.0 V, Enabled Q=H IOFFH Output Leakage Current (H) VOUT=6.0V,V+ and all inputs = 0.0V IOFFL Output Leakage Current (L) VOUT=-0.25V,V+ and all inputs = 0.0V -100 -1 uA VOH Output High Voltage Iout=-20mA 2.0 2.4 V VOL Output Low Voltage Iout=20mA VIH Input threshold H Vdd=3.6V (VIHMIN=0.7*VDD) A, B, C, D, E+, E- VIL Input Threshold L Vdd=3.0V (VILMAX=0.3*VDD) A, B, C, D, E+, E- IIH Input Lkg Current A, B, C, D, E+, E- IIL Input Lkg Current VIKL Input Clamp Diode Voltage VIKH ICC Notes: Min Typ Max (V+) -0.3 (V+) (V+) +0.6 1.9 2.3 -0.4 0 0.4 V 1.5 2.0 V -0.4 0 0.4 V -5 -0.1 -30 Units V V uA 0.1 5 uA -70 -100 mA 1 100 uA 0.1 0.5 2.5 V V 0.9 V -1 1 uA A, B, C, D, E+, E- -1 1 uA IIN=-20 mA A, B, C, D, E+, E- -1.5 Input Clamp Diode Voltage IIN=20 mA A, B, C, D, E+, E- Supply Current No load, Inputs = 0 V or V+ V+ (V+) + 1.5 V 120 uA 150 uA 1. “Line” pins refer to AQ-, AQ+, BQ-, BQ+, CQ-, CQ+, DQ-, DQ+, differential outputs 2. “Digital Input” or “Enable” pins refer to E+, E3. “Digital Input” pins refer to A, B, C, D 4. Output Short Circuit not intended to imply continuous operation ©2005 Peregrine Semiconductor Corp. All rights reserved. Page 4 of 7 Document No. 70-0157-01 │ UltraCMOS™ RFIC Solutions PE926C31 Product Specification Table 6. Pre-irradiation Electrical Specifications -55° C < Tcase < 125° C, 3.0 V < V+ < 3.6 V, PreRad, unless otherwise specified Param Description Conditions Pin(s) TPHL Prop Delay H-L RL=100 CL=50 pF TPLH Prop Delay H-L TSK1 Prop Delay Q+/Q- TSK2* Prop Delay Skew Ch/Ch TRISE* Rise Time 20%/80% AQ+, AQ-, BQ+, BQ-, CQ+, CQ-, DQ+, DQ- TFALL* Min Typ Max Units 3 9 15 nS 3 9 15 nS -3 0 3 nS -3 0 3 nS 3 10 nS Fall Time 20%/80% 3 10 nS TPHZ Prop Delay H-Z 12 20 nS TPZH Prop Delay Z-H 12 20 nS TPLZ Prop Delay L-Z 10 20 nS TPZL Prop Delay Z-L 10 20 nS Table 7. Post-irradiation Electrical Specifications 25° C, 3.0 V < V+ < 3.6 V, 300 KRad, unless otherwise specified Param Description Conditions Pin(s) TPHL Prop Delay H-L RL=100 CL=50 pF TPLH Prop Delay H-L TSK1 Prop Delay Q+/Q- TSK2* Prop Delay Skew Ch/Ch TRISE* Rise Time 20%/80% AQ+, AQ-, BQ+, BQ-, CQ+, CQ-, DQ+, DQ- TFALL* Min Typ Max Units 3 9 15 nS 3 9 15 nS -3 0 3 nS -3 0 3 nS 3 10 nS Fall Time 20%/80% 3 10 nS TPHZ Prop Delay H-Z 20 20 nS TPZH Prop Delay Z-H 20 20 nS TPLZ Prop Delay L-Z 10 20 nS TPZL Prop Delay Z-L 10 20 nS *Note: Guaranteed by design, not tested Document No. 70-0157-01 │ www.psemi.com ©2005 Peregrine Semiconductor Corp. All rights reserved. Page 5 of 7 PE926C31 Product Specification Figure 3. TPLH, TPHL Test Circuit Block Diagram 4,16 TPLH, TPHL measured from input 50% to output 50% thresholds. TRISE, TFALL measured from output 20% to output 80% thresholds. 2,6,10,14 DC 8,12 1,7,9,15 I+ + - VI 0.0 – (V+) Q3,5,11,13 Q+ TPLH TPLH Q-, Q+ Figure 2 : TPLH, TPHL TRISE TFALL Figure 4. TPLZ, TPZL, TPHZ, TPZH Test Circuit Block Diagram 4 TPZH, TPZL measured from input 50% to output 50% thresholds. TPHZ, TPLZ measured from input 50% to output 10% thresholds. 16 E+ 0 - (V+) DC V+ 3.3V 13 2,6,10,14 1,7,9,15 E(V+) - 0 + VI DC L: 0.0 H: (V+) R 110Ω L EE+ CL 50pF 3,5,11,13 Q+, QTPZH TPHZ TPZL TPLZ Q+, Q- Figure 3: TPHZ, TPZH, TPLZ, TPZL Table 8. Ordering Information Order Code Part Marking Description Shipping Method Package 926C31-01 PE926C31-01 Engineering Sample 16-lead FLAT PACK 1/Box 926C31-21 PE926C31-21 Flight Product, FP 16-lead FLAT PACK 25/Tray 926C31-00 PE926C31-EK Evaluation Kit Evaluation Board 1/Box ©2005 Peregrine Semiconductor Corp. All rights reserved. Page 6 of 7 Document No. 70-0157-01 │ UltraCMOS™ RFIC Solutions PE926C31 Product Specification Sales Offices United States Japan Peregrine Semiconductor Corp. Peregrine Semiconductor K.K. 9450 Carroll Park Drive San Diego, CA 92121 Tel 1-858-731-9400 Fax 1-858-731-9499 5A-5, 5F Imperial Tower 1-1-1 Uchisaiwaicho, Chiyoda-ku Tokyo 100-0011 Japan Tel: 011-81-3-3502-5211 Fax: 011-81-3-3502-5213 Europe China Peregrine Semiconductor Europe Peregrine Semiconductor Bâtiment Maine 13-15 rue des Quatre Vents F- 92380 Garches, France Tel: 011- 33-1-47-41-91-73 Fax : 011-33-1-47-41-91-73 28G, Times Square, No. 500 Zhangyang Road, Shanghai, 200122, P.R. China Tel: 011-86-21-5836-8276 Fax: 011-86-21-5836-7652 For a list of representatives in your area, please refer to our Web site at: www.psemi.com Data Sheet Identification Advance Information The product is in a formative or design stage. The data sheet contains design target specifications for product development. Specifications and features may change in any manner without notice. Preliminary Specification The data sheet contains preliminary data. Additional data may be added at a later date. Peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product. Product Specification The data sheet contains final data. In the event Peregrine decides to change the specifications, Peregrine will notify customers of the intended changes by issuing a DCN (Document Change Notice). Document No. 70-0157-01 │ www.psemi.com The information in this data sheet is believed to be reliable. However, Peregrine assumes no liability for the use of this information. Use shall be entirely at the user’s own risk. No patent rights or licenses to any circuits described in this data sheet are implied or granted to any third party. Peregrine’s products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the Peregrine product could create a situation in which personal injury or death might occur. Peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. The Peregrine name, logo, and UTSi are registered trademarks and UltraCMOS is a trademark of Peregrine Semiconductor Corp. ©2005 Peregrine Semiconductor Corp. All rights reserved. Page 7 of 7