93L14 Quad Latch General Description Features The 93L14 is a multifunctional 4-bit latch designed for general purpose storage applications in high speed digital systems. All outputs have active pull-up circuitry to provide high capacitance drive and to provide low impedance in both logic states for good noise immunity. Y Connection Diagram Logic Symbol Y Y Can be used as single input D latches or set/reset latches Active low enable gate input Overriding master reset Dual-In-Line Package TL/F/9612 – 2 VCC e Pin 16 GND e Pin 8 TL/F/9612 – 1 Order Number 93L14DMQB or 93L14FMQB See NS Package Number J16A or W16A Pin Names E D0–D3 S0 – S3 MR Q0–Q3 C1995 National Semiconductor Corporation TL/F/9612 Description Enable Input (Active LOW) Data Inputs Set Inputs (Active LOW) Master Reset Input (Active LOW) Latch Outputs RRD-B30M105/Printed in U. S. A. 93L14 Quad Latch June 1989 Absolute Maximum Ratings (Note) Note: The ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the ‘‘Electrical Characteristics’’ table are not guaranteed at the absolute maximum ratings. The ‘‘Recommended Operating Conditions’’ table will define the conditions for actual device operation. If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage 7V Input Voltage 5.5V Operating Free Air Temperature Range b 55§ C to a 125§ C MIL b 65§ C to a 150§ C Storage Temperature Range Recommended Operating Conditions Symbol 93L14 (MIL) Parameter Units Min Nom Max 4.5 5 5.5 VCC Supply Voltage VIH High Level Input Voltage VIL Low Level Input Voltage IOH High Level Output Voltage IOL Low Level Output Current TA Free Air Operating Temperature ts (H) ts (L) Setup Time HIGH or LOW Dn to E 10 20 ns th (H) th (L) Hold Time HIGH or LOW Dn to E 0 10 ns ts (H) Setup Time HIGH, Dn to Sn 15 ns th (L) Hold Time LOW, Dn to Sn 5 ns tw (L) E Pulse Width LOW 30 ns tw (L) MR Pulse Width LOW 25 ns trec Recovery Time, MR to E 5 ns 2 b 55 2 V V 0.7 V b 400 mA 4.8 mA 125 §C Electrical Characteristics Over recommended operating free air temperature range (unless otherwise noted) Symbol Parameter Conditions VI Input Clamp Voltage VCC e Min, II e b10 mA VOH High Level Output Voltage VCC e Min, IOH e Max, VIL e Max, VIH e Min VOL Low Level Output Voltage VCC e Min, IOL e Max, VIH e Min, VIL e Max II Input Current @ Max Input Voltage VCC e Max, VI e 5.5V IIH High Level Input Current VCC e Max, VI e 2.4V IIL Low Level Input Current VCC e Max, VI e 0.3V IOS Short Circuit Output Current VCC e Max (Note 2) ICC Supply Current VCC e Max (Note 3) Min Typ (Note 1) Max Units b 1.5 V 2.4 V 0.3 V 1 mA Inputs 20 Dn 30 Inputs b 400 Dn b 600 b 2.5 mA mA b 25 mA 16.5 mA Note 1: All typicals are at VCC e 5V, TA e 25§ C. Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second. Note 3: ICC is measured with all outputs open and all inputs grounded. Switching Characteristics VCC e a 5.0V, TA e a 25§ C (See Section 1 for waveforms and load configurations) Symbol CL e 15 pF Parameter Min Units Max tPLH tPHL Propagation Delay E to Qn 45 36 ns tPLH tPHL Propagation Delay Dn to Qn 30 30 ns tPLH Propagation Delay, MR to Qn 30 ns tPHL Propagation Delay, Sn to Qn 33 ns 3 Functional Description Truth Table The 93L14 consists of four latches with a common active LOW Enable input and active LOW Master Reset input. When the Enable goes HIGH, data present in the latches is stored and the state of the latch is no longer affected by the Sn and Dn inputs. The Master Reset when activated overrides all other input conditions forcing all latch outputs LOW. Each of the four latches can be operated in one of two modes: D-TYPE-LATCHÐFor D-type operation the S input of a latch is held LOW. While the common Enable is active the latch output follows the D input. Information present at the latch output is stored in the latch when the Enable goes HIGH. SET/RESET LATCHÐDuring set/reset operation when the common Enable is LOW a latch is reset by a LOW on the D input, and can be set by a LOW on the S input if the D input is HIGH. If both S and D inputs are LOW, the D input will dominate and the latch wil be reset. When the Enable goes HIGH, the latch remains in the last state prior to disablement. The two modes of latch operation are shown in the Truth Table. MR E D S Qn H H H L L H L H X L L X L L H H H H H L L L L H L H L H X L L H H X Qnb1 Qnb1 L X X X L Operation D Mode Qnb1 L H L R/S Mode RESET H e HIGH Voltage Level L e LOW Voltage Level X e Immaterial Qnb1 e Previous Output State Qn e Present Output State Logic Diagram TL/F/9612 – 3 4 Physical Dimensions inches (millimeters) 16-Lead Ceramic Dual-In-Line Package (J) Order Number 93L14DMQB NS Package Number J16A 5 93L14 Quad Latch Physical Dimensions inches (millimeters) (Continued) 16-Lead Ceramic Flat Package (W) Order Number 93L14FMQB NS Package Number W16A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. 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