DATASHEET ICS9DB102 Two Output Differential Buffer for PCIe Gen1 & Gen2 Description Features/Benefits The ICS9DB102 zero-delay buffer supports PCI Express clocking requirements. The ICS9DB102 is driven by a differential SRC output pair from an ICS CK410/CK505-compliant main clock. It attenuates jitter on the input clock and has a selectable PLL Band Width to maximize performance in systems with or without Spread-Spectrum clocking. • • • • • • Output Features • CLKREQ# pin for outputs 1 and 4/output enable for Express Card applications PLL or bypass mode/PLL can dejitter incoming clock Selectable PLL bandwidth/minimizes jitter peaking in downstream PLL’s Spread Spectrum Compatible/tracks spreading input clock for low EMI SMBus Interface/unused outputs can be disabled Industrial temperature range available Key Specifications 2 - 0.7V current mode differential output pairs (HCSL) • • Cycle-to-cycle jitter < 35ps Output-to-output skew < 25ps Functional Block Diagram CLKREQ0# CLKREQ1# PCIEX0 CLK_INT C LK_IN C SPREAD COMPATIBLE PLL PCIEX1 PLL_BW SMBDAT CONTROL LOGIC SMBCLK IREF IDT® Two Output Differential Buffer for PCIe Gen1 & Gen2 852 1 REV K 04/01/10 ICS9DB102 Two Output Differential Buffer for PCIe Gen1 & Gen2 Pin Configuration 1 2 3 4 5 6 7 8 9 10 ICS9DB102 PLL_BW CLK_INT CLK_INC **CLKREQ0# VDD GND PCIEXT0 PCIEXC0 VDD SMBDAT Power Groups 20 19 18 17 16 15 14 13 12 11 Pin Number VDD GND 5,9,12,16 6,15 9 6 20 19 20 19 VDDA GNDA IREF **CLKREQ1# VDD GND PCIEXT1 PCIEXC1 VDD SMBCLK Description PCI Express Outputs SMBUS IREF Analog VDD & GND for PLL core Note: Pins preceeded by '**' have internal 120K ohm pull down resistors 20-pin SSOP & TSSOP Pin Description PIN # PIN NAME PIN TYPE 1 PLL_BW INPUT 2 3 CLK_INT CLK_INC INPUT INPUT 4 **CLKREQ0# INPUT 5 6 7 8 9 10 11 12 13 14 15 16 VDD GND PCIEXT0 PCIEXC0 VDD SMBDAT SMBCLK VDD PCIEXC1 PCIEXT1 GND VDD 17 **CLKREQ1# 18 IREF OUTPUT 19 20 GNDA VDDA POWER POWER POWER POWER OUTPUT OUTPUT POWER I/O INPUT POWER OUTPUT OUTPUT POWER POWER INPUT DESCRIPTION 3.3V input for selecting PLL Band Width 0 = low, 1= high "True" reference clock input. "Complementary" reference clock input. Output enable for SRC/PCI Express output pair '0' 0 = enabled, 1 = tri-stated Power supply, nominal 3.3V Ground pin. True clock of differential PCI_Express pair. Complement clock of differential PCI_Express pair. Power supply, nominal 3.3V Data pin of SMBUS circuitry, 5V tolerant Clock pin of SMBUS circuitry, 5V tolerant Power supply, nominal 3.3V Complement clock of differential PCI_Express pair. True clock of differential PCI_Express pair. Ground pin. Power supply, nominal 3.3V Output enable for SRC/PCI Express output pair '1' 0 = enabled, 1 = tri-stated This pin establishes the reference current for the differential currentmode output pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. Ground pin for the PLL core. 3.3V power for the PLL core. Note: Pins preceeded by '**' have internal 120K ohm pull down resistors IDT® Two Output Differential Buffer for PCIe Gen1 & Gen2 852 2 REV K 04/01/10 ICS9DB102 Two Output Differential Buffer for PCIe Gen1 & Gen2 Absolute Max Symbol VDDA VDD Parameter 3.3V Core Supply Voltage 3.3V Output Supply Voltage Ts Tcase Storage Temperature Case Temperature Input ESD protection human body model ESD prot Min GND - 0.5 Max V DD + 0.5V V DD + 0.5V -65 150 115 2000 Units V V ° C °C V Electrical Characteristics - Input/Supply/Common Output Parameters TA = Tambient; Supply Voltage VDD = 3.3 V +/-5% PARAMETER SYMBOL CONDITIONS MIN Input High Voltage Tambcom Tambind V IH Commercial range Industrial range 3.3 V +/-5% 0 -40 2 70 85 V DD + 0.3 °C °C V 1 1 1 Input Low Voltage Input High Current V IL IIH 3.3 V +/-5% V IN = V DD V IN = 0 V; Inputs with no pullup resistors V IN = 0 V; Inputs with pull-up resistors Full Active, CL = Full load; all differential pairs tri-stated V DD = 3.3 V VSS - 0.3 -5 0.8 5 V uA 1 1 -5 uA 1 -200 uA 1 100 50 105 7 5 4.5 mA mA MHz nH pF pF 1 1 1 1 1 1 1.8 ms 1 Tambient IIL1 Input Low Current IIL2 Operating Supply Current I DD3.3OP Input Frequency 3 Pin Inductance1 Fi Lpin CIN COUT Input Capacitance1 Clk Stabilization1,2 Modulation Frequency Spread Spectrum Modulation Frequency PLL Bandwidth SMBus Voltage Low-level Output Voltage Current sinking at V OL = 0.4 V SCLK/SDATA Clock/Data Rise Time SCLK/SDATA Clock/Data Fall Time 80 TYP 75 27 100 MAX UNITS NOTES Logic Inputs Output pin capacitance From VDD Power-Up to 1st clock Triangular Modulation 30 33 kHz 1 fMOD Lexmark Modulation 25 45 KHz 1 400 KHz 1 BW PLL Bandwidth when PLL_BW=0 PLL Bandwidth when PLL_BW=1 1.2 MHz 1 5.5 0.4 V V mA 1 1 1 TSTAB 2.7 VDD V OLSMBUS IPULLUP @ IPULLUP SMBus SDATA pin 4 TRI2C (Max VIL - 0.15) to (Min VIH + 0.15) 1000 ns 1 TFI2C (Min VIH + 0.15) to (Max VIL - 0.15) 300 ns 1 1 Guaranteed by design and characterization, not 100% tested in production. IDT® Two Output Differential Buffer for PCIe Gen1 & Gen2 852 3 REV K 04/01/10 ICS9DB102 Two Output Differential Buffer for PCIe Gen1 & Gen2 Electrical Characteristics - PCIEX 0.7V Current Mode Differential Pair TA = Tambient; VDD = 3.3 V +/-5%; CL PARAMETER SYMBOL Current Source Output Zo Impedance Voltage High VHigh Voltage Low VLow Max Voltage Vovs Min Voltage Vuds =2pF, RS=33.2Ω, RP=49.9Ω, IREF = 475Ω CONDITIONS MIN TYP VO = Vx 3000 Statistical measurement on single ended signal using Measurement on single ended signal using absolute value. 660 -150 Crossing Voltage (abs) Vcross(abs) Crossing Voltage (var) d-Vcross Long Accuracy ppm Average period Tperiod Absolute min period Rise Time Fall Time Rise Time Variation Fall Time Variation Tabsmin tr tf d-tr d-tf tpd tpdbyp Input to Output Delay Duty Cycle dt3 Output-to-Output Skew tsk3 Jitter, Cycle to cycle tjcyc-cyc tjcyc-cycbyp 850 150 1150 V T = 50% PLL mode. Measurement from differential wavefrom Additve Jitter in Bypass Mode mV mV 1 1,3 1,3 1,3 1,3 350 550 mV 1,3 12 140 mV 1,3 0 10.0030 10.0533 0 3.7 700 700 125 125 150 4.2 ppm ns ns ns ps ps ps ps ps ns 1,2 2 2 1,2 1 1 1 1 1 1 45 55 % 1 25 ps 1 35 ps 1 30 ps 1 9.9970 9.9970 9.8720 175 175 30 30 PLL Mode. Bypass mode Measurement from differential wavefrom UNITS NOTES Ω -300 250 Variation of crossing over all edges see Tperiod min-max values 100.00MHz nominal 100.00MHz spread 100.00MHz nominal/spread VOL = 0.175V, VOH = 0.525V VOH = 0.525V V OL = 0.175V MAX 1 . Guaranteed by design, not 100% tested in production. 2 The 9DB102 does not add a ppm error to the input clock 3 IREF = V DD/(3xRR). For RR = 475Ω (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50Ω. IDT® Two Output Differential Buffer for PCIe Gen1 & Gen2 852 4 REV K 04/01/10 ICS9DB102 Two Output Differential Buffer for PCIe Gen1 & Gen2 Electrical Characteristics - PLL Parameters TA = Tambient; Supply Voltage VDD = 3.3 V +/-5% Group Parameter Description Min Typ Max Units Notes PLL Jitter Peaking jpeak-hibw (PLL_BW = 1) 0 1 2.5 dB 1,4 PLL Jitter Peaking jpeak-lobw (PLL_BW = 0) 0 1 2 dB 1,4 PLL Bandwidth PLL Bandwidth pllHIBW pllLOBW (PLL_BW = 1) (PLL_BW = 0) PCIe Gen 1 phase jitter (1.5 - 22 MHz) PCIe Gen 2 jitter (8-16 MHz, 5-16 MHz) Hi-Band >1.5MHz (PLL_BW=1) PCIe Gen 2 jitter (8-16 MHz, 5-16 MHz) Hi-Band >1.5MHz (PLL_BW=0) PCIe Gen 2 jitter (8-16 MHz, 5-16 MHz) Lo-Band <1.5MHz 2 0.4 2.5 0.5 3 1 MHz MHz 1,5 1,5 40 108 ps 1,2,3 2.7 3.1 ps rms 1,2,3 2.2 3.1 ps rms 1,2,3 1.3 3 ps rms 1,2,3 Jitter, Phase tjphasePLL NOTES: 1. Guaranteed by design and characterization, not 100% tested in production. 2. See http://www.pcisig.com for complete specs 3. Device driven by 932S421BGLF or equivalent 4. Measured as maximum pass band gain. At frequencies w ithin the loop BW, highest point of magnification is called PLL jitter peaking. 5. Measured at 3 db dow n or half pow er point. IDT® Two Output Differential Buffer for PCIe Gen1 & Gen2 852 5 REV K 04/01/10 ICS9DB102 Two Output Differential Buffer for PCIe Gen1 & Gen2 SRC Reference Clock Common Recommendations for Differential Routing Dimension or Value L1 length, route as non-coupled 50ohm trace 0.5 max L2 length, route as non-coupled 50ohm trace 0.2 max L3 length, route as non-coupled 50ohm trace 0.2 max Rs 33 Rt 49.9 Unit inch inch inch ohm ohm Figure 1 1 1 1 1 Down Device Differential Routing L4 length, route as coupled microstrip 100ohm differential trace 2 min to 16 max L4 length, route as coupled stripline 100ohm differential trace 1.8 min to 14.4 max inch inch 1 1 Differential Routing to PCI Express Connector L4 length, route as coupled microstrip 100ohm differential trace 0.25 to 14 max L4 length, route as coupled stripline 100ohm differential trace 0.225 min to 12.6 max inch inch 2 2 Figure 1: Down Device Routing L2 L1 Rs L4 L4' L2' L1' Rs Rt HCSL Output Buffer Rt L3' PCI Express Down Device REF_CLK Input L3 Figure 2: PCI Express Connector Routing L2 L1 Rs L4 L4' L2' L1' Rs Rt HCSL Output Buffer Rt L3' IDT® Two Output Differential Buffer for PCIe Gen1 & Gen2 PCI Express Add-in Board REF_CLK Input L3 852 6 REV K 04/01/10 ICS9DB102 Two Output Differential Buffer for PCIe Gen1 & Gen2 Alternative Termination for LVDS and other Common Differential Signals (figure 3) Vdiff Vp-p Vcm R1 R2 R3 R4 Note 0.45v 0.22v 1.08 33 150 100 100 0.58 0.28 0.6 33 78.7 137 100 0.80 0.40 0.6 33 78.7 none 100 ICS874003i-02 input compatible 0.60 0.3 1.2 33 174 140 100 Standard LVDS R1a = R1b = R1 R2a = R2b = R2 Figure 3 L2 L1 R3 R1a L4 R4 L4' L2' L1' R1b R2a HCSL Output Buffer R2b L3' Down Device REF_CLK Input L3 Cable Connected AC Coupled Application (figure 4) Component Value Note R5a, R5b 8.2K 5% R6a, R6b 1K 5% Cc 0.1 µF Vcm 0.350 volts Figure 4 3.3 Volts R5a R5b R6a R6b Cc L4 L4' Cc PCIe Device REF_CLK Input IDT® Two Output Differential Buffer for PCIe Gen1 & Gen2 852 7 REV K 04/01/10 ICS9DB102 Two Output Differential Buffer for PCIe Gen1 & Gen2 General SMBus serial interface information for the ICS9DB102 How to Write: How to Read: Controller (host) sends a start bit. Controller (host) sends the write address D4 (h) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 • ICS clock will acknowledge each byte one at a time • Controller (host) sends a Stop bit • • • • • • • • • • • • • • • • • • • • • • Index Block Read Operation Index Block Write Operation Controller (Host) starT bit T Slave Address D4(h) WRite WR Controller (host) will send start bit. Controller (host) sends the write address D4 (h) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D5 (h) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X (if X(h) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit Controller (Host) T starT bit Slave Address D4(h) WR WRite ICS (Slave/Receiver) ICS (Slave/Receiver) ACK ACK Beginning Byte = N Beginning Byte = N ACK ACK RT Repeat starT Slave Address D5(h) RD ReaD Data Byte Count = X ACK Beginning Byte N ACK X Byte ACK Data Byte Count = X ACK Beginning Byte N Byte N + X - 1 ACK X Byte ACK P stoP bit Byte N + X - 1 N P IDT® Two Output Differential Buffer for PCIe Gen1 & Gen2 Not acknowledge stoP bit 852 8 REV K 04/01/10 ICS9DB102 Two Output Differential Buffer for PCIe Gen1 & Gen2 SMBus Table: Device Control Register, READ/WRITE ADDRESS (D4/D5) Byte 0 Pin # Name Control Function Type 0 Functions controlled by Enables SMBus RW SW_EN Bit 7 SMBus Control registers RW RESERVED Bit 6 RESERVED RW Bit 5 RESERVED RW Bit 4 RESERVED RW Bit 3 RESERVED RW Bit 2 Selects PLL PLL BW #adjust RW Low BW Bit 1 Bandwidth PLL bypassed Bypasses PLL for RW PLL Enable Bit 0 (fan out mode) board test SMBus Table: Output Enable Register Byte 1 Pin # Name Control Function Type RESERVED RW Bit 7 RESERVED RW Bit 6 RESERVED RW Bit 5 RW RESERVED Bit 4 RESERVED RW Bit 3 RESERVED RW Bit 2 RESERVED RW Bit 1 RESERVED RW Bit 0 SMBus Table: Function Select Register Byte 2 Pin # Name Control Function Type RESERVED RW Bit 7 RESERVED RW Bit 6 RW RESERVED Bit 5 RESERVED RW Bit 4 RESERVED RW Bit 3 RESERVED RW Bit 2 RESERVED RW Bit 1 RESERVED RW Bit 0 SMBus Table: Vendor & Revision ID Register Byte 3 Pin # Name Control Function Type RID3 R Bit 7 RID2 R Bit 6 REVISION ID RID1 R Bit 5 RID0 R Bit 4 VID3 R Bit 3 VID2 R Bit 2 VENDOR ID VID1 R Bit 1 VID0 R Bit 0 IDT® Two Output Differential Buffer for PCIe Gen1 & Gen2 0 1 PWD Functions controlled by device pins 1 X X X X X High BW 1 PLL enabled (ZDB mode) 1 1 PWD X X X X X X X X 1 PWD X X X X X X X X 1 - PWD 0 0 0 1 0 0 0 1 - 0 - 0 - 852 9 REV K 04/01/10 ICS9DB102 Two Output Differential Buffer for PCIe Gen1 & Gen2 SMBus Table: DEVICE ID Byte 4 Pin # Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Control Function Type R R R Device ID R = 06 Hex R R R R 0 1 PWD 0 0 0 0 0 1 1 0 - SMBus Table: Byte Count Register Pin # Byte 5 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - Name Control Function Type 0 1 PWD BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0 Writing to this register will configure how many bytes will be read back, default is 06 = 6 bytes. RW RW RW RW RW RW RW RW - - 0 0 0 0 0 1 1 0 IDT® Two Output Differential Buffer for PCIe Gen1 & Gen2 852 10 REV K 04/01/10 ICS9DB102 Two Output Differential Buffer for PCIe Gen1 & Gen2 20-Pin SSOP Package Drawing and Dimensions SYMBOL A A1 A2 b c D E E1 e L N a ZD IDT® Two Output Differential Buffer for PCIe Gen1 & Gen2 20-Lead, 150 mil SSOP (QSOP) In Millimeters In Inches COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX 1.35 1.75 .053 .069 0.10 0.25 .004 .010 -1.50 -.059 0.20 0.30 .008 .012 0.18 0.25 .007 .010 SEE VARIATIONS SEE VARIATIONS 5.80 6.20 .228 .244 3.80 4.00 .150 .157 0.635 BASIC 0.025 BASIC 0.40 1.27 .016 .050 SEE VARIATIONS SEE VARIATIONS 0° 8° 0° 8° SEE VARIATIONS SEE VARIATIONS 852 11 REV K 04/01/10 ICS9DB102 Two Output Differential Buffer for PCIe Gen1 & Gen2 20-Pin TSSOP Package Drawing and Dimensions 20-Lead, 4.40 mm. Body, 0.65 mm. Pitch TSSOP (173 mil) (25.6 mil) In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A -1.20 -.047 A1 0.05 0.15 .002 .006 A2 0.80 1.05 .032 .041 b 0.19 0.30 .007 .012 c 0.09 0.20 .0035 .008 D SEE VARIATIONS SEE VARIATIONS E 6.40 BASIC 0.252 BASIC E1 4.30 4.50 .169 .177 e 0.0256 BASIC 0.65 BASIC L 0.45 0.75 .018 .030 N SEE VARIATIONS SEE VARIATIONS a 0° 8° 0° 8° aaa -0.10 -.004 c N L E1 E INDEX AREA 1 2 α D A A2 A1 VARIATIONS -Ce b N SEATING PLANE 20 D mm. MIN 6.40 D (inch) MAX 6.60 MIN .252 MAX .260 aaa C Reference Doc.: JEDEC Publication 95, MO-153 10-0035 Ordering Information Part / Order Number Shipping Packaging 9DB102BFLF Tubes 9DB102BFLFT Tape and Reel 9DB102BFILF Tubes 9DB102BFILFT Tape and Reel 9DB102BGLF Tubes 9DB102BGLFT Tape and Reel 9DB102BGILF Tubes 9DB102BGILFT Tape and Reel Package 20-pin SSOP 20-pin SSOP 20-pin SSOP 20-pin SSOP 20-pin TSSOP 20-pin TSSOP 20-pin TSSOP 20-pin TSSOP Temperature 0 to +70°C 0 to +70°C -40 to +85°C -40 to +85°C 0 to +70°C 0 to +70°C -40 to +85°C -40 to +85°C "LF" after the package code are the Pb-Free configuration and are RoHS compliant. "B" is the device revision designator (will not correlate to the datasheet revision). IDT® Two Output Differential Buffer for PCIe Gen1 & Gen2 852 12 REV K 04/01/10 ICS9DB102 Two Output Differential Buffer for PCIe Gen1 & Gen2 Revision History Rev. F G H J K Originator Issue Date Description 1. Added Phase Noise Parameters, Updated input to output delay values. 2. PLL BW moved to PLL parameters table. 8/6/2007 3. Added terminations tables. 12/14/2007 Updated General SMBus Interface Information. 10/29/2008 Corrected "HCSL" typos. 1. Added I-temp electricals 2. Changed datasheet title 1/15/2010 3. Updated Input Frequency parameter 4. Updated ordering information RW 4/1/2010 Updated ordering info for Rev B Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 408-284-6578 [email protected] Corporate Headquarters Asia Pacific and Japan Europe Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) IDT Singapore Pte. Ltd. 1 Kallang Sector #07-01/06 KolamAyer Industrial Park Singapore 349276 Phone: 65-6-744-3356 Fax: 65-6-744-1764 IDT Europe Limited 321 Kingston Road Leatherhead, Surrey KT22 7TU England Phone: 44-1372-363339 Fax: 44-1372-378851 © 2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, ICS, and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA